Semiconductor device

Abstract

To provide a small nonvolatile memory with sufficient capacity.SOLUTION: A nonvolatile memory includes a first well with a first conductivity type formed extending from a first region on one surface of a semiconductor substrate to the inside, a second well with a second conductivity type formed extending from a second region apart from the first region on the one surface of the semiconductor substrate to the inside, a third well with the first conductivity type formed extending from a third region apart from the second region on the one surface of the semiconductor substrate to the inside, and a conductive layer formed in the first region, the second region, and the third region on the one surface of the semiconductor substrate. The one surface includes a concave part formed at least in a part of a periphery of the first region and exposing a side surface of the first well. The conductive layer is formed to cover an upper surface of the first well exposed to the first region and at least a part of the side surface of the first well exposed to the concave part.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] As a non-volatile memory device, a non-volatile memory that stores and erases data by changing the charge storage state in a floating gate, which is an electrically insulated floating electrode layer, is known. As the structure of such a non-volatile memory, a so-called stack-type structure in which a polysilicon layer constituting a floating gate and a polysilicon layer constituting a control gate are stacked is common.

[0003] On the other hand, different from the stack-type non-volatile memory, a single-layer polysilicon-type non-volatile memory constituted by using a single layer of polysilicon is known (for example, Patent Document 1). In the single-layer polysilicon-type non-volatile memory, for example, a first well region that functions as a control gate, a second well region that functions as a read gate, and a third well region that functions as a tunnel gate are provided near the surface layer portion of a semiconductor substrate. On the substrate, a floating gate made of a tunnel oxide film and a single layer of polysilicon is formed so as to overlap from the first well region to the third well region.

[0004] Capacitors corresponding to the floating gate, the read gate, and the tunnel gate are formed in portions facing the floating gate with the tunnel oxide films of the first well region, the second well region, and the third well region interposed therebetween. Then, by applying voltages to the control gate, the read gate, and the tunnel gate respectively and changing the potential of the floating gate, operations such as data writing and erasing are performed.

[0005] For example, at the time of data writing, a voltage Vw (Vw > 0V) is applied to the control gate, 0V is applied to the tunnel gate, and an intermediate voltage Vc (0V < Vc < Vw) is applied to the read gate. In response to the voltage Vw applied to the control gate, the potential of the floating gate rises, and charge is injected from the third well region (i.e., the tunnel gate) into the floating gate. On the other hand, at the time of data erasure, 0V is applied to the control gate, a voltage Vw is applied to the tunnel gate, and an intermediate voltage Vc is applied to the read gate. In response to the voltage 0V applied to the control gate, the potential of the floating gate drops, and the charge accumulated in the floating gate moves to the third well region.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0007] In the single-layer polysilicon type non-volatile memory as described above, the "writing characteristics" representing the writing speed to the memory cell and the voltage required for writing are important. At the time of writing, the higher the potential of the floating gate, the easier it is to inject charge from the tunnel gate into the floating gate. For this reason, in terms of the writing characteristics, it is preferable that the capacitance of the capacitor of the control gate (hereinafter referred to as the writing capacitance) is relatively larger than the capacitance of the capacitor of the tunnel gate (hereinafter referred to as the erasing capacitance).

[0008] Generally, the capacitance of a capacitor such as a flat capacitor is proportional to the area of the electrodes. In the single-layer polysilicon type non-volatile memory as described above, the area of the overlapping portion between the floating gate and the control gate corresponds to the "area of the electrodes" in the write capacitance. Therefore, in order to increase the write capacitance, it is necessary to increase the area of the overlapping portion between the control gate and the floating gate. As a result, there has been a problem that the unit area of the memory cell increases and the chip size increases.

[0009] The present invention has been made in view of the above problems, and an object thereof is to provide a non-volatile memory having a small area and a sufficient capacitance.

Means for Solving the Problems

[0010] The semiconductor device according to the present invention is a semiconductor device constituting a non-volatile memory, and includes a semiconductor substrate, a first well of a first conductivity type formed so as to extend inward from a first region on one surface of the semiconductor substrate, a second well of a second conductivity type having a polarity opposite to that of the first conductivity type formed so as to extend inward from a second region separated from the first region on the one surface of the semiconductor substrate, a third well of the first conductivity type formed so as to extend inward from a third region separated from the second region on the one surface of the semiconductor substrate, and a conductive layer formed over the first region, the second region, and the third region on the one surface of the semiconductor substrate. A recess is provided on the one surface, which is formed at least in part on the periphery of the first region and exposes the side surface of the first well. The conductive layer is formed so as to cover the upper surface of the first well exposed in the first region and at least a part of the side surface of the first well exposed in the recess.

[0011] In addition, the semiconductor device according to the present invention includes a first well of a first conductivity type extending inward from a first region on one surface, a second well of a second conductivity type having a polarity opposite to that of the first conductivity type and extending inward from a second region spaced apart from the first region on the one surface, and a third well of the first conductivity type extending inward from a third region spaced apart from the second region on the one surface so that the second well is positioned between the first well. A semiconductor substrate including the third well, a separation layer extending inward from a fourth region between the first region and the second region on the one surface of the semiconductor substrate, and the first region, the second region, the third region, and the fourth region on the one surface of the semiconductor substrate. And a conductive layer provided across the regions and partially positioned between the first well and the separation layer in a direction in which the first region and the second region are separated.

[0012] Further, a method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device constituting a nonvolatile memory. A first well of a first conductivity type is formed so as to extend inward from a first region on one surface of a semiconductor substrate, and a third well of the first conductivity type is formed so as to extend inward from a third region spaced apart from the first region on the one surface of the semiconductor substrate. Forming a second well of a second conductivity type having a polarity opposite to that of the first conductivity type so as to extend inward from a second region located between the first region and the third region on the one surface of the semiconductor substrate; Forming a separation layer extending inward from a region located at a boundary portion between the first region and the second region on the one surface of the semiconductor substrate; and exposing a part of a side surface of the first well at a boundary portion between the separation layer and the first well. Forming a recess, and forming a conductive layer so as to cover an upper surface of the first well exposed in the first region and at least a part of a side surface of the first well exposed in the recess.

Advantages of the Invention

[0013] According to the semiconductor device of the present invention, it is possible to reduce the area while maintaining the capacitance of the memory cells in the nonvolatile memory.

Brief Description of the Drawings

[0014]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5A

Figure 5B

Figure 5C

Figure 5D

Figure 6A

Figure 6B

Figure 6C

Figure 7

Figure 8

Figure 9

Modes for Carrying Out the Invention

[0015] Hereinafter, preferred embodiments of the present invention will be described in detail. In the following descriptions of the respective embodiments and the accompanying drawings, the same reference numerals are assigned to substantially the same or equivalent parts.

Embodiment

[0016] FIG. 1 is a top view of a semiconductor device 100 according to this embodiment as viewed from above the element formation surface. The semiconductor device 100 is a semiconductor device that constitutes a memory cell of a single-layer polysilicon type non-volatile semiconductor memory.

[0017] The semiconductor device 100 includes a semiconductor substrate 10, a first well region 11, a second well region 12, and a third well region 13 that are formed to extend inward from the first surface (i.e., the element mounting surface) of the semiconductor substrate 10. Further, on the first surface of the semiconductor substrate 10, gate polysilicon 20 is formed over a region above the first well region 11, the second well region 12, and the third well region 13.

[0018] The semiconductor substrate 10 is composed of, for example, a Si (silicon) substrate and has a rectangular shape in a top view.

[0019] The first well region 11 and the third well region 13 are well regions of a first conductivity type (N-type in this embodiment). On the other hand, the second well region 12 is a well region of a second conductivity type (P-type in this embodiment) having a polarity opposite to that of the first conductivity type.

[0020] The first well region 11 is a region that functions as an active area of the semiconductor memory. The surface of the first well region 11 exposed on the first surface of the semiconductor substrate 10 (hereinafter simply referred to as the surface of the first well region 11) has a strip shape in a top view. The portion of the first well region 11 covered with the gate polysilicon 20 is a region that functions as a control gate of the semiconductor memory. In this embodiment, a region on the first surface of the semiconductor substrate 10 where the upper surface portion of the first well region 11 covered with the gate polysilicon 20 is located is referred to as a first region A1 (indicated by a two-dot chain line in FIG. 1).

[0021] Near the surface of the first well region 11 located outside the first region A1, an N-type diffusion layer (not shown) is formed, and a plurality of contacts CT1 made of a conductor such as tungsten are connected to the diffusion layer. The diffusion layer and the contacts CT1 are formed in a region not covered by the gate polysilicon 20 on the surface of the first well region 11 and are exposed on the first surface of the semiconductor substrate 10.

[0022] The second well region 12 is a region that constitutes a read field-effect transistor. The surface of the second well 12 exposed on the first surface of the semiconductor substrate 10 (hereinafter simply referred to as the surface of the second well region 12) has a strip-shaped shape extending parallel to the first well region 11 in a top view. The second well region 12 is formed to extend from a position (second region) separated from the first region A1 on the first surface of the semiconductor substrate 10 toward the inside of the semiconductor substrate 10.

[0023] The third well region 13 is a region that constitutes an erase area of the semiconductor memory. The third well region 13 is formed to extend from a position (third region) separated from the second region on the first surface of the semiconductor substrate 10 toward the inside of the semiconductor substrate 10. The third region faces the first region A1 with the second region interposed therebetween. That is, the third well region 13 is formed at a position facing the first well region 11 with the second well region 12 interposed therebetween. The surface of the third well region 13 exposed on the first surface of the semiconductor substrate 10 (hereinafter simply referred to as the surface of the third well region 13) has a rectangular shape in a top view.

[0024] An N-type diffusion layer (not shown) is formed in the third well region 13, and a plurality of contacts CT2 made of a conductor such as tungsten are connected to the diffusion layer. The diffusion layer and the contacts CT2 are formed in a region not covered by the gate polysilicon 20 on the surface of the third well region 13 and are exposed on the first surface of the semiconductor substrate 10. Note that the portion covered by the gate polysilicon 20 in the third well region 13 is a region that functions as a tunnel gate of the semiconductor memory.

[0025] The gate polysilicon 20 is a single-layer conductive layer made of a polysilicon film. The gate polysilicon 20 is formed so as to straddle the first well region 11, the second well region 12, and the third well region 13 and expose a part of each surface. In this embodiment, the gate polysilicon 20 includes, in a top view, a rectangular portion (hereinafter referred to as the first rectangular portion) covering the surface of the first well region 11, a rectangular portion (hereinafter referred to as the second rectangular portion) covering a part of the surface of the third well region 13, and a strip-shaped portion (hereinafter referred to as the strip portion) connecting the first rectangular portion and the second rectangular portion so as to cross the surface of the second well region 12. The strip portion of the gate polysilicon 20 and the surface of the second well region 12 extend such that their longitudinal directions intersect each other.

[0026] Further, a selection transistor 23 is formed so as to cover a part of the surface of the second well region 12. The selection transistor 23 has, for example, a rectangular shape in a top view and is arranged such that its long side direction is orthogonal to the exposed portion of the semiconductor substrate 10 of the second well region 12 on the first surface.

[0027] FIG. 2 is a cross-sectional view taken along the line X-X of FIG. 1.

[0028] The first well region 11, the second well region 12, and the third well region 13 are formed so as to extend inward from the first surface of the semiconductor substrate 10. In FIG. 2, the portion where the first well region 11, the second well region 12, and the third well region 13 are not formed is shown as a silicon substrate 18.

[0029] In the region near the surface portions of each of the first well region 11, the second well region 12, and the third well region 13, an element isolation region 14 made of an oxide film is formed. That is, the element isolation region 14 is formed so as to extend inward from the first surface of the semiconductor substrate 10. The element isolation region 14 has a STI (Shallow Trench Isolation) structure. Note that in FIG. 1, the illustration of the element isolation region 14 is omitted.

[0030] In the element isolation region 14 provided between the first well region 11 and the second well region 12 (that is, the element isolation region 14 formed so as to extend inward from the region between the first region A1 and the second region on the first surface of the semiconductor substrate 10), a stepped portion is provided in a portion adjacent to the first well region 11. In other words, the stepped portion is a recess provided on the first surface of the semiconductor substrate 10, formed at the periphery of the first region A1, and exposing a part of the side surface of the first well 11.

[0031] A tunnel oxide film 21 is formed between the gate polysilicon 20 and the surfaces of the first well region 11, the second well region 12, and the third well region 13. The tunnel oxide film 21 is composed of, for example, a silicon oxide film. The tunnel oxide film 21 is formed so as to cover the surface portions of the first well region 11, the second well region 12, and the third well region 13 that are exposed from the semiconductor substrate 10.

[0032] The gate polysilicon 20 has a flat plate portion formed so as to straddle the surfaces of the first well region 11, the second well region 12, and the third well region 13, and a convex portion 20A (the portion surrounded by the broken-line circle in FIG. 2) that protrudes from the flat plate portion toward the inside of the semiconductor substrate 10. The flat plate portion of the gate polysilicon 20 is composed of the first rectangular portion, the second rectangular portion, and the strip-shaped portion as described above in a top view. The first rectangular portion covers the surface of the first well region 11 exposed in the first region A1 on the first surface of the semiconductor substrate 10 of the first well region 11.

[0033] The convex portion 20A of the gate polysilicon 20 is located directly below the first rectangular portion in a top view. The convex portion 20A is disposed in a stepped portion (concave portion) of the element isolation region 14 formed at the boundary between the first well region 11 and the element isolation region 14, and is provided so as to cover a part of the side surface of the first well region 11 exposed by the stepped portion. That is, the gate polysilicon 20 is formed so as to cover the upper surface of the first well region 11 (i.e., the surface exposed on the first surface of the semiconductor substrate 10) and a part of the side surface facing the element isolation region 14.

[0034] In this embodiment, a part of the side surface (i.e., the side surface facing the element isolation region 14) extending from a pair of sides constituting the rectangular portion of the surface of the first well region 11 exposed in the first region A1 toward the inside of the semiconductor substrate 10 faces the convex portion 20A of the gate polysilicon 20 with the tunnel oxide film 21 interposed therebetween.

[0035] The gate polysilicon 20 is a conductive layer constituting the floating gate of the memory cell of the semiconductor memory included in the semiconductor device 100. Also, as described above, the portions covered by the gate polysilicon 20 in the first well region 11 and the third well region 13 are well regions that function as a control gate and a tunnel gate, respectively, when writing and erasing data to and from the memory cell. The second well region 12 is a well region that functions as a read gate when reading data from the memory cell.

[0036] For example, when writing data, a voltage Vw (Vw > 0V) is applied to the contact CT1, and 0V is applied to the contact CT2. As a result, the gate polysilicon 20 becomes a potential close to the voltage Vw, and charges are injected from the third well region 13 into the gate polysilicon 20. On the other hand, when erasing data, 0V is applied to the contact CT1, and the voltage Vw is applied to the contact CT2. As a result, the gate polysilicon 20 becomes a potential close to 0V, and charges move from the gate polysilicon 20 to the third well region 13. The tunnel oxide film 21 functions as a tunnel oxide film in the charge transfer between the gate polysilicon 20 and the third well region 13.

[0037] Note that an intermediate voltage Vc (0 < Vc < Vw) is applied to the contact CT3 connected to the second well region 12 during data writing and data erasing. Also, during data reading, a reading current corresponding to the charge accumulation state in the gate polysilicon 20 flows into the second well region 12.

[0038] In the semiconductor device 100 of this embodiment, as described above, the gate polysilicon 20 is formed so as to cover not only the upper surface of the first well region 11 but also a part of the side surface facing the element isolation region 14 of the first well region 11. Therefore, the semiconductor device 100 has higher data writing characteristics than other memory cells in which the gate polysilicon 20 covers only the upper surface of the first well 11 (that is, memory cells that do not cover a part of the side surface of the first well 11, unlike the semiconductor device 100 of this embodiment). This will be described below.

[0039] FIG. 3 is a circuit diagram showing the configuration of a single-layer polysilicon type memory cell such as the semiconductor device 100 of this embodiment as an equivalent circuit. Here, the capacitor of the control gate composed of the first well region 11 is C1, the capacitor of the tunnel gate composed of the third well region 13 is C2, the potential of the floating gate composed of the gate polysilicon 20 is Vfg, the read field effect transistor composed of the second well 12 is Tr1, and the selection transistor 23 is shown as Tr2.

[0040] During data writing, a writing voltage Vw is applied to one end of the capacitor C1. A writing voltage of 0V is applied to one end of the capacitor C2. The potential Vfg of the floating gate is the potential of the node n1 connecting the other ends of the capacitors C1 and C2.

[0041] It is desirable that the potential Vfg of the floating gate be close to the write voltage Vw applied to the control gate. That is, when the potential Vfg of the floating gate is large and close to the write voltage Vw, electrons can move sufficiently between the tunnel gate and the floating gate (i.e., between the third well region 13 and the gate polysilicon 20) during data writing.

[0042] Since the charges of capacitors C1 and C2 are the same, the relationship between the capacitances of capacitors C1 and C2 and the potential Vfg of the floating gate and the write voltage Vw is expressed as C1×(Vw - Vfg)=C2×Vfg. Therefore, the potential Vfg of the floating gate is as follows in the following formula (Formula 1).

[0043]

Formula

[0044] That is, the larger the capacitance of capacitor C1 compared to the capacitance of capacitor C2, the higher the potential Vfg of the floating gate.

[0045] Generally, the capacitance of a parallel plate capacitor is expressed as the following formula (Formula 2), where C is the capacitor capacitance, ε is the dielectric constant, d is the distance between the electrodes, and A is the electrode area.

[0046]

Formula

[0047] In a single-layer polysilicon type memory cell such as the semiconductor device 100 of this embodiment, when the capacitance of the control gate is C, the area of the portion where the first well 11 serving as the control gate and the gate polysilicon 20 serving as the floating gate face each other with the tunnel oxide film 21 interposed therebetween corresponds to the electrode area A. Therefore, if the area of the portion where each well region and the gate polysilicon 20 face each other with the tunnel oxide film 21 interposed therebetween is large, the capacitance is large, and if the area is small, the capacitance is small.

[0048] As described above, when the capacitance of the first well region 11, which is the data writing capacitance, is relatively large compared to the capacitance of the third well region 13, which is the erasing capacitance, it is easy to inject charge into the floating gate, and thus the writing characteristics are high. Therefore, when the area of the portion where the first well region 11 and the gate polysilicon 20 face each other is larger than the area of the portion where the third well region 13 and the gate polysilicon 20 face each other, high writing characteristics can be obtained.

[0049] In the semiconductor device 100 of this embodiment, the gate polysilicon 20 is formed so as to cover a part of the side face facing the element isolation region 14 of the first well region 11 in addition to the upper surface of the first well region 11. For this reason, the area of the portion where the first well region 11 and the gate polysilicon 20 face each other with the tunnel oxide film 21 interposed therebetween is relatively large. Therefore, the data writing characteristics are high.

[0050] If the gate polysilicon 20 is formed so as to cover only the upper surface of the first well region 11 and an attempt is made to realize the same capacitance of the control gate as that of the semiconductor device 100 of this embodiment, it is necessary to further extend the first well 11 and the gate polysilicon 20 in the horizontal direction to increase the area of the facing portion. For this reason, the size of the entire memory cell becomes large.

[0051] On the other hand, according to the semiconductor device 100 of this embodiment, since the gate polysilicon 20 is provided so as to face a part of the side surface of the first well region 11, the electrode area A is large, and there is no need to increase the area in the horizontal direction. Therefore, it is possible to suppress the memory size while improving the data writing characteristics.

[0052] Next, a method for manufacturing the semiconductor device 100 of this embodiment will be described along the manufacturing flow shown in FIG. 4.

[0053] First, as shown in FIG. 5A, a resist film 40 patterned by photolithography is formed on the surface of a semiconductor substrate 10 of the second conductivity type (for example, a P-type Si substrate), and impurities of the first conductivity type (in this embodiment, N-type), such as P+ (phosphorus) or As+ (arsenic), are implanted into the surface of the semiconductor substrate 10 by ion implantation. Thereby, the first well region 11 and the third well region 13 are formed (STEP101 in FIG. 4).

[0054] Next, as shown in FIG. 5B, a resist film 40 is formed on the surface of the semiconductor substrate 10 on the first well region 11 and the third well region 13, and impurities of the second conductivity type (in this embodiment, P-type) are implanted. Thereby, the second well region 12 is formed (STEP102 in FIG. 4).

[0055] Next, as shown in FIG. 5C, etching is performed on the surface of the semiconductor substrate 10 in which the first well region 11, the second well region 12, and the third well region 13 are formed to form grooves (STEP103 in FIG. 4).

[0056] Next, as shown in FIG. 5D, an insulating film such as SiO2 is formed on the entire surface of the semiconductor substrate 10 including the grooves by CVD (Chemical Vapor Deposition). Thereby, the element isolation region 14 is formed (STEP104 in FIG. 4).

[0057] Next, as shown in FIG. 6A, a resist film 40 patterned by photolithography is formed on the surface of the semiconductor substrate 10, and a part of the element isolation region 14 around the first well region 11 is removed by etching. As a result, a step (i.e., a recess) is formed in the element isolation region 14 around the first well region 11 (STEP105 in FIG. 4).

[0058] Next, as shown in FIG. 6B, a silicon oxide film covering the exposed portions of the surfaces of the first well region 11, the second well region 12, and the third well region 13 is formed by thermal oxidation. Thereby, the tunnel oxide film 21 is formed (STEP106 in FIG. 4).

[0059] Next, a polysilicon film is formed by CVD so as to cover the surfaces of the element isolation region 14 and the tunnel oxide film 21. Thereby, as shown in FIG. 6C, the gate polysilicon 20 is formed (STEP107 in FIG. 4).

[0060] After going through the above steps, the formation of the diffusion layer by ion implantation and the formation of contacts are performed, and the semiconductor device 100 of this embodiment is manufactured.

[0061] As described above, in the semiconductor device 100 of this embodiment, the gate polysilicon 20 is formed so as to cover the upper surface portion exposed on the first surface of the semiconductor substrate of the first well region 11 and a part of the side surface facing the element isolation region 14 of the first well region 11. Therefore, the area of the portion where the control gate and the floating gate face each other can be increased. For this reason, compared with a semiconductor device having a structure in which the gate polysilicon covers only the upper surface of the first well region, the area in the horizontal direction on the substrate surface of the control gate and the floating gate can be reduced. Therefore, according to the semiconductor device 100 of this embodiment, it is possible to provide a non-volatile memory having a small area and sufficient capacitance.

Example

[0062] Next, Example 2 of the present invention will be described. FIG. 7 is a top view of the semiconductor device 200 according to Example 2 as viewed from above the element formation surface.

[0063] In the semiconductor device 200 of this embodiment, in a top view, the active regions constituting the first well region 11 are not formed in a strip shape with a constant width as in Example 1, but rather a rectangular region having a function as a control gate and a narrow strip-shaped region extending from the rectangular region and connecting the control gates of adjacent memory cells are formed.

[0064] In Example 1, only two sides of the rectangular shape constituting the surface of the first well region 11 exposed in the first region A1 on the first surface of the semiconductor substrate 10 faced the element isolation region 14, whereas in this embodiment, all four sides face the element isolation region 14. And a stepped portion (concave portion) is formed in the portion facing the first well region 11. That is, in this embodiment, the stepped portion of the element isolation region 14 is formed so as to surround the periphery of the first well region 11 formed so as to extend from the first region A1.

[0065] The gate polysilicon 20 is formed so as to cover the entire rectangular region. And the convex portion 20A of the gate polysilicon 20 in this embodiment is provided so as to fill the stepped portion of the element isolation region 14 and surround the periphery of the first well region 11.

[0066] In Example 1, among the four sides constituting the first rectangular portion of the gate polysilicon 20, convex portions were provided only on the two sides along the extending direction of the active region. In contrast, in this embodiment, the first rectangular portion of the gate polysilicon 20 is formed so as to cover the entire rectangular region of the first well region, and convex portions are provided on all four sides constituting the first rectangular portion of the gate polysilicon 20.

[0067] Therefore, according to the configuration of this embodiment, the area of the portion where the first well region 11 and the gate polysilicon 20 face each other can be made larger than that of the semiconductor device 100 of the first embodiment. Therefore, it is possible to further improve the data writing characteristics.

[0068] FIG. 8 is a top view of a semiconductor device 300 according to a modified example of the second embodiment as viewed from above the element formation surface. In the semiconductor device 300 of the modified example, the first well region 11 located directly below the gate polysilicon 20 is composed of a plurality of strip-shaped regions in a top view.

[0069] FIG. 9 is a cross-sectional view along the line Y-Y of FIG. 8 (that is, a cross-sectional view only of the formation position of the first well region 11). In the semiconductor device 300 of the modified example, grooves are formed between each of the strip-shaped regions. An element isolation region 14 is formed at the lower part of the groove, and a convex portion of the gate polysilicon 20 is formed at the upper part of the groove.

[0070] According to such a configuration, since the area of the portion where the first well region 11 and the gate polysilicon 20 face each other can be further increased, it is possible to further improve the data writing characteristics.

[0071] Note that the present invention is not limited to that shown in the above embodiments. For example, in the above first embodiment, the case where polysilicon (gate polysilicon 20) is used as the conductive layer constituting the floating gate has been described as an example. However, the present invention is not limited to this, and a floating gate may be configured using a conductive layer made of another material having conductivity other than polysilicon.

[0072] Also, in the above embodiments, the case where the tunnel oxide film 21 is composed of a silicon oxide film has been described as an example. However, the present invention is not limited to this, and it may be configured using other insulating materials.

[0073] In the above embodiment, a step portion is provided at a portion of the element isolation region 14 that is in contact with the first well region 11, and the gate polysilicon 20 is formed so as to cover a part of the side surface portion of the first well region 11 at the step portion. However, the mode in which the gate polysilicon 20 covers the side surface of the first well region 11 is not limited to this. For example, a concave portion may be provided until it reaches the lower surface of the element isolation region 14, and the convex portion 20A of the gate polysilicon 20 may be configured to cover all of the portion of the first well region 11 facing the element isolation region 14.

[0074] In addition, the shapes of the first well region 11, the second well region 12, and the third well region 13 in a top view are not limited to those shown in the above embodiment.

[0075] In addition, the manufacturing method shown in the above embodiment is an example, and it may be manufactured by a process different from the above. For example, in the above embodiment, an impurity of the first conductivity type (N type) is ion-implanted into the semiconductor substrate 10 of the second conductivity type (P type) to form the first well region 11 and the third well region 13, and further an impurity of the second conductivity type (P type) is ion-implanted to form the second well region 12. However, different from this, for example, first, a semiconductor layer of the second conductivity type (P type) is formed on the surface layer portion of the semiconductor substrate 10, and the first well region 11 and the third well region 13 may be formed by performing ion implantation of an impurity of the first conductivity type (N type) into the semiconductor layer. According to this method, regions other than the first well region 11 and the third well region 13 of the semiconductor layer of the second conductivity type are formed as the second well region 12.

Explanation of Reference Numerals

[0076] 100, 200, 300 Semiconductor device 10 Semiconductor substrate 11 First well region 12 Second well region 13 Third well region 14 Element isolation region 18 Silicon substrate 20 Gate polysilicon 21 Tunnel oxide film 23 Selective Transistor 40 Resist Film

Claims

1. A semiconductor device constituting a non-volatile memory, comprising: a semiconductor substrate; a first well of a first conductivity type formed so as to extend inward from a first region on one surface of the semiconductor substrate; a second well of a second conductivity type having a polarity opposite to that of the first conductivity type, formed so as to extend inward from a second region on the one surface of the semiconductor substrate, the second region being separated from the first region; a third well of the first conductivity type formed so as to extend inward from a third region on the one surface of the semiconductor substrate, the third region being separated from the second region; a conductive layer formed on the one surface of the semiconductor substrate across the first region, the second region, and the third region; a separation layer extending inward from a region between the first region and the second region on the one surface of the semiconductor substrate and formed so as to be in contact with the first well and the second well; wherein: the first region has a rectangular shape in a top view at a portion where the upper surface of the first well and the conductive layer overlap; a recess is provided on the one surface so as to surround the periphery of the first region and expose a side surface of the first well; the recess includes portions formed along four sides of the rectangular shape of the periphery of the first region; an oxide film is formed on the surface of the first well to cover the upper surface exposed in the first region of the first well and the side surface exposed in the recess; the conductive layer is formed to cover the upper surface of the first well exposed in the first region and the side surface of the first well exposed in the recess, and to extend at least partially over the upper surface of the first well and the side surface of the first well via the oxide film; the upper surface of the separation layer is in contact with a part of the conductive layer and a part of the oxide film. A semiconductor device characterized by this.

2. The semiconductor device according to claim 1, wherein the conductive layer has a flat plate portion provided so as to face the first well in the first region, and a convex portion protruding from the flat plate portion and arranged at a position facing a side surface portion at the periphery of the first region of the first well.

3. The semiconductor device according to claim 2, wherein the convex portion of the conductive layer is provided so as to extend inward from a position surrounding the periphery of the first region on the one surface of the semiconductor substrate.

4. The first well is a well region that functions as a control gate that receives an application of a first voltage when writing data to the non-volatile memory. The third well is a well region that functions as a tunnel gate that receives an application of a second voltage smaller than the first voltage when writing data to the non-volatile memory. The semiconductor device according to any one of claims 1 to 3, wherein an area of the first region is larger than an area of the third region.

5. The semiconductor device according to claim 4, wherein the conductive layer is composed of a polysilicon layer of the first conductivity type and functions as a floating gate of the non-volatile memory.

6. The semiconductor device according to any one of claims 1 to 5, wherein the semiconductor substrate is a semiconductor substrate of the second conductivity type.

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