Semiconductor circuit

Abstract

To provide a semiconductor circuit that can protect a semiconductor device operating at low voltages from harmful pulses.SOLUTION: A semiconductor circuit 10 in a semiconductor device has a semiconductor element 1 including a first n-type semiconductor layer, a metal layer, and a Schottky barrier between the first n-type semiconductor layer and the metal layer, and the semiconductor element 1 is connected forward between the signal line and ground of the semiconductor device.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor circuit that protects semiconductor microelectronics from electrostatic discharge, surges such as lightning strikes, electromagnetic pulses, and intentional electromagnetic waves.

Background Art

[0002] Conventionally, many semiconductor microelectronics equipped with semiconductor circuits have been used. However, when a voltage higher than the operating voltage is applied to these semiconductor microelectronics, there is a possibility of failure. As overvoltage sources that cause this, electrostatic electricity, surges such as lightning strikes, electromagnetic pulses, and intentional electromagnetic waves are assumed. Semiconductor microelectronics have conventionally continued to aim for improvements in integration density and processing speed, and the miniaturization of circuit design within the chip shows no sign of stopping. Along with this, the reduction of the operating voltage has become remarkable for the purpose of reducing power consumption, and some operate at a very low voltage, well below 2V, and some operate at about 1.2V. The resistance of these low-voltage semiconductor microelectronics to overvoltage is no exception to the above example, and furthermore, their vulnerability is further exacerbated by the decrease in their own operating voltage.

[0003] As a surge suppression element including static electricity, conventionally, ceramic elements such as varistors mainly composed of zinc oxide (ZnO), junction elements such as TVS diodes, etc. have been mounted on a substrate to bypass the surge current and avoid failure. However, these elements generally have a high breakdown voltage characteristic of several tens of V to several hundreds of V, and thus there is a problem that they are not necessarily suitable for protecting harmful pulses of semiconductor microelectronics operating at a low voltage as described above.

[0004] Also, even if an attempt is made to apply the forward behavior of a conventional semiconductor p-n diode typified by Si and a Schottky diode to a function like a varistor, their forward rise voltage V fThey are about 0.6V to 0.7V and 0.2V to 0.3V respectively, which are lower than the operating voltage of semiconductor microelectronics. Therefore, in the operating voltage range of semiconductor microelectronics, it will always be in the on state and thus cannot be an element for bypassing harmful pulses. Furthermore, although there is also a method of integrating a capacitor on the substrate and using it as a protection element, in microelectronics with a high operating frequency, there is a problem that the crucial signal is shunted and attenuated, which hinders the normal operation of the circuit.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] In addition, Patent Document 1 discloses a method of providing Si diodes in series and in multiple stages in order to obtain a desired operating voltage. However, when a protection circuit is provided on the chip, depending on the harmful pulses applied, it may act on the bonding wire in the previous stage that reaches the chip and burn it out. Therefore, it is necessary to have a configuration that bypasses harmful pulses upstream of the bonding wire rather than providing a protection circuit on the chip. Also, the series multi-stage configuration has the drawback of increasing costs. As described above, at present, there is no semiconductor circuit that can protect semiconductor microelectronics, that is, semiconductor devices that operate at low voltages from harmful pulses. Therefore, there is a demand for a semiconductor circuit that can protect semiconductor devices operating at low voltages from harmful pulses.

[0007] The present invention has been made to solve the above problems, and an object thereof is to provide a semiconductor circuit that can protect a semiconductor device operating at a low voltage from harmful pulses.

Means for Solving the Problems

[0008] The semiconductor circuit of the present invention is provided in a semiconductor device, and has a semiconductor element including a first n-type semiconductor layer, a metal layer, and a Schottky barrier between the first n-type semiconductor layer and the metal layer, and the semiconductor circuit is forward-connected between a signal line and a ground of the semiconductor device.

[0009] The semiconductor circuit of the present invention can protect a semiconductor device operating at a low voltage from harmful pulses. Since this semiconductor circuit is provided as a semiconductor circuit rather than a configuration on a chip, harmful pulses can be bypassed on the front side of the bonding wire, so that burnout of the bonding wire can be avoided.

[0010] Further, the first n-type semiconductor layer of the semiconductor element included in the semiconductor circuit of the present invention is preferably formed having at least one oxide, nitride, or a compound thereof selected from the group consisting of Ga, In, Sn, Mg, Zn, Al, and B.

[0011] According to the semiconductor circuit of the present invention, since the first n-type semiconductor layer of the semiconductor element included in the semiconductor circuit contains a semiconductor having a larger bandgap than, for example, Si, etc., the forward turn-on voltage of the semiconductor element can be easily made higher than the operating voltage of the semiconductor device.

[0012] Further, the metal layer of the semiconductor element included in the semiconductor circuit of the present invention is preferably formed including one or more elements selected from the group consisting of Ti, Ni, Pt, W, Mo, Au, Ta, Cu, Fe, Ag, and Cr, or an alloy thereof.

[0013] According to the semiconductor circuit of the present invention, since the metal layer of the semiconductor element included in the semiconductor circuit is formed of the selected metal, the forward turn-on voltage can be adjusted by the metal. Therefore, the forward turn-on voltage can be easily set to a desired value.

[0014] In addition, the semiconductor element included in the semiconductor circuit of the present invention preferably includes a second n-type semiconductor layer having a composition different from that of the first n-type semiconductor layer and a larger bandgap than the first n-type semiconductor layer between the first n-type semiconductor layer and the metal layer.

[0015] According to the semiconductor circuit of the present invention, since the semiconductor element included in the semiconductor circuit has a second n-type semiconductor layer in addition to the first n-type semiconductor layer, it is possible to easily increase the forward turn-on voltage of the semiconductor element included in the semiconductor circuit.

[0016] In addition, at least one of the first n-type semiconductor and the second n-type semiconductor of the semiconductor element included in the semiconductor circuit of the present invention preferably contains one or more doping elements respectively selected from the group consisting of Al, Si, Mg, Zn, In, Ga, Ge, and Sn.

[0017] According to the semiconductor circuit of the present invention, since at least one of the first n-type semiconductor and the second n-type semiconductor of the semiconductor element included in the semiconductor circuit contains a doping element, the doping element contributes to adjusting the forward turn-on voltage of the semiconductor element to a desired value, and it is possible to easily make the forward turn-on voltage higher.

[0018] In addition, the forward turn-on voltage of the semiconductor element included in the semiconductor circuit of the present invention is preferably a voltage higher than the operating voltage of the semiconductor device.

[0019] According to the semiconductor circuit of the present invention, a semiconductor device operating at a low voltage can be more reliably protected from harmful pulses.

Brief Description of the Drawings

[0020]

Figure 1

Figure 2

Figure 3

Figure 4

Embodiments for Carrying Out the Invention

[0021] <Embodiment 1> Hereinafter, a semiconductor circuit 10 according to Embodiment 1 of the present invention will be described with reference to the accompanying drawings. FIG. 1 shows the semiconductor circuit 10 according to the present invention, which is configured to include a semiconductor element 1.

[0022] The semiconductor element 1 according to Embodiment 1 has a first n-type semiconductor layer, a metal layer, and a Schottky barrier between the first n-type semiconductor layer and the metal layer. The semiconductor element 1 according to Embodiment 1 is, for example, a Schottky barrier diode. When a voltage exceeding the forward rising voltage V such as a harmful pulse is applied to the semiconductor element 1, a forward bias current flows through the semiconductor element 1 and is grounded, and the semiconductor device including the semiconductor element 1 is protected from harmful pulses. The forward rising voltage V of the semiconductor element 1 is set to a value larger than the operating voltage V of the semiconductor device including the semiconductor circuit 10 including the semiconductor element 1. Therefore, the semiconductor element 1 does not bypass a signal below the forward rising voltage V, and when a harmful pulse voltage larger than the forward rising voltage V is applied, a forward bias current flows through the semiconductor element 1 and the harmful pulse is grounded. That is, the semiconductor element 1 is configured to exhibit behavior like a non-linear resistor that flows when a harmful pulse voltage is applied. f When a voltage exceeding the forward rising voltage V such as a harmful pulse is applied to the semiconductor element 1, a forward bias current flows through the semiconductor element 1 and is grounded, and the semiconductor device including the semiconductor element 1 is protected from harmful pulses. The forward rising voltage V of the semiconductor element 1 is, f is set to a value larger than the operating voltage V of the semiconductor device including the semiconductor circuit 10 including the semiconductor element 1. Therefore, the semiconductor element 1 does not bypass a signal below the forward rising voltage V, and when a harmful pulse voltage larger than the forward rising voltage V is applied, a forward bias current flows through the semiconductor element 1 and the harmful pulse is grounded. That is, the semiconductor element 1 is configured to exhibit behavior like a non-linear resistor that flows when a harmful pulse voltage is applied. a is set to a value larger than the operating voltage V of the semiconductor device including the semiconductor circuit 10 including the semiconductor element 1. Therefore, the semiconductor element 1 does not bypass a signal below the forward rising voltage V, and when a harmful pulse voltage larger than the forward rising voltage V is applied, a forward bias current flows through the semiconductor element 1 and the harmful pulse is grounded. That is, the semiconductor element 1 is configured to exhibit behavior like a non-linear resistor that flows when a harmful pulse voltage is applied. f The following signal does not bypass, and when a harmful pulse voltage larger than the forward rising voltage V is applied, a forward bias current flows through the semiconductor element 1 and the harmful pulse is grounded. That is, the semiconductor element 1 is configured to exhibit behavior like a non-linear resistor that flows when a harmful pulse voltage is applied. f The following signal does not bypass, and when a harmful pulse voltage larger than the forward rising voltage V is applied, a forward bias current flows through the semiconductor element 1 and the harmful pulse is grounded. That is, the semiconductor element 1 is configured to exhibit behavior like a non-linear resistor that flows when a harmful pulse voltage is applied.

[0023] The first n-type semiconductor layer is formed by having an oxide, a nitride, or a compound thereof containing one or more elements selected from the group consisting of Ga, In, Sn, Mg, Zn, Al, and B. For example, it is Ga2O3. The n-type semiconductor layer of the semiconductor element 1 according to the present embodiment has a forward rising voltage V fIt is preferably formed of a wide-bandgap semiconductor in order to increase [it]. Or, if the desired forward turn-on voltage V f can be obtained, the n-type semiconductor layer may be formed of any element other than the above.

[0024] The metal layer is formed to include one or more elements selected from the group consisting of Ti, Ni, Pt, W, Mo, Au, Ta, Cu, Fe, Ag, Cr, or an alloy thereof. A Schottky barrier is formed at the junction surface between the metal layer and the first n-type semiconductor layer.

[0025] Also, the first n-type semiconductor layer can contain a doping material as needed. The first n-type semiconductor layer can contain at least one of Al, Si, Mg, Zn, In, Ga, Ge, Sn as a doping material. By including an appropriate doping element in the first n-type semiconductor layer, the bandgap can be adjusted. That is, when the first n-type semiconductor layer contains a doping element, together with the elements of the n-type semiconductor contained in the first n-type semiconductor layer and the elements contained in the combined metal layer, the desired forward turn-on voltage V f can be obtained.

[0026] The forward turn-on voltage V at which a forward bias current starts to flow through the semiconductor element 1 f is set to a desired value in the range of about 2.5 V or less by the elements of the n-type semiconductor contained in the first n-type semiconductor layer and the elements contained in the combined metal layer. As shown in FIG. 1, in a desired semiconductor device, the semiconductor element 1 is connected in the forward direction between a signal line (LINE) and a ground (GND) to constitute a semiconductor circuit 10. Therefore, the semiconductor circuit 10 including the semiconductor element 1 can protect a semiconductor device having an operating voltage in the range of less than about 2.5 V from harmful pulses.

[0027] Next, a method for manufacturing the semiconductor element 1 included in the semiconductor circuit 10 will be described. First, a first n-type semiconductor layer is formed on a substrate by a known method. The substrate is formed of, for example, Si. The form of the semiconductor may be any of a single crystal, a polycrystal, an amorphous body, etc., and may be formed in a thin film or the like. As the thin film forming method, for example, mist CVD, sputtering, MO-CVD, etc. are used. In particular, mist CVD is likely to form a semiconductor layer with a uniform thickness and can contribute to adjustment in minute units such as in increments of 0.2 V to 0.3 V in order to make the forward rising voltage V f take a desired value, and is preferable. After forming the first n-type semiconductor layer, a metal layer is formed on the first n-type semiconductor layer. The metal layer is formed by a known method, and for example, film forming methods such as vapor deposition and sputtering are used.

[0028] Figure 2 is the energy band diagram of the semiconductor element 1. As an example, Figure 2 shows the energy band diagram of the semiconductor element 1 in which Ga2O3 is included in the first n-type semiconductor layer and Pt is included in the metal layer. In Figure 2, the lower broken line shown on the Ga2O3 side indicates the Fermi level of the Ga2O3 semiconductor layer, and the upper broken line indicates the conduction band level. In Figure 2, the Fermi levels of the Ga2O3 semiconductor layer and the Pt metal layer are aligned. Since a semiconductor has a forbidden band which is an energy band where there are no electron orbits at the center of the carrier distribution, the free electrons in the conduction band of the n-type semiconductor are at a higher energy level than the energy level where free electrons exist in the metal, and the valence band is at a lower energy level. When the n-type semiconductor layer and the metal layer are joined, the free electrons in the n-type semiconductor layer move to the metal layer side and decrease. As a result, the carrier distribution of the n-type semiconductor in the joined portion changes, so the position of the Fermi level changes, but the Fermi level itself does not move unless an external potential is applied. Therefore, the energy levels of the conduction band and the valence band of the n-type semiconductor in the joined portion change relative to the position of the Fermi level. In this way, a Schottky barrier is formed between the n-type semiconductor layer and the metal layer. In the present invention, the elements included in the n-type semiconductor layer and the metal layer used for the semiconductor element 1 are selected so that the Schottky barrier becomes as large as possible, and the forward rising voltage is increased. Further, by including a metal as a doping material in the n-type semiconductor layer, it is possible to contribute to easily obtaining a large forward rising voltage. In this embodiment, the band gap of Ga2O3 is 5 eV, and the Schottky barrier between Ga2O3 and Pt is 2 eV. On the other hand, regarding the capacitance of the semiconductor element 1, when the Pt electrode diameter is φ30 mm, the relative dielectric constant of Ga2O3 is 10, and the carrier density is 10 17 cm -3 , the capacitance is as low as 0.42 pF.

[0029] The operation of the semiconductor circuit 10 including the semiconductor element 1 configured as described above will be described. The semiconductor element has a forward rising voltage V f which is the operating voltage V of the semiconductor device aA semiconductor element with a slightly higher voltage is incorporated into the semiconductor circuit 10. For example, when the operating voltage V a of the semiconductor device is 1.2V, a semiconductor element 1 with a forward rising voltage V f of about 1.2V to 2.0V, which is slightly larger than 1.2V, is used. When a voltage greater than 1.2V, such as a harmful pulse, is applied to the semiconductor device, a forward bias current flows through the semiconductor element 1 and is bypassed, and the harmful pulse is grounded. Therefore, it is possible to prevent a noise current from flowing through the semiconductor device and prevent damage to an IC or the like provided in the semiconductor device due to harmful pulses.

[0030] In addition, the semiconductor element 1 included in the semiconductor circuit 10 according to the present invention is a Schottky diode. Therefore, the semiconductor circuit 10 according to the present invention has an advantage of a high response speed compared to a p-n junction diode, which is an element in which both majority carriers and minority carriers are involved. Therefore, the signal of the semiconductor device is not shunted and attenuated. In addition, since the semiconductor element 1 can be formed by a thin film technique, the semiconductor circuit 10 can be formed thinly and small, and thus can be easily formed on a substrate. In addition, since it is a thin single component, it does not disadvantageously affect securing a space for mounting upstream of the bonding wire. It is also advantageous for responsiveness in terms of low capacitance.

[0031] Therefore, according to Embodiment 1 of the present invention, it is possible to provide a semiconductor circuit capable of bypassing a harmful pulse and preventing damage to the semiconductor device even when a harmful pulse is applied to a semiconductor device having a low operating voltage.

[0032] <Embodiment 2> Hereinafter, the semiconductor circuit of Embodiment 2 according to the present invention will be described. Since the semiconductor circuit according to Embodiment 2 is the same as that of Embodiment 1, the description and illustration are omitted. The semiconductor element included in the semiconductor circuit of Embodiment 2 is different from that of Embodiment 1 only in that a second n-type semiconductor layer having a composition different from that of the first n-type semiconductor layer and a larger bandgap than the first n-type semiconductor layer is provided between the first n-type semiconductor layer and the metal layer.

[0033] The second n-type semiconductor layer has a composition different from that of the first n-type semiconductor layer and is formed having an oxide, a nitride, or a compound thereof containing one or more elements selected from the group consisting of Ga, In, Sn, Mg, Zn, Al, and B. For example, it is (Al,Ga)2O3 or the like. The n-type semiconductor layer of the semiconductor device according to Embodiment 2 is preferably formed of a wide bandgap semiconductor in order to increase the forward rising voltage V f . Alternatively, if a desired forward rising voltage V f can be obtained, the n-type semiconductor layer may be formed of any element other than those described above.

[0034] The semiconductor device according to Embodiment 2 is, for example, a Schottky barrier diode having two layers of n-type semiconductor layers. When a voltage exceeding the forward rising voltage V f such as a harmful pulse is applied to the semiconductor device, a forward bias current flows through the semiconductor device and is grounded, and the semiconductor device including the semiconductor device is protected from the harmful pulse. In the present embodiment, by providing the second n-type semiconductor layer in addition to the first n-type semiconductor layer, the bandgap can be increased. Thereby, the forward rising voltage V f of the semiconductor device can be increased.

[0035] Further, the first n-type semiconductor layer and the second n-type semiconductor layer can each contain an optimal doping material as necessary. The first n-type semiconductor layer and the second n-type semiconductor layer can each contain at least one optimal for each of Al, Si, Mg, Zn, In, Ga, Ge, and Sn as a doping material. By including appropriate doping elements in the first n-type semiconductor layer and the second n-type semiconductor layer, adjustment of the bandgap is possible. That is, by the first n-type semiconductor layer and the second n-type semiconductor layer containing a doping element, a desired forward rising voltage V f can be easily obtained by the combination of the elements of the n-type semiconductor and the elements of the metal layer contained in the first n-type semiconductor layer and the second n-type semiconductor layer.

[0036] The forward turn-on voltage V at which a forward bias current starts to flow through the semiconductor element 1 f is set to a desired value in a range greater than about 2V by the elements of the n-type semiconductor contained in the first n-type semiconductor layer, the elements of the n-type semiconductor contained in the second n-type semiconductor layer, and the elements contained in the combined metal layer. The semiconductor circuit including the semiconductor element of the present embodiment can protect a semiconductor device having an operating voltage V of about 2V or higher from harmful pulses. a

[0037] FIG. 3 is an energy band diagram of the semiconductor device according to Embodiment 2. As an example, FIG. 3 shows an energy band diagram of a semiconductor device in which Ga2O3 is included in the first n-type semiconductor layer, (Al,Ga)2O3 is included in the second n-type semiconductor layer, and Pt is included in the metal layer. In FIG. 3, the lower broken line shown on the n-type semiconductor side indicates the Fermi level of the semiconductor layers of Ga2O3 and (Al,Ga)2O3, and the upper broken line indicates the conduction band level. In FIG. 3, the Fermi levels of the Ga2O3 semiconductor layer and the Pt metal layer are aligned. In FIG. 2, the Fermi levels of the n-type semiconductor layer and the Pt metal layer are aligned. Since a semiconductor has a forbidden band, which is an energy band where there are no electron orbits at the center of the carrier distribution, the free electrons in the conduction band of the n-type semiconductor are at a higher energy level than the energy level where free electrons exist in the metal, and the valence band is at a lower energy level. When the n-type semiconductor layer and the metal layer are joined, the free electrons in the n-type semiconductor layer move to the metal layer side and decrease. As a result, the carrier distribution of the n-type semiconductor at the junction changes, so the position of the Fermi level changes. However, since the Fermi level itself does not move unless an external potential is applied, the energy levels of the conduction band and the valence band of the n-type semiconductor at the junction change relative to the position of the Fermi level. In this way, a Schottky barrier is formed between the n-type semiconductor layer and the metal layer. The semiconductor device of Embodiment 2 includes a second n-type semiconductor layer between the first n-type semiconductor layer and the metal layer. Therefore, compared with the semiconductor device 1 of Embodiment 1, the conduction band level of the semiconductor layer is higher. Also, similar to Embodiment 1, including a metal as a doping material in the n-type semiconductor layer can contribute to easily obtaining a large forward rising voltage. In this embodiment, by inserting (Al,Ga)2O3, which has a larger bandgap than Ga2O3, between Ga2O3 and Pt, an energy difference of 3 eV in the conduction band and 0.2 eV in the valence band is generated, and it is considered that a larger barrier height can be obtained than in Example 1. Thus, by having the second n-type semiconductor layer in addition to the first n-type semiconductor layer, the barrier height can be increased. With this configuration, the forward rising voltage V fIt can be a value 1 V larger than the case of only Ga2O3. On the other hand, regarding the capacitance of this semiconductor device, for a Pt electrode diameter of φ30 mm, a relative permittivity of Ga2O3 of 10, and a carrier density of 10 17 cm -3 the capacitance is as low as 0.38 pF.

[0038] The operation of a semiconductor circuit including the semiconductor device configured as described above will be described. The semiconductor device incorporates a semiconductor device in which the forward rising voltage V f is set slightly larger than the operating voltage V a of the semiconductor device. For example, when the operating voltage V a of the semiconductor device is 3 V, a semiconductor device with a forward rising voltage V f slightly larger than 3 V, about 3.2 V to 4 V, is used. When a voltage greater than 3 V, such as a harmful pulse, is applied to the semiconductor device, a forward bias current flows through the semiconductor device and is bypassed, and the harmful pulse is grounded.

[0039] Therefore, according to the second embodiment of the present invention, even when a harmful pulse is applied to a semiconductor device with a low operating voltage and slightly higher than that of the first embodiment, it is possible to provide a semiconductor circuit capable of bypassing the harmful pulse and preventing damage to the semiconductor device.

[0040] <Embodiment 3> Hereinafter, a semiconductor circuit according to Embodiment 3 of the present invention will be described. The semiconductor device according to Embodiment 3 is the same as the semiconductor device 1 according to Embodiment 1. The semiconductor circuit 20 according to Embodiment 3 is different from the semiconductor circuit 10 according to Embodiment 1 in that the semiconductor device 1 is connected to the semiconductor device in parallel and with reverse characteristics.

[0041] The semiconductor circuit 10 of Embodiment 1 connects the semiconductor element 1 in the forward direction in the semiconductor device to bypass the harmful pulses input from the signal line (LINE). However, harmful pulses may enter not only from the signal line (LINE) but also from the ground (GND). Therefore, the semiconductor circuit 20 of Embodiment 3 is configured as a semiconductor circuit 20 in which one semiconductor element 1 is connected in the forward direction in the semiconductor device and another semiconductor element 1 is connected in the reverse direction. Therefore, the semiconductor circuit 20 can bypass the harmful pulses entering from either the signal line (LINE) or the ground (GND). When harmful pulses enter the ground (GND) of the semiconductor device, the harmful pulses pass through the semiconductor element 1 connected in the reverse direction of the semiconductor circuit 20 and the signal line (LINE), and are bypassed to the ground (GND) by the semiconductor element 1 connected in the forward direction of the semiconductor circuit 20.

[0042] Therefore, according to Embodiment 3 of the present invention, even when a harmful pulse is applied to either the signal line (LINE) or the ground (GND), it is possible to provide a semiconductor circuit that can bypass the harmful pulse and prevent damage to the semiconductor device. Note that both or either one of the semiconductor elements of Embodiment 3 may be a semiconductor element of Embodiment 2, which includes a first n-type semiconductor layer, a metal layer, and a second n-type semiconductor layer having a composition different from that of the first n-type semiconductor layer and a larger bandgap than the first n-type semiconductor layer, between the first n-type semiconductor layer and the metal layer, instead of the semiconductor element 1 of Embodiment 1. Also, the forward rise voltage of the semiconductor element 1 can be set to an optimum value according to the operating voltage of the semiconductor device including the semiconductor circuit 20, etc., in the same manner as in Embodiments 1 and 2.

Description of Reference Numerals

[0043] 1 Semiconductor element 10, 20 Semiconductor circuit

Claims

1. A semiconductor circuit provided in a semiconductor device, wherein the semiconductor circuit has a semiconductor element including a first n-type semiconductor layer, a metal layer, and a Schottky barrier between the first n-type semiconductor layer and the metal layer, the semiconductor element is forward-connected between a signal line and ground of the semiconductor device, and the semiconductor element includes a second n-type semiconductor layer between the first n-type semiconductor layer and the metal layer, the second n-type semiconductor layer having a composition different from that of the first n-type semiconductor layer and a larger bandgap than the first n-type semiconductor layer. A semiconductor circuit.

2. The semiconductor circuit according to claim 1, wherein the first n-type semiconductor layer is formed of an oxide, a nitride, or a compound thereof containing at least one selected from the group consisting of Ga, In, Sn, Mg, Zn, Al, and B.

3. The semiconductor circuit according to claim 1 or 2, wherein the metal layer is formed of one or more elements selected from the group consisting of Ti, Ni, Pt, W, Mo, Au, Ta, Cu, Fe, Ag, and Cr, or an alloy thereof.

4. The semiconductor circuit according to any one of claims 1 to 3, wherein at least one of the first n-type semiconductor layer and the second n-type semiconductor layer contains one or more doping elements respectively selected from the group consisting of Al, Si, Mg, Zn, In, Ga, Ge, and Sn.

5. The semiconductor circuit according to any one of claims 1 to 4, wherein the forward turn-on voltage of the semiconductor element is a voltage higher than the operating voltage of the semiconductor device.

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