Semiconductor device

Abstract

To provide a semiconductor device capable of improving reliability.SOLUTION: A semiconductor device comprises a semiconductor part, a first electrode, a second electrode, and a control electrode. The semiconductor part is provided between the first and second electrodes and includes: first and third layers of a first conductivity type; and second, fourth and fifth layers of a second conductivity type. The first layer extends between the first and second electrodes. The second layer is provided between the first semiconductor layer and the second electrode. The third semiconductor layer is provided between the second layer and the second electrode. The fourth layer is provided between the first layer and the first electrode. The semiconductor part has: an active region including the control electrode, the second layer, and the third layer; and a termination region surrounding the active region. The fifth layer is provided in the first semiconductor layer, in the termination region.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The embodiment relates to a semiconductor device.

Background Art

[0002] Semiconductor devices used in power converters and the like are required to have high reliability. For example, it is important to have a large breakdown tolerance against high voltage and high current.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The embodiment provides a semiconductor device with improved reliability.

Means for Solving the Problems

[0005] The semiconductor device according to the embodiment includes a semiconductor portion, a first electrode, a second electrode, and a control electrode. The semiconductor portion includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, a fourth semiconductor layer of the second conductivity type, and a fifth semiconductor layer of the second conductivity type. The first electrode is provided on the back surface of the semiconductor portion, and the second electrode is provided on the front surface of the semiconductor portion. The first semiconductor layer extends between the first electrode and the second electrode, and the second semiconductor layer is provided between the first semiconductor layer and the second electrode. The third semiconductor layer is partially provided between the second semiconductor layer and the second electrode. The fourth semiconductor layer is provided between the first semiconductor layer and the first electrode. The control electrode is disposed inside a trench provided in the semiconductor portion, is located between the semiconductor portion and the second electrode, is electrically insulated from the semiconductor portion by a first insulating film, and is electrically insulated from the second electrode by a second insulating film. Further, the control electrode extends from the front surface side of the semiconductor portion into the first semiconductor layer, the second semiconductor layer faces the control electrode via the first insulating film, and the third semiconductor layer is configured to be in contact with the first insulating film. Furthermore, the semiconductor portion includes an active region including the control electrode, the second semiconductor layer, and the third semiconductor layer, and a termination region surrounding the active region. The fifth semiconductor layer is provided in the first semiconductor layer in the termination region and extends in a first direction along the boundary between the first semiconductor layer and the fourth semiconductor layer. In a second direction from the first electrode toward the second electrode, a first distance from the fifth semiconductor layer to the front surface of the semiconductor portion is longer than a second distance from the fifth semiconductor layer to the back surface of the semiconductor portion.

Brief Description of the Drawings

[0006]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Mode for Carrying Out the Invention

[0007] Hereinafter, embodiments will be described with reference to the drawings. The same parts in the drawings are denoted by the same reference numerals, and detailed descriptions thereof are appropriately omitted, and different parts will be described. Note that the drawings are schematic or conceptual, and the relationships between the thickness and width of each part, the ratio of the sizes between parts, etc. are not necessarily the same as those in reality. Also, even when representing the same part, the dimensions and ratios may be represented differently depending on the drawings.

[0008] Furthermore, the arrangement and configuration of each part will be described using the X-axis, Y-axis, and Z-axis shown in each figure. The X-axis, Y-axis, and Z-axis are mutually orthogonal and represent the X direction (first direction), Y direction, and Z direction (second direction), respectively. Also, there are cases where the Z direction is described as upward and the opposite direction as downward.

[0009] The impurity concentration of the semiconductor layer described in the embodiment can be measured, for example, by TOF-SIMS (Time of Flight-Secondary Ion Mass Spectrometry). Also, the relative high or low of the impurity concentration can be determined, for example, from the high or low of the carrier concentration obtained by SCM (Scanning Capacitance Microscopy). Also, distances such as the depth and thickness of the impurity region can be obtained, for example, by TOF-SIMS. Also, distances such as the depth, thickness, width, and interval of the impurity region can be obtained, for example, from a composite image of an SCM image and an AFM image (Atomic Force Microscope image).

[0010] FIGS. 1 and 2 are schematic cross-sectional views showing a semiconductor device 1 according to an embodiment. The semiconductor device 1 is an IGBT (Insulated Gate Bipolar Transistor). The semiconductor device 1 includes an active region AR and a termination region TR. FIG. 1 is a cross-sectional view showing the structure of the active region AR. FIG. 2 is a cross-sectional view showing the structure of the termination region TR.

[0011] As shown in FIG. 1, the semiconductor device 1 includes a semiconductor part 10, a first electrode 20, a second electrode 30, and a control electrode 40. The first electrode 20 is provided on the back surface 10B of the semiconductor part 10. The second electrode 30 is provided on the front surface 10F of the semiconductor part 10. The semiconductor part 10 is, for example, silicon. The first electrode 20 is, for example, a collector electrode. The second electrode 30 is, for example, an emitter electrode.

[0012] The control electrode 40 is disposed inside a trench TG1 provided on the front surface side of the semiconductor part 10. The control electrode 40 is provided between the semiconductor part 10 and the second electrode 30. The control electrode 40 is electrically insulated from the semiconductor part 10 by a first insulating film 43. Also, the control electrode 40 is electrically insulated from the second electrode 30 by a second insulating film 45. The first insulating film 43 is, for example, a gate insulating film. The second insulating film 45 is, for example, an interlayer insulating film. The first insulating film 43 and the second insulating film 45 are, for example, silicon oxide films.

[0013] As shown in FIG. 1, the semiconductor portion 10 includes, for example, a first semiconductor layer 11 of a first conductivity type, a second semiconductor layer 13 of a second conductivity type, a third semiconductor layer 15 of the first conductivity type, and a fourth semiconductor layer 17 of the second conductivity type. Hereinafter, the first conductivity type will be described as n-type and the second conductivity type will be described as p-type.

[0014] The first semiconductor layer 11 extends between the first electrode 20 and the second electrode 30. The first semiconductor layer 11 is, for example, an n-type base layer. The control electrode 40 extends into the first semiconductor layer 11 from the surface side of the semiconductor portion 10.

[0015] The second semiconductor layer 13 is provided between the first semiconductor layer 11 and the second electrode 30. The second semiconductor layer 13 is, for example, a p-type base layer. The second semiconductor layer 13 is provided so as to face the control electrode 40 via the first insulating film 43.

[0016] The third semiconductor layer 15 is partially provided between the second semiconductor layer 13 and the second electrode 30. The third semiconductor layer 15 is, for example, an n-type emitter layer. The third semiconductor layer 15 is provided so as to be in contact with the first insulating film 43. The second electrode 30 is electrically connected to the second semiconductor layer 13 and the third semiconductor layer 15.

[0017] The fourth semiconductor layer 17 is provided between the first semiconductor layer 11 and the first electrode 20. The fourth semiconductor layer 17 is, for example, a p-type collector layer. The first electrode 20 is electrically connected to the fourth semiconductor layer 17.

[0018] As shown in FIG. 2, the semiconductor portion 10 further includes a fifth semiconductor layer 19 of the second conductivity type, a sixth semiconductor layer 21 of the second conductivity type, a seventh semiconductor layer 23 of the first conductivity type, an eighth semiconductor layer 25 of the first conductivity type, and ninth semiconductor layers 27a and 27b of the second conductivity type.

[0019] The sixth semiconductor layer 21 is provided on the surface side of the semiconductor part 10 and is located at the boundary between the active region AR and the termination region TR. The sixth semiconductor layer 21 is provided between the first semiconductor layer 11 and the second electrode 30 in the direction from the first electrode 20 to the second electrode 30, for example, the Z direction. The sixth semiconductor layer 21 is, for example, a p-type guard ring. The sixth semiconductor layer 21 is provided so as to be connected to the second semiconductor layer 13.

[0020] The fifth semiconductor layer 19 is provided in the first semiconductor layer 11 in the termination region TR. The fifth semiconductor layer 19 is provided in a plate shape extending in a direction along the back surface 10B of the semiconductor part 10, for example, the X direction. Here, the “plate shape” means, for example, a shape extending in the X direction and the Y direction and having a thickness in the Z direction thinner than the lengths in the X direction and the Y direction.

[0021] The fifth semiconductor layer 19 is provided such that, for example, in the Z direction, a first distance D1 from the fifth semiconductor layer 19 to the surface 10F of the semiconductor part 10 is longer than a second distance D2 from the fifth semiconductor layer 19 to the back surface 10B of the semiconductor part 10. Also, the fifth semiconductor layer 19 is provided at a position separated from the fourth semiconductor layer 17 of the second conductivity type and is provided to have a floating potential in the first semiconductor layer 11 of the first conductivity type.

[0022] The seventh semiconductor layer 23 is provided between the first semiconductor layer 11 and the fourth semiconductor layer 17. The seventh semiconductor layer 23 is, for example, an n-type buffer layer. The seventh semiconductor layer 23 contains a first conductivity type impurity with a higher concentration than the concentration of the first conductivity type impurity in the first semiconductor layer 11 and is electrically connected to the first semiconductor layer 11. The fifth semiconductor layer 19 is provided at a position separated from the seventh semiconductor layer 23.

[0023] In the above example, the fourth semiconductor layer 17 is provided to extend from the active region AR to the termination region TR, but the embodiment is not limited thereto. For example, the fourth semiconductor layer 17 may not extend into the termination region TR, and the seventh semiconductor layer 23 may be connected to the first electrode 20 in the termination region TR.

[0024] The eighth semiconductor layer 25 is provided at a position spaced apart from the sixth semiconductor layer 21 on the surface side of the semiconductor portion 10. The eighth semiconductor layer 25 is a so-called EQPR (Equivalent Potential Ring) layer. The eighth semiconductor layer 25 contains a first conductivity type impurity at a concentration higher than the concentration of the first conductivity type impurity in the first semiconductor layer 11 and is electrically connected to the first semiconductor layer 11.

[0025] The ninth semiconductor layers 27a and 27b are provided between the sixth semiconductor layer 21 and the eighth semiconductor layer 25 on the surface side of the semiconductor portion 10. The ninth semiconductor layers 27a and 27b are, for example, p-type guard rings. The ninth semiconductor layers 27a and 27b are spaced apart from each other and are provided at positions spaced apart from the sixth semiconductor layer 21 and the eighth semiconductor layer 25. The ninth semiconductor layer 27a is provided between the sixth semiconductor layer 21 and the ninth semiconductor layer 27b. The ninth semiconductor layers 27a and 27b are not limited to this example. For example, a configuration in which three or more ninth semiconductor layers are provided may be used.

[0026] The first semiconductor layer 11 includes portions located between the fifth semiconductor layer 19 and the ninth semiconductor layer 27a and between the fifth semiconductor layer 19 and the ninth semiconductor layer 27b. Further, the first semiconductor layer 11 includes portions located between the ninth semiconductor layers 27a and 27b, between the sixth semiconductor layer 21 and the ninth semiconductor layer 27a, and between the eighth semiconductor layer 25 and the ninth semiconductor layer 27b, respectively.

[0027] The semiconductor device 1 further includes a third electrode 35, a fourth electrode 37a, a fourth electrode 37b, and a fifth electrode 50. The third electrode 35, the fourth electrodes 37a and 37b are provided on the semiconductor portion 10 through, for example, the second insulating film 45 in the termination region TR. The second insulating film 45 extends from the active region AR to the termination region TR along the surface 10F of the semiconductor portion 10. The embodiment is not limited to this example. For example, the surface of the termination region TR may be covered with an interlayer insulating film different from the second insulating film 45. Also, another interlayer insulating film may be provided on the second insulating film 45. Further, three or more fourth electrodes 37 may be provided according to the number of the ninth semiconductor layers 27.

[0028] The third electrode 35 is provided on the eighth semiconductor layer 25. The third electrode 35 is, for example, an EQPR electrode. The third electrode 35 is electrically connected to the eighth semiconductor layer 25.

[0029] The fourth electrodes 37a and 37b are provided between the second electrode 30 and the third electrode 35. The fourth electrodes 37a and 37b are spaced apart from each other and are provided spaced apart from the second electrode 30 and the third electrode 35. The fourth electrodes 37a and 37b are, for example, field plate electrodes.

[0030] The fourth electrode 37a is provided on the ninth semiconductor layer 27a. The fourth electrode 37b is provided on the ninth semiconductor layer 27b. The fourth electrodes 37a and 37b are electrically connected to the ninth semiconductor layers 27a and 27b, respectively, for example, via contact holes provided in the second insulating film 45.

[0031] The fifth electrode 50 is provided between the semiconductor part 10 and the second electrode 30. The fifth electrode 50 is disposed inside a trench TG2 provided on the surface side of the semiconductor part 10 and is electrically insulated from the semiconductor part 10 by a third insulating film 53. The third insulating film 53 is, for example, a silicon oxide film. The fifth electrode 50 extends, for example, into the sixth semiconductor layer 21 and is electrically connected to the second electrode 30. Note that the fifth electrode 50 may be provided so as to extend into the ninth semiconductor layers 27a and 27b.

[0032] FIG. 3 is a schematic plan view showing the semiconductor device 1 according to the embodiment. FIG. 3 is a plan view showing the surface 10F of the semiconductor part 10.

[0033] As shown in FIG. 3, the terminal region TR is provided so as to surround the active region AR. The active region AR includes a second semiconductor layer 13, a third semiconductor layer 15, and a control electrode 40. The terminal region TR includes a fifth semiconductor layer 19, a sixth semiconductor layer 21, an eighth semiconductor layer 25, and ninth semiconductor layers 27a and 27b (see FIG. 2). As shown in FIG. 3, the fifth semiconductor layer 19, the sixth semiconductor layer 21, the eighth semiconductor layer 25, and the ninth semiconductor layers 27a and 27b extend in the X direction or the Y direction.

[0034] The sixth semiconductor layer 21 is provided so as to surround the active region AR along the boundary between the active region AR and the terminal region TR. The ninth semiconductor layers 27a and 27b are each provided so as to surround the sixth semiconductor layer 21 and surround the active region AR outside the sixth semiconductor layer 21.

[0035] The fifth semiconductor layer 19 is provided so as to surround the active region AR between the sixth semiconductor layer 21 and the eighth semiconductor layer 25. The fifth semiconductor layer 19 is provided so as to be separated from the sixth semiconductor layer 21 and the eighth semiconductor layer 25 in a plan view parallel to the surface 10F of the semiconductor portion 10. In the plan view of the semiconductor portion 10, the fifth semiconductor layer 19 is provided to be, for example, 5 micrometers (μm) away from the eighth semiconductor layer 25.

[0036] Note that FIG. 3 is an example, and the fifth semiconductor layer 19 is not necessarily limited to the above form. The fifth semiconductor layer 19 does not necessarily need to be, for example, a single annular pattern surrounding the active region AR, and may be divided into a plurality of parts. Also, the width of the fifth semiconductor layer 19 does not need to be uniform, and may be formed wider than other parts at the corner portion of the active region AR.

[0037] FIG. 4 is a schematic diagram showing the structure of the semiconductor device according to the embodiment. FIG. 4 shows an example of the impurity concentration profile in the Z direction of the semiconductor portion 10. FIG. 4 shows the concentration distribution of the first-conductivity-type impurities in the first semiconductor layer 11 and the seventh semiconductor layer 23. Also, FIG. 4 shows the concentration distribution of the second-conductivity-type impurities in the fourth semiconductor layer 17 and the fifth semiconductor layer 19.

[0038] As shown in FIG. 4, the peak concentration of the second conductivity type impurities in the fifth semiconductor layer 19 is higher than the concentration of the first conductivity type impurities in the first semiconductor layer 11. Also, the peak concentration of the second conductivity type impurities in the fifth semiconductor layer 19 is lower than the concentration of the second conductivity type impurities in the fourth semiconductor layer 17.

[0039] The concentration of the first conductivity type impurities in the first semiconductor layer 11 is, for example, in the concentration range of 1×10 12 ~1×10 14 cm -3 . The concentration of the second conductivity type impurities in the fourth semiconductor layer 17 is, for example, 1×10 19 cm -3 . The concentration of the second conductivity type impurities in the fifth semiconductor layer 19 is, for example, 1×10 16 cm -3 . The concentration of the first conductivity type impurities in the seventh semiconductor layer 23 is, for example, 1×10 17 ~1×10 18 cm -3 .

[0040] Also, the peak concentration of the second conductivity type impurities in the fifth semiconductor layer 19 is lower than the concentration of the second conductivity type impurities (not shown) in the ninth semiconductor layers 27a and 27b. The concentration of the second conductivity type impurities in the ninth semiconductor layers 27a and 27b is, for example, 1×10 19 cm -3 . The reason why the peak concentration of the second conductivity type impurities in the fifth semiconductor layer 19 is lower than the concentration of the second conductivity type impurities in the fourth semiconductor layer 17 and the concentration of the second conductivity type impurities in the ninth semiconductor layers 27a and 27b is that when the semiconductor device 1 described later transitions from the on state to the off state, the fifth semiconductor layer 19 is depleted so that the fourth semiconductor layer 17 and the ninth semiconductor layers 27a and 27b are not depleted.

[0041] The first distance D1 in the Z direction from the fifth semiconductor layer 19 to the surface 10F of the semiconductor part 10 is the distance from the position of the concentration peak of the second conductivity type impurity in the fifth semiconductor layer 19 to the surface 10F of the semiconductor part 10. Also, the second distance D2 in the Z direction from the fifth semiconductor layer 19 to the back surface 10B of the semiconductor part 10 is the distance from the position of the concentration peak of the second conductivity type impurity in the fifth semiconductor layer 19 to the back surface 10B of the semiconductor part 10.

[0042] The thickness of the semiconductor part 10 in the Z direction, that is, the distance from the back surface 10B to the surface 10F of the semiconductor part 10 is, for example, 50 μm or more and 500 μm or less. The thickness of the fourth semiconductor layer 17 in the Z direction is, for example, 0.2 μm. The thickness of the seventh semiconductor layer 23 in the Z direction is, for example, 1 μm. The distance in the Z direction between the fifth semiconductor layer 19 and the seventh semiconductor layer 23 is, for example, 7 μm. Also, the thickness of the fifth semiconductor layer 19 in the Z direction is, for example, 4 μm. That is, the second distance D2 is, for example, 10 μm.

[0043] Next, with reference to FIGS. 5(a) to 5(d), a method for manufacturing the semiconductor device 1 will be described. FIGS. 5(a) to 5(d) are schematic cross-sectional views showing the manufacturing process of the semiconductor device 1 according to the embodiment.

[0044] As shown in FIG. 5(a), on the surface side of the semiconductor part 10, a second semiconductor layer 13, a sixth semiconductor layer 21, an eighth semiconductor layer 25, a ninth semiconductor layer 27a, a ninth semiconductor layer 27b, a control electrode 40, and a fifth electrode 50 are formed. The semiconductor part 10 is, for example, an n-type silicon wafer.

[0045] After forming trenches TG1 and TG2 on the surface side of the semiconductor part 10, a first insulating film 43 (see FIG. 1) and a third insulating film 53 that cover the inner surfaces thereof are formed. The first insulating film 43 and the third insulating film 53 are, for example, silicon oxide films formed by thermally oxidizing the semiconductor part 10. Subsequently, the control electrode 40 and the fifth electrode 50 are formed inside the trenches TG1 and TG2. The control electrode 40 and the fifth electrode 50 are, for example, conductive polysilicon.

[0046] Furthermore, by ion-implanting a second conductivity type impurity, such as boron (B), on the surface side of the semiconductor portion 10, a second semiconductor layer 13, a sixth semiconductor layer 21, and ninth semiconductor layers 27a and 27b are formed. The second semiconductor layer 13, the sixth semiconductor layer 21, and the ninth semiconductor layers 27a and 27b are formed by activating and diffusing the ion-implanted first conductivity type impurity by heat treatment.

[0047] Subsequently, by ion-implanting a first conductivity type impurity, such as phosphorus (P), on the surface side of the semiconductor portion 10, a third semiconductor layer 15 (see FIG. 1) and an eighth semiconductor layer 25 are formed. The third semiconductor layer 15 and the eighth semiconductor layer 25 are formed by activating the ion-implanted first conductivity type impurity by heat treatment.

[0048] Furthermore, a second insulating film 45 is formed on the surface 10F of the semiconductor portion 10. The second insulating film 45 is, for example, a silicon oxide film formed using CVD (Chemical Vapor Deposition). Contact holes communicating with the fifth electrode 50 and the ninth semiconductor layers 27a and 27b are formed in the second insulating film 45. Subsequently, the semiconductor portion 10 is thinned to a predetermined thickness by, for example, etching or polishing.

[0049] As shown in FIG. 5(b), on the back surface side of the semiconductor portion 10, a first conductivity type impurity, such as boron (B), is partially ion-implanted. The first conductivity type impurity is ion-implanted to a predetermined depth in the termination region TR. For example, boron ions B 2+ are ion-implanted with an acceleration energy of 5 MeV.

[0050] Furthermore, a second conductivity type impurity, such as boron (B), and a first conductivity type impurity, such as phosphorus (P), which will become the fourth semiconductor layer 17 and the seventh semiconductor layer 23, are ion-implanted on the back surface side of the semiconductor portion 10. Subsequently, the ion-implanted impurities are activated by heat treatment at, for example, 1000° C. or lower, and as shown in FIG. 5(c), the fourth semiconductor layer 17, the fifth semiconductor layer 19, and the seventh semiconductor layer 23 are formed.

[0051] As shown in FIG. 5(d), a first electrode 20 is formed on the back surface of the semiconductor portion 10. The first electrode 20 is, for example, a metal layer containing titanium (Ti) and aluminum (Al). Further, a second electrode 30, a third electrode 35, and fourth electrodes 37a and 37b are formed on the surface side of the semiconductor portion 10. The second electrode 30, the third electrode 35, and the fourth electrodes 37a and 37b are, for example, metal layers containing titanium nitride (TiN), tungsten (W), and aluminum (Al). Further, a resin layer 39 is formed on the surface side of the terminal region TR of the semiconductor portion 10. The resin layer 39 is provided so as to cover the fourth electrodes 37a and 37b. The resin layer 39 is, for example, a polyimide resin.

[0052] The semiconductor device 1 operates by applying a predetermined voltage (collector voltage) between the first electrode 20 and the second electrode 30 and applying a control voltage (gate voltage) between the second electrode 30 and the control electrode 40.

[0053] For example, when the control voltage is higher than the threshold value of the control electrode 40, an inversion layer of the first conductivity type is induced at the interface between the second semiconductor layer 13 and the first insulating film 43. As a result, first conductivity type carriers (electrons) are injected from the second electrode 30 into the first semiconductor layer 11 through the third semiconductor layer 15 and the inversion layer. Correspondingly, second conductivity type carriers (holes) are injected from the fourth semiconductor layer 17 into the first semiconductor layer 11 through the seventh semiconductor layer 23.

[0054] The first conductivity type carriers are discharged from the first semiconductor layer 11 to the first electrode 20 through the seventh semiconductor layer 23 and the fourth semiconductor layer 17. Also, the second conductivity type carriers are discharged from the first semiconductor layer 11 to the second electrode 30 through the second semiconductor layer 13. As a result, an on state is achieved in which a current (collector current) flows between the first electrode 20 and the second electrode 30.

[0055] On the other hand, when the control voltage becomes lower than the threshold value of the control electrode 40, the inversion layer induced between the second semiconductor layer 13 and the first insulating film 43 disappears. For this reason, the injection of the first-conductivity-type carriers from the second electrode 30 into the first semiconductor layer 11 stops, and the injection of the second-conductivity-type carriers from the first electrode 20 into the first semiconductor layer 11 also stops. Thereafter, the discharge of the first-conductivity-type carriers from the first semiconductor layer 11 to the first electrode 20 and the discharge of the second-conductivity-type carriers from the first semiconductor layer 11 to the second electrode 30 continue, and the first semiconductor layer 11 is depleted. As a result, the semiconductor device 1 reaches the off state. Hereinafter, the characteristics after the semiconductor device 1 shifts (turns off) from the on state to the off state will be described.

[0056] FIG. 6 is a schematic diagram showing the characteristics of the semiconductor device 1 according to the embodiment. FIG. 6 shows the electric field distribution in the vicinity of the surface 10F side of the termination region TR when the semiconductor device 1 is turned off.

[0057] As shown in FIG. 6, the electric field distribution in the termination region TR has peaks at the outer edge 21e of the sixth semiconductor layer 21, the outer edge 27ae of the ninth semiconductor layer 27a, and the outer edge 27be of the ninth semiconductor layer 27b, respectively.

[0058] In this way, by providing the ninth semiconductor layers 27a and 27b so as to surround the active region AR, the electric field in the termination region TR can be extended in the lateral direction. Thereby, the electric field concentration at the outer edge 21e of the sixth semiconductor layer 21 connected to the active region AR can be alleviated, and the breakdown voltage of the termination region TR can be increased.

[0059] Furthermore, by providing the fifth semiconductor layer 19 in the first semiconductor layer 11, the electric field strength at the outer edge 27ae of the ninth semiconductor layer 27a is made higher than the electric field strength at the outer edge 21e of the sixth semiconductor layer 21 and the electric field strength at the outer edge 27be of the ninth semiconductor layer 27b.

[0060] Figs. 7(a) and (b) are schematic cross-sectional views showing the characteristics of the semiconductor device 1 according to the embodiment. Fig. 7(a) shows the path of the electron current Ie at the time of avalanche breakdown of the semiconductor device 2 according to the comparative example. In the termination region of the semiconductor device 2, the fifth semiconductor layer 19 is not provided. Fig. 7(b) shows the path of the electron current Ie at the time of avalanche breakdown of the semiconductor device 1.

[0061] When the voltage Vce applied between the first electrode 20 and the second electrode 30 is increased at the turn-off of the semiconductor devices 1 and 2, for example, avalanche breakdown occurs in the termination region TR. Avalanche breakdown occurs in a portion where the electric field strength in the termination region TR is high. As shown in Fig. 6, if the electric field strength at the outer edge 27ae of the ninth semiconductor layer 27a is higher than that of other portions, avalanche breakdown occurs at the outer edge 27ae of the ninth semiconductor layer 27a. In other words, the outer edge 27ae of the ninth semiconductor layer 27a becomes the breakdown point.

[0062] In the semiconductor device 2 shown in Fig. 7(a), the electron current Ie generated by avalanche breakdown flows from the outer edge 27ae of the ninth semiconductor layer 27a through the seventh semiconductor layer 23 and the fourth semiconductor layer 17 to the first electrode 20.

[0063] In the semiconductor device 1 shown in Fig. 7(b), the electron current Ie flows in the direction of the eighth semiconductor layer 25, avoiding the fifth semiconductor layer 19. For this reason, the path of the electron current Ie becomes longer and the electrical resistance becomes larger.

[0064] Figs. 8(a) and (b) are another schematic cross-sectional views showing the characteristics of the semiconductor device 1 according to the embodiment. Fig. 8(a) shows the path of the electron current Ie at the time of avalanche breakdown of the semiconductor device 2 according to the comparative example. Fig. 8(b) shows the path of the electron current Ie at the time of avalanche breakdown of the semiconductor device 1.

[0065] In Figs. 8(a) and (b), the current density in the first semiconductor layer 11 is represented. The shade of the color in the display indicates the magnitude relationship of the current density. As indicated by the arrows in the figure, the electron current Ie flows along the region with a high current density.

[0066] FIG. 9 is a schematic cross-sectional view showing the characteristics of semiconductor devices 1 and 2 according to the embodiment. FIG. 9 is a graph showing the voltage-current characteristics at turn-off. The horizontal axis represents the voltage Vce applied between the first electrode 20 and the second electrode 30. The vertical axis represents the current Ice flowing between the first electrode 20 and the second electrode 30. "EB" in FIG. 9 represents the characteristics of the semiconductor device 1, and "CE" represents the characteristics of the semiconductor device 2.

[0067] As shown in FIG. 9, in the semiconductor device 2, when the voltage Vce is increased and reaches the breakdown voltage VB1, avalanche breakdown occurs. At this time, while the current Ice flows, the density of space charges (electrons and holes) in the first semiconductor layer 11 increases. Therefore, the resistance of the current path in the first semiconductor layer 11 becomes small, and the voltage Vce decreases, that is, so-called snap-back occurs. When snap-back occurs, the increase in the current Ice is accelerated, and element breakdown due to overcurrent may occur.

[0068] In the semiconductor device 1, avalanche breakdown occurs when the voltage Vce reaches the breakdown voltage VB2. Further, as the voltage Vce increases, the current Ice also gradually increases. When the current Ice reaches Isn a p, the decrease in the voltage Vce starts and snap-back occurs.

[0069] In the semiconductor device 1, the path of the electron current Ie is long and its electrical resistance is large. Therefore, the voltage Vce does not decrease immediately after avalanche breakdown is started, and when the current Ice reaches Isn a p level, snap-back occurs. That is, the electrical resistance in the path of the electron current Ie acts as a so-called ballast resistance and can suppress the accelerated increase in the current Ice. Thus, in the semiconductor device 1, the breakdown voltage VB is lower than that of the semiconductor device 2, but snap-back can be suppressed. In other words, in the semiconductor device 1, the breakover tolerance can be improved.

[0070] FIG. 10 is a graph showing another characteristic of the semiconductor device 1 according to the embodiment. FIG. 10 is a graph showing the relationship between the concentration of the second conductivity type impurity in the fifth semiconductor layer 19 and the breakdown voltage VB. The horizontal axis represents the impurity concentration in the fifth semiconductor layer 19. The vertical axis represents the breakdown voltage VB.

[0071] The three graphs in FIG. 10 are shown with the second distance D2 from the back surface 10B of the semiconductor portion 10 to the fifth semiconductor layer 19 as a parameter. For example, when the second distance D2 is 5 μm and 10 μm, the impurity concentration of the fifth semiconductor layer 19 is 5×10 15 cm -3 In the following region, the breakdown voltage VB is substantially constant. When the impurity concentration of the fifth semiconductor layer 19 exceeds 5×10 15 cm -3 the breakdown voltage VB decreases. In other words, when the impurity concentration of the fifth semiconductor layer 19 exceeds 5×10 15 cm -3 the electron current Ie starts to flow around the fifth semiconductor layer 19, making it possible to improve the breakdown tolerance.

[0072] On the other hand, when D2 is 30 μm, the breakdown voltage VB increases as the impurity concentration of the fifth semiconductor layer 19 increases, and when the impurity concentration of the fifth semiconductor layer 19 exceeds 7×10 15 cm -3 the breakdown voltage VB decreases.

[0073] FIGS. 11(a) and (b) are graphs showing yet another characteristic of the semiconductor device 1 according to the embodiment. FIG. 11(a) is a graph showing the relationship between the second distance D2 from the back surface 10B of the semiconductor portion 10 to the fifth semiconductor layer 19 and the breakdown voltage VB. The vertical axis in FIG. 11(a) is the breakdown voltage VB. FIG. 11(b) is a graph showing the relationship between the second distance D2 and Isn a p. The vertical axis in FIG. 11(b) is the ratio of Isn a p0 when the fifth semiconductor layer 19 is not provided to Isn a p.

[0074] As shown in Fig. 11(a), the breakdown voltage VB increases as the second distance D2 becomes longer. On the other hand, as shown in Fig. 11(b), Isn a p rapidly decreases when the second distance D2 is greater than 10 μm. Isn a When Isn

[0075] Fig. 12 is a graph showing other characteristics of the semiconductor device 1 according to the embodiment. Fig. 12 is a graph showing the relationship between the external charge accumulated in the terminal region TR and the breakdown voltage VB. The horizontal axis represents the charge amount, and the vertical axis represents the breakdown voltage VB.

[0076] In the resin layer 39 (see Fig. 2) covering the terminal region TR, for example, metal ions invading from the outside are likely to accumulate. The external charge caused by such metal ions affects the electric field distribution in the terminal region TR. For example, when positive charges are accumulated between the third electrode 35 and the fourth electrode 37b, the lateral extension of the electric field in the terminal region TR is suppressed. For this reason, the electric field strength at the outer edge 27be (see Fig. 6) of the ninth semiconductor layer 27b may increase, and the breakdown voltage VB may decrease.

[0077] "EB" shown in Fig. 12 represents the characteristics of the semiconductor device 1. Also, "CE" represents the characteristics of the semiconductor device 2 (see Fig. 7(a)) according to the comparative example.

[0078] As shown in Fig. 12, in the semiconductor device 2, as the amount of positive charge increases, the breakdown voltage VB decreases. In contrast, in the semiconductor device 1, even when the amount of positive charge increases, the breakdown voltage VB does not decrease. That is, in the semiconductor device 1, by providing the fifth semiconductor layer 19, it is possible to suppress the increase in the electric field at the outer edge 27be of the ninth semiconductor layer 27b. Thus, in the semiconductor device 1, it is possible to improve the charge robustness and prevent a decrease in breakdown voltage in the termination region TR.

[0079] FIGS. 13(a) and (b) are schematic diagrams showing a semiconductor device 3 according to a modified example of the embodiment. FIG. 13(a) is a cross-sectional view showing the structure of the termination region TR of the semiconductor device 3. FIG. 13(b) represents the impurity concentration profile of the semiconductor portion 10. The horizontal axis is the depth from the back surface 10B of the semiconductor portion 10. The vertical axis is the impurity concentration.

[0080] As shown in FIG. 13(a), the first semiconductor layer 11 includes a first region 11a and a second region 11b. The first region 11a is, for example, an n-type base region. The second region 11b is, for example, an n-type buffer region. The second region 11b is provided between the first region 11a and the fourth semiconductor layer 17. The fifth semiconductor layer 19 is provided in the second region 11b. The second region 11a is formed, for example, by performing proton irradiation on the back surface side of the semiconductor portion 10 (see FIG. 5(b)).

[0081] As shown in FIG. 13(b), the second region 11b contains a first-conductivity-type impurity at a higher concentration than the concentration of the first-conductivity-type impurity in the first region 11a. The second region 11b is formed, for example, from the back surface 10B of the semiconductor portion 10 to a depth of, for example, 20 μm. The distribution of the second-conductivity-type impurity in the second region 11b has, for example, a plurality of concentration peaks 24a, 24b, and 24c The fifth semiconductor layer 19 is provided between the concentration peaks of the second-conductivity-type impurity in the second region 11b 24a and 24b and the fourth semiconductor layer 17.

[0082] Alternatively, the second region 11b may be formed such that the distribution of the second-conductivity-type impurity has one concentration peak. In that case, the fifth semiconductor layer 19 is provided between the concentration peak of the second-conductivity-type impurity and the fourth semiconductor layer 17.

[0083] Also in this example, by providing the fifth semiconductor layer 19 in the termination region TR, it is possible to improve the breakdown withstand voltage and the charge robustness.

[0084] Although some embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalent scope thereof.

Explanation of Reference Numerals

[0085] 1, 2, 3... semiconductor device, 10... semiconductor part, 10B... back surface, 10F... front surface, 11... first semiconductor layer, 11a... first region, 11b... second region, 13... second semiconductor layer, 15... third semiconductor layer, 17... fourth semiconductor layer, 19... fifth semiconductor layer, 21e, 27ae, 27be... outer edge, 20... first electrode, 21... sixth semiconductor layer, 23... seventh semiconductor layer, 25... eighth semiconductor layer, 27a, 27b... ninth semiconductor layer, 30... second electrode, 35... third electrode, 37a, 37b... fourth electrode, 39... resin layer, 40... control electrode, 43... first insulating film, 45... second insulating film, 50... fifth electrode, 53... third insulating film, AR... active region, D1... first distance, D2... second distance, Ie... electron current, TG1, TG2... trench, TR... termination region

Claims

1. A semiconductor part including a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, a fourth semiconductor layer of the second conductivity type, and a fifth semiconductor layer of the second conductivity type; A first electrode provided on the back surface of the semiconductor part; A second electrode provided on the front surface of the semiconductor part, wherein the first semiconductor layer extends between the first electrode and the second electrode, the second semiconductor layer is provided between the first semiconductor layer and the second electrode, the third semiconductor layer is partially provided between the second semiconductor layer and the second electrode, and the fourth semiconductor layer is configured to be provided between the first semiconductor layer and the first electrode; A control electrode disposed inside a trench provided in the semiconductor part, positioned between the semiconductor part and the second electrode, electrically insulated from the semiconductor part by a first insulating film, electrically insulated from the second electrode by a second insulating film, and extending into the first semiconductor layer from the front surface side of the semiconductor part, wherein the second semiconductor layer is configured to face the control electrode via the first insulating film; Comprising; The semiconductor part includes an active region including the control electrode, the second semiconductor layer, and the third semiconductor layer, and a termination region surrounding the active region; The fifth semiconductor layer is provided in the first semiconductor layer in the termination region and extends in a first direction along the boundary between the first semiconductor layer and the fourth semiconductor layer; In a second direction from the first electrode toward the second electrode, a first distance from the fifth semiconductor layer to the front surface of the semiconductor part is longer than a second distance from the fifth semiconductor layer to the back surface of the semiconductor part; The second distance is 10 micrometers or less; A semiconductor device in which an impurity concentration in the fifth semiconductor layer is greater than 5×10 15 cm -3.

2. The semiconductor part further includes a sixth semiconductor layer of the second conductivity type; The sixth semiconductor layer is provided on the front surface side of the semiconductor part and extends along the boundary between the active region and the termination region; The semiconductor device according to claim 1, wherein the fifth semiconductor layer is spaced apart from the sixth semiconductor layer and is provided closer to the termination region side than the sixth semiconductor layer.

3. The semiconductor device according to claim 2, wherein in a plan view parallel to the front surface of the semiconductor part, the fifth semiconductor layer is located outside the sixth semiconductor layer.

4. The semiconductor part further includes a seventh semiconductor layer of the first conductivity type, wherein the seventh semiconductor layer is provided between the first semiconductor layer and the fourth semiconductor layer, and contains a first conductivity type impurity with a higher concentration than the concentration of the first conductivity type impurity in the first semiconductor layer. The semiconductor device according to any one of claims 1 to 3.

5. The semiconductor part further includes an eighth semiconductor layer of the first conductivity type, wherein the eighth semiconductor layer is provided on the surface side of the semiconductor part, is spaced apart from the sixth semiconductor layer, is provided on the terminal region side of the sixth semiconductor layer, and contains a first conductivity type impurity with a higher concentration than the concentration of the first conductivity type impurity in the first semiconductor layer. In a plan view parallel to the surface of the semiconductor part, the fifth semiconductor layer is provided between the sixth semiconductor layer and the eighth semiconductor layer. The semiconductor device according to claim 2 or 3.

6. The semiconductor device according to claim 5, wherein the fifth semiconductor layer is provided in a plate shape extending in the first direction.

7. The semiconductor part further includes a ninth semiconductor layer of the second conductivity type, wherein the ninth semiconductor layer is provided between the sixth semiconductor layer and the eighth semiconductor layer on the surface side of the semiconductor part. The semiconductor device according to claim 5 or 6, wherein the fifth semiconductor layer is located between the fourth semiconductor layer and the ninth semiconductor layer in the second direction.

8. The semiconductor device further includes a third electrode provided on the eighth semiconductor layer, and a fourth electrode provided on the ninth semiconductor layer. The second electrode, the third electrode, and the fourth electrode are spaced apart from each other. The third electrode is electrically connected to the eighth semiconductor layer. The fourth electrode is electrically connected to the ninth semiconductor layer. The semiconductor device according to claim 7.

9. The semiconductor device according to any one of claims 1 to 8, further including a resin layer provided on the surface side of the semiconductor part and covering the terminal region.

Images