System and method for measuring a post-bonding overlay

Abstract

The wafer shape metrology system includes a wafer shape metrology subsystem configured to perform one or more stress-free shape measurements on a first wafer, a second wafer, and a post-bonded pair of the first and second wafers. The wafer shape metrology system includes a controller communicatively coupled to the wafer shape metrology subsystem. The controller is configured to receive the stress-free shape measurements from the wafer shape subsystem, predict overlay between one or more features on the first wafer and the second wafer based on the stress-free shape measurements of the first wafer, the second wafer, and the post-bonded pair of the first wafer and the second wafer, and provide feedback adjustments to one or more process tools based on the predicted overlay. Further, feedforward and feedback adjustments can be provided to the one or more process tools.

Description

Technical Field

[0001] The present invention generally relates to the field of measurement, and more particularly to a system and method for measuring a post-bonding overlay using a wafer shape measurement tool.

Background Art

[0002] (Cross-reference to Related Applications)

[0003] This application claims the benefit of U.S. Provisional Application No. 63 / 124,629, filed on December 11, 2020, under 35 U.S.C. § 119(e), the entire disclosure of which is incorporated herein by reference.

[0004] Conventional methods for measuring a post-bonding overlay after bonding two semiconductor wafers involve placing an overlay measurement target (such as a box-in-box structure or an AIM target) on either of the wafers to be bonded. By using infrared light that penetrates the silicon wafer and comparing the relative positions of the targets, the overlay results can be obtained. In such conventional overlay measurements, it was necessary to have measurement targets on both wafers. This can be disadvantageous for two reasons. First, depending on the bonding flow, additional processing may be required by placing a measurement target on a so-called carrier wafer. Second, since targets are required, there is a limit to the achievable measurement density.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Patent Document 3

SUMMARY OF THE INVENTION

PROBLEMS TO BE SOLVED BY THE INVENTION

[0006] Therefore, it is desirable to provide a system and method that eliminate the drawbacks of the conventional approaches as described above.

MEANS FOR SOLVING THE PROBLEMS

[0007] According to one or more embodiments of the present disclosure, a wafer measurement system is disclosed. In one embodiment, the wafer measurement system includes a wafer shape measurement subsystem configured to perform one or more stress-free shape measurements on a first wafer, a second wafer, and a post-bonding pair of the first wafer and the second wafer. In another embodiment, the wafer measurement system includes a controller communicatively coupled to the wafer shape measurement subsystem, the controller including one or more processors configured to execute a set of program instructions stored in a memory. In another embodiment, the set of program instructions is configured to cause the one or more processors to receive one or more stress-free shape measurement values from the wafer shape subsystem, predict an overlay between one or more features on the first wafer and one or more features on the second wafer based on the one or more stress-free shape measurement values of the first wafer, the second wafer, and the post-bonding pair of the first wafer and the second wafer, and provide a feedback adjustment to one or more process tools based on the predicted overlay.

[0008] In accordance with one or more alternative and / or additional embodiments of the present disclosure, a wafer measurement system is disclosed. In one embodiment, the wafer measurement system includes a wafer shape measurement subsystem configured to perform one or more stress-free shape measurements on a first wafer and a second wafer. In another embodiment, the wafer shape measurement system includes a controller communicatively coupled to the wafer shape measurement subsystem, the controller including one or more processors configured to execute a set of program instructions stored in a memory. In another embodiment, the set of program instructions is configured to cause the one or more processors to receive one or more stress-free shape measurements of the first wafer and the second wafer from the wafer shape subsystem, measure a first shape distortion of the first wafer by comparing the shape of the first wafer to a first reference structure, measure a second shape distortion by comparing the shape of the second wafer to a second reference structure, predict an overlay between one or more features on the first wafer and one or more features on the second wafer based on the one or more stress-free shape measurements of the first wafer and the second wafer, the first shape distortion, and the second wafer shape distortion, and provide a feedforward adjustment to one or more process tools based on the predicted overlay.

[0009] It should be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not necessarily restrictive of the invention as claimed. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the general description, serve to explain the principles of the invention.

[0010] Many advantages of the present disclosure can be better understood by those skilled in the art by referring to the accompanying drawings.

Brief Description of the Drawings

[0011]

Figure 1A

Figure 1B

Figure 1C

Figure 2

Figure 3

DETAILED DESCRIPTION OF THE INVENTION

[0012] The present disclosure has been particularly shown and described with respect to specific embodiments and their specific features. The embodiments shown herein are to be considered illustrative rather than restrictive. It should be readily apparent to those skilled in the art that various changes and modifications in form and detail can be made without departing from the spirit and scope of the present disclosure. Hereinafter, reference will be made in detail to the disclosed subject matter shown in the accompanying drawings.

[0013] Generally referring to FIGS. 1A - 3, a system and method for post-bonding overlay measurement according to one or more embodiments of the present disclosure are illustrated.

[0014] Embodiments of the present disclosure are directed to the measurement of relative overlay between two bonded wafers caused by shape-based distortion. Embodiments of the present disclosure may utilize shape measurements performed on first and second incoming wafers and post-bonded wafer pairs. Embodiments of the present disclosure may transform shape data collected from a first wafer, a second wafer (before bonding), and a post-bonded pair (after bonding) to predict overlay data and provide feedback control. Additional embodiments of the present disclosure may transform shape data collected from a first wafer and a second wafer (before bonding), measure shape distortion of the first and second wafers relative to a reference structure, and provide feedforward control. The conversion of shape data to predicted overlay information may be performed using machine learning algorithms and / or machine models.

[0015] Embodiments of the present disclosure may be implemented to achieve stringent overlay requirements on two wafers after an inter-wafer bonding process (e.g., hybrid bonding or fusion bonding). For example, embodiments of the present disclosure may be utilized to minimize / reduce overlay in an inter-wafer bonding process involved in the manufacture of image sensors (e.g., backlit image sensor technology), 3D NAND technology where device wafers and memory wafers are bonded together, and the backside power rail process of logic devices where device wafers are bonded to carrier wafers. In all of these examples, stringent overlay tolerances are required. In image sensors and 3D NAND technology, overlay requirements are implemented to ensure reliable connections for direct electrical connection of Cu pads on one wafer to Cu pads on another wafer. In the case of backside power rail technology, it is desirable to reduce wafer distortion so that subsequent lithography can achieve the overlay tolerance required for via exposure, considering the general correction capabilities of the scanner (e.g., correction per field (CPE) correction).

[0016] The process for measuring a post-bonding overlay may include, but is not limited to, i) performing a wafer shape measurement step, ii) performing a feature extraction step in which certain parameters of the wafer are extracted from the wafer shape data, and iii) converting the extracted parameters via an algorithm (e.g., a machine learning algorithm or a machine model) into an overlay between features of a first wafer and a second wafer. Based on the result of the overlay prediction, a control algorithm (e.g., a feedback or feed-forward algorithm) may be implemented. In the case of feedback control, the control algorithm may be used to optimize the bond settings of subsequent wafers. In the case of feed-forward control, the incoming wafer shape distortion may be used to adjust the bond settings.

[0017] FIG. 1A shows a simplified block diagram of a wafer shape measurement system 100 for post-bonding overlay measurement according to one or more embodiments of the present disclosure.

[0018] In an embodiment, the system 100 includes a wafer shape measurement subsystem 102. The system 100 may also include a controller 104 communicatively coupled to the detector output of the wafer shape measurement subsystem 102. The controller 104 may include one or more processors 106 and a memory 108. The one or more processors 106 of the controller 104 may be configured to execute a set of program instructions stored in the memory 108. The set of program instructions may be configured to cause the one or more processors 106 to perform the various steps and processes of the present disclosure.

[0019] The wafer shape measurement subsystem 102 may include any wafer shape tool or system known in the art that is capable of obtaining one or more shape parameters from one or more wafers. In an embodiment, the wafer shape measurement subsystem 102 includes an interferometer subsystem configured to perform one or more measurement and / or characterization processes on one or more wafers. For example, the wafer shape measurement subsystem 102 may include a dual interferometer system (e.g., a dual Fizeau interferometer) configured to perform measurements on both sides of a wafer. For example, the wafer shape measurement subsystem 102 may include a first interferometer subsystem 105a configured to generate a first illumination beam 101a for performing one or more measurements on a first surface of the wafer, and a second interferometer subsystem 105b configured to generate a second illumination beam 101b for performing one or more measurements on a second surface of the wafer opposite the first surface. The wafer measurement subsystem 102 may include a patterned wafer geometry (PWG) tool, such as a PWG tool manufactured by KLA INC. The use of interferometers for wafer characterization is generally described in U.S. Patent No. 6,847,458, filed March 20, 2003, U.S. Patent No. 8,949,057, filed October 27, 2011, and U.S. Patent No. 9,121,684, filed January 15, 2013, which are hereby incorporated by reference in their entirety.

[0020] Note that a dual-sided interferometer, such as a PWG tool, may be particularly useful for implementation in the context of the processes of the present disclosure. For example, thickness and / or thickness change information may be input to the machine learning algorithms and / or machine models of the present disclosure. Further, dual-sided measurements provide flexibility when one surface has an attribute that makes the measurement uncertain. Further, dual-sided measurements allow for averaging of shape information from two measurements, improving certainty.

[0021] Note that the scope of the present disclosure is not limited to the dual interferometer system of the PWG implementation, and can be extended to include any wafer measurement system or tool known in the art, including but not limited to a single-sided interferometer system.

[0022] In an embodiment, the wafer shape measurement subsystem 102 is configured to perform wafer shape measurement while the wafer is in a stress-free or near stress-free state. For the purposes of the present disclosure, the term "stress-free" should be interpreted to mean a configuration in which there is little force applied to the wafer from external sources. The term "stress-free" may alternatively be interpreted as "free-standing". In a state where external stress is removed, the remaining deviation from a flat wafer shape is typically induced via a stress layer present on the front surface of the wafer or due to stress imposed by a bonding process. Note that these stresses caused by the layers present on the wafer are interpreted as internal stresses. In this sense, the "shape" of the wafer is a combination of the "natural shape" (i.e., the shape of the bare wafer) and the shape caused by internal stresses on any surface of the wafer, such as a thin film.

[0023] In an embodiment, as shown in FIG. 1B, the wafer measurement subsystem 102 may perform (1) shape measurement of a first wafer, (2) shape measurement of a second wafer, and (3) shape measurement of a post-bonded pair of wafers. Note that the measurements of the pre-bonded first and second wafers can be used to predict the shape of the post-bonded pair of wafers based on the shape mismatch between the first wafer and the second wafer, as well as the influence of the bonder and the bonding process on the post-bonded pair.

[0024] In an embodiment, the wafer measurement subsystem 102 may perform a first shape measurement on the first wafer 110a and then transmit the shape measurement data to the controller 104 via the data signal 103a. The wafer measurement subsystem 102 may perform a second shape measurement on the second wafer 110b and then transmit the shape measurement data to the controller 104 via the data signal 103b. Next, the first wafer 110a and the second wafer 110b may undergo a bonding process via a bonder (not shown) to form a post-bonding wafer pair 110c. The wafer measurement subsystem 102 may perform a third shape measurement on the post-bonding wafer pair 110c and then transmit the shape measurement data to the controller 104 via the data signal 103c.

[0025] In an embodiment, following the bonding process, the controller 104 converts the measured shape information of the first wafer 110a, the second wafer 110b, and the post-bonding wafer pair 110 into local shape parameters that characterize the local shape characteristics. For example, these parameters may include the first and second partial derivatives of the shape, or the prediction of in-plane displacement from the shape using different mechanical models. For example, the local shape parameters may include, but are not limited to, local shape curvature (LSC) and / or in-plane distortion (IPD). Additional metrics that have been conventionally used to predict the distortion of wafers on a scanner may also be utilized. Such metrics include, but are not limited to, mechanical models that describe the relationship between wafer shape and overlay based on approaches such as plate theory, finite element method, or proprietary modeling approaches such as parameters from Gen3, Gen4, and / or Gen5 models manufactured by KLA Corporation.

[0026] Explanations for capturing the effects of both the incoming wafer and the post-bonding wafer are described in the 2004 doctoral thesis by K. Turner, "Wafer Bonding: Mechanics-based Models and Experiments, Massachusetts Institute of Technology". In this approximation, the global warpage localized from the warp of the final bonded wafer (and the resulting IPD) can be described by the following equation.

Number

Number

[0027] In an embodiment, the first algorithm executed by the controller 104 includes a machine learning algorithm. The machine learning algorithm applied by the controller 104 may include, but is not limited to, a deep learning algorithm, and may include any machine learning algorithm known in the art. For example, the deep learning algorithm may include, but is not limited to, a neural network (e.g., a convolutional neural network (CNN), a generative adversarial network (GAN), a recurrent neural network (RNN), etc.). In the present embodiment, the controller 104 generates a plurality of parameters from the wafer shape for each measurement (the first wafer 110a, the second wafer 110b, and the post-bonding wafer pair 110c). For example, the controller 104 may locally generate IPD, Gen4, etc. for the first wafer 110a, the second wafer 110b, and the post-bonding wafer pair 110c. Next, the controller 104 may use any of these generated parameters as an input to the machine learning algorithm. For example, in the case of a neural network, the controller 104 may locally generate IPD, Gen4, etc. for the first wafer 110a, the second wafer 110b, and the post-bonding wafer pair 110c, and input these metrics into the neural network.

[0028] In an embodiment, the controller 104 may train a machine learning algorithm. For example, the controller 104 may receive and then utilize IR overlay data measured at the same location for training. In an embodiment, the alignment-induced overlay error caused by not only the relative x-y shift but also the rigid rotation error is removed from the overlay data used for training. In an embodiment, once trained, an overlay prediction may be performed using a machine learning algorithm such as a neural network.

[0029] In alternative and / or additional embodiments, a mechanical model may be used instead of (or in combination with) a machine learning algorithm. Similar to the procedure used to predict the overlay of a warped wafer chucked on a lithography scanner, a set of mechanical equations describing the wafer shape may be approximately solved. In an embodiment, the mechanical model may be based on plate theory or beam theory. In an embodiment, the mechanical model is based on a numerical solution of the continuum mechanics equations governing the linear elastic deformation of solids. For example, the mechanical model may include, but is not limited to, techniques such as plate theory or the finite element method. Consistent with the equations shown above, the intermediate shape of the wafer during bonding provides a major adjustment.

[0030] In an embodiment, as shown in FIG. 1C, the controller 104 may provide one or more control signals 113 to one or more process tools 112. For example, the controller 104 may generate one or more feedforward and / or feedback control signals configured to adjust one or more upstream and / or downstream process tools. Process tools that may be adjusted may include, but are not limited to, lithography tools, film deposition tools, polishing tools, etching tools, bonders, etc. In this regard, the predicted overlay information may be used to minimize (or at least reduce) the overlay observed in the bonded wafer pair.

[0031] In an embodiment, the controller 104 may provide feedback control. For example, the predicted post-bonding overlay may be used to adjust the process control of the bonder. Examples of such process adjustments include adjustment of the vacuum pressure applied during bonding or adjustment for non-uniform temperature distribution. The effects of these changes may be characterized as a control signature. Using standard optimization algorithms, a signature characterized for adjustment of the bonder, and a scaled combination of the signatures, the resulting overlay may be minimized.

[0032] In additional and / or alternative embodiments, the controller 104 may provide feedforward control. In an embodiment, prior to the bonding process, the controller 104 may apply a model to determine a first shape distortion of the first wafer 110a by comparing a first wafer shape to a first reference structure and a second shape distortion of the second wafer 110a by comparing a second wafer shape to a second reference structure. The first reference structure and the second reference structure may include, but are not limited to, an ideal flat wafer. Next, the controller 104 may predict an overlay between one or more features on the first wafer 110a and one or more features on the second wafer 110b based on the shape measurements of the first wafer 110a and the second wafer 110b, the first shape distortion, and the second wafer shape distortion. In this regard, the controller 104 may apply a machine learning algorithm and / or a machine model as previously described herein. Next, the controller 104 may provide a feedforward adjustment to one or more process tools (e.g., a bonder) based on the predicted overlay. For example, in the case of a wafer with a high initial warp, the changing signature of the incoming wafer warp affects the outgoing post-bonding distortion. In this case, the post-bonding signature can be generated with a modified process. Using pre-measurements of two incoming wafers and one outgoing wafer, a bonding signature can be generated from an initial calibration run. In feedforward control, the incoming signatures are combined to generate a predicted overlay result. This can be optimized according to the procedures described herein to provide the lowest possible post-bonding overlay. Note that the pre-bonding shape measurements of the wafers 110a, 110b in combination with a model for determining distortion can be used to select pairs of wafers to be bonded to minimize overlay error.

[0033] One or more processors 106 of the controller 104 can include any processor or processing element known in the art. For the purposes of the present disclosure, the term "processor" or "processing element" can be broadly defined to include any device having one or more processing or logic elements (e.g., one or more microprocessor devices, one or more application specific integrated circuit (ASIC) devices, one or more field programmable gate arrays (FPGA), or one or more digital signal processors (DSP)). In this sense, one or more processors 106 can include any device configured to execute algorithms and / or instructions (e.g., program instructions stored in memory). In one embodiment, one or more processors 106 can be embodied as a desktop computer, a mainframe computer system, a workstation, an image computer, a parallel processor, a network computer, or any other computer system configured to execute a program that operates as described throughout the present disclosure or is configured to operate in conjunction with the measurement system 100. Further, different subsystems of the system 100 may include processors or logic elements suitable for performing at least some of the steps described in the present disclosure. Accordingly, the above description should not be construed as a limitation on the embodiments of the present disclosure, but should be construed merely as an example. Further, the steps described throughout the present disclosure may be executed by a single controller or, alternatively, by a plurality of controllers. Further, the controller 104 may include one or more controllers housed within a common housing or within a plurality of housings. In this way, any controller or combination of controllers may be individually packaged as a module suitable for integration into the measurement system 100. Further, the controller 104 may analyze data received from the wafer measurement subsystem 102 and supply the data to additional components within the measurement system 100 or external to the measurement system 100.

[0034] The memory medium 108 may include any storage medium known in the art suitable for storing program instructions executable by one or more associated processors 106. For example, the memory medium 108 may include a non-transitory memory medium. As another example, the memory medium 108 may include, but is not limited to, read-only memory (ROM), random access memory (RAM), magnetic or optical memory devices (e.g., disks), magnetic tapes, solid state drives, etc. It should be further noted that the memory medium 108 may be housed in a common controller housing with one or more processors 106. In one embodiment, the memory medium 108 may be located remotely with respect to the physical location of one or more processors 106 and controller 104. For example, one or more processors 106 of the controller 104 may access a remote memory (e.g., a server) accessible via a network (e.g., the Internet, an intranet, etc.).

[0035] Note that one or more components of the disclosed system 100 may be communicatively coupled to various other components of the system in any manner known in the art. For example, the wafer measurement subsystem 102, controller 104, process tool 112, and user interface may be communicatively coupled to each other and to other components by wired (e.g., copper wire, fiber optic cable, etc.) or wireless connections (e.g., RF coupling, IR coupling, data network communication (e.g., WiFi, WiMax, 3G, 4G, 4G LTE, 5G, Bluetooth, etc.)).

[0036] Figure 2 shows a method of measuring an overlay between features on a post-bonded wafer pair in accordance with one or more embodiments of the present disclosure. Note that the steps of method 200 may be performed in whole or in part by the wafer measurement system 100. However, it is further recognized that method 200 is not limited to the wafer measurement system 100 in that additional or alternative system-level embodiments may perform all or part of the steps of method 200.

[0037] In step 202, wafer shape measurement is performed on the first wafer. For example, as shown in FIG. 1B, the wafer shape subsystem 102 may perform wafer shape measurement on the first wafer 110a before the wafer bonding process.

[0038]

[0037] In step 204, wafer shape measurement is performed on the second wafer. For example, as shown in FIG. 1B, the wafer shape subsystem 102 may perform wafer shape measurement on the second wafer 110b before the wafer bonding process.

[0039] In step 206, the first wafer and the second wafer are bonded to form a bonded pair of wafers. For example, a bonder (not shown) may bond the first wafer 110a and the second wafer 110b in the wafer-to-wafer bonding process. The bonder may be configured for hybrid wafer bonding or fusion wafer bonding.

[0040] In step 208, wafer shape measurement is performed on the post-bonded pair of the second wafer. For example, as shown in FIG. 1B, the wafer shape subsystem 102 may perform wafer shape measurement on the post-bonded pair of wafers 110c after the bonding process.

[0041] In step 210, an overlay between features on the first wafer and features on the second wafer is predicted based on shape measurement values from the first wafer, the second wafer, and the bonded pair of wafers. In an embodiment, the controller 104 may measure or predict an overlay between features on the first wafer 110a and features on the second wafer 110b based on shape measurement values from the first wafer 110a, the second wafer 110b, and the bonded pair of wafers 110c. For example, the controller 104 may execute an algorithm that correlates the shape information of the first wafer 110a, the second wafer 110b, and the bonded pair of wafers 110c to the overlay between features on the first wafer 110a and the second wafer 110b. In a first step, the measured shape information of steps 204, 206, and 208 may be converted by the controller 104 into local shape parameters that characterize local shape characteristics. Examples of such parameters are local shape curvatures, IPDs, and any other shape metrics used in the art to predict wafer distortion (e.g., plate theory, finite element method, or distortions in scanners predicted by machine models used to describe the relationship between wafer shape and overlay based on approaches such as proprietary modeling approaches such as parameters of Gen3, Gen4, and / or Gen5 models manufactured by KLA Corporation). Next, the acquired parameters are used by the controller 104 to predict the overlay. For example, the controller 104 may input the acquired shape parameters into a machine learning algorithm (e.g., a neural network), which correlates the acquired shape parameters to the overlay between features of the first wafer 110a and the second wafer 110b in the pair of wafers 110c. Suitable shape parameters for the machine learning algorithm may include local metrics such as curvature or shape gradient, or the shape of the wafer may be represented by a polynomial (e.g., X, Y, X 2 , XY, Y 2...), or a global metric adapted to Zernike polynomials naturally defined on the disk. These terms are not limiting and are merely examples. As another example, the controller 104 may input one or more of the acquired shape parameters into a physical / mechanical model to predict the overlay between features of the first wafer 110a and the second wafer 110b in the wafer pair 110c.

[0042] In step 212, one or more feedback adjustments are provided to the process tool. For example, as shown in FIG. 1C, one or more control signals 113 are sent to one or more process tools 112 to adjust one or more states of the one or more process tools 112 to minimize / maximize the overlay between the first wafer 110a and the second wafer 110b. For example, the controller 104 may generate one or more feedback control signals configured to adjust one or more upstream process tools. The process tools that can be adjusted may include, but are not limited to, lithography tools, film deposition tools, polishing tools, etching tools, bonders, etc. In this regard, the predicted overlay information can be used to minimize (or at least reduce) the overlay observed in future bonded wafer pairs.

[0043] FIG. 3 shows a method for predicting the overlay between features on a post-bonded wafer pair in accordance with one or more embodiments of the present disclosure. Note that the steps of method 300 may be performed in whole or in part by the wafer measurement system 100. However, it is further recognized that method 300 is not limited to the wafer measurement system 100 in that additional or alternative system-level embodiments may perform all or some of the steps of method 300. In addition, it can be interpreted that the various steps of method 200 are applicable to method 300 unless otherwise specified.

[0044] In step 302, wafer shape measurement is performed on the first wafer. For example, as shown in FIG. 1B, wafer shape subsystem 102 may perform wafer shape measurement on the first wafer 110a before the wafer bonding process.

[0045] In step 304, wafer shape measurement is performed on the second wafer. For example, as shown in FIG. 1B, wafer shape subsystem 102 may perform wafer shape measurement on the second wafer 110b before the wafer bonding process.

[0046] In step 306, a first shape distortion of the first wafer and a second shape distortion of the second wafer are measured. For example, the controller 104 may apply a model (e.g., a mechanical model based on plate theory) to compare the shape of the first wafer 110a with a reference structure in order to identify the distortion within the first wafer 110a. Similarly, the controller 104 may apply a model to compare the shape of the second wafer 110b with a reference structure in order to identify the distortion within the second wafer 110b. In an embodiment, the reference structure may include an idealized flat wafer. In additional embodiments, the reference structure may include shape information obtained from a previously measured wafer.

[0047] In step 308, the overlay between the features on the first wafer and the features on the second wafer is predicted based on the shape measurement values from the first and second wafers and the shape distortion of the first and second wafers. In an embodiment, when the wafer measurement subsystem 102 receives the shape information of the first wafer 110a and the second wafer 110b and measures the shape distortion based on the reference structure, the controller 104 may predict the overlay between the features on the first wafer 110a and the features on the second wafer 110b based on the shape measurement values and the shape distortion of the first wafer 110a and the second wafer 110b. For example, the controller 104 may execute an algorithm that correlates the shapes and shape distortions of the first wafer 110a and the second wafer 110b with the overlay between the features on the first wafer 110a and the second wafer 110b. In a first step, the measured shape information of steps 204 and 206 may be converted by the controller 104 into local shape parameters that characterize the local shape characteristics. Similar to method 200, examples of such parameters are local shape curvatures, IPDs, and other arbitrary shape metrics used in the art to predict wafer distortion (e.g., distortion on the scanner (e.g., Gen3, Gen4, Gen5 parameters)). Next, the obtained parameters and the shape distortion information of step 306 are used to predict the overlay by the controller 104. For example, the controller 104 may input the obtained shape parameters and shape distortion information into a machine learning algorithm (e.g., a neural network), which correlates the obtained shape parameters and shape distortion (before bonding) with the overlay between the features of the first wafer 110a and the second wafer 110b when the wafers 110a and 110b are bonded. Similar to method 200, suitable shape parameters for the machine learning algorithm may include local metrics such as curvature or shape gradient, or the shape of the wafer may be represented by a polynomial (e.g., X, Y, X 2 , XY, Y 2...), or a global metric adapted to Zernike polynomials naturally defined on the disk. As another example, the controller 104 may input one or more of the acquired shape parameters and shape distortions into a physical / mechanical model to predict the overlay between features of the first wafer 110a and the second wafer 110b in a pair of wafers 110c. It should be further noted that the machine learning model and the mechanical model can be used in combination with each other.

[0048] In step 310, one or more feedforward adjustments are provided to the process tool. For example, as shown in FIG. 1C, one or more feedforward control signals 113 are transmitted to one or more process tools 112 to adjust one or more states of the one or more process tools 112 to minimize / reduce the overlay between the first wafer 110a and the second wafer 110b. For example, the controller 104 may generate one or more feedforward control signals configured to adjust one or more downstream process tools. The process tools that can be adjusted may include, but are not limited to, lithography tools, film deposition tools, polishing tools, etching tools, bonders, etc. In this regard, the predicted overlay information may be used to minimize (or at least reduce) the overlay observed on the bonded wafer pair 110c.

[0049] In an embodiment, the pre-bonding shape measurements of the wafers 110a, 110b in combination with a model for determining the distortion may be used to select a pair of wafers to be bonded to minimize the overlay error.

[0050] Those skilled in the art will recognize that the components, operations, devices, objects, and the accompanying discussions described herein are used as examples for conceptual clarification, and various configuration changes are contemplated. As a result, when used in this specification, the specific exemplifications and accompanying discussions described are intended to be representative of their more general classes. In general, the use of any specific exemplification is intended to be representative of its class, and the exclusion of specific components, operations, devices, and objects should not be considered limiting.

[0051] Those skilled in the art will understand that there are various media (e.g., hardware, software, and / or firmware) that can implement the processes and / or systems and / or other technologies described herein, and the preferred medium will vary depending on the context in which the process and / or system and / or other technology is deployed. For example, if the implementer determines that speed and accuracy are of utmost importance, the implementer can primarily choose a hardware and / or firmware medium; alternatively, if flexibility is of utmost importance, the implementer can primarily choose a software implementation; and furthermore, alternatively, the implementer can choose some combination of hardware, software, and / or firmware. Thus, while there are several possible media that can implement the processes and / or devices and / or other technologies described herein, none of them is inherently superior to the others in that the choice of the medium depends on both the context in which the medium is deployed and the specific concerns (e.g., speed, flexibility, or predictability) of the implementer, which can both vary.

[0052] The foregoing description has been presented to enable a person skilled in the art to make and use the invention as provided in the context of a particular application and its requirements. As used herein, directional terms such as "top," "bottom," "over," "under," "upper," "upward," "lower," "down," "downward," etc. are intended to provide a relative position for purposes of explanation and are not intended to specify an absolute reference frame. Various modifications to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments. Accordingly, the invention is not intended to be limited to the particular embodiments shown and described, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0053] Regarding the use of substantially any plural and / or singular terms herein, one of ordinary skill in the art can convert from plural to singular and / or from singular to plural as appropriate, depending on the context and / or application. Various singular / plural permutations are not explicitly defined herein for clarity.

[0054] All of the methods described herein may include storing the results of one or more steps of the method embodiment in a memory. The results may include any of the results described herein and may be stored in any manner known in the art. The memory may include any memory described herein or any other suitable storage medium known in the art. After the results are stored, the results may be accessed from the memory, used by any of the method or system embodiments described herein, formatted for display to a user, used by another software module, method, or system, and so on. Further, the results may be stored "permanently," "semi-permanently," "temporarily," or for a period of time. For example, the memory may be random access memory (RAM), and the results need not necessarily persist indefinitely in the memory.

[0055] Each embodiment of the methods described above is further contemplated to be able to include any other step(s) of any other method(s) described herein. Additionally, each of the embodiments of the methods described above may be performed by any of the systems described herein.

[0056] The subject matter described herein may show different components that are included within or connected to other components. It should be understood that such depicted architectures are merely exemplary, and in practice, many other architectures that achieve the same functionality may be implemented. Conceptually, any arrangement of components to achieve the same function is effectively "coordinated" so that the desired function is achieved. Thus, in this specification, any two components combined to achieve a particular function can be considered to be "coordinated" with each other so that the desired function is achieved, regardless of the architecture or intervening components. Similarly, any two components thus coordinated can also be considered to be "connected" or "coupled" to each other to achieve the desired functionality, and any two components that can be coordinated in this way can also be considered to be "couplable" to each other to achieve the desired functionality. Specific examples of couplable include, but are not limited to, components that can physically fit together and / or physically interact, as well as components that can interact wirelessly and / or wirelessly interact, and components that can interact logically and / or logically interact.

[0057] Furthermore, it will be understood that the present invention is defined by the appended claims. In general, the terms used in this specification, particularly in the appended claims (e.g., the principal part of the appended claims), will be understood by those skilled in the art to be generally intended as "open" terms (e.g., the term "comprising" should be construed as "including but not limited to", the term "having" should be construed as "having at least", the term "including" should be construed as "including but not limited to", etc.). Further, if a specific number is intended in an introduced claim recitation, such intent will be clearly stated in the claim, and those skilled in the art will understand that if there is no such statement, there is no such intent. To assist understanding, for example, in the appended claims that follow, it may include introducing claim recitations using introductory phrases such as "at least one" and "one or more". However, just because such phrases are used, when a claim recitation is introduced by an indefinite article such as "a" or "an", even if both an introductory phrase such as "one or more" or "at least one" and an indefinite article such as "a" or "an" are included within the same claim, it should not be construed that a particular claim containing the introduced claim recitation is limited to examples containing only one of the recited matters (e.g., "a" and / or "an" should usually be construed as meaning "at least one" or "one or more"), and the same applies when a claim recitation is introduced using a definite article. In addition, those skilled in the art will understand that even if a specific number is explicitly stated in an introduced claim recitation, such a statement should usually be construed as meaning at least the recited number (e.g., if there is a statement simply saying "two recited matters" without other modifiers, this statement means "at least" two recited matters, or "two or more" recited matters).Furthermore, when notations similar to "at least one of A, B, and C, etc." are used, generally, such syntax is intended to have a meaning that those skilled in the art can understand (for example, "a system having at least one of A, B, and C" may include, but is not limited to, a system having only A, only B, only C, both A and B, both A and C, both B and C, and / or all of A, B, and C, etc.). Furthermore, when notations similar to "at least one of A, B, or C, etc." are used, generally, such syntax is intended to have a meaning that those skilled in the art can understand (for example, "a system having at least one of A, B, or C" may include, but is not limited to, a system having only A, only B, only C, both A and B, both A and C, both B and C, and / or all of A, B, and C, etc.). Furthermore, it should be understood by those skilled in the art that any disjunctive and / or disjunctive clause representing two or more selectable terms is intended to include one of those terms, any of those terms, or both of those terms, regardless of whether it is in the specification, claims, or drawings. For example, the clause "A or B" would be understood to include the possibilities of "A" or "B", or "A and B".

[0058] It will be apparent that many of the present disclosure and its attendant advantages will be understood from the foregoing description, and various changes may be made in the form, structure, and arrangement of the components without departing from the disclosed subject matter or sacrificing all of its important advantages. The described forms are merely illustrative, and it is the intention of the following claims to embrace and include such changes. Furthermore, it should be understood that the present invention is defined by the appended claims.

Claims

1. A wafer shape measurement system, comprising: a first wafer, a second wafer, and a wafer shape measurement subsystem configured to perform stress-free shape measurements on the first wafer, the second wafer, and a post-bonding pair of the first wafer and the second wafer, respectively; a controller communicatively coupled to the wafer shape measurement subsystem, the controller including one or more processors configured to execute a set of program instructions stored in a memory, the set of program instructions causing the one or more processors to: receive the stress-free shape measurement values from the wafer shape measurement subsystem; predict an overlay between one or more features on the first wafer and one or more features on the second wafer based on the stress-free shape measurement values of the first wafer, the second wafer, and the post-bonding pair of the first wafer and the second wafer; provide feedback control to one or more process tools among a lithography tool, a film deposition tool, a polishing tool, an etching tool, and a bonder based on the predicted overlay; wherein the wafer shape measurement system is configured as such; predicting the overlay between the one or more features on the first wafer and the one or more features on the second wafer based on the stress-free shape measurement values of the first wafer, the second wafer, and the post-bonding pair of the first wafer and the second wafer respectively includes: extracting wafer shape parameters as local shape parameters characterizing local shape characteristics from the stress-free shape measurement values of the first wafer, the second wafer, and the post-bonding pair of the first wafer and the second wafer respectively, and executing a predetermined algorithm for correlating the extracted wafer shape parameters with the overlay between the one or more features on the first wafer and the one or more features on the second wafer.

2. The wafer shape measurement system according to claim 1, wherein the extracted wafer shape parameters include at least one of local shape curvature (LSC) or in-plane distortion (IPD).

3. The wafer shape measurement system according to claim 1, further comprising inputting the extracted wafer shape parameters into a machine learning algorithm to predict the overlay between the one or more features on the first wafer and the one or more features on the second wafer.

4. The wafer shape measurement system according to claim 3, further comprising training the machine learning algorithm.

5. The wafer shape measurement system according to claim 4, wherein training the machine learning algorithm includes training the machine learning algorithm with infrared overlay data.

6. The wafer shape measurement system according to claim 1, further comprising inputting the extracted wafer shape parameters into a machine model to predict the overlay between the one or more features on the first wafer and the one or more features on the second wafer.

7. Providing the one or more feedback controls to the one or more process tools based on the predicted overlay includes The wafer shape measurement system according to claim 1, comprising providing the one or more feedback controls to a bonder based on the predicted overlay and adjusting one or more process controls of the bonder.

8. The wafer shape measurement subsystem of the wafer shape measurement system according to claim 1 includes a first interferometer subsystem and a second interferometer subsystem.

9. A system comprising a controller configured to receive shape measurements from a wafer shape measurement subsystem, the controller including one or more processors configured to execute a set of program instructions stored in a memory, the set of program instructions causing the one or more processors to receive stress-free shape measurements from the wafer shape measurement subsystem, predict an overlay between one or more features on a first wafer and one or more features on a second wafer based on the stress-free shape measurements of each of the first wafer, the second wafer, and the post-bonding pair of the first wafer and the second wafer. Based on the predicted overlay, providing feedback control to one or more process tools among a lithography tool, a film forming tool, a polishing tool, an etching tool, and a bonder, is configured as, Predicting the overlay between the one or more features on the first wafer and the one or more features on the second wafer based on the stress-free shape measurement values of each of the first wafer, the second wafer, and the post-bonding pair of the first wafer and the second wafer, A system comprising extracting wafer shape parameters as local shape parameters characterizing local shape characteristics from the stress-free shape measurement values of each of the first wafer, the second wafer, and the post-bonding pair of the first wafer and the second wafer, and executing a predetermined algorithm for correlating the extracted wafer shape parameters with the overlay between one or more features on the first wafer and one or more features on the second wafer.

10. The system according to claim 9, wherein the extracted wafer shape parameters include at least one of local shape curvature (LSC) or in-plane strain (IPD).

11. The system according to claim 9, further comprising inputting the extracted wafer shape parameters into a machine learning algorithm to predict the overlay between the one or more features on the first wafer and the one or more features on the second wafer.

12. The system according to claim 11, further comprising training the machine learning algorithm.

13. The system according to claim 12, wherein training the machine learning algorithm includes training the machine learning algorithm with infrared overlay data.

14. The system according to claim 9, further comprising inputting the extracted wafer shape parameters into a mechanical model to predict the overlay between the one or more features on the first wafer and the one or more features on the second wafer.

15. Providing one or more feedback controls to the one or more process tools based on the predicted overlay, The system of claim 9, comprising providing the one or more feedback controls to a bonder based on the predicted overlay to adjust one or more process controls of the bonder.

16. The system of claim 9, wherein the wafer shape measurement subsystem comprises a first interferometer subsystem and a second interferometer subsystem.

17. A method comprising: obtaining stress-free shape measurement values for a first wafer, a second wafer, and a post-bonding pair of the first wafer and the second wafer, respectively; predicting an overlay between one or more features on the first wafer and one or more features on the second wafer based on the stress-free shape measurement values of the first wafer, the second wafer, and the post-bonding pair of the first wafer and the second wafer; providing feedback adjustment to one or more process tools among a lithography tool, a film deposition tool, a polishing tool, an etching tool, and a bonder based on the predicted overlay; including predicting the overlay between the one or more features on the first wafer and the one or more features on the second wafer based on the stress-free shape measurement values of the first wafer, the second wafer, and the post-bonding pair of the first wafer and the second wafer comprises: extracting wafer shape parameters as local shape parameters characterizing local shape characteristics from the stress-free shape measurement values of the first wafer, the second wafer, and the post-bonding pair of the first wafer and the second wafer, respectively, and executing a predetermined algorithm for correlating the extracted wafer shape parameters with the overlay between one or more features on the first wafer and one or more features on the second wafer.

18. A wafer shape measurement system comprising: a wafer shape measurement subsystem configured to perform stress-free shape measurement on a first wafer and a second wafer; A controller communicably coupled to the wafer shape measurement subsystem, the controller including one or more processors configured to execute a set of program instructions stored in a memory, the set of program instructions causing the one or more processors to, receive, from the wafer shape measurement subsystem, respective stress-free shape measurement values for the first wafer and the second wafer, determine a first wafer shape distortion of the first wafer by comparing the shape of the first wafer to a first reference structure, and determine a second wafer shape distortion of the second wafer by comparing the shape of the second wafer to a second reference structure, predict an overlay between one or more features on the first wafer and one or more features on the second wafer of the post-bonding pair of the first wafer and the second wafer based on the respective stress-free shape measurement values of the first wafer and the second wafer, the first wafer shape distortion, and the second wafer shape distortion, configured to provide a feedforward adjustment to one or more process tools among a lithography tool, a film deposition tool, a polishing tool, an etching tool, a bonder based on the predicted overlay, Predicting an overlay between one or more features on the first wafer and one or more features on the second wafer based on the respective stress-free shape measurement values of the first wafer and the second wafer, the first wafer shape distortion, and the second wafer shape distortion, including extracting wafer shape parameters as local shape parameters characterizing local shape characteristics from the respective stress-free shape measurement values of the first wafer and the second wafer, and executing a predetermined algorithm that correlates the extracted wafer shape parameters, the first wafer shape distortion, and the second wafer shape distortion to an overlay between one or more features on the first wafer and one or more features on the second wafer, a wafer shape measurement system. Claim 19 The wafer shape measurement system according to claim 18, wherein at least one of the first reference structure or the second reference structure includes an idealized flat plate. Claim 20 The system according to claim 18, wherein the extracted wafer shape parameters include at least one of local shape curvature (LSC) or in-plane distortion (IPD).

21. The system according to claim 18, further comprising inputting the extracted wafer shape parameters of the first wafer and the second wafer, and the first wafer shape distortion and the second wafer shape distortion into a machine learning algorithm to predict an overlay between one or more features on the first wafer and one or more features on the second wafer.

22. The system according to claim 21, further comprising training the machine learning algorithm.

23. The system according to claim 22, wherein training the machine learning algorithm includes training the machine learning algorithm with infrared overlay data.

24. The system according to claim 18, further comprising inputting the extracted wafer shape parameters of the first wafer and the second wafer, and the first wafer shape distortion and the second wafer shape distortion into a mechanical model to predict an overlay between one or more features on the first wafer and one or more features on the second wafer.

25. Providing one or more feedforward controls to one or more process tools based on the predicted overlay The system according to claim 18, wherein providing one or more feedforward controls to one or more process tools based on the predicted overlay includes providing one or more feedforward controls to a bonder based on the predicted overlay.

26. The system according to claim 18, wherein the wafer shape measurement subsystem comprises a first interferometer subsystem and a second interferometer subsystem.

27. A system comprising a controller configured to receive wafer shape measurements from a wafer shape measurement subsystem, the controller including one or more processors configured to execute a set of program instructions stored in a memory, the set of program instructions causing the one or more processors to receive, from the wafer shape measurement subsystem, stress-free shape measurement values of a first wafer and a second wafer respectively By comparing the shape of the first wafer with a first reference structure, a first wafer shape distortion of the first wafer is determined, and by comparing the shape of the second wafer with a second reference structure, a second wafer shape distortion of the second wafer is determined. Based on the stress-free shape measurement values of the first wafer and the second wafer, the first wafer shape distortion, and the second wafer shape distortion, an overlay between one or more features on the first wafer and one or more features on the second wafer of the post-bonding pair of the first wafer and the second wafer is predicted. Based on the predicted overlay, feed-forward control is provided to one or more process tools among a lithography tool, a film formation tool, a polishing tool, an etching tool, and a bonder. It is configured as follows. Predicting an overlay between one or more features on the first wafer and one or more features on the second wafer based on the stress-free shape measurement values of the first wafer and the second wafer, the first wafer shape distortion, and the second wafer shape distortion is including extracting wafer shape parameters as local shape parameters that characterize local shape characteristics from the stress-free shape measurement values of the first wafer and the second wafer respectively, and executing a predetermined algorithm that correlates the extracted wafer shape parameters, the first wafer shape distortion, and the second wafer shape distortion with the overlay between one or more features on the first wafer and one or more features on the second wafer. A system.

28. The system according to claim 27, wherein at least one of the first reference structure or the second reference structure includes an idealized flat plate.

29. The system according to claim 27, wherein the extracted wafer shape parameters include at least one of local shape curvature (LSC) or in-plane distortion (IPD).

30. Further, inputting the extracted wafer shape parameters of the first wafer and the second wafer, and the first shape distortion and the second wafer shape distortion into a machine learning algorithm to predict an overlay between one or more features on the first wafer and one or more features on the second wafer, the system according to claim 27.

31. Further, training the machine learning algorithm, the system according to claim 30.

32. Training the machine learning algorithm includes training the machine learning algorithm with infrared overlay data, the system according to claim 31.

33. Further, inputting the extracted wafer shape parameters of the first wafer and the second wafer, and the first shape distortion and the second wafer shape distortion into a machine model to predict an overlay between one or more features on the first wafer and one or more features on the second wafer, the system according to claim 27.

34. Providing one or more feedforward controls to one or more process tools based on the predicted overlay is Providing one or more feedforward controls to a bonder based on the predicted overlay, the system according to claim 27.

35. The wafer shape measurement subsystem includes a first interferometer subsystem and a second interferometer subsystem, the system according to claim 27.

36. A method comprising: Obtaining respective stress-free shape measurement values of a first wafer and a second wafer before bonding; Determining a first wafer shape distortion of the first wafer before bonding by comparing the shape of the first wafer with a first reference structure, and determining a second wafer shape distortion of the second wafer before bonding by comparing the shape of the second wafer with a second reference structure; Predicting an overlay between one or more features on the first wafer and one or more features on the second wafer after bonding based on respective stress-free shape measurement values of the first wafer and the second wafer before bonding, the shape distortion of the first wafer before bonding, and the shape distortion of the second wafer before bonding; Providing a feed-forward adjustment to one or more process tools among a lithography tool, a film formation tool, a polishing tool, an etching tool, and a bonder based on the predicted overlay; Predicting an overlay between one or more features on the first wafer and one or more features on the second wafer after bonding based on respective stress-free shape measurement values of the first wafer and the second wafer before bonding, the shape distortion of the first wafer before bonding, and the shape distortion of the second wafer before bonding, Including extracting wafer shape parameters as local shape parameters characterizing respective local shape characteristics before bonding from respective stress-free shape measurement values of the first wafer and the second wafer before bonding, and executing a predetermined algorithm correlating the extracted wafer shape parameters, the shape distortion of the first wafer before bonding, and the shape distortion of the second wafer before bonding with an overlay between one or more features on the first wafer and one or more features on the second wafer after bonding. A method.

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