Transistor

Abstract

This transistor comprises: an amorphous substrate; a conductive alignment layer on the amorphous substrate; a heterojunction structure including a semiconductor layer which is on the conductive alignment layer and a polarization layer which contacts the semiconductor layer; and a gate electrode on the heterojunction structure. The heterojunction structure includes a depression in a region overlapping with the gate electrode. The depression may be provided to the polarization layer, and may be provided to the semiconductor layer.

Description

Technical Field

[0001] One embodiment of the present invention relates to a transistor using a compound semiconductor, particularly a High Electron Mobility Transistor (HEMT).

Background Art

[0002] Gallium nitride (GaN) is a direct-transition semiconductor with a large bandgap. Focusing on the properties of gallium nitride, gallium nitride has characteristics such as a large saturated electron mobility and a high breakdown voltage. In recent years, by utilizing these characteristics of gallium nitride, the development of transistors for high-frequency power device applications, so-called HEMTs, has been promoted.

[0003] In an HEMT, it has a hetero-junction structure in which not only a gallium nitride film but also an aluminum gallium nitride (AlGaN) film is provided in contact with the gallium nitride film. At the interface between the gallium nitride film and the aluminum gallium nitride film, charges are induced by the spontaneous polarization of the gallium nitride film in the semiconductor layer and the piezo-electric effect of the aluminum gallium nitride in the polarization layer, and a high-density two-dimensional electron gas (2DEG) is formed. Since the concentration of the two-dimensional electron gas in the HEMT is large and the saturated electron mobility is also high, high-speed operation is possible in the HEMT.

[0004] The gallium nitride film of the HEMT is generally formed at a high temperature of 800°C to 1000°C using MOCVD (Metal Organic Chemical Vapor Deposition) or HVPE (Hydride Vapor Phase Epitaxy) on a sapphire substrate where it is difficult to increase the area.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0006] As described above, generally, a gallium nitride film is formed on a sapphire substrate at a high temperature. However, it is difficult to increase the area of the sapphire substrate, and it is difficult to reduce the manufacturing cost. Therefore, a technology development is also underway to provide an orientation layer for controlling the c-axis orientation of a gallium nitride film on an amorphous substrate such as a glass substrate that can be made large in area, and to form the gallium nitride film at a low temperature by sputtering. However, since an orientation layer such as a metal has conductivity, a HEMT including such a conductive orientation layer has a problem that the leakage current through the conductive orientation layer increases and the breakdown voltage decreases. In addition, HEMTs tend to have the property of being normally-on type (depletion type).

[0007] In view of the above problems, one object of an embodiment of the present invention is to provide a transistor including a conductive orientation layer on an amorphous substrate and having a reduced leakage current.

Means for Solving the Problems

[0008] A transistor according to an embodiment of the present invention includes an amorphous substrate, a conductive orientation layer on the amorphous substrate, a heterojunction structure including a semiconductor layer on the conductive orientation layer and a polarization layer in contact with the semiconductor layer, and a gate electrode on the heterojunction structure. The heterojunction structure includes a recess in a region overlapping the gate electrode.

[0009] Also, a transistor according to an embodiment of the present invention includes an amorphous substrate, a conductive orientation layer on the amorphous substrate, a heterojunction structure including a semiconductor layer on the conductive orientation layer and a polarization layer in contact with the semiconductor layer, a gate electrode on the heterojunction structure, and a p-type semiconductor layer overlapping the gate electrode and in contact with the polarization layer.

[0010] Also, a transistor according to an embodiment of the present invention includes an amorphous substrate, a conductive alignment layer on the amorphous substrate, a semiconductor layer on the conductive alignment layer, a gate electrode on the semiconductor layer, an insulating layer covering the gate electrode, and a polarization layer covering the insulating layer and in contact with the semiconductor layer.

Brief Description of the Drawings

[0011]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

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Figure 7A

Figure 7B

Figure 8

Embodiments for Carrying Out the Invention

[0012] Hereinafter, each embodiment according to the present invention will be described with reference to the drawings. It should be noted that each embodiment is merely an example, and those that can be easily conceived by those skilled in the art by appropriately changing while maintaining the gist of the invention are naturally included in the scope of the present invention. In addition, for the purpose of making the description clearer, the drawings may schematically show the width, thickness, shape, etc. of each part compared to the actual aspect. However, the illustrated shapes and the like are merely examples and do not limit the interpretation of the present invention.

[0013] In this specification, expressions such as "α includes A, B, or C", "α includes any one of A, B, and C", and "α includes one selected from the group consisting of A, B, and C" do not exclude the case where α includes a plurality of combinations of A to C unless otherwise specified. Furthermore, these expressions do not exclude the case where α includes other elements.

[0014] In this specification, for the sake of convenience of explanation, terms such as "upper" or "above" or "lower" or "below" are used. In principle, based on the substrate on which the structure is formed, the direction from the substrate to the structure is defined as "upper" or "above". Conversely, the direction from the structure to the substrate is defined as "lower" or "below". Therefore, in the expression of a structure on a substrate, the surface of the structure facing the substrate becomes the lower surface of the structure, and the opposite surface becomes the upper surface of the structure. Also, in the expression of a structure on a substrate, it only explains the vertical relationship between the substrate and the structure, and other members may be arranged between the substrate and the structure. Furthermore, the terms "upper" or "above" or "lower" or "below" mean the stacking order in a structure in which a plurality of layers are stacked, and they do not have to be in an overlapping positional relationship in a plan view.

[0015] In this specification, the letters such as "first", "second", or "third" appended to each component are for convenience of distinguishing each component and do not have any further meaning unless otherwise specified.

[0016] In this specification and the drawings, when collectively representing a plurality of identical or similar configurations, the same reference numerals are used. When separately representing each of these plurality of configurations, they may be represented with appended lowercase or uppercase alphabets. Also, when separately representing a plurality of parts within one configuration, hyphens and natural numbers may be used.

[0017] The following embodiments can be combined with each other as long as no technical contradiction occurs.

[0018] <First Embodiment> FIG. 1 is a schematic cross-sectional view showing the configuration of a transistor 10 according to an embodiment of the present invention.

[0019] As shown in FIG. 1, the transistor 10 includes an amorphous substrate 100, a conductive alignment layer 105, a heterojunction structure 110, a source electrode 120, a drain electrode 125, a gate insulating layer 130, and a gate electrode 135. The conductive alignment layer 105 is provided on the amorphous substrate 100. The heterojunction structure 110 is provided on the conductive alignment layer 105. The heterojunction structure 110 includes a semiconductor layer 112 and a polarization layer 114 in contact with the semiconductor layer 112, and the semiconductor layer 112 is in contact with the conductive alignment layer 105. The source electrode 120 and the drain electrode 125 are provided on the semiconductor layer 112 and are in contact with the semiconductor layer 112. The gate electrode 135 is provided on the polarization layer 114. The gate insulating layer 130 is provided between the polarization layer 114 and the gate electrode 135.

[0020] In the polarization layer 114 of the heterojunction structure 110, a concave portion is provided in a region overlapping with the gate electrode 135. That is, in the polarization layer 114, the film thickness of the region overlapping with the gate electrode 135 is smaller than the film thickness of the region not overlapping with the gate electrode 135. Also, a gate insulating layer 130 is provided in the concave portion of the polarization layer 114. The gate insulating layer 130 may be provided so as to be filled in the concave portion or may be provided so as to cover the concave portion. Note that the concave portion can be formed by etching or the like.

[0021] The amorphous substrate 100 is a support substrate of the transistor 10 including the heterojunction structure 110. Although details will be described later, since the semiconductor layer 112 and the polarization layer 114 of the heterojunction structure 110 are formed by sputtering, the amorphous substrate 100 may have, for example, a heat resistance of about 600°C. Therefore, as the amorphous substrate 100, for example, an amorphous glass substrate can be used. Also, as the amorphous substrate 100, resin substrates such as a polyimide substrate, an acrylic substrate, a siloxane substrate, or a fluororesin substrate can also be used. Such an amorphous glass substrate or resin substrate is a substrate that can be made large in area. Note that a polycrystalline substrate can also be used instead of the amorphous substrate 100. In the formation of the transistor 10, since the semiconductor layer 112 of the heterojunction structure 110 is crystal-grown on the conductive alignment layer 105, an amorphous glass substrate, a resin substrate, or a polycrystalline substrate larger than the sapphire substrate used in the normal film formation of a gallium nitride film can be used as the support substrate of the transistor 10.

[0022] Although not shown, a base layer may be provided on the amorphous substrate 100. The base layer can prevent the diffusion of impurities from the amorphous substrate 100 or external impurities (for example, moisture or sodium (Na), etc.). For example, as the base layer, a silicon nitride (SiN x ) film or the like can be used. Also, as the base layer, a laminated film of a silicon oxide (SiO x ) film and a silicon nitride (SiN x ) film can also be used.

[0023] The conductive alignment layer 105 can improve the crystallinity of the semiconductor layer 112 formed on the conductive alignment layer 105. Specifically, the conductive alignment layer 105 can control the c-axis of the film formed on the conductive alignment layer 105 to grow in the film thickness direction. In other words, the conductive alignment layer 105 can control the semiconductor layer 112 to have c-axis orientation. For example, when the semiconductor layer 112 is a gallium nitride film, the gallium nitride film having a hexagonal close-packed structure grows in the c-axis direction to minimize the surface energy. However, by forming a gallium nitride film on the conductive alignment layer 105, the crystal growth of the gallium nitride film in the c-axis direction is promoted. As the conductive alignment layer 105, a conductive material having a hexagonal close-packed structure, a face-centered cubic structure, or a structure similar thereto can be used. Here, the structure similar to the hexagonal close-packed structure or the face-centered cubic structure includes a crystal structure in which the c-axis is not 90° with respect to the a-axis and the b-axis. The conductive alignment layer 105 using a conductive material having a hexagonal close-packed structure or a structure similar thereto is oriented in the (0001) direction, that is, the c-axis direction, with respect to the amorphous substrate 100 (hereinafter referred to as the (0001) orientation of the hexagonal close-packed structure). In addition, the conductive alignment layer 105 using a material having a face-centered cubic structure or a structure similar thereto is oriented in the (111) direction with respect to the amorphous substrate 100 (hereinafter referred to as the (111) orientation of the face-centered cubic structure). Since the conductive alignment layer 105 has the (0001) orientation of the hexagonal close-packed structure or the (111) orientation of the face-centered cubic structure, the crystal growth of the gallium nitride film formed on the conductive alignment layer 105 in the c-axis direction is promoted, and the semiconductor layer 112 has a highly crystalline c-axis orientation. Note that the semiconductor layer 112 is not limited to a gallium nitride film.

[0024] The crystallinity of the semiconductor layer 112 on the conductive alignment layer 105 is affected by the surface state of the conductive alignment layer 105. Therefore, the conductive alignment layer 105 preferably has a surface with few irregularities and is smooth. For example, the arithmetic mean roughness (Ra) of the surface of the conductive alignment layer 105 is preferably less than 2.3 nm. Also, the root mean square roughness (Rq) of the surface of the conductive alignment layer 105 is preferably less than 2.9 nm. When the surface roughness of the conductive alignment layer 105 satisfies the above conditions, the semiconductor layer 112 has a higher crystalline c-axis orientation. Note that the film thickness of the conductive alignment layer 105 is preferably 50 nm or more.

[0025] The conductive alignment layer 105 has conductivity. As the conductive alignment layer 105, for example, titanium (Ti), titanium nitride (TiN x ), titanium oxide (TiO x ), graphene, zinc oxide (ZnO), magnesium diboride (MgB2), aluminum (Al), silver (Ag), calcium (Ca), nickel (Ni), copper (Cu), strontium (Sr), rhodium (Rh), palladium (Pd), cerium (Ce), ytterbium (Yb), iridium (Ir), platinum (Pt), gold (Au), lead (Pb), actinium (Ac), thorium (Th), BiLaTiO, SrFeO, BiFeO, BaFeO, ZnFeO, or PMnN-PZT, etc. can be used. In particular, it is preferable to use titanium, graphene, or zinc oxide as the conductive alignment layer 105. Note that the conductive alignment layer 105 can be formed using any method (apparatus) such as sputtering or CVD.

[0026] The heterojunction structure 110 has a structure in which a semiconductor layer 112 containing a first compound semiconductor and a polarization layer 114 containing a second compound semiconductor different from the first compound semiconductor are in contact with each other. That is, in the heterojunction structure 110, a heterojunction having a band discontinuity is formed between the first compound semiconductor and the second compound semiconductor, and a two-dimensional electron gas (2DEG) 116 with a high concentration and high mobility is generated at the junction interface due to spontaneous polarization and the piezoelectric effect. However, as described above, in the transistor 10, a recess overlapping with the gate electrode 135 is provided in the polarization layer 114, and the polarization layer 114 includes a region with a small film thickness. In this region, since the piezoelectric effect is weakened, the concentration of the two-dimensional electron gas 116 formed in the semiconductor layer 112 decreases or disappears. Therefore, in the region of the semiconductor layer 112 overlapping with the gate electrode 135, the leakage current between the two-dimensional electron gas 116 and the conductive alignment layer 105 can be suppressed. On the other hand, in the region of the semiconductor layer 112 that does not overlap with the gate electrode 135 (that is, does not overlap with the recess of the polarization layer 114), the concentration of the two-dimensional electron gas 116 is kept high due to the piezoelectric effect. Therefore, in the transistor 10, the short-channel effect can be reduced while suppressing the parasitic resistance of the source electrode 120 and the drain electrode 125. Also, when a voltage is applied to the gate electrode 135, a channel of the two-dimensional electron gas 116 is formed, so the transistor 10 has the property of normally-off type (enhancement type).

[0027] Each of the first compound semiconductor and the second compound semiconductor is, for example, gallium nitride (GaN) and aluminum gallium nitride (AlGaN), but is not limited thereto. As described above, since the semiconductor layer 112 is formed on the conductive alignment layer 105, the semiconductor layer 112 has a highly crystalline c-axis orientation. Also, since the polarization layer 114 is formed on the semiconductor layer 112 having a highly crystalline c-axis orientation, the polarization layer 114 also has a highly crystalline c-axis orientation.

[0028] Here, as an example of the formation of the semiconductor layer 112 or the polarization layer 114, the film formation of a gallium nitride film using sputtering will be described.

[0029] An amorphous substrate 100 is disposed in a vacuum chamber facing a gallium nitride target. The composition ratio of gallium nitride in the gallium nitride target is preferably such that the ratio of gallium to nitrogen is 0.7 or more and 2 or less. Further, nitrogen can be supplied to the vacuum chamber separately from the sputtering gas (such as argon (Ar) or krypton (Kr)). In that case, the composition ratio of gallium nitride in the gallium nitride target is preferably such that gallium is more than nitrogen. For example, nitrogen can be supplied using a nitrogen radical source. The sputtering power supply may be any of a DC power supply, an RF power supply, or a pulsed DC power supply.

[0030] The amorphous substrate 100 in the vacuum chamber may be heated. For example, the amorphous substrate 100 can be heated at a temperature of room temperature or higher and less than 600 °C, preferably 100 °C or higher and 400 °C or lower. At this temperature, it can also be applied to an amorphous glass substrate with low heat resistance. Further, this temperature is lower than the film formation temperature in MOCVD or HVPE.

[0031] After sufficiently evacuating the inside of the vacuum chamber, a sputtering gas is supplied. Further, a voltage is applied between the amorphous substrate 100 and the gallium nitride target at a predetermined pressure to generate plasma, and a gallium nitride film is formed.

[0032] As described above, the method for forming a gallium nitride film by sputtering has been described, but the configuration or conditions of sputtering can be appropriately changed. Note that if an aluminum gallium nitride target is used instead of a gallium nitride target, an aluminum gallium nitride film can be formed. Further, if a gallium nitride target doped with magnesium is used, a p-type gallium nitride film (p-type semiconductor film) can be formed.

[0033] Each of the source electrode 120 and the drain electrode 125 can be made of a metal such as, for example, aluminum (Al), titanium (Ti), platinum (Pt), nickel (Ni), tantalum (Ta), or gold (Au), or an alloy thereof. Each of the source electrode 120 and the drain electrode 125 may be a single film or a laminated film.

[0034] Each of the source electrode 120 and the drain electrode 125 may be provided on the semiconductor layer 112 or embedded in the semiconductor layer 112. Also, each of the source electrode 120 and the drain electrode 125 may be provided on the polarization layer 114 or embedded in the polarization layer 114.

[0035] The gate insulating layer 130 can be made of, for example, silicon oxide (SiO x ), aluminum oxide (AlO x ), hafnium oxide (HfO x ), lanthanum oxide (LaO x ), silicon nitride (SiN x ), or aluminum nitride (AlN x ), etc. The gate insulating layer 130 may be a single film or a laminated film.

[0036] The gate electrode 135 can be made of a metal such as, for example, aluminum (Al), titanium (Ti), platinum (Pt), nickel (Ni), tantalum (Ta), or gold (Au), or an alloy thereof. The gate electrode 135 may be a single film or a laminated film.

[0037] Note that the transistor 10 may be configured without the gate insulating layer 130 provided. In this case, the gate electrode 135 is in contact with the polarization layer 114 and functions as a so-called Schottky gate electrode.

[0038] As described above, the transistor 10 includes a heterojunction structure 110 with controlled crystallinity on the conductive alignment layer 105. The polarization layer 114 of the heterojunction structure 110 overlaps with the gate electrode 135 and includes a region with a small film thickness (a region where a recess is provided). Therefore, in the transistor 10, the piezoelectric effect in the region where the polarization layer 114 overlaps with the gate electrode 135 is weakened, and the leakage current between the two-dimensional electron gas 116 formed in the semiconductor layer 112 and the conductive alignment layer 105 can be suppressed. Also, when a voltage is applied to the gate electrode 135, a channel of the two-dimensional electron gas 116 is formed. Therefore, the transistor 10 has the property of being normally-off (enhancement type).

[0039] <Second Embodiment> FIG. 2 is a schematic cross-sectional view showing the configuration of a transistor 20 according to an embodiment of the present invention. Hereinafter, when the configuration of the transistor 20 is the same as that of the transistor 10, the description of the configuration of the transistor 20 may be omitted.

[0040] As shown in FIG. 2, the transistor 20 includes an amorphous substrate 200, a conductive alignment layer 205, a heterojunction structure 210, a source electrode 220, a drain electrode 225, a p-type semiconductor layer 240, and a gate electrode 235. The conductive alignment layer 205 is provided on the amorphous substrate 200. The heterojunction structure 210 is provided on the conductive alignment layer 205. The heterojunction structure 210 includes a semiconductor layer 212 and a polarization layer 214 in contact with the semiconductor layer 212, and the semiconductor layer 212 is in contact with the conductive alignment layer 205. The source electrode 220 and the drain electrode 225 are provided on the semiconductor layer 212 and are in contact with the semiconductor layer 212. The gate electrode 235 is provided on the polarization layer 214. The p-type semiconductor layer 240 overlaps with the gate electrode 235 and is provided between the polarization layer 214 and the gate electrode 235. Also, the p-type semiconductor layer 240 is in contact with the polarization layer 214.

[0041] The p-type semiconductor layer 240, by contacting the polarization layer 214, can cause holes in the p-type semiconductor layer 240 to reduce the polarity of the polarization layer 214 and weaken the piezoelectric effect of the polarization layer 214. As a result, the concentration of the two-dimensional electron gas 216 in the region overlapping with the gate electrode 235 of the semiconductor layer 212 decreases or disappears. Therefore, in the region of the semiconductor layer 212 that overlaps with the gate electrode 235, the leakage current between the two-dimensional electron gas 216 and the conductive alignment layer 205 can be suppressed. On the other hand, in the region of the semiconductor layer 212 that does not overlap with the p-type semiconductor layer 240, the concentration of the two-dimensional electron gas 216 is kept high due to the piezoelectric effect. Therefore, in the transistor 20, the short-channel effect can be reduced while suppressing the parasitic resistance of the source electrode 220 and the drain electrode 225. Also, when a voltage is applied to the gate electrode 235, a channel of the two-dimensional electron gas 216 is formed, so the transistor 20 has the property of being normally-off (enhancement type).

[0042] As described above, the transistor 20 includes a heterojunction structure 210 with controlled crystallinity on the conductive alignment layer 205, and the polarization layer 214 of the heterojunction structure 210 contacts a p-type semiconductor layer 240 that overlaps with the gate electrode 235. Therefore, in the transistor 20, the piezoelectric effect in the region of the polarization layer 214 that overlaps with the gate electrode 235 is weakened, and the leakage current between the two-dimensional electron gas 216 formed in the semiconductor layer 212 and the conductive alignment layer 205 can be suppressed. Also, when a voltage is applied to the gate electrode 235, a channel of the two-dimensional electron gas 216 is formed, so the transistor 20 has the property of being normally-off (enhancement type).

[0043] <Third Embodiment> FIG. 3 is a schematic cross-sectional view showing the configuration of a transistor 30 according to an embodiment of the present invention. Hereinafter, when the configuration of the transistor 30 is the same as that of the transistor 10, the description of the configuration of the transistor 30 may be omitted.

[0044] As shown in FIG. 3, the transistor 30 includes an amorphous substrate 300, a conductive alignment layer 305, a semiconductor layer 312, a source electrode 320, a drain electrode 325, a gate insulating layer 330, a gate electrode 335, an insulating layer 345, and a polarization layer 314. The conductive alignment layer 305 is provided on the amorphous substrate 300. The semiconductor layer 312 is provided on the conductive alignment layer 305 and is in contact with the conductive alignment layer 305. The source electrode 320 and the drain electrode 325 are provided on the semiconductor layer 312 and are in contact with the semiconductor layer 312. The gate electrode 335 is provided on the semiconductor layer 312. The gate insulating layer 330 is provided between the semiconductor layer 312 and the gate electrode 335. The insulating layer 345 covers the gate insulating layer 330 and the gate electrode 335. The polarization layer 314 covers the insulating layer 345 and is in contact with the semiconductor layer 312 between the source electrode 320 and the drain electrode 325.

[0045] In the manufacture of the transistor 30, the polarization layer 314 is formed after the source electrode 320 and the drain electrode 325 are formed, but it is not limited thereto. The source electrode 320 and the drain electrode 325 may be formed after the polarization layer 314 is formed.

[0046] In the polarization layer 314, the region that does not overlap with the gate electrode 335 is in contact with the semiconductor layer 312, and the region that overlaps with the gate electrode 335 is not in contact with the semiconductor layer 312. Therefore, a two-dimensional electron gas 316 is not formed in the region of the semiconductor layer 312 that overlaps with the gate electrode 335. Therefore, the leakage current between the two-dimensional electron gas 316 and the conductive alignment layer 305 can be suppressed in the region of the semiconductor layer 312 that overlaps with the gate electrode 335. On the other hand, in the region of the semiconductor layer 312 that is in contact with the polarization layer 314, the concentration of the two-dimensional electron gas 316 is kept high due to the piezoelectric effect. Therefore, in the transistor 30, the short-channel effect can be reduced while suppressing the parasitic resistance of the source electrode 320 and the drain electrode 325. Further, when a voltage is applied to the gate electrode 335, a channel of the two-dimensional electron gas 316 is formed, so that the transistor 30 has the property of being normally-off (enhancement type).

[0047] The insulating layer 345 can function as a protective film for the gate insulating layer 330 and the gate electrode 335, and can also function as an underlying film for the polarization layer 314. As the insulating layer 345, for example, silicon oxide (SiO x ), aluminum oxide (AlO x ), hafnium oxide (HfO x ), lanthanum oxide (LaO x ), silicon nitride (SiN x ), or aluminum nitride (AlN x ) can be used. The insulating layer 345 may be a single layer or a laminated layer.

[0048] Note that the transistor 30 may be configured without the insulating layer 345. In this case, since the source electrode 320, the drain electrode 325, and the gate electrode 335 can be formed by processing a single film, the manufacturing process can be shortened and the manufacturing cost can be suppressed.

[0049] As described above, the transistor 30 includes the heterojunction structure 310 with controlled crystallinity on the conductive alignment layer 305, and the semiconductor layer 312 and the polarization layer 314 are not in contact in the region overlapping with the gate electrode 335. Therefore, in the transistor 30, the formation of the two-dimensional electron gas 316 in the region of the semiconductor layer 312 overlapping with the gate electrode 335 is suppressed, and the leakage current between the two-dimensional electron gas 316 and the conductive alignment layer 305 can be suppressed. Also, when a voltage is applied to the gate electrode 335, a channel of the two-dimensional electron gas 316 is formed, so the transistor 30 has the property of being normally-off (enhancement type).

[0050] <Fourth Embodiment> FIG. 4 is a schematic cross-sectional view showing the configuration of a transistor 40 according to an embodiment of the present invention. Hereinafter, when the configuration of the transistor 40 is the same as that of the transistor 10, the description of the configuration of the transistor 40 may be omitted.

[0051] As shown in FIG. 4, the transistor 40 includes an amorphous substrate 400, a conductive alignment layer 405, a heterojunction structure 410, a source electrode 420, a drain electrode 425, a gate insulating layer 430, and a gate electrode 435. The conductive alignment layer 405 is provided on the amorphous substrate 400. The heterojunction structure 410 is provided on the conductive alignment layer 405. The heterojunction structure 410 includes a semiconductor layer 412 and a polarization layer 414 in contact with the semiconductor layer 412, and the polarization layer 414 is in contact with the conductive alignment layer 405. The source electrode 420 and the drain electrode 425 are provided on the polarization layer 414 and in contact with the polarization layer 414. Also, the source electrode 420 and the drain electrode 425 are in contact with the semiconductor layer 412. The gate electrode 435 is provided on the semiconductor layer 412. The gate insulating layer 430 is provided between the semiconductor layer 412 and the gate electrode 435.

[0052] In the polarization layer 414 of the heterojunction structure 410, a recess is provided in a region overlapping with the gate electrode 435. That is, in the polarization layer 414, the film thickness of the region overlapping with the gate electrode 435 is smaller than the film thickness of the region not overlapping with the gate electrode 435. Also, the semiconductor layer 412 is provided so as to cover the recess of the polarization layer 414.

[0053] In the semiconductor layer 412 of the heterojunction structure 410, a recess is provided in a region overlapping with the gate electrode 435. However, the recess of the semiconductor layer 412 is formed by covering the recess of the polarization layer 414. Therefore, in the semiconductor layer 412, the film thickness of the region overlapping with the gate electrode 435 may be substantially the same as the film thickness of the region not overlapping with the gate electrode 435. Also, the gate insulating layer 430 is provided in the recess of the semiconductor layer 412. The gate insulating layer 430 may be provided so as to fill a part of the recess, or may be provided so as to cover the recess.

[0054] In the transistor 40, a polarization layer 414 exists between a semiconductor layer 412 in which a two-dimensional electron gas 416 is formed and a conductive alignment layer 405. Since the polarization layer 414 is an insulator, it has a higher breakdown voltage than the semiconductor layer 412. Further, in the heterojunction structure 410, the polarization layer 414 includes a recess with a small film thickness, and the piezoelectric effect is weakened in the recess, so that the concentration of the two-dimensional electron gas 416 formed in the region overlapping with the gate electrode 435 of the semiconductor layer 412 is reduced or has disappeared. Therefore, in the transistor 40, the leakage current between the two-dimensional electron gas 416 and the conductive alignment layer 405 can be suppressed.

[0055] As described above, the transistor 40 includes a heterojunction structure 410 with controlled crystallinity on the conductive alignment layer 405, and includes a polarization layer 414 with a high breakdown voltage between the semiconductor layer 412 and the conductive alignment layer 405. Therefore, in the transistor 40, not only can the leakage current between the two-dimensional electron gas 416 and the conductive alignment layer 405 be suppressed, but also the leakage current between the source electrode 420 or the drain electrode 425 and the conductive alignment layer 405 can be suppressed. Further, when a voltage is applied to the gate electrode 435, a channel of the two-dimensional electron gas 416 is formed, so that the transistor 40 has a normally-off type (enhancement type) property.

[0056] <Fifth Embodiment> FIG. 5 is a schematic cross-sectional view showing the configuration of a transistor 50 according to an embodiment of the present invention. Hereinafter, when the configuration of the transistor 50 is the same as that of the transistor 20, the description of the configuration of the transistor 50 may be omitted.

[0057] As shown in FIG. 5, the transistor 50 includes an amorphous substrate 500, a conductive alignment layer 505, a p-type semiconductor layer 540, a heterojunction structure 510, a source electrode 520, a drain electrode 525, a gate insulating layer 530, and a gate electrode 535. The conductive alignment layer 505 is provided on the amorphous substrate 500. The p-type semiconductor layer 540 overlaps with the gate electrode 535 and is provided on the conductive alignment layer 505. The heterojunction structure 510 covers the p-type semiconductor layer 540 and is provided on the conductive alignment layer 505. The heterojunction structure 510 includes a semiconductor layer 512 and a polarization layer 514 in contact with the semiconductor layer 512, and the polarization layer 514 is in contact with the p-type semiconductor layer 540 and the conductive alignment layer 505. The source electrode 520 and the drain electrode 525 are provided on the polarization layer 514 and are in contact with the polarization layer 514. Also, the source electrode 520 and the drain electrode 525 are in contact with the semiconductor layer 512. The gate electrode 535 is provided on the semiconductor layer 512. The gate insulating layer 530 is provided between the semiconductor layer 512 and the gate electrode 535.

[0058] In the transistor 50, a p-type semiconductor layer 540 that overlaps with the gate electrode 535 and is in contact with the polarization layer 514 is provided. Therefore, the concentration of the two-dimensional electron gas 516 in the region of the semiconductor layer 512 that overlaps with the gate electrode 535 decreases or disappears. Therefore, in the region of the semiconductor layer 512 that overlaps with the gate electrode 535, the leakage current between the two-dimensional electron gas 516 and the conductive alignment layer 505 can be suppressed. Also, in the transistor 50, a polarization layer 514 exists between the semiconductor layer 512 in which the two-dimensional electron gas 516 is formed and the conductive alignment layer 505. Since the polarization layer 514 is an insulator, it has a higher breakdown voltage than the semiconductor layer 512. Therefore, in the transistor 50, the leakage current between the two-dimensional electron gas 516 and the conductive alignment layer 505 can be suppressed.

[0059] As described above, the transistor 50 includes a heterojunction structure 510 with controlled crystallinity on the conductive alignment layer 505, and the polarization layer 514 of the heterojunction structure 510 is in contact with a p-type semiconductor layer 540 that overlaps with the gate electrode 535. Therefore, in the transistor 50, the piezoelectric effect in the region of the polarization layer 514 that overlaps with the gate electrode 535 is weakened, and the leakage current between the two-dimensional electron gas 516 formed in the semiconductor layer 512 and the conductive alignment layer 505 can be suppressed. Also, when a voltage is applied to the gate electrode 535, a channel of the two-dimensional electron gas 516 is formed, so the transistor 50 has the property of being normally-off (enhancement type). Furthermore, the transistor 50 includes a polarization layer 514 with high breakdown voltage between the semiconductor layer 512 and the conductive alignment layer 505. Therefore, in the transistor 50, not only can the leakage current between the two-dimensional electron gas 516 and the conductive alignment layer 505 be suppressed, but also the leakage current between the source electrode 520 or the drain electrode 525 and the conductive alignment layer 505 can be suppressed.

[0060] <Sixth Embodiment> FIG. 6 is a schematic cross-sectional view showing the configuration of a transistor 60 according to an embodiment of the present invention. In the following, when the configuration of the transistor 60 is the same as that of the transistor 10, the description of the configuration of the transistor 60 may be omitted.

[0061] As shown in FIG. 6, the transistor 60 includes an amorphous substrate 600, a conductive alignment layer 605, a crystalline insulating layer 650, a heterojunction structure 610, a source electrode 620, a drain electrode 625, a gate insulating layer 630, and a gate electrode 635. The conductive alignment layer 605 is provided on the amorphous substrate 600. The crystalline insulating layer 650 is provided on the conductive alignment layer 605. The heterojunction structure 610 is provided on the crystalline insulating layer 650. The heterojunction structure 610 includes a semiconductor layer 612 and a polarization layer 614 in contact with the semiconductor layer 612, and the semiconductor layer 612 is in contact with the conductive alignment layer 605. The source electrode 620 and the drain electrode 625 are provided on the semiconductor layer 612 and are in contact with the semiconductor layer 612. The gate electrode 635 is provided on the polarization layer 614. The gate insulating layer 630 is provided between the polarization layer 614 and the gate electrode 635.

[0062] The crystalline insulating layer 650 can electrically insulate the conductive alignment layer 605 and the semiconductor layer 612. By providing the crystalline insulating layer 650 between the conductive alignment layer 605 and the semiconductor layer 612, the leakage current between the two-dimensional electron gas 616 formed in the semiconductor layer 612 and the conductive alignment layer 605 can be suppressed. Further, since the crystalline insulating layer 650 serves as an underlying film for the semiconductor layer 612, it preferably has a crystal structure that does not inhibit the crystal growth of the semiconductor layer 612. As the crystalline insulating layer 650, for example, aluminum nitride (AlN x ), aluminum oxide (AlO x ), or gallium oxide (GaO x ) etc. can be used.

[0063] As described above, the transistor 60 includes a crystalline insulating layer 650 that does not inhibit the crystal growth of the semiconductor layer 612 between the conductive alignment layer 605 and the semiconductor layer 612. Therefore, in the transistor 60, the leakage current between the two-dimensional electron gas 616 formed in the semiconductor layer 612 and the conductive alignment layer 605 can be suppressed.

[0064] <Embodiment 7> FIG. 7A and FIG. 7B are a schematic cross-sectional view and a plan view, respectively, showing the configuration of a transistor 70 according to an embodiment of the present invention. In FIG. 7B, for convenience, a part of the configuration of the transistor 70 is shown. Hereinafter, when the configuration of the transistor 70 is the same as that of the transistor 10, the description of the configuration of the transistor 70 may be omitted.

[0065] As shown in FIG. 7A, the transistor 70 includes an amorphous substrate 700, a conductive alignment layer 705, a heterojunction structure 710, a source electrode 720, a drain electrode 725, a gate insulating layer 730, and a gate electrode 735. The conductive alignment layer 705 is provided on the amorphous substrate 700. The heterojunction structure 710 is provided on the conductive alignment layer 705. The heterojunction structure 710 includes a semiconductor layer 712 and a polarization layer 714 in contact with the semiconductor layer 712, and the semiconductor layer 712 is in contact with the conductive alignment layer 705. The source electrode 720 and the drain electrode 725 are provided on the semiconductor layer 712 and are in contact with the semiconductor layer 712. The gate electrode 735 is provided on the polarization layer 714. The gate insulating layer 730 is provided between the polarization layer 714 and the gate electrode 735.

[0066] As shown in FIG. 7B, the conductive alignment layer 705 is divided into a plurality of parts by the groove portion 707. That is, in a plan view, the groove portion 707 is provided between the source electrode 720 and the gate electrode 735 and between the gate electrode 735 and the drain electrode 725, and is divided into three conductive alignment layers 705 (the first conductive alignment layer 705-1, the second conductive alignment layer 705-2, and the third conductive alignment layer 705-3). Specifically, the first conductive alignment layer 705-1 overlaps with the source electrode 720. The second conductive alignment layer 705-2 overlaps with the gate electrode 735. The third conductive alignment layer 705-3 overlaps with the drain electrode 725. Also, the first conductive alignment layer 705-1, the second conductive alignment layer 705-2, and the third conductive alignment layer 705-3 are electrically insulated from each other. Therefore, even if a leakage current occurs between the two-dimensional electron gas 716 formed in the region overlapping with the gate electrode 735 of the semiconductor layer 712 and the conductive alignment layer 705, this leakage current is not electrically connected to the source electrode 720 or the drain electrode 725. That is, in the transistor 70, the leakage current between the source electrode 720 and the drain electrode 725 through the conductive alignment layer 705 is suppressed.

[0067] Note that the number of divisions of the conductive alignment layer 705 is not limited to three. However, the number of divisions of the conductive alignment layer 705 is preferably three or more so that the leakage current between the source electrode 720, the gate electrode 735, or the drain electrode 725 and the conductive alignment layer 705 can be separated. Also, the shape of the conductive alignment layer 705 may be a strip shape extending in one direction, or may be a rectangular shape partitioned in a grid pattern.

[0068] As described above, in the transistor 70, since the conductive alignment layer 705 is divided, the leakage current between the source electrode 720 and the drain electrode 725 through the conductive alignment layer 705 is suppressed. Also, since the conductive alignment layer 705 is divided, the parasitic capacitance generated by the conductive alignment layer 705 can be reduced.

[0069] <Eighth Embodiment> FIG. 8 is a schematic cross-sectional view showing the configuration of a transistor 80 according to an embodiment of the present invention. Hereinafter, when the configuration of the transistor 80 is the same as that of the transistor 70, the description of the configuration of the transistor 80 may be omitted.

[0070] As shown in FIG. 8, the transistor 80 includes an amorphous substrate 800, a first conductive alignment layer 805-1, a second conductive alignment layer 805-2, a third conductive alignment layer 805-3, a heterojunction structure 810, a source electrode 820, and a drain electrode 825. The first conductive alignment layer 805-1, the second conductive alignment layer 805-2, and the third conductive alignment layer 805-3 are provided on the amorphous substrate 800. The heterojunction structure 810 is provided on the first conductive alignment layer 805-1, the second conductive alignment layer 805-2, and the third conductive alignment layer 805-3. The heterojunction structure 810 includes a semiconductor layer 812 and a polarization layer 814 in contact with the semiconductor layer 812, and the polarization layer 814 is in contact with the conductive alignment layer 805. The source electrode 820 and the drain electrode 825 are provided on the polarization layer 814. Further, the source electrode and the drain electrode 825 are in contact with the semiconductor layer 812.

[0071] A groove portion 807 is provided between the first conductive alignment layer 805-1 and the second conductive alignment layer 805-2 and between the second conductive alignment layer 805-2 and the third conductive alignment layer 805-3. In other words, the conductive alignment layer 805 is divided into three. Further, the first conductive alignment layer 805-1, the second conductive alignment layer 805-2, and the third conductive alignment layer 805-3 are electrically insulated from each other. In the transistor 80, although no gate electrode is provided, the second conductive alignment layer 805-2 functions as a gate electrode. That is, by applying a voltage to the second conductive alignment layer 805-2, a two-dimensional electron gas 816 is formed.

[0072] As described above, in the transistor 80, since the conductive alignment layer 805 is divided, the leakage current between the source electrode 820 and the drain electrode 825 through the conductive alignment layer 805 is suppressed. Further, since the conductive alignment layer 805 is divided, the parasitic capacitance generated by the conductive alignment layer 805 can be reduced. Also, since the second conductive alignment layer 805-2, which is one of the divided conductive alignment layers 805, functions as a gate electrode, there is no need to separately provide a gate electrode. Furthermore, the transistor 80 includes a heterojunction structure 810 with controlled crystallinity on the conductive alignment layer 805, and includes a polarization layer 814 with high breakdown voltage between the semiconductor layer 812 and the conductive alignment layer 805. Therefore, in the transistor 80, not only can the leakage current between the two-dimensional electron gas 816 and the conductive alignment layer 805 be suppressed, but also the leakage current between the source electrode 820 and the first conductive alignment layer 805-1 and the leakage current between the drain electrode 825 and the third conductive alignment layer 805-3 can be suppressed.

[0073] As described above, each of the embodiments described as embodiments of the present invention can be implemented in appropriate combination as long as they do not contradict each other. Also, based on each embodiment, those in which those skilled in the art appropriately add, delete, or change the design of components, or those in which they add, omit, or change the conditions of processes, are also included in the scope of the present invention as long as they have the gist of the present invention.

[0074] Even if there are other operational effects different from those brought about by the above-described embodiments, those that are obvious from the description in this specification or can be easily predicted by those skilled in the art are naturally understood to be brought about by the present invention.

Description of Reference Numerals

[0075] 10: Transistor, 100: Amorphous substrate, 105: Conductive alignment layer, 110: Heterojunction structure, 112: Semiconductor layer, 114: Polarization layer, 116: Two-dimensional electron gas, 120: Source electrode, 125: Drain electrode, 130: Gate insulating layer, 135: Gate electrode 20: Transistor, 200: Amorphous substrate, 205: Conductive alignment layer, 210: Heterojunction structure, 212: Semiconductor layer, 214: Polarization layer, 216: Two-dimensional electron gas, 220: Source electrode, 225: Drain electrode, 235: Gate electrode, 240: p-type semiconductor layer 30: Transistor, 300: Amorphous substrate, 305: Conductive alignment layer, 312: Semiconductor layer, 314: Polarization layer, 316: Two-dimensional electron gas, 320: Source electrode, 325: Drain electrode, 330: Gate insulating layer, 335: Gate electrode, 345: Insulating layer 40: Transistor, 400: Amorphous substrate, 405: Conductive alignment layer, 410: Heterojunction structure, 412: Semiconductor layer, 414: Polarization layer, 416: Two-dimensional electron gas, 420: Source electrode, 425: Drain electrode, 430: Gate insulating layer, 435: Gate electrode 50: Transistor, 500: Amorphous substrate, 505: Conductive alignment layer, 510: Heterojunction structure, 512: Semiconductor layer, 514: Polarization layer, 516: Two-dimensional electron gas, 520: Source electrode, 525: Drain electrode, 530: Gate insulating layer, 535: Gate electrode, 540: p-type semiconductor layer 60: Transistor, 600: Amorphous substrate, 605: Conductive alignment layer, 610: Heterojunction structure, 612: Semiconductor layer, 614: Polarization layer, 616: Two-dimensional electron gas, 620: Source electrode, 625: Drain electrode, 630: Gate insulating layer, 635: Gate electrode, 650: Crystalline insulating layer 70: Transistor, 700: Amorphous substrate, 705: Conductive alignment layer, 707: Groove, 710: Heterojunction structure, 712: Semiconductor layer, 714: Polarization layer, 720: Source electrode, 725: Drain electrode, 730: Gate insulating layer, 735: Gate electrode 80: Transistor, 800: Amorphous substrate, 805: Conductive alignment layer, 807: Groove, 810: Heterojunction structure, 812: Semiconductor layer, 814: Polarization layer, 816: Two-dimensional electron gas, 820: Source electrode, 825: Drain electrode

Claims

1. An amorphous substrate; A conductive alignment layer on the amorphous substrate; A heterojunction structure including a semiconductor layer on the conductive alignment layer and a polarization layer in contact with the semiconductor layer; A gate electrode on the heterojunction structure, comprising: The heterojunction structure includes a recess in a region overlapping with the gate electrode; The conductive alignment layer is divided into a plurality of parts, a transistor.

2. The transistor according to claim 1, wherein a gate insulating layer is provided in the recess.

3. The transistor according to claim 1, wherein the recess is provided in the polarization layer.

4. The transistor according to claim 1, wherein the recess is provided in the semiconductor layer.

5. Furthermore, the transistor according to claim 1, including a crystalline insulating layer between the conductive alignment layer and the heterojunction structure.

6. An amorphous substrate; A conductive alignment layer on the amorphous substrate; A heterojunction structure including a semiconductor layer on the conductive alignment layer and a polarization layer in contact with the semiconductor layer; A gate electrode on the heterojunction structure; A p-type semiconductor layer overlapping with the gate electrode and in contact with the polarization layer, comprising: The conductive alignment layer is divided into a plurality of parts, a transistor.

7. The transistor according to claim 6, wherein the p-type semiconductor layer is provided between the gate electrode and the polarization layer.

8. The transistor according to claim 6, wherein the p-type semiconductor layer is provided between the conductive alignment layer and the polarization layer.

9. Furthermore, the transistor according to claim 6, including a crystalline insulating layer between the conductive alignment layer and the heterojunction structure.

10. An amorphous substrate; A conductive alignment layer on the amorphous substrate; A semiconductor layer on the conductive alignment layer; A gate electrode on the semiconductor layer; An insulating layer covering the gate electrode; A polarization layer covering the insulating layer and in contact with the semiconductor layer, a transistor.

11. The transistor according to claim 10, wherein the conductive alignment layer is divided into a plurality of parts.

12. The semiconductor layer includes gallium nitride, The polarization layer includes aluminum gallium nitride, the transistor according to any one of claims 1 to 11.

13. The transistor according to any one of claims 1 to 11, wherein the conductive alignment layer includes at least one selected from titanium, graphene, and zinc oxide.

14. The amorphous substrate is an amorphous glass substrate, the transistor according to any one of claims 1 to 11.

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