Semiconductor device, and method of manufacturing the same

Abstract

To provide a semiconductor device including an inductor having an improved performance, and a manufacturing method of the semiconductor device.SOLUTION: A semiconductor device includes: a circuit section formed on a semiconductor substrate; a first insulation film formed while covering at least a part of an area of the semiconductor substrate containing an upper part of the circuit section; re-wiring formed on the first insulation film; a coil formed on the first insulation film by rewiring and connected with the circuit section; a first soft magnetic film formed in an opening of the first insulation film arranged below the coil; and a second soft magnetic film formed on the first soft magnetic film while covering at least a part of the coil.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device.

Background Art

[0002] As one form of packaging of semiconductor devices, WL-CSP (Wafer Level-Chip Size Package) is known. WL-CSP is a type of ultra-small integrated circuit called CSP (Chip Size Package). CSP is basically a form of BGA (Ball Grid Arrey), which is a package in which the size of BGA is significantly reduced and is reduced to almost the same size as the semiconductor chip to be mounted. On the other hand, in WL-CSP, in the manufacturing process, a redistribution layer is formed on the pads on the circuit surface at the wafer level, and after sealing the surface with, for example, resin leaving the connection portions on the redistribution, it is singulated into individual chips. According to WL-CSP, there is an effect that the occupied area can be significantly reduced when mounting a semiconductor integrated circuit on a substrate such as a printed circuit board.

[0003] As a document disclosing a technology related to BGA, for example, Patent Document 1 is known. The fan-out semiconductor package module according to Patent Document 1 includes a core member having a first through hole and a second through hole spaced apart from each other, a semiconductor chip disposed in the first through hole and having an active surface on which connection pads are disposed and an inactive surface opposite to the active surface, a second passive component disposed in the second through hole, a first encapsulant covering at least a part of each of the core member and the second passive component and filling at least a part of the second through hole, a reinforcing member disposed on the first encapsulant, a second encapsulant covering at least a part of the semiconductor chip and filling at least a part of the first through hole, and a connecting member disposed on the core member, the active surface of the semiconductor chip, and the second passive component and including connection pads and a redistribution layer electrically connected to the second passive component.

[0004] On one hand, an inductor is an essential passive component for the circuits that make up a semiconductor device. The inductor may be formed by a spiral pattern (coil) on the circuit surface of the semiconductor device using a wiring material or the like. However, in that case, due to space limitations, there are limits to increasing, for example, the wiring length or the number of turns. Therefore, since the value of the inductance obtained is also limited, when an inductance value greater than a certain level is required, it is mounted separately from the semiconductor device as an individual component. In the fan-out semiconductor package module according to Patent Document 1, the inductor as a passive component is also arranged in the through-hole in the form of an individual component.

[0005] FIG. 11(a) shows a cross-sectional view of a semiconductor device 150 according to a comparative example in which an inductor region 100 according to the comparative example is formed inside. The "inductor region" refers to a region of a configuration that exhibits the function of an inductor in the semiconductor device 150. The semiconductor device 150 is manufactured using WL-CSP technology. As shown in FIG. 11(a), the semiconductor device 150 includes pads 12-1 and 12-2, a passivation film 13, vias 16-1 and 16-2, insulating films 14 and 15, rewiring 17, posts 18, solder terminals 19, and a mold 20 formed on a semiconductor substrate 11.

[0006] FIG. 11(b) shows a cross-sectional view of the inductor region 100. As shown in FIG. 11(b), the inductor region 100 includes a semiconductor substrate 11, pads 12-3 and 12-4, a passivation film 13, vias 16-3 and 16-4, an insulating film 25, rewiring 17, and a mold 20. However, the insulating film 25 represents the insulating films 14 and 15 in FIG. 11(a) as one film. The rewiring 17 is arranged in a spiral shape on the upper part of the insulating film 25 to form a coil 22. The vias 16-3 and 16-4 are connected to one end and the other end of the coil 22, respectively, and are connected to a circuit portion formed on a semiconductor chip (not shown) via the pads 12-3 and 12-4. Here, the "semiconductor chip" refers to the semiconductor element in the state before rewiring in the semiconductor device 150.

Prior Art Documents

Patent Document

[0007]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0008] In the WL-CSP, it would be extremely convenient if an inductor could be mounted inside the semiconductor device. However, until now, only inductors with limited inductance values in limited fields such as communication have been mounted inside the semiconductor device. That is, there was a limit to the inductance value of the inductor region 100 of the semiconductor device 150. Among inductors, inductors for high-power applications such as power circuits (hereinafter, "power inductors") are particularly required to have a small wiring resistance and to be able to secure a desired inductance value. Therefore, conventionally, power inductors have been arranged as individual components outside the semiconductor device. As a result, there has been a limit to the reduction of the occupied area of the semiconductor device and its related components. For example, in order to be mounted in the WL-CSP like the semiconductor device 150, an improvement in its performance (inductance, wiring resistance, etc.) has been required when compared with inductors of the same shape and occupied area.

[0009] In view of the above circumstances, an object of the present invention is to provide a semiconductor device including an inductor with improved performance and a method for manufacturing the semiconductor device.

Means for Solving the Problems

[0010] To solve the above problems, a semiconductor device according to the present invention includes a circuit portion formed on a semiconductor substrate, a first insulating film formed to cover at least a part of a region on the semiconductor substrate including the upper portion of the circuit portion, a rewiring formed on the first insulating film, a coil formed on the first insulating film by the rewiring and connected to the circuit portion, a first soft magnetic film formed in an opening of the first insulating film provided below the coil, and a second soft magnetic film formed on the first insulating film to cover at least a part of the coil.

[0011] To solve the above problems, a semiconductor device according to another aspect of the present invention includes a circuit portion formed on a semiconductor substrate, an insulating film formed to cover at least a part of a region on the semiconductor substrate including the upper portion of the circuit portion, a rewiring formed on the insulating film, a coil formed on the insulating film by the rewiring and connected to the circuit portion, and a soft magnetic film formed on the insulating film to cover at least a part of the coil.

[0012] To solve the above problems, a method of manufacturing a semiconductor device according to the present invention includes forming a circuit portion on a semiconductor substrate, forming a first insulating film in a region including the upper portion of the circuit portion except for a first predetermined region, forming a first soft magnetic film inside the first predetermined region, forming a coil connected to the circuit portion on the upper portion of the first soft magnetic film, forming a second insulating film in a region above the first insulating film except for a second predetermined region that overlaps at least a part of the first predetermined region in plan view, and forming a second soft magnetic film inside the second predetermined region.

[0013] In order to solve the above problems, a method for manufacturing a semiconductor device according to another aspect of the present invention forms a circuit portion on a semiconductor substrate, forms an insulating film in a region including the upper portion of the circuit portion and covering at least a part of the region on the semiconductor substrate, forms a first soft magnetic film on the insulating film, forms a coil connected to the circuit portion on the upper portion of the first soft magnetic film, and forms a second soft magnetic film covering at least a part of the coil on the first soft magnetic film.

Effect of the Invention

[0014] According to the present invention, there is an effect that a semiconductor device including an inductor with improved performance and a method for manufacturing the semiconductor device can be provided.

Brief Description of the Drawings

[0015]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Embodiments for Carrying Out the Invention

[0016] Hereinafter, with reference to the drawings, embodiments of the present invention will be described in detail. In the embodiments described below, a form in which the semiconductor device according to the present invention is applied to a semiconductor device including an inductor region will be exemplified and described. In the following embodiments, for the sake of convenience, the inductor region and the semiconductor device including the inductor region will be separately described. However, the semiconductor device according to the present embodiment may be in the form of an inductor alone or in a form including peripheral circuits. In the following embodiments, a form in which the inductor in the inductor region is applied particularly to a power inductor for high-power applications will be exemplified and described.

[0017] [First Embodiment] With reference to FIGS. 1 to 6, a semiconductor device 50 including an inductor region 10 according to the present embodiment will be described.

[0018] FIG. 1(a) is a cross-sectional view of a semiconductor device 50 according to the present embodiment, and FIG. 1(b) is a plan view, respectively. FIG. 1(a) is a cross-sectional view taken along line A-A of FIG. 1(b). An inductor region 10 is formed in the semiconductor device 50. The "inductor region" refers to a region of a configuration that exhibits the function of an inductor in the semiconductor device 50. In the present embodiment, in addition to a coil 22 formed by wiring (rewiring 17 described later), it refers to a region including configurations that define the function as an inductor, such as a first soft magnetic film 24-1 and a second soft magnetic film 24-2. Further, the semiconductor device 50 according to the present embodiment forms the inductor region 10 on top of a semiconductor substrate on which no circuit is formed. However, the inductor region 10 may be formed on top of a circuit portion on which a circuit is formed.

[0019] The semiconductor device 50 shown in FIG. 1 is also manufactured using the WL-CSP technology, similar to the semiconductor device 150, and has basically the same configuration as the semiconductor device 150 shown in FIG. 11(a). That is, as shown in FIG. 1(a), the semiconductor device 50 includes a semiconductor substrate 11, pads 12-1, 12-2 (hereinafter, when collectively referred to, including the pads 12-3, 12-4 described later, as "pads 12"), a passivation film 13, insulating films 14, 15, vias 16-1, 16-2 (hereinafter, when collectively referred to, including the vias 16-3, 16-4 described later, as "vias 16"), rewiring 17, posts 18, solder terminals 19, and a mold 20. The pads 12 are formed of aluminum (Al) as an example and are exposed from the openings provided in the passivation film 13. The passivation film 13 is formed of a silicon nitride film as an example and covers a part of the semiconductor substrate 11 and the pads 12. The insulating films 14, 15 are formed of a polyimide film as an example. The insulating film 14 covers a part of the passivation film 13 and the pads 12, and the insulating film 15 covers a part of the insulating film 14 and the vias 16-1, 16-2. Here, the layer including the rewiring 17, the insulating films 14, 15, and the posts 18 is the "rewiring layer" according to the present embodiment.

[0020] In the semiconductor device 50 shown in FIG. 1(a), an inductor region 10 is formed in the region surrounded by the dotted line. Although there is no limitation on the material of the semiconductor substrate 11, in the present embodiment, a silicon (Si) substrate is used as an example. In addition, the details of the first soft magnetic film 24-1 and the second soft magnetic film 24-2 shown in FIG. 1(a) will be described later.

[0021] As shown in FIG. 1(b), a coil 22 is formed in the inductor region 10, and terminals 21-1 and 21-2 are arranged at one end and the other end of the coil 22, respectively. In the present embodiment, the "coil 22" refers to the wiring portion formed by the spiral rewiring 17. In other words, the coil 22 according to the present embodiment is formed in the rewiring layer.

[0022] The semiconductor substrate 11, pads 12-1 and 12-2, and passivation film 13 shown in FIG. 1(a) are the parts manufactured by the manufacturing process of the semiconductor chip, and the insulating films 14 and 15, vias 16-1 and 16-2, rewiring 17, post 18, solder terminal 19, and mold 20 are the parts manufactured by the rewiring process. In the present embodiment, the wiring layer for forming the coil 22 on the insulating film 15 and the vias 16-1 and 16-2 (including the vias 16-3 and 16-4 described below) are referred to as the rewiring 17.

[0023] The insulating film 14 is provided with vias 16-1 and 16-2, and one end of each via is connected to the pads 12-1 and 12-2, respectively. Also, the other ends of the vias 16-1 and 16-2 are connected to the rewiring 17 on the insulating film 15. In the semiconductor device 50, the rewiring 17 on the insulating film 14 enables the wiring to be extended to the position of the post 18.

[0024] The post 18 and the solder terminal 19 are terminals when the semiconductor device 50 is mounted on an external printed circuit board (not shown) or the like. The post 18 is formed of copper (Cu) as an example. The mold 20 is a sealing resin that protects the circuit or the like formed on the semiconductor substrate 11 from the outside air or the like.

[0025] FIG. 2(a) shows a cross-sectional view of the inductor region 10 according to the present embodiment, and FIG. 2(b) shows a plan view. FIG. 2(a) represents a cross-section cut along the line B-B shown in FIG. 2(b). As shown in FIG. 2(a), the inductor region 10 includes the semiconductor substrate 11, pads 12-3 and 12-4, passivation film 13, vias 16-3 and 16-4, rewiring 17, the first soft magnetic film 24-1 and the second soft magnetic film 24-2 (collectively referred to as "soft magnetic film 24" when referred to generally), and the mold 20.

[0026] As shown in FIGS. 2(a) and 2(b), a coil 22 is formed in the rewiring 17. The coil 22 according to the present embodiment is formed by arranging substantially rectangular wiring in a spiral shape. However, the shape of the coil 22 is not limited to this, and circular or elliptical wiring may be arranged in a spiral shape to form it. The vias 16-3 and 16-4 are connected to the terminal 21-1 which is one end of the coil 22 and the terminal 21-2 which is the other end, respectively, and are connected to the circuits formed in the semiconductor chip via the pads 12-3 and 12-4, respectively.

[0027] Here, the inductor region 10 according to the present embodiment is considered so that the performance such as inductance and wiring resistance is improved with respect to the inductor region 100 according to the comparative example so that it can be used as a power inductor as an example. That is, as shown in FIG. 2(a), the inductor region 10 according to the present embodiment includes a first soft magnetic film 24-1 and a second soft magnetic film 24-2 that are not present in the inductor region 100. The soft magnetic film 24-1 is formed on the passivation film 13, and the soft magnetic film 24-2 is formed to cover the rewiring 17 on which the coil 22 and the like are formed on the soft magnetic film 24-1. Here, the material of the soft magnetic film 24 is not particularly limited, but in the present embodiment, an insulating film such as a resin containing magnetic powder of a soft magnetic material is used as an example.

[0028] The soft magnetic film 24-1 and the soft magnetic film 24-2 are not separated from each other, and are integrally formed in the present embodiment. However, the soft magnetic film 24-1 and the soft magnetic film 24-2 may be separated when it does not matter in consideration of the inductance value and the like of the inductor region 10. Further, it may be a form in which either the soft magnetic film 24-1 or the soft magnetic film 24-2 is arranged.

[0029] According to the inductor region 10 according to the present embodiment, leakage magnetic flux is suppressed by the action of the soft magnetic film 24, and the value of the inductance L increases compared to an inductor region of the same size without the soft magnetic film 24. Also, since the wiring length can be shortened due to the increase in the inductance L, the wiring resistance decreases. That is, according to the inductor region 10, its performance can be improved. Further, the magnetic flux generated by the coil 22 is confined within the first soft magnetic film 24-1 and the second soft magnetic film 24-2, and leakage to the outside is suppressed. Therefore, the influence of the magnetic flux by the coil 22 on other circuits formed on the semiconductor substrate 11 is suppressed. For this reason, in the inductor region 100 according to the comparative example without the soft magnetic film, there is concern about the generation of noise or the like in other circuits due to the magnetic flux of the coil 22, but the inductor region 10 according to the present embodiment can suppress the generation of noise or the like in other circuits.

[0030] Referring to FIG. 3, the suppression of the leakage of the magnetic flux will be described in more detail. FIG. 3 is a diagram conceptually showing the relationship between the soft magnetic film 24 and the coil 22 shown in FIG. 2(a). That is, a rewiring 17 that forms a part of the coil 22 is formed on the soft magnetic film 24, and the rewiring 17 is further surrounded by the soft magnetic film 24. A current IL flows through the rewiring 17 in the direction shown in FIG. 3. The current IL shown on the left side of FIG. 3 flows in the direction from the back to the front, and the current IL shown on the right side flows in the direction from the front to the back.

[0031] In the configuration shown in FIG. 3, magnetic fluxes Φ in the rotational direction shown in the figure are generated in the left and right rewiring lines 17. In the left rewiring line 17, a counterclockwise magnetic flux Φ is generated, and in the right rewiring line 17, a clockwise magnetic flux Φ is generated. Most of the generated magnetic flux Φ is confined within the soft magnetic film 24, suppressing leakage to the outside. Due to this closed magnetic circuit structure, the inductance value becomes larger compared to an inductor region of the same size without the soft magnetic film 24, improving the performance of the inductor region 10. Also, in this embodiment, since the coil 22 is formed directly on the semiconductor substrate 11, the wiring length is shortened, reducing the wiring resistance, which also improves the performance of the inductor region 10. Further, even when a circuit is formed on the main surface (not shown) of the semiconductor substrate 11 below the coil 22, for example, the magnetic flux Φ is confined within the soft magnetic film 24, suppressing the influence on the circuit. This suppresses the generation of unintended electromotive force, noise, etc.

[0032] Next, the actions of the soft magnetic film 24-1 and the soft magnetic film 24-2 according to this embodiment will be described more specifically. FIGS. 4 and 5 show the results of confirming the above effects by simulation using an electromagnetic field simulator. FIG. 4 shows the models used in this simulation. FIG. 4(a) shows the case where the soft magnetic film 24 is not arranged, FIG. 4(b) shows the case where only the soft magnetic film 24-2 is arranged above the coil 22, and FIG. 4(c) shows the configurations in the cases where the soft magnetic films 24-1 and 24-2 are arranged above and below the coil 22, respectively. FIG. 5 shows the simulation results of the distribution of the magnetic flux Φ. FIGS. 5(a), (b), and (c) show the results corresponding to FIGS. 4(a), (b), and (c), respectively. The conditions for this simulation are as follows. Thickness of the insulating film 26-1 (polyimide film) = 3 μm Thickness of the insulating film 26-2 = 10 μm Thickness of the soft magnetic film 24-1 = 3 μm Thickness of the soft magnetic film 24-2 = 10 μm

[0033] FIG. 6 shows the outer shape of the coil 22 used in this simulation. As shown in FIG. 6, in this simulation, the outer shape of the coil 22 is substantially square. The simulation conditions for the coil 22 are as follows. Wiring material: Copper (Cu) Wiring width = 8 μm, wiring pitch = 8 μm Thickness of the wiring = 7 μm Length of one side of the coil 22 = 0.6 mm

[0034] As is clear from comparing FIG. 5(a) with FIGS. 5(b) and 5(c), it can be seen that the spread of the magnetic flux Φ is significantly suppressed by arranging the soft magnetic film 24-2, or the soft magnetic films 24-1 and 24-2. Here, when only the soft magnetic film 24-2 is arranged above the coil 22 shown in FIG. 4(b) and when the soft magnetic films 24-1 and 24-2 are arranged above and below the coil 22 shown in FIG. 4(c), there seems to be no significant difference in the spread of the magnetic flux Φ. However, in reality, there is a difference in the magnitude of the magnetic flux vector, and the inductance value is significantly larger when both the soft magnetic films 24-1 and 24-2 shown in FIG. 4(c) are arranged. Although not shown in FIG. 4, the case where only the soft magnetic film 24-1 is arranged below the coil 22 has also been simulated, and in this case, although it is inferior to the result of FIG. 4(b), it is clearly effective compared to FIG. 4(a).

[0035] [Second Embodiment] Referring to FIGS. 7 to 10, the semiconductor device 50A and the inductor region 10A according to this embodiment will be described. This embodiment is a form in which an insulating film is arranged around the inductor region. Therefore, since the main configurations of the inductor region and the semiconductor device are common to the first embodiment described above, the same reference numerals are given to the same configurations and the overlapping description is omitted.

[0036] FIG. 7(a) shows a cross-sectional view of the inductor region 10A, and FIG. 7(b) shows a plan view of the inductor region 10A. FIG. 7(a) shows a cross-section cut along the line C-C shown in FIG. 7(b).

[0037] As shown in FIGS. 7(a) and 7(b), the inductor region 10A includes a first support insulating film 25-1 and a second support insulating film 25-2 (collectively referred to as "support insulating film 25" hereinafter) that are not present in the inductor region 10 (see FIG. 2). The first support insulating film 25-1 defines the shape of the first soft magnetic film 24-1, and the second support insulating film 25-2 defines the shape of the second soft magnetic film 24-2. Here, the second support insulating film 25-1 represents the insulating films 14 and 15 shown in FIG. 1(a) as one layer. In other words, the support insulating film 25-1 is formed of the same film as the insulating films 14 and 15. Since the inductor region 10A according to the present embodiment includes the support insulating film 25, it is easy to control the shape of the soft magnetic film 24, and thus it is easy to control the shape of the magnetic flux generated by the coil 22. There is no particular limitation on the material of the support insulating film 25, but in the present embodiment, a photosensitive polyimide resin is used as an example. Note that the "first support insulating film 25-1" and the "second support insulating film 25-2" are examples of the "first insulating film" and the "second insulating film" according to the present invention, respectively.

[0038] FIG. 8 shows a cross-sectional view of the semiconductor device 50A according to the present embodiment. In the semiconductor device 50A, the inductor region 10A is formed on the upper part of the circuit portion 27 in which a circuit is formed on the semiconductor substrate 11. Of course, the inductor region 10A may be formed on the upper part of the semiconductor substrate 11 where the circuit portion 27 is not formed in the semiconductor device 50A. As shown in FIG. 8, the first support insulating film 25-1 extends along the circuit portion 27, and the post 18 is formed on the upper part of the first support insulating film 25-1. The second support insulating film 25-2 is formed on the upper part of the first support insulating film 25-1. The coil 22 of the inductor region 10A is connected to the related circuit formed in the circuit portion 27 via the pads 12-3 and 12-4.

[0039] Next, a method for manufacturing a semiconductor device 50A including an inductor region 10A according to the present embodiment will be described with reference to FIGS. 9 and 10. Note that the manufacturing method according to the present embodiment is performed in a state of a semiconductor wafer. In the following description, attention will be paid to one inductor region 10A and the semiconductor device 50A among them for explanation.

[0040] First, a semiconductor wafer on which a circuit portion 27 (not shown in FIG. 9), pads 12, and a passivation film 13, that is, a semiconductor chip is formed, is prepared on the main surface (not shown) of a semiconductor substrate 11. Then, a first support insulating film 25-1 is formed so as to surround a region for forming the inductor region 10A on the passivation film 13 (see FIG. 7(b)) using photolithography and etching (FIG. 9(a)).

[0041] Next, a first soft magnetic film 24-1 is applied and cured inside the first support insulating film 25-1 that surrounds the formation region of the inductor region 10A (FIG. 9(b)).

[0042] Next, openings are provided at portions where vias 16-3 and 16-4 of the first support insulating film 25-1 are to be formed. Then, a metal material (for example, Cu) is plated, and a rewiring 17 (that is, a coil 22) is formed using photolithography and etching (FIG. 9(c)). An intermediate process of the semiconductor device 50A in this step is shown in FIG. 10(a). As shown in FIG. 10(a), the first support insulating film 25-1 extends also to a region other than the region corresponding to the inductor region 10A (including the circuit portion 27 and the like), and a post 18 is formed after the formation of the rewiring 17.

[0043] Next, a second support insulating film 25-2 that surrounds the formation region of the inductor region 10A is formed on the upper portion of the first support insulating film 25-1 using photolithography and etching (FIG. 9(d)).

[0044] Next, a second soft magnetic film 24-2 is applied and cured inside the second support insulating film 25-2 (FIG. 9(e)).

[0045] Next, a mold 20 is applied to and cured on the upper portions of the first support insulating film 25-1, the second support insulating film 25-2, and the second soft magnetic film 24-2 (FIG. 9(f)). Thereafter, it is singulated into individual semiconductor chips, and a semiconductor device 50A including an inductor region 10A is manufactured. An intermediate stage of the semiconductor device 50A in this process is shown in FIG. 10(b). As shown in FIG. 10(b), the mold 20 extends also to regions other than the region corresponding to the inductor region 10A (including the circuit portion 27, etc.) and fills the periphery of the post 18. A solder terminal 19 is formed on the upper portion of the post 18.

[0046] Note that the semiconductor device 50 according to the above embodiment is also manufactured according to the above manufacturing process. Since the semiconductor device 50 does not include the second support insulating film 25-2, insulating films 14 and 15 (see FIG. 1(a)) are formed in regions other than the region where the inductor region 10 is formed, and the inductor region 10 is formed in a region where the insulating films 14 and 15 are not formed. More specifically, as an example, it is manufactured by the following rewiring process. · Insulating films 14 and 15 are formed over the entire surface. At this time, vias 16 are also formed. · Openings are provided in the insulating films 14 and 15 in the region where the inductor region 10 is to be formed. Alternatively, a mask may be used to prevent the insulating films 14 and 15 from being formed in the region where the inductor region 10 is to be formed. · The soft magnetic film 24-1 is applied to the above openings and cured. · A rewiring 17 including a coil 22 is formed on the upper portions of the insulating film 15 and the soft magnetic film 24-1, and further, a post 18 is formed. · Using photolithography and etching, the soft magnetic film 24-2 is applied to the upper portion of the rewiring 17 and cured.

[0047] Note that in each of the above embodiments, the form in which the coil 22 is provided on the upper portion of the insulating film 15 has been illustrated and described. However, considering the layout, etc., it may be provided on the upper portion of the insulating film 14, or considering the inductance value, etc., it may be provided on the upper portions of both the insulating films 14 and 15 and the two may be connected by a via.

[0048] In each of the above embodiments, a form in which vias are provided in the soft magnetic film 24 disposed below the coil 22 to connect the coil 22 and the circuit portion 27 has been illustrated and described. However, when it is not desired to provide vias in the soft magnetic film 24, or when it is desired to connect to a circuit portion 27 disposed at a position away from the coil 22, the end of the coil 22 may be extended to the upper part of the insulating film 25-1, and vias may be provided in the insulating film 25-1 to connect to the circuit portion 27.

[0049] In each of the above embodiments, a form in which the first soft magnetic film 24-1 and the second soft magnetic film 24-2 are formed of the same material has been illustrated and described. However, in consideration of the manufacturing process and the like, they may be formed of different materials.

Explanation of Reference Numerals

[0050] 10, 10A, 100 Inductor Region 11 Semiconductor Substrate 12, 12-1, 12-2, 12-3, 12-4 Pad 13 Passivation Film 14 Insulating Film 15 Insulating Film 16, 16-1, 16-2, 16-3, 16-4 Via 17 Rewiring 18 Post 19 Solder Terminal 20 Mold 21-1, 21-2 Terminal 22 Coil 24 Soft Magnetic Film 24-1 First Soft Magnetic Film 24-2 Second Soft Magnetic Film 25 Insulating Film 25-1 First Support Insulating Film 25-2 Second Support Insulating Film 26-1 First Insulating Film 26-2 Second Insulating Film 27 Circuit Portion 50, 50A, 150 Semiconductor Device IL Current Φ Magnetic Flux

Claims

1. A circuit portion formed on a semiconductor substrate, a first insulating film formed to cover at least a part of a region on the semiconductor substrate including the upper part of the circuit portion, rewiring formed on the first insulating film, a coil formed on the first insulating film by the rewiring and connected to the circuit portion, a first soft magnetic film formed in an opening of the first insulating film provided below the coil, a second soft magnetic film formed on the first soft magnetic film covering at least a part of the coil, characterized by comprising a semiconductor device.

2. The first insulating film is formed surrounding the first soft magnetic film, further comprising a second insulating film formed on the upper part of the first insulating film and surrounding the second soft magnetic film, characterized by the semiconductor device according to Claim 1.

3. The first soft magnetic film and the second soft magnetic film are integrated, and the coil is embedded in the integrated first soft magnetic film and second soft magnetic film, characterized by the semiconductor device according to Claim 1 or Claim 2.

4. The coil is connected to the circuit portion via a via provided in the first soft magnetic film, characterized by the semiconductor device according to any one of Claims 1 to 3.

5. A terminal for connection to the outside, further comprising a terminal provided on the first insulating film and connected to the circuit portion via a via formed in the first insulating film, characterized by the semiconductor device according to any one of Claims 1 to 4.

6. Forming a circuit portion on a semiconductor substrate, forming a first insulating film in a region including the upper part of the circuit portion and excluding a first predetermined region, forming a first soft magnetic film inside the first predetermined region, forming a coil connected to the circuit portion on the upper part of the first soft magnetic film, forming a second insulating film in a region above the first insulating film and excluding a second predetermined region that overlaps at least a part of the first predetermined region in plan view, forming a second soft magnetic film inside the second predetermined region, characterized by a method of manufacturing a semiconductor device.

7. Forming a circuit portion on a semiconductor substrate, forming an insulating film in a region including the upper part of the circuit portion and covering at least a part of the region on the semiconductor substrate, forming a first soft magnetic film in an opening of the insulating film, A coil connected to the circuit portion is formed on the upper portion of the first soft magnetic film, and a second soft magnetic film covering at least a part of the coil is formed on the first soft magnetic film. A method of manufacturing a semiconductor device.

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