Three-dimensional semiconductor processing

Abstract

To provide a method and a system for fabricating a structure in a semiconductor by selective etching of the semiconductor.SOLUTION: A system 100 includes a laser 104, an etching chamber 102 configured to contain an etchant, and a computing device 106 that controls a laser to illuminate a semiconductor 108 located within the etching chamber 102. The laser 104 generates holes at focal point 144 in the atomic lattice of the semiconductor 108 by multiphoton absorption (MPA). An etchant 110 in the etching chamber etches the semiconductor 108 and a surface 112 on the basis of the generation of holes in the lattice.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] This application claims priority to U.S. Provisional Patent Application No. 62 / 480,259, filed Mar. 31, 2017, entitled “3D Silicon Processing,” and U.S. Provisional Patent Application No. 62 / 618,205, filed Jan. 17, 2018, entitled “3D Semiconductor Processing,” which are hereby incorporated by reference in their entirety.

Background Art

[0002] Microfabrication refers to the various techniques used to manufacture integrated circuits (ICs) and microelectromechanical systems (MEMS). ICs and MEMS fabricated using conventional microfabrication techniques have features on the order of microns or nanometers. Conventional microfabrication of ICs and MEMS is a layer-by-layer process in which semiconductor layers (and various other materials) are deposited, patterned with lithography tools, and etched to define part of the final shape. Generally, these conventional microfabrication techniques are limited to forming structures with shapes similar to extruded two-dimensional forms, sometimes referred to as 2.5D.

[0003] Furthermore, these conventional microfabrication techniques are complex, time-consuming, and expensive. In one example, the fabrication of a single layer of a device can include the following steps: (1) depositing a thin film on a substrate or wafer, (2) coating the thin film with a photoresist masking layer, (3) patterning the photoresist masking layer with photolithography, (4) etching the thin film layer through the photoresist masking layer, (5) removing the photoresist masking layer, and (6) thoroughly cleaning the substrate or wafer before subsequent layers are deposited and patterned in a similar manner.

Summary of the Invention

[0004] The following is a concise summary of the subject matter that is described in more detail herein. This summary is not intended to be limiting with respect to the scope of the claims.

[0005] Various techniques for fabricating structures in a semiconductor by selective etching of the semiconductor are described herein. These techniques are suitable for fabricating various three-dimensional (3D) structures (e.g., three-dimensional space) in a semiconductor. Further, these techniques are suitable for etching structures having a smaller feature size in a semiconductor than is generally possible using conventional selective etching techniques.

[0006] In various exemplary embodiments, the semiconductor is etched by an electrochemical reaction at the surface of the semiconductor exposed to an etchant. The exposed surface of the semiconductor is selectively etched based on the controlled generation of holes (i.e., generally modeled as particles having a positive charge called holes, the absence of electrons in the lattice) in the atomic lattice of the semiconductor. In the etching reaction, holes at the exposed surface of the semiconductor cause oxidation of the semiconductor, and then the oxidation is etched by the etchant. The holes are selectively generated by irradiating the semiconductor with an irradiation source (e.g., a laser) having an energy lower than the bandgap energy of the semiconductor. A single photon of sub-bandgap energy does not have enough energy to transition an electron in the semiconductor from the valence band to the conduction band. Thus, light of normal sub-bandgap energy cannot generate holes in the atomic lattice of the semiconductor. The sub-bandgap energy light emitted from the irradiation source is focused to a spot of sufficient intensity to cause multiphoton absorption (MPA) in the semiconductor. When this occurs, the photon energies of multiple photons combine to exceed the bandgap energy of the semiconductor, exciting electrons from the valence band to the conduction band and thereby generating holes in the atomic lattice of the semiconductor at the spot of the irradiation source. The holes can be selectively generated in the region near the spot of the irradiation source where etching is desired, thereby confining the etching to the region near the spot.

[0007] Since the light emitted by the irradiation source is light with a sub-bandgap energy that does not undergo line absorption, the semiconductor exhibits transparency to the light emitted by the irradiation source. By moving the focus of the irradiation source within the body of the semiconductor, selective control can be achieved such that semiconductor etching occurs at positions that cannot be etched according to conventional semiconductor etching methods. Therefore, three-dimensional structures that are not easily formed by conventional microfabrication techniques can be etched within the body of the semiconductor. In an exemplary embodiment, the irradiation source can be positioned to face a second surface (e.g., the back surface) of the semiconductor, which is on the opposite side of the surface exposed to the etching solution. In this embodiment, the irradiation source emits light through the semiconductor towards the focus within the semiconductor body, towards the second surface of the semiconductor. Irradiating the semiconductor through the second surface on the opposite side of the etching surface avoids possible scattering of the emitted light that can cause unwanted etching of the semiconductor or reduce the achievable resolution of the semiconductor structure.

[0008] In other exemplary embodiments, the irradiation source is controlled using a computing device that incorporates a physical model of charge carrier movement within the semiconductor. Generally, holes generated at a first position within the semiconductor can move within the semiconductor under the influence of various forces caused by, for example, an electric field, charge dispersion, etc. Therefore, in some instances, holes generated at a first position within the semiconductor can move to positions within the semiconductor other than the position to be etched as desired. By incorporating a physical model of charge carrier movement, the computing device can control the irradiation source such that holes are generated by the emitted light at the position where they ultimately move to the desired etching position. As an example, the computing device is provided with the desired etching position of the semiconductor. The computing device outputs a prediction based on the physical model, and the prediction indicates that holes generated at the first position are expected to move to the desired etching position. The physical model can output a prediction based on charge carrier diffusion within the semiconductor, the electric field applied to the semiconductor (e.g., by a bias voltage), and the current flow within the electrochemical cell that causes the etching reaction. The computing device then controls the output of the irradiation source to irradiate the semiconductor at that focus at the first position predicted by the physical model.

[0009] The above summary presents a simplified overview in order to provide a basic understanding of some aspects of the systems and / or methods discussed in this specification. This summary is not an extensive overview of the systems and / or methods discussed in this specification. It is not intended to identify key / important elements or to delineate the scope of such systems and / or methods. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that will be presented later. **Brief Description of the Drawings**

[0010]

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[0011] Various techniques related to the selective etching of light-controlled semiconductors are described herein with reference to the figures, and throughout, like reference numerals are used to refer to like elements. In the following description, for the sake of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more aspects. However, it may be apparent that such one or more aspects may be practiced without these specific details. In other instances, well-known structures and devices are illustrated in block diagram form in order to facilitate the description of one or more aspects. Further, it should be understood that functions described as being performed by certain system elements may be implemented by multiple elements. Similarly, for example, one element may be configured to perform functions described as being performed by multiple elements.

[0012] Furthermore, the expression “or” is intended to mean an inclusive “or” rather than an exclusive “or”. That is, unless otherwise specified or clear from the context, the expression “X uses A or B” is intended to mean any natural inclusive substitution. That is, the expression “X uses A or B” is satisfied by any of the following examples. X uses A. X uses B. Or, X uses both A and B. In addition, the articles “a” and “an” as used in this application and the appended claims should generally be construed to mean “one or more” unless otherwise specified or it is clear from the context that they refer to the singular form.

[0013] Furthermore, as used herein, the expressions "element" and "system" are intended to encompass computer-readable data storage configured with computer-executable instructions that, when executed by a processor, cause certain functions to be performed. The computer-executable instructions can include routines, functions, and the like. It should also be understood that an element or system can be localized in a single device or distributed among several devices. Further, as used herein, the expression "exemplary" is intended to mean serving as an example or instance of something and is not intended to indicate preference.

[0014] It should be understood that as used in this specification, a "hole" in a semiconductor lattice refers to the absence of an electron at a position within the semiconductor lattice. Although various operations and events regarding holes as physical entities are referred to herein, such descriptions are merely intended to facilitate understanding of various aspects and it should be understood that they may reflect some inaccuracies regarding the underlying physical processes. For example, when referring herein to an electric field that applies a force to a hole to cause hole movement, in reality the electric field applies a force to the electrons in the semiconductor lattice, thereby causing electron movement, but it should be understood that the result of such movement can be appropriately explained by conceptualizing the hole as a virtual particle. Such references to holes are made for ease of understanding and are consistent with descriptions commonly used in semiconductor manufacturing technology.

[0015] Referring to FIG. 1, an exemplary system 100 that facilitates selectively controlled semiconductor etching is illustrated. System 100 includes an etching chamber 102, a laser 104, and a computing device 106 that controls laser 104. Etching chamber 102 includes a semiconductor element 108 to be etched as desired and an etching solution 110 that selectively oxidizes and etches semiconductor 108 at positions where holes exist in the atomic lattice of semiconductor 108. To generate holes in a specific region of semiconductor 108, laser 104 emits a light beam 109 onto semiconductor 108 based on a control signal received from computing device 106. Semiconductor 108 is then etched by etching solution 110 at a position where the generated holes move to a first surface 112 of semiconductor 108 that is exposed to etching solution 110. Thus, laser 104 is controlled such that semiconductor 108 is etched at a desired location based on the location where laser 104 generates holes in semiconductor 108.

[0016] The composition of the etching solution 110 is selected based on the chemical composition of the semiconductor 108. By way of example, and not limitation, in applications where the semiconductor 108 includes silicon or other group IV elements (e.g., silicon, carbon, germanium, etc.), the etching solution 110 may include hydrofluoric acid (HF). For example, the etching solution 110 may be a solution of 1% to 30% HF. In other embodiments, other chemicals that produce fluorine atoms for the reaction, such as ammonium hydroxide / ammonium fluoride, can also be used. In various embodiments, the etching solution 110 may include a surfactant (e.g., ethanol, dimethylformamide, acetonitrile, etc.) that promotes wetting of the etching solution 110 on the surface 112 of the semiconductor 108 and facilitates removal of the etching gas from the surface 112 of the semiconductor 108. It should be understood that the methods and systems described herein are suitable for selective etching of various semiconductors. In some exemplary embodiments, the semiconductor 108 includes elemental semiconductors such as silicon, carbon (diamond, graphene, carbon nanotubes, etc.), germanium, etc. In other exemplary embodiments, the semiconductor 108 includes III-V semiconductors (e.g., gallium arsenide, indium phosphide, etc.), group III nitrides (e.g., gallium nitride, indium gallium nitride), II-VI semiconductors (e.g., zinc oxide, cadmium telluride, etc.), or other semiconductor compounds (e.g., silicon carbide, silicon germanium, etc.). The composition of the etching solution 110 can be selected to facilitate etching of the semiconductor to be desirably etched.

[0017] Various details regarding the construction and operation of the system 100 for selectively etching the semiconductor element 108 are described herein. The etching chamber 102 includes a first storage container 114 and a second storage container 116. The first storage container 114 contains the etching solution 110. The containers 114, 116 are connected by a seal 118 (e.g., an O-ring when the containers 114, 116 are annular) that prevents the etching solution 110 from leaking out of the etching chamber 102. The semiconductor 108 is placed within the second storage container 116 such that a first surface 112 of the semiconductor 108 is exposed to the etching solution 110.

[0018] System 100 further includes a voltage source 120 that facilitates an etching reaction at the surface 112 of the semiconductor 108 and establishes an electric field within the semiconductor. The voltage source 120 is connected to an anode electrode 122 and a cathode electrode 124 at the positive and negative terminals of the voltage source 120, respectively. The anode electrode 122 is located within the second storage container 116 in contact with a conductive material 126. The conductive material 126 is disposed in contact with a second surface 128 of the semiconductor 108 opposite the surface 112 that is exposed to the etching solution 110. When a voltage is applied to the electrodes 122, 124 by the voltage source 120, an electric field is established within the semiconductor 108 that can be used to direct charge carriers to a desired location within the semiconductor 108. For example, the voltage source 120 can be controlled to establish an electric field within the semiconductor 108 that tends to move positive charge carriers, such as holes, toward the etching surface 112.

[0019] The second containment vessel 116 further includes a window 130 that is located on the outer surface 132 of the vessel 116 and extends through the surface 132 to face the back surface 128 of the semiconductor 108 (i.e., the surface opposite the surface to be etched). The window 130 is transmissive to the light beam 109 emitted by the laser 104. The laser 104 is positioned to face the window 130 and emits the light beam 109 through the window 130 toward the back side 128 of the semiconductor 108. The conductive material 126 is selected or configured to be transmissive to the light beam emitted by the laser 104. By way of example, and not limitation, the conductive material 126 may be saline, acid, base, a transmissive conductive oxide, a very thin metal film (e.g., 10 - 50 nm), a metal mesh, graphene, carbon nanotubes, a transmissive conductive polymer, etc. In other exemplary embodiments, the conductive material 126 may be a diluted HF solution. When the etchant 110 contains HF, using the HF solution as the conductive material 126 can suppress an undesirable reaction therebetween when the etchant 110 and the conductive material 126 are in contact. The system 100 may further include a focusing lens 134 (e.g., an objective lens, or a special optical focusing element) that receives the light beam 109 from the laser 104 and focuses the light beam 109 through the window 130 to a focal point within the semiconductor element 108. The light beam 109 may become a focal cone after exiting the focusing lens 134, but for simplicity and illustration, the light beam 109 (and in some subsequent figures) is illustrated as a straight light beam until it reaches the focal position 144.

[0020] The computing device 106 includes a processor 136, a memory 138 operably coupled to the processor 136, and a data store 140 operably coupled to the processor 136. The memory 138 includes instructions that, when executed by the processor 136, cause the processor 136 to perform various functions. The process control element 142 controls various aspects of the process for selectively etching the semiconductor 108. For example, the process control element 142 controls the direction and position of the laser 104 and / or the focusing lens 134 with respect to irradiating a particular location on the semiconductor 108. The process control element 142 may also be configured to control other etching input variables such as the intensity of the light beam 109, the bias voltage provided by the voltage source 102, and the temperature of the etchant 110.

[0021] The operation of the system 100 for selectively etching the semiconductor 108 is described herein. The etching of the semiconductor 108 by the etchant 110 occurs based on a series of chemical reactions that are carried out at the etching surface 112 of the semiconductor 108 where there are holes in the atomic lattice at the surface 112. For example, in an exemplary embodiment where the semiconductor 108 includes silicon and the etchant 110 includes hydrofluoric acid, the etching reaction is the following two-step electrochemical reaction.

[0022] Si + 2F - + 2h + → SiF2(1)

[0023] SiF2 + 2HF → SiF4 + H2(2)

[0024] In the chemical reaction shown in Equation 1, holes with positive charges on the surface of the silicon semiconductor promote the reaction between negatively charged fluorine ions and neutral silicon, generating SiF2 on the surface. The chemical reaction of Equation 2 is an etching reaction in which the HF etching solution reacts with SiF2 to generate gaseous SiF4 and H2. Therefore, the electrochemical etching reaction described in Equations 1 and 2 can be controlled by controlling the number and position of holes in the semiconductor. Etching occurs where there are holes, and no etching occurs where there are no holes. Other alternative chemical reaction equations have been presented for the silicon electrochemical etching of silicon with an intermediate silicon oxide stage. Generally, various presented reaction equations and experimental results have demonstrated that holes are required for etching to occur.

[0025] In the exemplary system 100, holes are generated by irradiating the semiconductor 108 with the laser 104. Since the electrochemical etching reaction between the etching solution 110 and the semiconductor 108 is promoted by the presence of holes, the etching of the semiconductor 108 can be controlled based on the irradiation of the semiconductor 108 by the laser 104. To generate holes in the semiconductor, sufficient energy must be imparted to the electrons in the semiconductor lattice so that the electrons transition from the valence band to the conduction band across the semiconductor's bandgap. Conventionally, therefore, lasers have been used in which each photon has an energy greater than the bandgap energy of the semiconductor to generate holes in the semiconductor.

[0026] On the one hand, the laser 104 is a laser that emits light with photon energy smaller than the bandgap energy of the semiconductor 108. Light with sub-bandgap energy is not normally absorbed by the semiconductor 108, and thus the semiconductor 108 is generally transparent to the light beam 109 emitted by the laser 104. The focusing lens 134 is configured to focus the light beam 109 onto a strong focus 144 of the semiconductor 108. Normally, light with sub-bandgap energy does not give electrons enough energy to become free from their positions in the semiconductor lattice (thereby generating holes), but when the focusing lens 134 focuses the light beam onto a strong focus 144, multiphoton absorption (MPA) occurs, and multiple photons give energy to electrons almost simultaneously. When electrons absorb multiple photons each having energy lower than the bandgap, enough energy is given, and the electrons may move from the valence band to the conduction band, thereby generating holes.

[0027] By way of example, referring now to FIG. 2, a conceptual diagram of generating holes in the atomic lattice of a semiconductor is shown. Certain aspects regarding electrons, photons, and holes are illustrated and described with respect to FIG. 2, but it should be understood that such aspects are intended only as a conceptual diagram to facilitate understanding of the basic physical process and are not intended as a completely accurate illustration of the physical processes inside the atomic nucleus. FIG. 2 illustrates a snapshot of a semiconductor 200 including a plurality of electrons e - . The electrons e - are bound to either the valence band of the semiconductor 200 or the conduction band of the semiconductor 200. FIG. 2 further illustrates a light beam 202 of light, for example, emitted by a laser. As shown in FIG. 2, the light beam 202 includes a plurality of photons p, and each of the photons p has energy lower than the bandgap energy of the semiconductor 200.

[0028] First, the light beam 202 is not focused in the region 204. In the unfocused region 204, since there is no possibility that two or more photons will simultaneously give energy to one electron, the light beam 202 has no possibility of giving the electron enough energy to cross the bandgap from the valence band to the conduction band. The light beam 202 is focused at the focal point 206 within the semiconductor 200. At the focal point 206, the fluence of the light beam 202 (i.e., the energy per unit area) increases compared to the unfocused region 204. Therefore, at the focal point 206, there is a high possibility that two or more photons will give energy to one electron almost simultaneously. MPA occurs at the focal point 206 of the light beam 202. For example, as shown in FIG. 2, two photons 208, 210 reach the electron 212 simultaneously. The photons 208, 210 give the electron 212 enough energy to move the electron 212 from its position in the atomic lattice of the semiconductor 200, as indicated by the arrow extending from the electron 212. On the other hand, in the snapshot shown in FIG. 2, only a single photon 214 reaches the other electron 216. Since the photon p of the light beam 202 has sub-bandgap energy, the single photon 214 is not sufficient to give the electron 216 enough energy to move the electron 216 from its position in the lattice, and therefore, the photon 214 is not absorbed and the electron 216 does not leave the valence band. Electron e - When leaving its position in the lattice of the semiconductor 200, a positive hole h + is left behind. For example, the hole 220 remains in its position, while the electron 218 is shown moving away from its position in the lattice.

[0029] Referring again to FIG. 1, holes are generated at the focus 144 by the MPA of the light ray 109 of the sub-bandgap energy by electrons in the atomic lattice of the semiconductor 108 at the focus 144. The holes generated at the focus 144 can move to the etching surface 112, causing oxidation and subsequent etching of the semiconductor 108 at the position of the holes on the surface 112. As an example, the semiconductor 108 includes an etching mechanism 146 that extends from the surface 112 into the semiconductor 108. As the holes generated at the focus 144 move to the bottom surface 148 of the etching mechanism 146, the etching solution 110 oxidizes and etches the bottom surface 148 of the mechanism 146, further extending the mechanism 146 into the body of the semiconductor 108.

[0030] The process control element 142 can control various parameters of the electrochemical etching of the semiconductor 108 by the etching solution 110 in the etching chamber 102 to facilitate the etching of the desired mechanism. For example, the electric field can be established and variably controlled so as to affect the size and shape of the mechanism etched in the semiconductor 108. In the system 100, the computing device 106 is connected to the voltage source 120, and the process control system 142 is configured to control the output of the voltage source 120. The process control system 142 can control the voltage source 120 to establish an electric field in the semiconductor 108. As referred to above, the electric field is maintained such that the holes are washed away to the etching surface 112. Establishing an electric field in the semiconductor 108 using the voltage source 120 facilitates the selective etching of the surface 112 of the semiconductor 108 by directing the holes to the desired positions in the lattice of the semiconductor. Various internal electric fields (not due to the voltage source 120) within the semiconductor 108 can exert a force on the holes in the semiconductor 108, causing drift of the semiconductor. Further, the holes diffuse in the semiconductor 108 from a region of high concentration to a region of low concentration. Establishing an electric field in the semiconductor 108 using the voltage source 120 can reduce the effect of other electric fields and carrier diffusion on the final position of the holes on the surface 112 of the semiconductor 108 by reducing the time between when the holes are generated at the focus 144 of the laser 104 and when the holes reach the surface 112.

[0031] As an example, referring now to FIG. 3, there is depicted a diagram showing the movement of holes under the influence of two different electric fields. FIG. 3 illustrates a semiconductor element 300 that includes a first surface 302 exposed to an etchant 304 and a second surface 306 opposite the first surface 302, and a light ray 308 of light having a sub-bandgap energy enters the semiconductor 300 through the second surface 306. The light ray 308 generates a plurality of holes 310-314 at a focus 316 of the light ray 308 located within the semiconductor 300. The holes 310-314 move toward the etching surface 302 of the semiconductor 300 under the influence of an electric field E. For a first intensity of the electric field E, the holes 310-314 move to respective positions 318-322. If the electric field E is increased to a higher second intensity (e.g., by increasing the voltage output of the voltage source 120 in the system 100), the holes 310-314 can be flushed more rapidly by the etching surface 302. As shown in FIG. 3, under the influence of the electric field of the higher second intensity, the holes 310, 314 move to respective positions 324, 326 that are closer to each other than positions 318, 322. Thus, the size (e.g., diameter) of the etching mechanism for a given set of irradiation parameters (e.g., size, position, intensity of the laser focus) can increase by reducing the intensity of the electric field E, or can decrease by increasing the intensity of the electric field E.

[0032] With regard to etching a desired mechanism into the semiconductor 108, still other parameters of the system 100 can be controlled by the process control element 142. In an exemplary embodiment, the process control element 142 outputs a control signal to the laser 104 and / or the focusing lens 134 to adjust the size, intensity, or position of the focus 144 within the semiconductor 108 and thereby affect the resulting etching.

[0033] As an example, referring here to FIG. 4, a diagram is depicted showing the differences in the movement of holes in a semiconductor with respect to foci of various sizes and positions. FIG. 4 illustrates a semiconductor element 400 that includes a first surface 402 exposed to an etchant 404 and a second back surface 406 on the opposite side of the first surface 402, and light rays 408-412 of sub-bandgap energy light are depicted as entering the semiconductor 400 through the back surface 406. Each of the light rays 408-412 has a different combination of focus size and position with respect to the etch surface 402. Light ray 408 has a focus 414 with a focus width fw1 at a depth d1 from the etch surface 402. Holes 416, 418 are depicted as initially being spaced apart by a maximum distance of fw1 at the focus 414. Due to carrier diffusion, an internal or induced electric field, or various other forces, the holes 416, 418 move to positions 420, 422 on the etch surface 402 of the semiconductor 400. Positions 420, 422 are located a width w1 apart, and the value of w1 depends on various etch parameters described herein. Similarly, light ray 410 has a focus 424. The focus 424 of light ray 410 has the same focus width fw1 as the focus 414 of the first light ray 408, but the focus 424 is located at a depth d2 that is shallower than the depth d1 of the first focus 414. As a result, when all other conditions are the same, holes 426, 428 generated at the maximum distance of fw1 at the focus 424 move to respective second positions 430, 432 on the etch surface 420 and are separated by a width w2 that is narrower than the width w1. When the size of the focus is the same, increasing the distance between the focus and the etch surface can increase the size of the etching mechanism at the etch surface of the semiconductor.

[0034] The width of the focus can also affect the width of the resulting etching mechanism. Further referring to FIG. 4, the third light beam 412 has a focus 434 located at the same depth d2 as the focus 424 of the second light beam 410. The focus 434 of the third light beam 412 further has a focus width fw2 that is larger than the focus width fw1 of the second light beam 410. The holes 436, 438 are illustrated as being generated with a maximum distance of fw2 at the focus 434. The holes 436, 438 are illustrated as moving to respective second positions 440, 442 on the etching surface 402, and the positions 440, 442 are spaced apart by a width w3. The width w3 is larger than the width w2, indicating that a larger focus width fw2 generates a larger etching mechanism width w3 when all other conditions are the same.

[0035] The position of the focus 144 of the laser 104 is further controlled relative to the position of an existing etching mechanism in the semiconductor 108 and can affect the size or shape of the resulting etching mechanism. For example, the focus 144 may be positioned very close to the surface of the etching mechanism in the semiconductor 108 such that the internal electric field established by the shape of the etching mechanism modifies the behavior of the holes generated at the focus 144 (e.g., within 10 nanometers from the surface of the mechanism, from 10 to 200 microns from the surface of the mechanism, or greater, depending on the carrier diffusion length of a particular semiconductor). In a non-limiting example, referring now to FIG. 5, an exemplary illustration of the etching of a semiconductor 500 is shown, where holes are generated very close to an existing etching mechanism to reduce the size of the etching. The semiconductor includes a front surface 502 exposed to an etching solution 504 and a back surface 506 through which a light beam 508 of sub-bandgap energy light enters the semiconductor 500. The semiconductor 500 includes a mechanism 510 etched on the surface 502 of the semiconductor 500. The mechanism 510 has a first width w i in the surface 502. In an exemplary embodiment, the initial width w iIt is based on the width of the focus 512 of the light beam 508, the intensity of the induced electric field E in the semiconductor 500, the relative difference in the concentration of charge carriers between the surface 502 and the position of the focus 512, etc. As the mechanism 510 extends into the semiconductor 500, the width of the mechanism 510 tapers to a smaller final width w due to the electric field focusing of the charge carriers at the tip 514 of the mechanism 510. f Tapers.

[0036] By way of example, a plurality of holes 516-520 are generated at the focus 512 of the light beam 508. Under the influence of the induced electric field E, the holes 516-520 move from the focus 512 of the light beam 508 towards the etched surface 502 of the semiconductor 500. In the absence of an existing mechanism, the minimum width of the etching mechanism at the surface 502 can be limited by the focus size of the light beam 508. For example, with respect to initially etching the mechanism 510 at the surface 502 of the semiconductor 500, the first width w may be the width of the focus 512. As the mechanism 510 is etched into the semiconductor, the surfaces of the mechanism 510 (e.g., the inner surfaces 522, 524) curve the electric field lines (not shown) from the surface 506 towards the mechanism 510, specifically towards the tip 514 of the mechanism 510. Such a change in the electric field by the mechanism 510 exerts a force on the holes to cause them to move through the semiconductor 500. Thus, the holes 516-520 generated at the focus 512 of the light beam 508 are attracted to positions 526-530 within the width w towards the tip 514 of the mechanism 510. While there is no mechanism 510, the holes 516-520 may spread apart as they move towards the surface 502 (e.g., due to charge carrier diffusion in the semiconductor 500), and the surface of the mechanism 510 attracts the holes towards the surface. i Is the width of the focus 512. As the mechanism 510 is etched into the semiconductor, the surfaces of the mechanism 510 (e.g., the inner surfaces 522, 524) curve the electric field lines (not shown) from the surface 506 towards the mechanism 510, specifically towards the tip 514 of the mechanism 510. Such a change in the electric field by the mechanism 510 exerts a force on the holes to cause them to move through the semiconductor 500. Thus, the holes 516-520 generated at the focus 512 of the light beam 508 are attracted to positions 526-530 within the width w towards the tip 514 of the mechanism 510. f Within. Without the mechanism 510, the holes 516-520 may spread apart as they move towards the surface 502 (e.g., due to charge carrier diffusion in the semiconductor 500), and the surface of the mechanism 510 attracts the holes towards the surface.

[0037] In an exemplary embodiment, the final width w of the mechanism 510 fis smaller than the width of the focus 512. Thus, referring back to FIG. 1, by placing the focus 144 of the laser 104 near the etching mechanism of the semiconductor 108, the mechanism may be etched within the semiconductor 108 and be smaller than the resolution limit of the laser 104 and the focusing lens 134. In one embodiment, if the laser 104 has a minimum focus size of 500 nanometers, the process control element 142 controls the laser 104 to utilize an electric field that focuses on an etching mechanism of a small dimension of about 10 nanometers.

[0038] Light of the sub-bandgap energy is not absorbed by the semiconductor 108 except at the focus 144 of the laser 104, so the focus 144 can be located anywhere within the three-dimensional body of the semiconductor 108. This enables the etching of three-dimensional mechanisms within the semiconductor 108 without the need for a direct line-of-sight path to the etching surface 112 of the semiconductor 108, which is generally required in conventional mask-based etching.

[0039] For example, referring now to FIG. 6, an exemplary etching of a semiconductor 600 is illustrated, where a cavity 602 is formed within the body of the semiconductor 600. As shown in FIG. 6, the semiconductor 600 includes a front surface 604 that is exposed to an etchant 606 and a back surface 608 through which a beam 610 of sub-bandgap energy light enters the semiconductor 600. The cavity 602 is disposed within the volume of the semiconductor 600 rather than on the surface of the semiconductor 600. Since the semiconductor 600 is transparent to the beam 608 except at the focus 612 of the beam 610, the focus 612 can be positioned to generate holes at any location within the body of the semiconductor 600. With regard to etching the cavity 602, additional path mechanisms 614, 616 are etched prior to etching the cavity 602. By controlling the generation of holes within the semiconductor 600 using the beam 608, the location of etching by the etchant 606 can be controlled, and for the mechanisms to be etched, the etchant 606 must be able to reach the mechanisms. Thus, the first path mechanism 614 is etched to enter the volume of the semiconductor 600 from the front surface 604. Since the etchant 606 can reach the second path mechanism 616 via the first path 614, the second path mechanism 616 is etched following the first path mechanism 614. Thereafter, since the etchant 606 can reach the cavity 602 via the already etched path mechanisms 614, 616, the cavity 602 can be etched.

[0040] For ease of understanding, various aspects of the etching mechanism are shown in a two-dimensional form in the figures, but it should be understood that the techniques described herein are suitable for etching mechanisms of substantially any three-dimensional shape. Referring now to FIG. 7, a three-dimensional view 700 of the etching mechanisms 602, 614, 616 illustrated in FIG. 6 is shown. In the three-dimensional view 700, the semiconductor 600 is shown as having a rectangular solid shape. The first path mechanism 614 is a rectangular path mechanism that extends from the front surface 604 into the body of the semiconductor 600. The second path mechanism 616 is also a rectangular path mechanism and extends horizontally outward from the first path mechanism 614 within the body of the semiconductor 600. The cavity 602 is shown as a three-dimensional cavity that connects to the second path mechanism 616 and is thereby connected to the front surface 604 of the semiconductor 600 by the two path mechanisms 614, 616.

[0041] Referring again to FIG. 1, the process control element 142 can further control the temperature and composition of the etchant 110 to maintain the desired etching parameters. The system 100 further includes a composition controller 150 and a temperature controller 152 coupled to the computing device 106. The composition controller 150 is coupled to the interior of the first storage container 114 by an opening 154 in the storage container 114. The composition controller 150 can be controlled by the process control element 142 to remove by-products of the etching reaction from the first storage container 114 and / or to introduce additional etchant to maintain the target composition of the etchant 110 within the storage container 114. The temperature controller 152 is coupled to a heating / cooling device 156 located within the storage container 114. In response to receiving a control signal from the computing device 106, the temperature controller 152 controls the heating / cooling device 156 to heat or cool the etchant 110 within the storage container 114 to maintain the target temperature of the etchant 110 (e.g., as directed by a control signal transmitted to the temperature controller 152 by the computing device 106).

[0042] It should be understood that any or all of the various forces, parameters, and variables described herein may affect the movement of holes within semiconductor 108. Thus, under the influence of a number of variable physical parameters (e.g., temperature, voltage between electrodes 122, 124, size, intensity, and position of focus 144, composition of semiconductor 108, etc.), holes generated at one location may move to other locations. To facilitate the etching of semiconductor 108 according to a desired etching pattern, memory 138 includes an etching modeling element 158 that outputs etching control instructions to process control element 142 based on an etching definition input to computing device 106. Further, feedback may be introduced into the control algorithm by monitoring the current I flowing within the electrochemical etching cell (which is related to the rate of etching occurring), monitoring the current temperature of etching solution 110, monitoring the products resulting from the etching process (as identified, for example, by composition controller 150), or monitoring the image of the etching front as the etching progresses.

[0043] Regarding etching the semiconductor 108 according to a desired pattern, exemplary operations of the etching modeling element 158 and the process control element 142 are described herein. An etching definition is provided to the etching modeling element 158, and the etching definition indicates the positions and dimensions of various features to be etched as desired in the semiconductor 108. That is, the etching definition indicates a plurality of positions (e.g., by an operator of the system 100) where it is desirable for the semiconductor 108 to be etched, and collectively the plurality of positions define the structure of one or more features to be etched. In an exemplary embodiment, the etching definition includes a computer-aided design (CAD) file that indicates the dimensions of the semiconductor and the respective positions and dimensions of one or more etching features of the semiconductor. The input of the etching definition to the etching modeling element 158 may further include one or more desired parameters of the etching. By way of example and not limitation, the etching definition may include data indicating the composition of the semiconductor 108, the positions of existing etched features in the semiconductor 108, the desired operating parameters of the laser 104 and / or the voltage source 120, and the like.

[0044] The etching modeling element 158 is configured to output etching control instructions to the process control element 142 based on the etching definition. The etching control instructions define control parameters regarding various aspects of the system 100 to be used by the process control element 142 regarding performing the desired etching described in the etching definition. In an exemplary embodiment, the etching control instructions include a plurality of positions of the focus 144 of the laser 104. In other examples, the etching control instructions may include data indicating the composition of the etchant 110, the temperature of the etchant 110, the voltage output of the voltage source 120, and the like.

[0045] In the exemplary system 100, to avoid scattering of the light beam 109 by already-etched mechanisms in the semiconductor 108, such as the mechanism 146, the light beam 109 is radiated onto the back surface 128 of the semiconductor 108. Scattering of the light beam 109 by the mechanisms to be etched in the semiconductor 108 can usually be avoided by irradiating the semiconductor 108 from the back side 128 with the laser 104 and by etching the mechanism closest to the etching surface 112 first before etching the mechanisms further away from the etching surface 112. However, for more complex three-dimensional structures, it may be necessary to etch the mechanisms in a different order to avoid scattering of the light beam 109. The etching modeling element 158 can be configured to generate etching control instructions to minimize the light beam 109 crossing already-etched mechanisms in the semiconductor 108.

[0046] In an exemplary embodiment, the etching modeling element 158 generates etching control instructions based on a physical model 160 that is configured to output a prediction of the movement of holes in the semiconductor 108. In one example, a desired etching position is provided to the physical model 160 (e.g., as indicated in the etching specification provided to the etching modeling element 158), and the physical model 160 outputs a prediction that includes an irradiation position, with the prediction indicating that holes generated at the irradiation position are expected to move to the desired etching position. That is, the physical model 160 receives the desired etching position of the semiconductor 108 and outputs a prediction of where the focus 144 of the laser 104 can be positioned to effect the desired etching.

[0047] The physical model 160 generates a prediction of the irradiation position relative to a desired etching position based on various parameters that affect the movement of holes in the semiconductor 108. Such physical effects include, but are not limited to, charge carrier diffusion, an induced electric field within the semiconductor 108 (e.g., caused by the voltage established between electrodes 122, 124), and current flow I through an electrochemical cell including the conductive materials 126, the semiconductor 108, the etchant 110, the electrodes 122, 124, and the voltage source 120. In generating the irradiation position prediction, the physical model 160 can further model the effects of these parameters based on other underlying data that can affect the modeled physical process. For example, the physical model 160 can model the effect of charge carrier diffusion based on the composition of the semiconductor 108 and the concentration of dopants or other impurities within the semiconductor 108. In other examples, the physical model 160 can model the effect of the induced electric field based on the voltage applied between the electrodes 122, 124.

[0048] In addition to receiving data regarding desired etching parameters (e.g., as specified in the etching definition presented to the etching modeling element 158), the physical model 160 receives data regarding the current state of one or more operating parameters of the system 100. For example, the process control element 142 can output data to the physical model 160 in real time, where the data indicates the current flow I, and the current flow I indicates the reaction rate of the etching reaction (e.g., the reactions described in Equations 1 and 2 above). Thus, the physical model 160 can continuously generate an up-to-date prediction of the irradiation position regarding the mechanism to be etched as desired, based on data regarding the current state of the system 100. The etching modeling element 158 generates up-to-date control instructions based on the prediction and transmits the up-to-date control instructions to the process control element 142, facilitating the control of the system 100 by the process control element 142 based on the latest information regarding the system situation.

[0049] In other exemplary embodiments, the physical model 160 may be configured to generate an irradiation position prediction based on the simulation results 162 stored in the data store 140. In one embodiment, the simulation results 162 include a number (e.g., hundreds or thousands or more) of results of simulated etching of a semiconductor according to various etching parameters. The physical model 160 may be configured to execute a machine learning algorithm on the simulation results 162 to identify simulation results of etching that exhibit an etching pattern similar to the desired etching as directed by the etching definition received by the etching modeling element 158. And the physical model 160 can output an irradiation position prediction based on the identified results.

[0050] Specific examples of physical effects modeled by the physical model 160 are described herein, but it is contemplated that the physical model 160 can model almost any physical process that can affect the resulting etching position of holes generated by the focus 144 of the laser 104 at the irradiation position.

[0051] It should be understood that systems and methods for selective electrochemical etching of various semiconductors are suitable for various sizes of etching mechanisms. For example, the mechanism can be etched according to the techniques described herein to have a size on the order of 10 nanometers to 1 micron, a size on the order of 10 microns to 1 millimeter, or any large mechanism.

[0052] Although various aspects of the exemplary system 100 operable with respect to selective etching of a semiconductor have been described in detail above, it should be understood that other configurations are possible and contemplated within the scope of the present disclosure. Referring now to FIG. 8, another exemplary system 800 is illustrated, where the semiconductor 108 is contained within an etching chamber 802 configured for front-side irradiation by a plurality of sub-bandgap energy lasers 804-808. The etching chamber 802 includes a first storage container 810 containing an etching solution 110 and a second storage container 812 containing the semiconductor 108 and a conductive element 814. The first storage container 810 further includes a window 816, and the light rays 818-822 emitted by respective lasers 804-808 pass through the window 816 and are focused by respective focusing lenses 824-828 toward the front-side etching surface 112 of the semiconductor 108. The light rays 818-822 are emitted toward the front-side surface 112 of the semiconductor 108, but it should be understood that the light rays 818-822 can be focused at respective foci within the body of the semiconductor 108 and beneath the surface 112. In the exemplary system 800, a voltage source 120 is connected between a conductive element 814 that makes electrical contact with the backside 128 of the semiconductor 108 and an electrode 830 located in the first storage container 810.

[0053] The process control element 142 of the computing device 106 can be configured to independently control the plurality of lasers 804-808 to etch the semiconductor 108 more quickly. For example, since the etching of the semiconductor 108 by the etching solution 110 is performed by holes that facilitate the etching reaction, generating holes simultaneously at multiple locations of the semiconductor 108 by the lasers 804-808 enables several mechanisms to be etched simultaneously. Any number of lasers can be included in a system for selective electrochemical etching of a semiconductor and can be controlled by the process control element 142. In other examples, it may be desirable for the process control element 142 to control the plurality of lasers to operate in parallel so that the same mechanism can be etched simultaneously multiple times within the semiconductor 108.

[0054] FIG. 9 illustrates an exemplary method related to selective etching of a semiconductor by irradiating the semiconductor with sub-bandgap energy. The method is illustrated and described as a series of operations performed in an order, but it should be understood and recognized that the method is not limited by the order of this sequence. For example, some operations may occur in a different order than described herein. Additionally, operations may occur simultaneously with other operations. Further, in some instances, not all operations are required to perform the method described herein.

[0055] Furthermore, the operations described herein may be computer-executable instructions implemented on one or more processors and / or stored on a computer-readable medium or media. The computer-executable instructions may include routines, subroutines, programs, execution threads, and / or the like. Additionally, the results of the operations of the method may be stored on a computer-readable medium and displayed on a display device and / or the like.

[0056] Referring now to FIG. 9, a method 900 is illustrated that facilitates selective etching of a semiconductor by irradiating the semiconductor with sub-bandgap energy. Method 900 begins at 902, and at 904, a voltage is applied between a first surface of the semiconductor and a second surface of the semiconductor. By way of example, a voltage may be applied between the first and second surfaces of the semiconductor by applying a voltage across electrodes (e.g., electrodes 122, 124 illustrated in exemplary system 100) immersed in a conductive solution that contacts the first and second surfaces of the semiconductor, respectively. At 906, the semiconductor is irradiated at a first location by a laser that emits light having an energy lower than the bandgap energy of the semiconductor. The laser is focused at a sufficient intensity such that holes are generated at the first location of the semiconductor, and etching of the semiconductor occurs at a second location based on the holes generated at the first location. The method then ends at 908.

[0057] Referring now to FIG. 10, a high-level diagram of an exemplary computing device 1000 that can be used in accordance with the systems and methods described herein is illustrated. For example, the computing device 1000 can be used in a system that controls the operation of a system for selective etching of semiconductors (e.g., system 100, system 800). As another example, the computing device 1000 can be used in a system that performs simulations of the movement of charge carriers within a semiconductor based on a physical model. The computing device 1000 includes at least one processor 1002 that executes instructions stored in a memory 1004. For example, the instructions may be instructions for performing functions described as being implemented by one or more of the elements described above, or instructions for performing one or more of the methods described above. The processor 1002 can access the memory 1004 via a system bus 1006. In addition to storing executable instructions, the memory 1004 can also store simulation results, etching definitions, states of various process parameters of the selective etching system, and the like.

[0058] The computing device 1000 further includes a data store 1008 that can be accessed by the processor 1002 via the system bus 1006. The data store 1008 can include executable instructions, simulation results, and the like. The computing device 1000 also includes an input interface 1010 that enables external devices to communicate with the computing device 1000. For example, the input interface 1010 can be used to receive instructions from an external computing device, a user, and the like. The computing device 1000 also includes an output interface 1012 that connects the computing device 1000 to one or more external devices. For example, the computing device 1000 can display text, images, and the like via the output interface 1012.

[0059] External devices that communicate with the computing device 1000 via the input interface 1010 and the output interface 1012 are contemplated to be included in an environment that provides almost any type of user interface with which a user can interact. Examples of types of user interfaces include graphical user interfaces, natural user interfaces, and the like. For example, a graphical user interface receives input from a user using one or more input devices such as a keyboard, a mouse, a remote control device, etc., and outputs it to an output device such as a display. Further, a natural user interface may enable a user to interact with the computing device 1000 without the constraints imposed by input devices such as a keyboard, a mouse, a remote control device, etc. Rather, a natural user interface may utilize voice recognition, touch and touch pen recognition, gesture recognition both on and adjacent to the screen, air gestures, head and eye tracking, voice and sound, vision, touch, gesture, machine intelligence, and the like.

[0060] In addition, although illustrated as a single system, it should be understood that the computing device 1000 may be a distributed system. Thus, for example, some devices may communicate using a network connection and may jointly perform operations described as being performed on the computing device 1000.

[0061] The various functions described in this specification may be performed by hardware, software, or any combination thereof. If performed by software, the functions may be stored or transmitted as one or more instructions or code on a computer-readable medium. A computer-readable medium includes a computer-readable storage medium. A computer-readable storage medium may be any commercially available storage medium accessible by a computer. By way of example, and not limitation, such computer-readable storage medium may be RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can store the desired program code in the form of instructions or data structures and that is accessible by a computer. As used herein, disk and disc include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc (BD), where disk typically magnetically reproduces data and disc typically optically reproduces data using a laser. Further, a propagated signal is not included within the scope of a computer-readable storage medium. A computer-readable medium also includes a communication medium including any medium that facilitates transfer of a computer program from one location to another. A connection, for example, may be a communication medium. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of communication medium. Combinations of the above should also be included within the scope of computer-readable medium.

[0062] Alternatively, or in addition, the functions described herein may be performed, at least in part, by one or more hardware logic elements. By way of example, and without limitation, exemplary types of hardware logic elements that may be used include field programmable gate arrays (FPGA), application specific integrated circuits (ASIC), application specific standard products (ASSP), system on chip systems (SOC), complex programmable logic devices (CPLD), and the like.

[0063] The foregoing includes examples of one or more embodiments. Of course, it is not possible to describe all conceivable modifications and alternative forms of the above apparatus or method for purposes of illustrating the foregoing aspects, but one of ordinary skill in the art will recognize that many further modifications and changes in the various aspects are possible. Accordingly, the described aspects are intended to embrace all such alternative forms, modifications, and variations that fall within the spirit and scope of the appended claims. Further, to the extent that the term "includes" is used in either the detailed description or the claims, such term is intended to be inclusive in a manner similar to the term "comprising" as interpreted when used as a transitional term in a claim.

Claims

1. A system comprising: a laser; an etching chamber configured to contain an etchant; a computing device configured to perform operations, the operations including: controlling the laser to irradiate a workpiece disposed within the etching chamber, wherein the laser generates holes within a lattice of the workpiece at a first position by multi-photon absorption (MPA), and the etchant within the etching chamber etches a surface of the workpiece at a second position based on the holes being generated within the lattice of the workpiece at the first position, the first position being within the lattice of the workpiece and the second position being on the surface of the workpiece; a computing device; a system.

2. The system of claim 1, wherein the laser has a photon energy less than a bandgap energy of the workpiece.

3. The system of claim 1, wherein the holes are generated within a volume of the workpiece beneath a surface of the workpiece.

4. The system of claim 1, wherein the surface is a front surface and the laser is controlled to irradiate the workpiece from a back side of the workpiece.

5. The system of claim 1, wherein the laser generates the holes at a focus of the laser by the MPA, and a fluence of a light beam emitted by the laser propagating within a region distal from the focus of the laser reduces a likelihood of the MPA occurring within the workpiece within the region as compared to occurrence at the focus of the laser.

6. The system of claim 1, wherein the operations further include controlling the laser to maintain irradiation of the workpiece by the laser such that additional holes are generated within the lattice of the workpiece by the MPA, and the etchant continues to etch the surface of the workpiece while the workpiece is irradiated by the laser.

7. The system of claim 1, wherein the operations further include controlling the laser to move a focus of the laser while the workpiece is irradiated such that a mechanism having a cavity is etched within the workpiece, and at least a portion of the cavity has no direct path to a surface of the workpiece.

8. The system according to claim 1, wherein the operation further comprises controlling the laser to move the focus of the laser while the workpiece is irradiated so that a mechanism following the path of the focus of the laser is etched within the workpiece.

9. A system comprising: a semiconductor workpiece; an etching chamber configured to accommodate the semiconductor workpiece; an etching agent disposed within the etching chamber; a laser configured to selectively irradiate the semiconductor workpiece disposed within the etching chamber; a control system configured to perform an operation, the operation comprising: controlling the laser to irradiate the semiconductor workpiece, the laser having a photon energy lower than the bandgap energy of the semiconductor workpiece, the laser generating holes in the lattice of the semiconductor workpiece at a first position by multi-photon absorption (MPA), and the etching agent etching the surface of the semiconductor workpiece at a second position based on the holes being generated in the lattice of the semiconductor workpiece at the first position, the first position being within the lattice of the semiconductor workpiece and the second position being on the surface of the semiconductor workpiece comprising; a control system; comprising; a system.

10. The system according to claim 9, wherein the etching agent is contained in an etching solution, and the etching solution comprises a surfactant.

11. The system according to claim 9, wherein the etching agent comprises at least one of hydrofluoric acid and ammonium fluoride.

12. The system according to claim 9, wherein the semiconductor workpiece comprises at least one of an elemental semiconductor, a III-V semiconductor, a III-nitride, a II-VI semiconductor, silicon carbide, and silicon germanium.

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