Method and apparatus for subtractive self-alignment

Abstract

A method for forming an interconnect structure for a semiconductor device is described. The method includes depositing an etch stop layer on a substrate by physical vapor deposition, followed by in-situ deposition of a metal layer on the etch stop layer. The in-situ deposition includes flowing a plasma processing gas into a chamber and exciting the plasma processing gas into a plasma to deposit the metal layer on the etch stop layer on the substrate. The substrate is continuously under vacuum during the deposition process and is not exposed to ambient air.

Description

Technical Field

[0001]

[0001] Embodiments of the present disclosure relate to the field of interconnect structures and interconnect structure manufacturing. Specifically, embodiments of the present disclosure provide a method for generating an interconnect structure comprising aligned vias and / or contacts using a subtractive method.

Background Art

[0002]

[0002] Interconnect structures, such as personal computers, workstations, computer servers, mainframes, and other computer-related devices such as printers, scanners, and hard disk drives, use logic and memory devices that provide substantial data storage functionality and capacity while suppressing power consumption. Feature scaling has been the driving force behind the growing semiconductor industry. By scaling features smaller and smaller, the density of functional units can be increased in the limited area of a semiconductor chip. For example, by reducing the size of transistors, the number of memory or logic devices incorporated on a chip can be increased, and products with increased capacity can be manufactured. However, there are still problems with the driving force for higher capacity than ever before. The need to optimize the performance of each device is becoming increasingly important.

[0003]

[0003] On-chip electrical interconnects were previously produced using a "dual damascene" manufacturing technique in which openings were created through various layers of the device structure and these openings were filled with a conductive material to form interconnects between layers and between device features located on individual layers. Dual damascene can enable the formation of vias (Vx) self-aligned with the upper metal lines (Mx). However, for chips based on a pitch of 50 nm (half-pitch dimension of 25 nm) and smaller feature sizes, there are gap filling and resistance constraints, and the use of the "dual damascene" manufacturing technique that has been relied on so far is infeasible.

[0004]

[0004] Therefore, a processing method for improving line resistance and via resistance is required.

Summary of the Invention

[0005]

[0005] One or more embodiments of the present disclosure are directed to a method of forming an interconnect structure. In one or more embodiments, the method includes depositing an etch stop layer on a substrate, the depositing including physical vapor deposition; and in-situ depositing a metal layer on the etch stop layer, the in-situ depositing including flowing a plasma processing gas into a chamber, exciting the plasma processing gas into plasma, and depositing a metal layer on the etch stop layer on the substrate, the substrate being continuously under vacuum and not exposed to ambient air.

[0006]

[0006] Another embodiment of the present disclosure is directed to a processing tool. In one or more embodiments, the processing tool includes a central transfer station including a robot configured to move wafers; and a plurality of process stations each connected to the central transfer station and providing a processing area separated from the processing areas of adjacent process stations, the plurality of process stations including a first physical vapor deposition chamber and a second physical vapor deposition chamber.

[0007]

[0007] A further embodiment of the present disclosure is directed to a non-transitory computer-readable medium including instructions. In one or more embodiments, the non-transitory computer-readable medium, when executed by a controller of a processing chamber, causes the processing chamber to perform a process of depositing an etch stop layer on a substrate, a process of in-situ depositing a metal layer on the etch stop layer, and a process of continuously maintaining the substrate under vacuum.

[0008]

[0008] To better understand the above-described features of the present disclosure, a more detailed description of the present disclosure briefly summarized above is obtained by referring to embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that since the present disclosure may admit other equally effective embodiments, the accompanying drawings illustrate only typical embodiments of the present disclosure and should not be considered as limiting the scope of the present disclosure.

Brief Description of the Drawings

[0009]

Figure 1

[0009] It is a schematic cross-sectional view of a physical vapor deposition chamber according to one or more embodiments of the present disclosure.

Figure 2

[0010] It is a cross-sectional view of a substrate according to one or more embodiments of the present disclosure.

Figure 3

[0011] It is a cross-sectional view of a substrate according to one or more embodiments of the present disclosure.

Figure 4

[0012] It is a cross-sectional view of a substrate according to one or more embodiments of the present disclosure.

Figure 5

[0013] It is an isometric view of an interconnect structure according to one or more embodiments of the present disclosure.

Figure 5A

[0014] It is a cross-sectional view of the interconnect structure of FIG. 5 according to one or more embodiments.

Figure 5B

[0015] It is a top view of the interconnect structure of FIG. 5 according to one or more embodiments.

Figure 6

[0016] It is an isometric view of an interconnect structure according to one or more embodiments of the present disclosure.

Figure 6A

[0017] It is a cross-sectional view of the interconnect structure of FIG. 6 according to one or more embodiments.

Figure 6B

[0018] It is a top view of the interconnect structure of FIG. 6 according to one or more embodiments.

Figure 7

[0019] An isometric view of an interconnection structure according to one or more embodiments of the present disclosure.

Figure 7A

[0020] A cross-sectional view of the interconnection structure of FIG. 7 according to one or more embodiments.

Figure 7B

[0021] A top view of the interconnection structure of FIG. 7 according to one or more embodiments.

Figure 8

[0022] A cross-sectional view of an interconnection structure according to one or more embodiments.

Figure 9

[0023] A cross-sectional view of an interconnection structure according to one or more embodiments.

Figure 10

[0024] An isometric view of an interconnection structure according to one or more embodiments of the present disclosure.

Figure 10A

[0025] A cross-sectional view of the interconnection structure of FIG. 10 according to one or more embodiments.

Figure 10B

[0026] A top view of the interconnection structure of FIG. 10 according to one or more embodiments.

Figure 11

[0027] An isometric view of an interconnection structure according to one or more embodiments of the present disclosure.

Figure 11A

[0028] A cross-sectional view of the interconnection structure of FIG. 11 according to one or more embodiments.

Figure 11B

[0029] A top view of the interconnection structure of FIG. 7 according to one or more embodiments.

Figure 12

[0030] An isometric view of an interconnection structure according to one or more embodiments of the present disclosure.

Figure 12A

[0031] A cross-sectional view of the interconnection structure of FIG. 12 according to one or more embodiments.

Figure 12B

[0032] A top view of the interconnection structure of FIG. 12 according to one or more embodiments.

Figure 13

[0033] An isometric view of an interconnection structure according to one or more embodiments of the present disclosure.

Figure 13A

[0034] A cross-sectional view of the interconnection structure of FIG. 13 according to one or more embodiments.

Figure 13B

[0035] A top view of the interconnection structure of FIG. 13 according to one or more embodiments.

Figure 14

[0036] An isometric view of an interconnection structure according to one or more embodiments of the present disclosure.

Figure 14A

[0037] A cross-sectional view of the interconnection structure of FIG. 14 according to one or more embodiments.

Figure 14B

[0038] A top view of the interconnection structure of FIG. 14 according to one or more embodiments.

Figure 15

[0039] A flowchart of a method according to one or more embodiments of the present disclosure.

Figure 16

[0040] A cluster tool is shown according to one or more embodiments.

DETAILED DESCRIPTION OF THE INVENTION

[0010]

[0041] Before describing some exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of the configurations or processing steps presented in the following description. The present disclosure is capable of other embodiments and can be implemented or executed in various ways.

[0011]

[0042] Terms such as "precursor", "reactant", "reactive gas", etc. used in this specification and the claims are used interchangeably to refer to any gas species that can react with the substrate surface.

[0012]

[0043] As used herein, "substrate" refers to any substrate on which film processing is performed during the manufacturing process or the surface of a material formed on a substrate. For example, the substrate surface on which processing can be performed includes materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. The substrate includes, but is not limited to, semiconductor wafers. The substrate can be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In the present disclosure, in addition to the direct film processing on the surface of the substrate itself, any of the disclosed film processing steps can also be performed on the underlying layer formed on the substrate, which will be disclosed in more detail later. The term "substrate surface" is intended to include such underlying layers as the context indicates. Thus, for example, when a film / layer or a partial film / layer is deposited on the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0013]

[0044] One or more embodiments advantageously provide an integrated process for forming interconnects. In one or more embodiments, both core metal deposition and metal etch stop deposition are optimized to low-resistance films with their own process capabilities. The deposition chamber is integrated into the same processing platform at a high vacuum level to avoid unwanted metal oxidation.

[0014]

[0045] One or more embodiments of the present disclosure advantageously provide a method that enables alignment of vias (with respect to the bottom line) based on a subtractive scheme. Embodiments of the self-aligned subtractive scheme enable the formation of an interconnect structure with an etch stop layer / liner. Some embodiments advantageously provide self-alignment of vias.

[0015]

[0046] One or more embodiments of the present disclosure advantageously improve the resistance scaling of chip interconnects. Resistance scaling includes two parts: line resistance and via resistance. In one or more embodiments, the line resistance is improved by implementing a low-resistance metal deposition. In one or more embodiments, the via resistance is improved (without vacuum breakage) by integrating an ultra-thin and low-resistance metal etch stop layer.

[0016]

[0047] In one or more embodiments, compared to conventional dual damascene interconnect manufacturing, the process of one or more embodiments advantageously achieves a line resistance reduction of 15 - 50% or more and a via resistance reduction of 20 - 30% or more. When compared to the conventional dual damascene method of depositing metal, the process of one or more embodiments achieves a film resistance of 50% or more for both the core metal film and the metal etch stop film. Additionally, in one or more embodiments, the integrated platform further reduces the effective resistivity by approximately 20%.

[0017]

[0048] An example of a physical vapor deposition chamber 50 useful for depositing the etch stop layer and metal layer of one or more embodiments is schematically shown in FIG. 1. The physical vapor deposition chamber 50 includes a vacuum chamber 52 disposed around a central axis 54. Above the vacuum chamber 52, a target 56 is supported through an isolator 58. The isolator 58 hermetically seals the target 56 to the vacuum chamber 52 and electrically insulates the target 56 from the electrically grounded vacuum chamber 52. A vacuum pump system (not shown) evacuates the interior of the vacuum chamber 52 to a pressure in the low millitorr range.

[0018]

[0049] In one or more embodiments, the shape of the front surface of the target 56 can be planar or generally concave with the outer peripheral edge being thicker than the inner diameter portion. The target 56 includes a layer of metal facing the interior of the vacuum chamber 52, and the metal layer typically contains no more than 5 atomic percent of elements other than the metal to be deposited, in order to provide a source of sputtered metal.

[0019]

[0050] To excite the plasma processing gas into plasma, the DC power supply 60 biases the target negatively with respect to the grounded vacuum chamber 52 or a grounded sidewall shield (not shown).

[0020]

[0051] In one or more embodiments, the plasma processing gas includes one or more of neon (Ne), argon (Ar), krypton (Kr), and xenon (Xe), and is supplied from a gas source through a mass flow controller into the vacuum chamber 52. In certain embodiments, the plasma processing gas includes krypton (Kr). Without intending to be bound by theory, it is believed that the use of a gas source 62 that includes krypton (Kr) as the plasma processing gas does not result in the implantation of krypton atoms. Thus, in one or more embodiments, the plasma processing gas comprises, consists essentially of, or consists of krypton (Kr). In some embodiments, the plasma processing gas includes substantially only krypton atoms. In one or more embodiments, the gas source 62 is connected to the vacuum chamber 52 through a mass flow controller 64.

[0021]

[0052] In one or more embodiments, the target power excites the plasma processing gas into a plasma, and the positive charge ions of the plasma are accelerated towards the target 54 to sputter metal atoms from the target. The density of the plasma is increased by disposing a magnetron 66 behind the target 56 where an inner magnetic pole 68 of one magnetic polarity is surrounded by an outer magnetic pole 70 of the opposite magnetic polarity. The magnetic poles 68, 70 project a magnetic field into the vacuum chamber 52 parallel to the surface of the target 56 to capture electrons and thereby increase the plasma density and as a result the sputtering rate. To enhance the uniformity of sputtering and the utilization rate of the target, the magnetic poles 68, 70 are asymmetric with respect to the central axis 54 but are supported on an arm 72 connected to a shaft 74 extending along the central axis 54. A motor 76 rotates the shaft 74, thereby rotating the magnetron 66 around the central axis 54 to provide at least azimuthal uniformity.

[0022]

[0053] A pedestal 80 within the vacuum chamber 52 supports the substrate 82 facing the target 56 so as to be coated with the metal sputtered from the target 56. Optionally, an RF power source 84 biases the pedestal 80 through a capacitive coupling circuit 86. The pedestal 80 is conductive so as to act as an electrode. The RF bias in the presence of the plasma within the vacuum chamber 52 generates a negative DC self-bias on the pedestal 80, as a result of which the sputtered metal ions are accelerated towards the substrate 82 and their trajectories penetrate deeply into all the high aspect ratio holes formed in the substrate 82.

[0023]

[0054] In one or more embodiments, the physical vapor deposition processing chamber used for the deposition of the etch stop layer is different from the physical vapor deposition processing chamber used for the deposition of the metal layer in terms of the sputter plasma source. In one or more embodiments, the physical vapor deposition processing chamber used for the deposition of the bulk metal has a DC or RF source, and the physical vapor deposition processing chamber used for the deposition of the etch stop layer has an RF source. In addition, the physical vapor deposition processing chamber used for the deposition of the bulk metal has a pedestal / waf er temperature that operates at a high temperature above 250 °C, and the deposition of the etch stop layer occurs at a low temperature from about 20 °C to about 400 °C. Further, the physical vapor deposition processing chamber used for the deposition of the bulk metal uses krypton (Kr) as the sputter gas, and the deposition of the etch stop layer uses N2 (nitridation) for a titanium (Ti) target or argon (Ar) for a titanium nitride (TiN) target.

[0024]

[0055] Embodiments of the present disclosure generate an interconnect structure that includes the deposition of multiple layers of material followed by the use of subtractive techniques such as dry etching techniques or atomic layer etching (ALE). In one or more embodiments, the conductive interconnect structure formed is surrounded by a dielectric material as needed.

[0025]

[0056] As shown in Figure 2, in one or more embodiments, a first etch stop layer 110 is formed on a substrate 102. The substrate 102 can be any suitable material described herein. For illustrative purposes only, the substrate 102 will be described hereinafter as a silicon substrate. In one or more embodiments, the substrate 102 represents a structure that contacts the underlying semiconductor structure to connect to a semiconductor device underlying the interconnect structure. The substrate 102 can be, for example, a tungsten plug when connected to a FEOL (front end of the line) device such as a transistor, capacitor, or resistor; or the substrate 102 can be copper or other conductive plug material when interconnects are required.

[0026]

[0057] The illustrated embodiment includes an optional barrier layer 106. In one or more embodiments, the barrier layer 106 includes a liner. In one or more embodiments, the barrier layer 106 can also be omitted from the stack. For example, if the first metal layer 108 has good adhesion to the substrate 102, the optional barrier layer 106 may not be necessary. The optional barrier layer 106 can be any suitable material capable of enhancing the adhesion of the first metal layer 108 to the substrate 102. In one or more embodiments, the barrier layer 106 includes one or more of tantalum (Ta), titanium (Ti), tantalum nitride (TaN), titanium nitride (TiN), or tantalum / tantalum nitride (Ta / TaN). The optional barrier layer 106 can be deposited by any suitable technique known to those skilled in the art, including but not limited to atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), evaporation, or plating.

[0027]

[0058] In one or more embodiments, the first metal (conductive) layer 108 is on the optional barrier layer 106; or on the substrate 102 if the optional barrier layer 106 is omitted. In one or more embodiments, the barrier layer 106 includes a liner. The first metal layer 108 can be any suitable layer deposited by any suitable technique known to those skilled in the art. In one or more embodiments, the first metal layer 108 is deposited using physical vapor deposition.

[0028]

[0059] In one or more embodiments, the first etch stop layer 110, which is also a conductor layer, is located on the first metal layer 108. In one or more embodiments, the first etch stop layer 110 includes an etch stop material. The etch stop material can include any suitable material known to those skilled in the art. In one or more embodiments, the etch stop material includes one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), tungsten (W), or ruthenium (Ru). In a particular embodiment, the etch stop material includes titanium nitride (TiN).

[0029]

[0060] In one or more embodiments, the first etch stop layer 110 is formed by physical vapor deposition (PVD) using a processing chamber as shown in FIG. 1. In one or more embodiments, a radio frequency (RF) source is used to generate a highly ionized plasma having a high concentration of metal ions. Without intending to be bound by theory, the highly ionized plasma is thought to facilitate a change in the crystal orientation of the first etch stop layer 110, resulting in a beneficial combination of tensile stress and high density, which in turn results in excellent etch selectivity.

[0030]

[0061] In one or more embodiments, a target 54 containing an etch stop material is provided in the processing chamber 50 shown in FIG. 1. The pedestal 80 includes a high current electrostatic chuck at a temperature in the range of about 20° C. to about 400° C., including the range of about 200° C. to about 300° C. In one or more embodiments, the pedestal 80 within the processing chamber 50 supports the substrate 102 opposite the target 54 such that the first etch stop layer 110 sputtered from the target 54 coats the substrate 102. In one or more embodiments, an RF power source biases the pedestal supporting the substrate 102 through a capacitive coupling circuit. The pedestal is conductive so as to act as an electrode. The RF bias in the presence of the plasma within the processing chamber generates a negative DC self-bias on the pedestal 80, such that the sputtered etch stop material ions are accelerated toward the substrate 102, and their trajectories penetrate deeply into all of the high aspect ratio holes formed in the substrate 102. In one or more embodiments, the RF power source is in the range of about 1 kW to about 10 kW, including the range of about 2 kW to about 3 kW.

[0031]

[0062] In one or more embodiments, the first etch stop layer 110 deposited on the substrate 102 has a thickness in the range of about 0.5 nm to 5.0 nm.

[0032]

[0063] As shown in FIG. 3, in one or more embodiments, after the first etch stop layer 110 is deposited, a metal layer 112 is deposited on the first etch stop layer 110. In one or more embodiments, the metal layer 112 includes a low-resistance core metal. In one or more embodiments, a lower-resistance core metal is deposited with a high-temperature biasable electrostatic chuck (ESC). In one or more embodiments, the metal layer 112 is deposited by a physical vapor deposition process. In one or more embodiments, the metal layer 112 may include one or more of ruthenium (Ru), molybdenum (Mo), tungsten (W), copper (Cu), cobalt (Co), iridium (Ir), metal silicide, and metal alloy. In one or more embodiments, the metal layer 112 includes one or more of ruthenium (Ru), molybdenum (Mo), tungsten (W), copper (Cu), cobalt (Co), and iridium (Ir). In a particular embodiment, the metal layer 112 includes ruthenium (Ru). In other particular embodiments, the metal layer 112 includes molybdenum (Mo). In other particular embodiments, the metal layer 112 includes tungsten (W).

[0033]

[0064] In one or more embodiments, a target 54 including a metal to be sputtered to deposit the metal layer 112 is provided in a processing chamber, such as chamber 50 shown in FIG. 1. The processing chamber may also include a pedestal for supporting the substrate 102. The pedestal 80 includes a high-current electrostatic chuck at a temperature of less than about 500°C. In one or more embodiments, the temperature ranges from about 200°C to about 450°C. In one or more embodiments, a nuclide selected from neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), and combinations thereof is introduced into the chamber and excited into a plasma to deposit the metal layer 112 on the first etch stop layer 110 on the substrate 102.

[0034]

[0065] In one or more embodiments, the DC power supply is negatively biased to a target of about 500 W to about 10 kW, including from about 900 W to about 8 kW and from about 900 W to about 2 kW, with respect to the grounded processing chamber 50 or the grounded sidewall shield, and excites a plasma processing gas, such as neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), into a plasma.

[0035]

[0066] In one or more embodiments, an AC power supply provides power in the range of about 0 W to about 500 W, including from about 200 W to about 400 W.

[0036]

[0067] In one or more embodiments, the pressure in the processing chamber is in the range of about 5 mTorr to about 100 mTorr, including from about 5 mTorr to about 50 mTorr.

[0037]

[0068] As shown in FIG. 4, in one or more embodiments, a metal seed 105 is first deposited, and then a bulk metal layer 112 is deposited on the metal seed 105. Without intending to be bound by theory, depositing the metal seed 105 first and subsequently depositing the bulk metal layer 112 is thought to improve the metal particles. Thus, as shown in FIG. 4, in one or more embodiments, a target 54 containing the metal of the metal layer 112 is provided within the processing chamber. The processing chamber may also include a pedestal 80 that supports the substrate. The pedestal 80 includes a high current electrostatic chuck at a temperature of less than about 500 °C. In one or more embodiments, the temperature is in the range of about 200 °C to about 450 °C. In one or more embodiments, a nuclide selected from neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), and combinations thereof is flowed into the chamber and excited into a plasma to deposit the metal seed 105 on the first etch stop layer 110 on the substrate 102.

[0038]

[0069] In one or more embodiments, the metal seed 105 comprises the same material as the metal layer 112. In one or more embodiments, the metal seed 105 comprises one or more of ruthenium (Ru), molybdenum (Mo), tungsten (W), copper (Cu), cobalt (Co), iridium (Ir), metal silicide, and metal alloy. In one or more embodiments, the metal seed 105 comprises one or more of ruthenium (Ru), molybdenum (Mo), tungsten (W), copper (Cu), cobalt (Co), and iridium (Ir). In one or more particular embodiments, the metal seed 105 comprises ruthenium (Ru). In other particular embodiments, the metal seed 105 comprises molybdenum (Mo).

[0039]

[0070] In one or more embodiments, the DC power supply biases the target 54 negatively from about 500 W to about 10 kW with respect to the grounded processing chamber 50 or the grounded sidewall shield, exciting a plasma processing gas such as neon (Ne), argon (Ar), krypton (Kr), or xenon (Xe) into a plasma.

[0040]

[0071] In one or more embodiments, the AC power supply provides power in the range of from about 0 W to about 500 W.

[0041]

[0072] Thereafter, in one or more embodiments, the metal layer 112 is then deposited on the metal seed 105. In one or more embodiments, a target 54 containing the metal of the metal layer 112 is provided within the processing chamber. The processing chamber may also include a pedestal 80 that supports the substrate. The pedestal 80 includes a high-current electrostatic chuck at a temperature of less than about 500°C. In one or more embodiments, the temperature ranges from about 200°C to about 450°C. In one or more embodiments, a nuclide selected from neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), and combinations thereof is flowed into the chamber and excited into a plasma to deposit the metal layer 112 on the metal seed 105 over the first etch stop layer 110 on the substrate 102.

[0042]

[0073] In one or more embodiments, the DC power supply biases the target 54 negatively with respect to the grounded processing chamber 50 or the grounded sidewall shield at about 900 W to about 8 kW and about 900 W to about 2 kW, and excites a plasma processing gas, such as neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), into a plasma.

[0043]

[0074] In one or more embodiments, the AC power supply provides power in the range of about 200 W to about 400 W.

[0044]

[0075] As shown in FIG. 5, by depositing the first etch stop layer and the 110 metal layer 112 (and optionally the metal seed 105) in such a manner, an interconnect structure having no failing etch stop layer is obtained.

[0045]

[0076] FIG. 5 is an isometric view 100 of an exemplary starting “stack” 101 of layers used to form an interconnect structure. FIG. 5A is a cross-sectional view 100A of the device shown in FIG. 5. FIG. 5B is a top view 100B of the interconnect structure shown in FIG. 5. Those skilled in the art will understand that the exemplary “stack” 101 shown is merely one possible configuration and should not be construed as limiting the scope of the present disclosure.

[0046]

[0077] In one or more embodiments, the first metal (conductive) layer 108 is on an optional barrier layer 106; or, if the optional barrier layer 106 is omitted, on the substrate 102. In one or more embodiments, the barrier layer 106 includes a liner. The first metal layer 108 can be any suitable layer deposited by any suitable technique known to those skilled in the art. In one or more embodiments, the first metal layer 108 is deposited using physical vapor deposition as described above with respect to the metal layer 112. In some embodiments, the first metal layer 108 is a conformal layer of a material selected from metals such as, but not limited to, tungsten (W), cobalt (Co), ruthenium (Ru), molybdenum (Mo), aluminum (Al), copper (Cu), silicon compounds, graphene, or combinations thereof. In one or more embodiments, the first metal layer includes ruthenium (Ru).

[0047]

[0078] In one or more embodiments, the first etch stop layer 110, which is also a conductor layer, is located on the first metal layer 108. In one or more embodiments, the second metal layer 112 is formed on the first etch stop layer 110. The second metal layer 112 may be the same as (but need not be) the first metal layer 108 described above. In one or more embodiments, the second metal layer 112 includes a metal that forms pillars. In some embodiments, the metal that forms pillars is selected from, for example, but not limited to, tungsten (W), cobalt (Co), ruthenium (Ru), molybdenum (Mo), aluminum (Al), copper (Cu), silicon compounds, graphene, or one or more of combinations thereof. In one or more embodiments, the second metal layer 112 includes ruthenium (Ru).

[0048]

[0079] In one or more embodiments, the first etch stop layer 110 is for etching stop of the second metal layer 112. In one or more embodiments, the second metal layer 112 contains ruthenium (Ru), and the first etch stop layer 110 contains one or more of titanium, tantalum, titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), or molybdenum (Mo), etc. In one or more embodiments, when the first metal layer 108 and the second metal layer 112 are different materials and have high etching selectivity to each other, the first etch stop layer 110 is omitted.

[0049]

[0080] In one or more embodiments, the second etch stop layer 114 is located on the second metal layer 112. In one or more embodiments, the composition of the second etch stop layer 114 may be the same as that of the first etch stop layer 110 (but it is not necessary to be so). In one or more embodiments, by having the first etch stop layer 110 and the second etch stop layer 114 as the same material, the process is simplified. In one or more embodiments, the second etch stop layer 114 is deposited using a technique selected from CVD, PVD, ALD, deposition from an evaporated metal source, electroplating, and can be any suitable material including, but not limited to, a conformal layer of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), W, Co, Ru, niobium (Nb), niobium nitride (NbN), and combinations thereof, or can be an oxide of titanium (Ti) doped with a dopant such as a silicon compound.

[0050]

[0081] In one or more embodiments, the second etch stop layer 114 is for etching stop of the hard mask layer 116. In one or more embodiments, the hard mask layer 116 includes silicon oxide, and the second etch stop layer 114 includes one or more of titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), silicon nitride (SiN), silicon carbonitride (SiCN), or silicon oxynitride (SiON). In one or more embodiments, the second etch stop layer 114 is omitted and does not exist. In some embodiments, the etchant for the hard mask layer 116 does not affect the second metal layer 112. For example, when the hard mask layer 116 includes silicon oxide (SiO) and the second metal layer 112 includes ruthenium, the second etch stop layer 114 does not exist.

[0051]

[0082] In one or more embodiments, the hard mask layer 116 is located on the second etch stop layer 114. In one or more embodiments, the hard mask layer is used in combination with an overlying "lithography stack" for transferring device patterns through the underlying layers 114, 112, 110, and 108 described above. In one or more embodiments, the hard mask layer 116 is a single layer. In other embodiments, the hard mask layer 116 is a combination of layers. The hard mask layer 116, although not described herein, is fabricated in one or more embodiments using materials and patterning techniques known in the prior art as being able to provide patterns below 10nm Node (16nm HPCD). In some embodiments, the hard mask layer 116 includes a metallic or dielectric mask material. Suitable dielectric materials include, but are not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), aluminum oxide (AlOx), aluminum nitride (AlN), and combinations thereof. Those skilled in the art will recognize that the use of chemical formulas such as SiO to represent silicon oxide does not imply any specific stoichiometric relationship between the elements. The formula merely identifies the major elements of the film.

[0052]

[0083] In one or more embodiments, an anti-reflective bottom coating (BARC) 118 and a photoresist 120 are formed thereon. The illustrated photoresist 120 is patterned with trenches 122; however, the pattern can be any suitable shape or combination of shapes.

[0053]

[0084] In one or more embodiments, the combination of the hard mask layer 116, the anti-reflective bottom coating (BARC) 118, and the photoresist 120 is referred to herein as a first "lithographic patterning structure".

[0054]

[0085] FIG. 6 is an isometric view 200 of a partially patterned structure formed from the starting stack 101 shown in FIG. 5. FIG. 6A is a cross-sectional view 200A of the structure shown in FIG. 6. FIG. 6B is a top view 200B of the structure shown in FIG. 6. In one or more embodiments, the second metal layer 112 is etched in a first direction toward the top surface of the first etch stop layer 110 to produce a first conductive line 202 that extends upwardly above the first etch stop layer 110. In one or more embodiments, forming the first conductive line 202 includes exposing the patterned interconnect stack 101 to an etch gas and etching the patterned interconnect stack at a high etch rate. In one or more embodiments, the second metal layer 112 is etched at a high rate in the range of about 0.5 nm / sec to about 5 nm / sec, including about 1 nm / sec, about 1.5 nm / sec, about 2 nm / sec, about 2.5 nm / sec, about 3 nm / sec, about 3.5 nm / sec, about 4 nm / sec, about 4.5 nm / sec, or about 5 nm / sec, for a period in the range of about 10 seconds to about 100 seconds, including about 10 seconds to about 80 seconds, about 20 seconds to about 90 seconds, or about 10 seconds to about 60 seconds. Without intending to be bound by theory, a combination of high etch rates over a short time is thought to minimize sputtering of the hard mask layer 116. In one or more embodiments, the second metal layer 112 includes ruthenium (Ru) and is etched in a SYM3 (registered trademark) etch chamber of Applied Materials, Inc. (Santa Clara, California, SCLA), etc. In one or more embodiments, the source power is in the range of about 500 watts (W) to about 1800 W, the bias power is in the range of about 50 W to about 300 W, the pulsed duty cycle of the bias power is in the range of about 15% to about 90%, the pressure is in the range of about 5 mTorr to about 50 mTorr, the temperature of the electrostatic chuck is in the range of about 30° C. to about 90° C., the gas flow of oxygen is in the range of about 100 sccm to about 700 sccm, and the gas flow of chlorine is in the range of about 20 sccm to 100 sccm.

[0055]

[0086] In one or more embodiments, located on the conductive line 202 formed from the second metal layer 112 are the lines 204 of the second etch stop layer 114 and the lines 206 of the hard mask layer 116. In one or more embodiments, the conductive line 202 is formed from a metal that provides an effective resistivity determined by the size of the nodes of the semiconductor structure. In one or more embodiments, the trench 208 separates columns of the second metal layer 112, and the second metal layer 112 is further processed to be conductive interconnect contacts.

[0056]

[0087] FIG. 7 is an isometric view 300 of the partially patterned structure shown in FIG. 6 after removal of the patterning stack. FIG. 7A is a cross-sectional view 300A of the structure shown in FIG. 7. FIG. 7B is a top view 300B of the structure shown in FIG. 7. In one or more embodiments, the first etch stop layer 110 is etched down to the top surface of the first metal layer 108, and then the first metal layer 108 is etched to form the second conductive line 212 above an optional barrier layer 106 on the substrate 102. In one or more embodiments, the barrier layer 106 includes a liner. In one or more embodiments, the first etch stop layer 110 is titanium nitride (TiN) and is etched in a SYM3 (registered trademark) etching chamber of Applied Materials, Inc. (Santa Clara, California). In one or more embodiments, the source power ranges from about 300 W to about 1000 W, the bias power ranges from about 50 W to about 300 W, the pressure ranges from about 4 to about 15 mTorr, the temperature of the electrostatic chuck ranges from about 30 °C to about 70 °C, the chlorine gas flow ranges from about 30 sccm to about 250 sccm, the methane gas flow ranges from about 10 sccm to about 100 sccm, and the nitrogen gas flow ranges from about 30 to about 500 sccm. In one or more embodiments, the etching process of titanium nitride (TiN) is etched by pulsing the bias and source power in a frequency range from about 1000 Hz to about 10000 Hz and a duty cycle range from about 15% to about 90%.

[0057]

[0088] FIG. 8 is a cross-sectional view of a structure according to one or more embodiments. As shown in FIG. 8, in one or more embodiments, the second metal layer 112 of the first conductive line 202 is stabilized in the etching process of the first metal layer 108. The etching in the stabilization process reduces the erosion / thickness deficiency of the sidewalls of the first conductive line 202 by preventing active species (e.g., radicals or energetic ions) from the reaction with the first conductive line 202. In one or more embodiments, the sidewalls 203 of the first conductive line 202 are stabilized by utilizing the hard mask sputtering effect of sputtering the hard mask material 214 onto the sidewalls 203 of the first conductive line 202. In one or more embodiments, the hard mask material 214 to be sputtered is an oxide, such as silicon oxide, and the first metal layer 108 is ruthenium (Ru). In one or more embodiments, the hard mask sputtering effect is achieved by mixing a dilution gas (e.g., Ar, H2, He, N2) with the etching gas. In one or more embodiments, the hard mask sputtering effect is achieved by mixing a dilution gas (e.g., Ar, H2, He, N2) with the etching gas for the etching of ruthenium (Ru). In one or more embodiments, the etching of ruthenium (Ru) is performed in a SYM3 (registered trademark) etching chamber of Applied Materials, Inc. (Santa Clara, California). In one or more embodiments, the source power ranges from about 300 W to about 1800 W, the bias power ranges from about 50 W to about 300 W, the pulsed duty cycle of the bias power ranges from about 15% to about 90%, the pressure ranges from about 4 mTorr to about 30 mTorr, the temperature of the electrostatic chuck ranges from about 30 °C to about 90 °C, the gas flow of oxygen ranges from about 100 to about 700 sccm, and the gas flow of chlorine ranges from about 20 to about 100 sccm. In one or more embodiments, the dilution gas is nitrogen (N2) and is provided at a flow rate of 10 to 100 sccm.

[0058]

[0089] FIG. 9 is a cross-sectional view of a structure according to one or more embodiments. As shown in FIG. 9, in one or more embodiments, the sputtered hard mask 214 on the sidewall 203 of the first conductive line 202 is then removed by a wet etching process or a dry etching process. In some embodiments, the sputtered hard mask 214 includes a metallic or dielectric mask material. Suitable dielectric materials include, but are not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), aluminum oxide (AlOx), aluminum nitride (AlN), and combinations thereof. In one or more embodiments, the sputtered hard mask 214 includes silicon oxide and is removed by a dilute hydrofluoric acid (DHF) wash. In one or more embodiments, the DHF wash is performed in a dilution range of about 100:1 to about 2000:1 for a period of about 10 seconds to about 10 minutes. In one or more embodiments, the sputtering of the sputtered hard mask 214 includes adding a diluent gas to the etching gas. In one or more particular embodiments, the sputtered hard mask 214 includes silicon oxide, the second conductive line 212 includes ruthenium (Ru), and the diluent gas includes nitrogen (N2).

[0059]

[0090] In one or more embodiments, located on the second conductive line 212 formed from the first metal layer 108 are the lines 210 of the first etch stop layer 110, the first conductive line 202, the lines 204 of the second etch stop layer 114, and the lines 206 of the hard mask layer 116. In one or more embodiments, the second conductive line 212 is formed from a metal that provides an effective resistivity determined by the size of the nodes of the semiconductor structure. In one or more embodiments, trenches 208 separate columns of the conductive lines 202, 212 that extend upwardly, and these conductive lines are further processed to be conductive interconnect contacts.

[0060]

[0091] Figure 10 is an isometric view 400 of a partially patterned structure shown in FIG. 7 after filling a previously etched trench 208 with a second BARC or spin-on dielectric material 124, which is used to support a photoresist 126 to be applied later. In one or more embodiments, the BARC (bottom anti-reflective coating) or spin-on dielectric material 124 is formed from at least one polymer component, a cross-linking component, and an acid generator. In one or more embodiments, the BARC or spin-on dielectric material 124 is post-cured after application to the substrate surface such that the precursor material can penetrate into spaces having minimum critical dimensions. FIG. 10A is a cross-sectional view 600A of the structure shown in FIG. 10. FIG. 10B is a top view 600B of the structure shown in FIG. 10, which includes trenches filled with BARC or spin-on dielectric 124. The trenches separate rows of material that are to be further processed to form conductive interconnects.

[0061]

[0092] In one or more embodiments, the combination of a bottom anti-reflective coating (BARC) or spin-on dielectric material 124 and a photoresist 126 is referred to herein as a second "lithographic patterning structure".

[0062]

[0093] Figure 11 is an isometric view 700 of a partially patterned structure shown in FIG. 10 after etching a series of spaces (trenches) 130 at a certain angle with respect to a previously etched trench 128 (not shown as it is filled with BARC or spin-on dielectric 124). In one or more embodiments, the BARC or spin-on dielectric layer 124 and the hard mask layer 116 are etched downward to the top surface of the first conductive line 202. FIG. 11A is a cross-sectional view 700A of the structure shown in FIG. 11. FIG. 11B is a top view 700B of the structure shown in FIG. 1.

[0063]

[0094] FIG. 12 is an isometric view 800 of a partially patterned structure shown in FIG. 11 after etching a series of spaces (trenches) 130 at a certain angle with respect to a previously etched trench 128 (not shown as it is filled with BARC or spin-on dielectric 124). In one or more embodiments, the BARC or spin-on dielectric layer 124 and the conductive line 202 are etched up to the upper surface of the lines of the first etch stop layer 210. FIG. 12A is a cross-sectional view 800A of the structure shown in FIG. 12. FIG. 12B is a top view 800B of the structure shown in FIG. 12.

[0064]

[0095] FIG. 13 is an isometric view 900 of a partially patterned structure shown in FIG. 12 after removing the BARC or spin-on dielectric layer 124 by a dry etching process using an etching liquid plasma that typically does not affect layers 206, 202, 210, 212, 106, and 102. In one or more embodiments, the plasma etching process utilizes a mixture of H2 / N2 or H2 / O2 with or without any dilution gas (e.g., Ar, He). FIG. 13A is a cross-sectional view 900A of the structure shown in FIG. 13. FIG. 13B is a top view 900B of the structure shown in FIG. 13.

[0065]

[0096] FIG. 14 is an isometric view 100 of a partially patterned structure shown in FIG. 13 after removing the first etch stop layer 210 and the barrier layer 106 by a dry etching process using an etchant plasma that typically does not affect layers 202, 210, 212, 106, and 102. In one or more embodiments, the plasma etching process utilizes a mixture of H2 / N2 or H2 / O2 with or without any diluent gas (e.g., Ar, He). Without intending to be bound by theory, since the first etch stop layer 210 and the barrier layer 106 are conductive layers, it is believed that they must be etched in the same pattern as the first metal layer 108 so that no lines are shortened. In one or more embodiments, the barrier layer 106 includes a liner that must be etched. FIG. 14A is a cross-sectional view 1000A of the structure shown in FIG. 14. FIG. 14B is a top view 1000B of the structure shown in FIG. 14.

[0066]

[0097] FIG. 15 is a process flow diagram of a method 1100 according to one or more embodiments of the present disclosure. In step 1106, an etch stop layer is formed on a substrate. As described above, the etch stop layer can be formed by physical vapor deposition (PVD) for depositing a thin film. In step 1108, a metal layer is deposited on the etch stop layer by physical vapor deposition. In step 1110, an interconnect stack is formed. In step 1120, a first conductive line is formed (e.g., by a subtractive etching process). In step 1130, a second conductive line is formed (e.g., by a subtractive etching process). In step 1140, a dielectric material (e.g., BARC or spin-on dielectric) is deposited. In step 1150, an interconnect device is etched to form self-aligned vias. In step 1160, the dielectric material is removed. In step 1170, the first etch stop layer 210 and the barrier layer 106 are etched. In one or more embodiments, the barrier layer 106 includes a liner that is etched.

[0067]

[0098] In some embodiments, the deposition of the first etch stop layer 110 and the second metal layer 112 is performed in an integrated system. In one or more embodiments, the integrated system prevents oxidation of the first etch stop layer 110, which can increase the resistance of the first etch stop layer 110. In some embodiments, the deposition of the barrier layer 106 and the first metal layer 108 is performed in an integrated system. In one or more embodiments, the integrated system prevents oxidation of the barrier layer 106, which can increase the resistance of the barrier layer 106. In one or more embodiments, the barrier layer 106 includes a liner, and the integrated system prevents oxidation of the liner, which can increase the resistance of the liner.

[0068]

[0099] By using a stack of varying layers including a line metal; an etch stop material layer having a relatively high conductivity component (in the form of a metal or a doped ceramic or polymer material); and a pattern transfer layer (typically including a hard masking material) forming a lithography stack; and by applying subtractive techniques to form a desired structure within the stack, it is possible to form interconnect conduits in the form of struts, for example, without the need to fill small capillaries with a fluid conductive material. The method of forming the interconnect structure described above allows for pitches of 50 nm or less in the By design to proceed.

[0069]

[0100] In one or more embodiments, the substrate is moved from a first physical vapor deposition chamber in which the first etch stop layer 110 is deposited to a separate second physical vapor deposition chamber in which the metal layer 108 is deposited. In one or more embodiments, the movement of the substrate from the first chamber to the second chamber is an integrated process performed under vacuum without an air break.

[0070] In one or more embodiments, the substrate then moves to another processing chamber for further processing. The substrate can be moved directly from the physical vapor deposition chamber to a separate processing chamber, or it can be moved from the physical vapor deposition chamber to one or more transfer chambers and then to a separate processing chamber. Thus, the processing apparatus can include a plurality of chambers that communicate with a transfer station. This type of apparatus is sometimes also referred to as a "cluster tool" or "clustered system".

[0071]

[0102] Generally, a cluster tool is a modular system comprising a plurality of chambers that perform various functions including central detection and orientation of the substrate, degassing, annealing, deposition and / or etching. According to one or more embodiments, the cluster tool includes at least a first chamber and a central transfer chamber. The central transfer chamber can accommodate a robot capable of reciprocally transporting the substrate between and among the processing chambers and the load lock chamber. The transfer chamber is typically maintained in a vacuum state and provides an intermediate stage for reciprocally transporting the substrate from one chamber to another and / or to a load lock chamber positioned at the front end of the cluster tool. Two well-known cluster tools that can be adapted for the present invention are Centura® and Endura®, both available from Applied Materials, Inc. (Santa Clara, Calif.). However, the exact arrangement and combination of the chambers can be varied for the purpose of performing specific steps of the processes described herein. Other processing chambers that can be used include, but are not limited to, cyclic layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etching, pre-cleaning, chemical cleaning, heat treatments such as rapid thermal processing (RTP), plasma nitridation, degassing, orientation, hydroxylation, and other substrate processing. By performing the processes within the chambers on the cluster tool, surface contamination of the substrate by atmospheric impurities can be avoided without oxidizing prior to depositing the next film.

[0072]

[0103] According to one or more embodiments, the substrate is continuously under vacuum or "load lock" conditions and is not exposed to ambient air when moved from one chamber to the next. Thus, the transfer chamber is under vacuum and is "pumped down" under vacuum pressure. An inert gas may be present within the processing chamber or the transfer chamber. In some embodiments, the inert gas is used as a purge gas to remove some or all of the reactants. According to one or more embodiments, a purge gas is injected at the outlet of the deposition chamber to prevent reactants from moving from the deposition chamber to the transfer chamber and / or additional processing chambers. Thus, the flow of inert gas forms a curtain at the outlet of the chamber.

[0073]

[0104] The substrate can be processed within a single substrate deposition chamber, where one substrate is loaded, processed, and unloaded before another substrate is processed. The substrate can also be processed in a continuous manner similar to a conveyor system where multiple substrates are individually loaded into the first portion of the chamber, move through the chamber, and are unloaded from the second portion of the chamber. The shape of the chamber and associated conveyor system can form a linear path or a curved path. Additionally, the processing chamber can be a carousel in which multiple substrates move around a central axis and are exposed to processes such as deposition, etching, annealing, cleaning, etc. throughout the carousel path.

[0074]

[0105] During processing, the substrate can be heated or cooled. Such heating or cooling can be achieved by any suitable means including, but not limited to, changing the temperature of the substrate support and flowing heated or cooled gas over the substrate surface. In some embodiments, the substrate support includes a heater / cooler that can be controlled to conductively change the substrate temperature. In one or more embodiments, the gas (reactive or inert gas) being used is heated or cooled to locally change the substrate temperature. In some embodiments, the heater / cooler is arranged adjacent to the substrate surface within the chamber to change the substrate temperature by convection.

[0075]

[0106] The substrate may also be stationary or rotated during processing. The rotating substrate can be rotated continuously or stepwise. For example, the substrate may be rotated throughout the process or rotated incrementally between exposures to different reactive or purge gases. Rotating the substrate (continuously or stepwise) during processing can help to achieve more uniform deposition or etching, for example, by minimizing the effects of local variability in the geometry of the gas flow.

[0076]

[0107] Additional embodiments of the present disclosure are directed to a processing tool 900 for forming and the described method of a memory device, as shown in FIG. 16. The cluster tool 900 includes at least one central transfer station 921, 931 having a plurality of sides. Robots 925, 935 are positioned within the central transfer stations 921, 931 and are configured to move the robot blades and wafers to each of the plurality of sides.

[0077]

[0108] The cluster tool 900 includes a plurality of process chambers 902, 904, 906, 908, 910, 912, 914, 916, and 918, also referred to as process stations, connected to a central transfer station. The various process chambers provide separate processing areas isolated from adjacent process stations. The process chambers can be any suitable chambers including, but not limited to, physical vapor deposition chambers, one or more transfer spaces, wafer orienters / gas bleed chambers, annealing chambers, and etching chambers. The specific arrangement of the process chambers and components can be varied according to the cluster tool and should not be construed as limiting the scope of the present disclosure.

[0078]

[0109] In some embodiments, the cluster tool 900 includes at least one physical vapor deposition chamber. In some embodiments, the cluster tool 900 includes two physical vapor deposition chambers connected to the central transfer station.

[0079]

[0110] In the embodiment shown in FIG. 16, a factory interface 950 is connected to the front of the cluster tool 900. The factory interface 950 includes a loading chamber 954 and an unloading chamber 956 on the front surface 951 of the factory interface 950. The loading chamber 954 is shown on the left side and the unloading chamber 956 is shown on the right side, but those skilled in the art will understand that this represents only one possible configuration.

[0080]

[0111] The size and shape of the loading chamber 954 and the unloading chamber 956 can vary, for example, according to the substrates processed within the cluster tool 900. In the illustrated embodiment, the loading chamber 954 and the unloading chamber 956 are sized to hold a wafer cassette containing a plurality of wafers positioned within the cassette.

[0081]

[0112] Robot 952 is within factory interface 950 and can move between loading chamber 954 and unloading chamber 956. Robot 952 can transfer wafers from a cassette in loading chamber 954 through factory interface 950 to load lock chamber 960. Also, robot 952 can transfer wafers from load lock chamber 962 through factory interface 950 to a cassette in unloading chamber 956. As will be understood by those skilled in the art, factory interface 950 can have multiple robots 952. For example, factory interface 950 can have a first robot that transfers wafers between loading chamber 954 and load lock chamber 960 and a second robot that transfers wafers between load lock chamber 962 and unloading chamber 956.

[0082]

[0113] The illustrated cluster tool 900 has a first section 920 and a second section 930. The first section 920 is connected to factory interface 950 through load lock chambers 960, 962. The first section 920 includes a first transfer chamber 921 in which at least one robot 925 is positioned internally. Robot 925 is also referred to as a robotic wafer transfer mechanism. The first transfer chamber 921 is centrally located with respect to load lock chambers 960, 962, processing chambers 902, 904, 916, 918, and buffer chambers 922, 924. In some embodiments, robot 925 is a multi-arm robot that can move multiple wafers independently at a time. In some embodiments, the first transfer chamber 921 includes multiple robotic wafer transfer mechanisms. The robot 925 within the first transfer chamber 921 is configured to move wafers between the chambers around the first transfer chamber 921. Individual wafers are carried on a wafer transfer blade located at the distal end of the first robotic mechanism.

[0083]

[0114] After processing the wafer within the first section 920, the wafer can be passed through the transfer chamber to the second section 930. For example, the chambers 922, 924 can be one-way or two-way transfer chambers. The transfer chambers 922, 924 can be used, for example, to cryogenically cool the wafer prior to processing in the second section 930, or to enable cooling or post-processing of the wafer prior to returning to the first section 920.

[0084]

[0115] The system controller 990 is in communication with the first robot 925, the second robot 935, the first plurality of processing chambers 902, 904, 916, 918, and the second plurality of processing chambers 906, 908, 910, 912, 914. The system controller 990 can be any suitable component capable of controlling the processing chambers and robots. For example, the system controller 990 can be a computer including a central processing unit (CPU) 992, a memory 994, an input / output (I / O) 996, and a support circuit 998. The controller 990 can control the processing tool 900 directly or via a computer (or controller) associated with a particular processing chamber and / or support system component.

[0085]

[0116] In one or more embodiments, the controller 990 can be one of any form of general-purpose computer processor that can be used in an industrial environment to control various chambers and sub-processors. The memory 994 of the controller 990 or the computer-readable medium can be one or more of readily available memories such as non-transitory memory (e.g., random access memory (RAM)), read-only memory (ROM), floppy disks, hard disks, optical storage media (e.g., compact disks or digital video disks), flash drives, or any other form of digital storage, local or remote, etc. The memory 994 can hold an instruction set operable by a processor (CPU 992) to control the parameters and components of the processing tool 900.

[0086]

[0117] The support circuit 998 is connected to the CPU 992 to support the processor in a conventional manner. These circuits include a cache, a power supply device, a clock circuit, an input / output circuit, and subsystems, etc. One or more processes, when executed or launched by the processor, may be stored in the memory 994 as software routines that cause the processor to control the operation of the processing tool 900 or individual processing units in the manner described herein. The software routines may be stored and / or executed by a second CPU (not shown) located remotely from the hardware controlled by the CPU 992.

[0087]

[0118] Some or all of the processes and methods of the present disclosure may be executed in hardware. Thus, the process may be implemented in software and executed using a computer system, for example, in hardware as an application-specific integrated circuit or other type of hardware implementation, or as a combination of software and hardware. When executed by a processor, the software routines convert a general-purpose computer into a special-purpose computer (controller) that controls the operation of the chamber so that the process is carried out.

[0088]

[0119] In some embodiments, the controller 990 has one or more configurations for executing individual processes or sub-processes to implement the method. The controller 990 can be connected to an intermediate component that implements the function of the method and configured to cause this intermediate component to perform steps. For example, the controller 990 can be connected to a physical vapor deposition chamber and configured to control this chamber.

[0089]

[0120] The process can generally be stored in the memory 994 of the system controller 990 as a software routine that, when executed by a processor, causes the process of the present disclosure to be implemented in the processing chamber. The software routine may be stored and / or executed by a second processor (not shown) that is remotely located from the hardware controlled by the processor. Some or all of the methods of the present disclosure may be implemented in hardware. Thus, the process can be implemented in software, using a computer system, and executed in hardware, for example, as an application specific integrated circuit or other type of hardware implementation, or as a combination of software and hardware. When executed by a processor, the software routine converts a general purpose computer into a specific purpose computer (controller) that controls the operation of the chamber so that the process is implemented.

[0090]

[0121] In some embodiments, the system controller 990 is configured to control a physical vapor deposition chamber to deposit an etch stop layer on a wafer at a temperature in the range of about 20°C to about 400°C and to control an RF power source to have a power in the range of about 1 kW to about 10 kW.

[0091]

[0122] In some embodiments, the system controller 990 is configured to control a physical vapor deposition chamber to deposit a metal layer on the etch stop layer on a wafer at a temperature in the range of about 200°C to about 450°C and to control a DC power source to have a power in the range of about 500 W to about 10 kW at a pressure in the range of about 5 mTorr to about 100 mTorr.

[0092]

[0123] In one or more embodiments, the processing tool comprises a central transfer station having a robot configured to move a wafer; a plurality of process stations each connected to the central transfer station and providing a processing area separated from the processing areas of adjacent process stations, the plurality of process stations including a first physical vapor deposition chamber and a second physical vapor deposition chamber; and a controller connected to the central transfer station and the plurality of process stations, the controller being configured to activate the robot, move the wafer between the process stations, and control the processes performed at each of the process stations.

[0093]

[0124] Hereinafter, the present disclosure will be described with reference to the following examples. Before describing some exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of the configurations or processing steps shown in the following description. The present disclosure is capable of other embodiments and can be implemented or executed in various ways.

Example

[0094]

[0126] Example 1

[0127] A layer of titanium nitride (TiN) having a thickness of about 1.5 nm was formed on a substrate by physical vapor deposition. The TiN layer was formed in a PVD chamber at a temperature of 260°C.

[0095]

[0128] A layer of ruthenium (Ru) having a thickness of 10 to 100 nm was formed on the titanium nitride (TiN) layer by physical vapor deposition. The Ru layer was formed in a PVD chamber at a temperature in the range of about 250°C to about 450°C.

[0096]

[0129] Two physical vapor deposition processing chambers were integrated and the deposition process was carried out under vacuum without an air break.

[0097]

[0130] Next, a substrate containing Ru on the TiN etching stop layer was pressurized to <100 mTorr in a direct plasma environment of source and bias, and etched by Applied Materials' SYM3 in a combined process of halogen (Cl, Br), oxygen, Ar, He, and N2.

[0098] [00131 Example 2 - Comparative Example

[0132] A layer of titanium nitride (TiN) having a thickness of about 1.5 nm was formed on the substrate by atomic layer deposition. The TiN layer was formed in an atomic layer deposition chamber at a temperature of 340 °C.

[0099]

[0133] A layer of ruthenium (Ru) having a thickness of 10 - 100 nm was formed on the titanium nitride (TiN) layer by chemical vapor deposition (CVD). The Ru layer was formed in a chemical vapor deposition chamber at a temperature of about 150 °C to about 250 °C.

[0100]

[0134] The atomic layer deposition processing chamber and the chemical vapor deposition chamber were integrated into a processing tool, and the deposition process was carried out under vacuum without an air break.

[0101]

[0135] Next, a substrate containing Ru on the TiN etching stop layer was pressurized to <100 mTorr in a direct plasma environment of source and bias, and etched by Applied Materials' SYM3 in a process of a combination of halogen (Cl, Br), oxygen, Ar, He, and N2. There was no room for the TiN etching stop layer to open. The lines were merged due to TiN impurities and TiN oxidation (TiOx).

[0102] [00136 Example 3 - Comparative Example

[0137] A layer of titanium nitride (TiN) having a thickness of about 1.5 nm was formed on the substrate by physical vapor deposition. The TiN layer was formed in a physical vapor deposition chamber at a temperature from room temperature to 300 °C.

[0103]

[0138] A ruthenium (Ru) layer having a thickness of 10 to 100 nm was formed on a titanium nitride (TiN) layer by physical vapor deposition. The Ru layer was formed in a physical vapor deposition chamber at a temperature of 250 to 450 °C.

[0104]

[0139] The two physical vapor deposition processing chambers were not integrated into a single processing tool, and there was an air break between the deposition of TiN and the deposition of the Ru layer.

[0105]

[0140] Next, the substrate containing Ru on the TiN etching stop layer was pressurized to <100 mTorr in a direct plasma environment of source and bias, and etched by Applied Materials' SYM3 in a process of a combination of halogen (Cl, Br), oxygen, Ar, He, N2.

[0106]

[0141] Results: TIFF0007702414000001.tif78170

[0107]

[0095] The results show that the device formed in Example 1 has , Example superior resistance compared to the devices of 2 and 3. The device (stack) of Example 1 has a line resistance 15 to 50% greater and a via resistance reduction 20 to 30% greater. In addition, the TiN etching stop layer of Example 1 can be over-etched normally without failure of the etching stop layer, while the Side, Example 2 etching stop layers of 1 and 3 cannot be over-etched.

[0108] In the context of describing the materials and methods set forth in this specification (particularly in the context of the claims), the use of the terms "a," "an," "the," and similar indicatives should be construed to include both the singular and the plural unless otherwise indicated herein or clearly contradicted by the context. The recitation of numerical ranges herein is merely intended to serve as a shorthand way of referring individually to each separate value falling within the range, and each separate value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or clearly contradicted by the context. The use of any and all examples, or exemplary language (e.g., "such as," "etc.") provided herein is merely intended to better illustrate the materials and methods and is not limiting of the scope unless otherwise claimed. Any language in the specification should not be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods.

[0109] Throughout this specification, references to "one embodiment," "some embodiments," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one or more embodiments," "in some embodiments," "in an embodiment," or "in embodiments" in various places throughout this specification are not necessarily referring to the same embodiment of the present disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0110]

[0098] Although the disclosure of this specification has been described with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. Those skilled in the art will appreciate that various modifications and variations can be made to the methods and apparatuses of the present disclosure without departing from the essence and scope of the present disclosure. Therefore, the present disclosure is intended to cover modifications and variations that are within the scope of the claims and their equivalents.

Claims

1. A method of forming an interconnection, comprising: depositing an etch stop layer on a substrate, wherein the deposition includes physical vapor deposition at a temperature in the range of about 200°C to about 300°C; in-situ depositing a metal layer on the etch stop layer at a temperature in the range of about 200°C to about 450°C, wherein the in-situ deposition includes flowing a plasma treatment gas into a processing chamber, exciting the plasma treatment gas into plasma, and depositing the metal layer on the etch stop layer on the substrate; and the substrate is continuously under vacuum and not exposed to ambient air.

2. The method according to claim 1, wherein the etch stop layer has a thickness in the range of about 0.5 nm to 5 nm.

3. The method according to claim 1, wherein an RF power source provides power in the range of about 1 kW to about 10 kW for depositing the etch stop layer.

4. The method according to claim 3, wherein the RF power source provides power in the range of about 2 kW to about 3 kW for depositing the etch stop layer.

5. The method according to claim 1, wherein the etch stop layer includes one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), tungsten (W), or ruthenium (Ru).

6. The method according to claim 5, wherein the etch stop layer includes titanium nitride (TiN).

7. The method according to claim 1, wherein the metal layer includes ruthenium (Ru) and has a thickness in the range of 10 nm to 100 nm.

8. The method according to claim 1, wherein a power source negatively biases a metal target from about 500 W to about 10 kW to excite the plasma treatment gas into plasma.

9. The method according to claim 8, wherein the plasma treatment gas includes one or more of neon (Ne), argon (Ar), krypton (Kr), or xenon (Xe).

10. The method according to claim 9, wherein the plasma treatment gas includes krypton (Kr).

11. The method according to claim 1, wherein the metal layer includes one or more of ruthenium (Ru), molybdenum (Mo), tungsten (W), copper (Cu), cobalt (Co), iridium (Ir), metal silicide, and metal alloy.

12. The method according to claim 1, further comprising depositing a metal seed on the etching stop layer before depositing the metal layer, wherein depositing the metal seed comprises flowing a plasma processing gas into the processing chamber, exciting the plasma processing gas into plasma, and depositing the metal seed on the etching stop layer.

13. The method according to claim 12, wherein the metal seed comprises one or more of ruthenium (Ru), molybdenum (Mo), tungsten (W), copper (Cu), cobalt (Co), iridium (Ir), metal silicide, and metal alloy.

14. A processing tool, the processing tool comprising: A central transfer station including a robot configured to move a wafer; A plurality of process stations each connected to the central transfer station and providing a processing area separated from the processing areas of adjacent process stations, the plurality of process stations including a first physical vapor deposition chamber and a second physical vapor deposition chamber; A controller connected to the central transfer station and the plurality of process stations, the controller being configured to operate the robot to move the wafer between process stations and control processes occurring at each of the process stations; Including, The controller controls a first process, the first process including depositing an etching stop layer on a substrate by physical vapor deposition in the first physical vapor deposition chamber at a temperature in the range of about 200°C to about 300°C; The controller controls a second process, the second process including in-situ depositing a metal layer on the etching stop layer at a temperature in the range of about 200°C to about 450°C, the in-situ deposition being performed by flowing a plasma processing gas into the second physical vapor deposition chamber, exciting the plasma processing gas into plasma, and depositing the metal layer on the etching stop layer on the substrate; Processing tool.

15. The processing tool according to claim 14, wherein the wafer is continuously under vacuum and not exposed to ambient air.

16. The processing tool according to claim 15, wherein the controller is configured to operate the robot to move the wafer between the first physical vapor deposition chamber and the second physical vapor deposition chamber without breaking vacuum.

17. The processing tool according to claim 14, wherein the first physical vapor deposition chamber includes a first target including one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), tungsten (W), or ruthenium (Ru), and the second physical vapor deposition chamber includes a second target including one or more of ruthenium (Ru), molybdenum (Mo), tungsten (W), copper (Cu), cobalt (Co), iridium (Ir), metal silicide, and metal alloy.

18. When executed by a controller of a processing chamber, the processing chamber is caused to deposit an etch stop layer on a substrate at a temperature in a range from about 200°C to about 300°C, in-situ deposit a metal layer on the etch stop layer at a temperature in a range from about 200°C to about 450°C, and continuously maintain the substrate under vacuum A non-transitory computer-readable medium including instructions to perform.

19. The non-transitory computer-readable medium according to claim 18, wherein the in-situ deposition includes flowing a plasma processing gas into the processing chamber, exciting the plasma processing gas into plasma, and depositing the metal layer on the etch stop layer on the substrate.

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