Semiconductor device and method of manufacturing the same

Abstract

To make it possible to suppress an increase in the warpage of a semiconductor chip while reducing on-resistance.SOLUTION: In an area in which a pad placement area Re and an active area Rb overlap, pads 12a to 12e are arranged through a separation dielectric film on top of a source electrode material 113, which is a surface electrode. Thereby, a two-layer wiring electrode structure in which two layers of wiring electrode material are stacked is formed is provided. Furthermore, a one-layer wiring electrode structure in which the source electrode 113, which is the surface electrode, is configured of one layer of wiring electrode material in the area of the active area Rb that does not overlap the pad placement area Re is provided.SELECTED DRAWING: Figure 2B

Description

Technical Field

[0001] The present invention relates to a semiconductor device having pads provided on a chip surface and a method for manufacturing the same.

Background Art

[0002] Conventionally, there has been a semiconductor device in which a semiconductor element such as a switching element is formed in a semiconductor chip (see, for example, Patent Document 1). In such a semiconductor device, an active region that can be operated as a semiconductor element is arranged in a wide range including the center of the semiconductor chip. Then, a region different from the active region in the semiconductor chip, specifically, a region along one side of the semiconductor chip adjacent to the active region is used as a pad arrangement region, and pads are arranged in this pad arrangement region.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in the above semiconductor device, since the active region and the pad arrangement region are separate regions, the pad arrangement region becomes a region where the semiconductor element cannot be operated. For this reason, the ratio of the active region to the total area of the semiconductor chip decreases by the amount of the pad arrangement region, and the on-resistance of the semiconductor element cannot be made very small.

[0005] Therefore, the present inventors have found a structure in which the active region is expanded and the region below the pad in the pad arrangement region is also an active region. With such a configuration, the ratio of the active region to the total area of the semiconductor chip can be increased, and the on-resistance of the semiconductor element can be reduced.

[0006] When the semiconductor device has such a structure, since the semiconductor element is formed below the pad arrangement region, the wiring electrode material constituting the electrode connected to the semiconductor element has the wiring electrode material constituting the pad further stacked thereon. That is, the second-layer upper wiring electrode is stacked on the first-layer lower wiring electrode connected to the semiconductor element. And in the pad arrangement region, since it is necessary to insulate the lower wiring electrode and the upper wiring electrode, an insulating film is arranged between them, and in the region of the active region that does not overlap with the pad arrangement region, it is conceivable that the lower wiring electrode and the upper wiring electrode are connected.

[0007] However, as a result of the inventors' intensive studies, it has been found that when the wiring electrode materials are stacked, the thickness becomes too large, and the warpage generated in the semiconductor chip at high temperatures increases.

[0008] In view of the above points, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can suppress an increase in the warpage of a semiconductor chip while reducing the on-resistance.

Means for Solving the Problems

[0009] To achieve the above object, the invention according to claim 1 is a semiconductor device constituted by a semiconductor chip (10), in which a semiconductor element is formed, and on one surface side of the semiconductor chip, an active region (Ra) where a surface electrode (113) constituted by a wiring electrode material and connected to the semiconductor element is arranged, and a pad arrangement region (Re) provided overlapping the active region in the normal direction to one surface of the semiconductor chip and where pads (12a to 12e) constituted by a wiring electrode material are arranged. And in the region where the pad arrangement region and the active region overlap, the pad is arranged on the surface electrode via a separation insulating film (116), so that a two-layer wiring electrode structure with two layers of wiring electrode materials stacked is formed, and in the region of the active region that does not overlap with the pad arrangement region, The surface electrode is exposed from the separation insulating film, and this exposed portion serves as the pad (11) of the surface electrode, and the surface electrode has a single-layer wiring electrode structure constituted by a single layer of wiring electrode material.

[0010] Thus, on one side of the semiconductor chip, the surface electrode with the largest area among the portions composed of the wiring electrode material has a single-layer wiring structure. That is, at the position where the pads are arranged, even if a two-layer wiring electrode structure is formed with the pads laminated on the surface electrode, at the position where only the surface electrode is arranged, it is made into a single-layer wiring electrode structure without a laminated structure. For this reason, it becomes possible to suppress an increase in the warpage of the semiconductor chip at high temperatures. Therefore, by forming a semiconductor element below the pad arrangement region, a wide range of the semiconductor chip can be made into an active region to reduce the on-resistance, and it becomes possible to suppress an increase in the warpage of the semiconductor chip.

[0011] The invention according to claim 10 is a method for manufacturing a semiconductor device including a semiconductor chip (10) in which a semiconductor element is formed on a semiconductor substrate. After forming a semiconductor element on the semiconductor substrate, an interlayer insulating film (112) is formed on one side of the semiconductor substrate and contact holes (112a to 112c) are formed in the interlayer insulating film. A lower wiring electrode composed of a first-layer wiring electrode material is formed and patterned on the interlayer insulating film including the inside of the contact holes, thereby forming a surface electrode (113) connected to the semiconductor element in the active region (Rb) where the semiconductor element is formed. A separation insulating film (116) is formed on the surface electrode. An upper wiring electrode composed of a second-layer wiring electrode material is formed and patterned on the separation insulating film, thereby forming pads (12a to 12e) in a pad arrangement region (Re) overlapping the active region. By forming the pads, in the region of the active region that does not overlap the pad arrangement region, the upper wiring electrode formed on the surface electrode is removed the surface electrode is exposed from the separation insulating film, and the pad (11) of the surface electrode is formed by this exposed portion, and to make the surface electrode into a single-layer wiring electrode structure composed of the lower wiring electrode, and in the region of the active region that overlaps the pad arrangement region, the pads are arranged on the surface electrode to make a two-layer wiring electrode structure of the lower wiring electrode and the upper wiring electrode.

[0012] Thus, when forming the pads, in the region of the active area that does not overlap with the pad arrangement area, the upper layer wiring electrode formed on the surface electrode is removed, so that the surface electrode has a single-layer wiring electrode structure constituted by the lower layer wiring electrode. And in the region of the active area that overlaps with the pad arrangement area, pads are arranged on the surface electrode, so that a two-layer wiring electrode structure of the lower layer wiring electrode and the upper layer wiring electrode is formed. Therefore, by forming a semiconductor element below the pad arrangement area, a semiconductor device capable of reducing the on-resistance by making a wide range of the semiconductor chip an active area and suppressing an increase in the warpage of the semiconductor chip can be manufactured.

[0013] Note that the reference numerals in parentheses attached to each component etc. show an example of the correspondence relationship between the component etc. and the specific components etc. described in the embodiments described later.

Brief Description of Drawings

[0014]

Figure 1

Figure 2A

Figure 2B

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Embodiments for Carrying Out the Invention

[0015] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each of the following embodiments, parts that are identical or equivalent to each other will be described with the same reference numerals.

[0016] (First Embodiment) The first embodiment will be described. First, with reference to FIG. 1, a case where the semiconductor device according to this embodiment is applied to a power module will be described as an example.

[0017] The power module shown in FIG. 1 incorporates a semiconductor chip 10 corresponding to the semiconductor device of this embodiment and is used, for example, as a switching device for motor drive. Specifically, the power module includes a semiconductor chip 10, a heat sink 20, a heat sink 30, etc. Further, the semiconductor chip 10, the heat sink 20, and the heat sink 30 are joined by a joining material 50 including first to third joining materials 50a to 50c. And these are configured to be sealed with a molding resin 60.

[0018] Specifically, with one side of the semiconductor chip 10 located below the paper surface defined as the bottom surface and the opposite side located above the paper surface defined as the top surface, the bottom surface of the semiconductor chip 10 and the top surface of the heat sink 20 are joined by a first bonding material 50a. The heat sink 20 is composed of a laminate in which a metal layer 21, an insulating layer 22, and a metal layer 23 are laminated in sequence, and the metal layer 23 side is joined to the bottom surface of the semiconductor chip 10 via the first bonding material 50a. Also, the top surface of the semiconductor chip 10 and the heat sink 30 are joined by a second bonding material 50b or a third bonding material 50c. The heat sink 30 is composed of a laminate in which a metal layer 31, an insulating layer 32, and a metal layer 33 are laminated in sequence, and the metal layer 33 is divided into a plurality of connection portions 33a, 33b. Then, the divided plurality of connection portions 33a, 33b sides are joined to the top surface of the semiconductor chip 10 via the second bonding material 50b or the third bonding material 50c.

[0019] As will be described later, the connection portion 33a is connected to a source electrode 113 corresponding to the surface electrode of the active region Rb of the semiconductor chip 10 shown in FIG. 2A, and the connection portion 33b is connected to each of the pads 12a to 12e in the pad arrangement region Re of the semiconductor chip 10. In FIG. 1, only one connection portion 33b is shown, but there are as many as the number of pads 12a to 12e. Also, the connection portion 33a is provided with a lead-out portion (not shown), and by pulling out the lead-out portion from the molding resin 60, it can be electrically connected to the outside. Also, each connection portion 33b is provided with a lead-out portion (not shown), and by pulling out the lead-out portion from the molding resin 60, it can be electrically connected to the outside. The metal layer 23 is also provided with a lead-out portion (not shown), and by pulling out the lead-out portion from the molding resin 60, it can be electrically connected to the outside.

[0020] In the case of this embodiment, the bonding material 50 including the first to third bonding materials 50a to 50c is composed of a bonding metal such as lead-free solder, which is a conductive material, or a conductive adhesive. And, the semiconductor chip 10, the heat sink 20, and the heat sink 30 are physically and electrically connected to each other by the bonding material 50.

[0021] With such a configuration, on the upper surface of the semiconductor chip 10, electrical connection with the outside is made and heat dissipation is performed via the second bonding material 50b, the third bonding material 50c, and the heat sink 30. Also, on the lower surface of the semiconductor chip 10, electrical connection with the outside is made and heat dissipation is performed via the first bonding material 50a and the heat sink 20.

[0022] The semiconductor chip 10 is a semiconductor device in which semiconductor elements are formed on a semiconductor substrate such as silicon carbide (SiC), and is, for example, in the shape of a rectangular thin plate. The semiconductor chip 10 may be made of a material other than SiC. However, in the case of SiC, since a high breakdown voltage semiconductor element is applied, the semiconductor chip 10 may become hotter than in the case of being made of other materials, and the influence of warpage may increase. For this reason, when the semiconductor chip 10 is made of SiC, it is preferable to apply the present disclosure.

[0023] Examples of the semiconductor elements formed on the semiconductor chip 10 include a vertical MOSFET, a vertical IGBT (insulated gate bipolar transistor), and the like. In the case of the present embodiment, although the detailed structure will be described later, a vertical MOSFET is formed on the semiconductor chip 10.

[0024] A connection portion 33a is joined to a part of the upper surface of the semiconductor chip 10, and a plurality of connection portions 33b are connected to the outside of the semiconductor chip 10 rather than the portion connected to the connection portion 33a. The surface electrode provided in the active region Rb of the semiconductor chip 10, that is, the source electrode 113 in the vertical MOSFET, is connected to the connection portion 33a. Also, each of the pads 12a to 12e provided in the pad arrangement region Re of the semiconductor chip 10 is connected to the connection portion 33b. In FIG. 1, only one connection portion 33b is shown, but there are as many as the number of pads 12a to 12e. On the other hand, a back surface electrode, that is, a drain electrode 114 in the case of a vertical MOSFET, is formed on the back surface of the semiconductor chip 10, and the entire surface of the back surface electrode is connected to the metal layer 23 in the heat sink 20.

[0025] The heat sink 20 insulates between the metal layer 21 and the metal layer 23 disposed on both sides of the insulating layer 22 by the insulating layer 22, and has high heat dissipation performance by forming the metal layer 21 and the metal layer 23 of a metal with high heat transfer rate such as copper. Since the metal layer 21 and the metal layer 23 are insulated, while exposing the metal layer 21 side from the mold resin 60 to form a heat dissipation surface where heat dissipation is likely to occur, the metal layer 23 is insulated from the outside.

[0026] The heat sink 30 insulates between the metal layer 31 and the metal layer 33 disposed on both sides of the insulating layer 32 by the insulating layer 32, and has high heat dissipation performance by forming the metal layer 31 and the metal layer 33 of a metal with high heat transfer rate such as copper. Since the metal layer 31 and the metal layer 33 are insulated, while exposing the metal layer 31 side from the mold resin 60 to form a heat dissipation surface where heat dissipation is likely to occur, the metal layer 33 is insulated from the outside. Further, the metal layer 33 is divided into a plurality to form connection portions 33a and 33b. The connection portion 33b is a portion that is conventionally constituted by a bonding wire, but here it is also constituted by a part of the metal layer 33 included in the heat sink 30 so as to obtain high heat dissipation performance.

[0027] The mold resin 60 seals the semiconductor chip 10, the heat sink 20, the heat sink 30, and the like. From the mold resin 60, one surface of the heat sink 20 and the heat sink 30, and one end of the lead-out portion of the metal layer 23 and the metal layer 33 (not shown) are exposed. And at one end of each exposed lead-out portion, it is electrically connectable to the outside.

[0028] Next, the detailed structure of the semiconductor chip 10 in the semiconductor device configured as described above will be described.

[0029] As shown in FIGS. 2A and 2B, the semiconductor chip 10 is configured in a plate shape with a rectangular upper surface shape. The semiconductor chip 10 is provided with an internal region Ra, an active region Rb, a connecting region Rc, an outer peripheral region Rd, and a pad arrangement region Re.

[0030] The inner region Ra is a region including the central part of the semiconductor chip 10, and is a part where the source electrode 113 corresponding to the surface electrode described later is exposed. This part is the source pad 11.

[0031] The active region Rb is a region in the semiconductor chip 10 where the semiconductor element operates. In the present embodiment, a vertical MOSFET is formed as the semiconductor element in the active region Rb. The active region Rb is formed while surrounding the inner region Ra and reaching a position separated a predetermined distance inward from the outer edge of the semiconductor chip 10, and is a rectangular region in the present embodiment.

[0032] The connecting region Rc is a region provided between the active region Rb and the outer peripheral region Rd, and is, for example, in the shape of a rectangular frame, and includes a gate wiring layer 120 and the like that constitute a gate liner described later.

[0033] The outer peripheral region Rd is arranged over the entire circumference of the outer edge of the semiconductor chip 10 so as to surround the active region Rb and the connecting region Rc, and is a region provided with an outer peripheral breakdown voltage structure and the like, and is in the shape of a rectangular frame in the present embodiment.

[0034] The pad arrangement region Re is a region where various pads 12a to 12e are arranged. The pad arrangement region Re is a part of the active region Rb, here, a region along one side of the rectangular active region Rb, the lower side in the drawing in FIG. 2A. And the pad arrangement region Re is formed so as to overlap the active region Rb in a top view of the semiconductor chip 10 seen from the normal direction.

[0035] In the case of the present embodiment, the portion shown by the two-dot chain line in the figure is the connecting region Rc, the inside of the connecting region Rc is the active region Rb, and the outside is the outer peripheral region Rd. Also, the portion surrounded by the one-dot chain line in the figure is the pad arrangement region Re.

[0036] Furthermore, a temperature-sensitive element region 13 in which a temperature-sensitive element is formed is provided within a pad arrangement region Re that overlaps with the active region Rb of the semiconductor chip 10, and it is possible to grasp the temperature rise of the semiconductor element based on the temperature detection by the temperature-sensitive element.

[0037] Note that the pad arrangement region Re is provided with a plurality of pads 12a to 12e. In the case of this embodiment, the pad arrangement region Re is provided with a cathode pad 12a, an anode pad 12b, a gate pad 12c, a first sense pad 12d, and a second sense pad 12e from the left side of the paper surface. These are electrically connected to each part of the vertical MOSFET provided in the active region Rb and each part of the temperature-sensitive element provided in the temperature-sensitive element region 13. By connecting these pads 12a to 12e to the connection portion 33b, electrical connection with the outside can be performed through the lead-out portion provided in the connection portion 33b.

[0038] Also, the semiconductor chip 10 has a cross-sectional configuration shown in FIGS. 3 and 4, and a vertical MOSFET is formed in the active region Rb.

[0039] The semiconductor chip 10 uses an n + -type substrate 101 made of a semiconductor material such as Si or SiC, and an n + -type low-concentration layer 102 having a lower impurity concentration than the n + -type substrate 101 is epitaxially grown on the main surface of the n - -type substrate 101.

[0040] 〔Configuration of Active Region Rb〕 As shown in FIGS. 3 and 4, in the active region Rb, a JFET portion 102a arranged in a stripe shape with one direction as the longitudinal direction is formed in the n - -type low-concentration layer 102 at a position away from the n + -type substrate 101. The n - -type low-concentration layer 102 including the JFET portion 102a may have the same impurity concentration, but here the JFET portion 102a is n -By setting the impurity concentration higher than that of other parts of the low-concentration layer 102, a lower on-resistance can be achieved.

[0041] A p-type first deep layer 103 is formed between the JFET parts 102a, and the first deep layer 103 is also arranged in a stripe shape with one direction as the longitudinal direction. These JFET parts 102a and the first deep layer 103 are configured with the same thickness.

[0042] Also, on the JFET parts 102a and the first deep layer 103, a current diffusion layer 104 formed wide with a direction intersecting the longitudinal direction of these as the longitudinal direction and a second deep layer 105 formed narrower than the current diffusion layer 104 are alternately and repeatedly arranged. And the second deep layer 105 is connected to the first deep layer 103. Further, on the current diffusion layer 104 and the second deep layer 105, a p-type base region 106 is formed, and on the p-type base region 106, an n + -type source region 107 and a p + -type contact region 108 are formed. The n + -type source region 107 is formed on the part of the p-type base region 106 corresponding to the current diffusion layer 104, and the p + -type contact region 108 is formed on the part of the p-type base region 106 corresponding to the second deep layer 105.

[0043] A gate trench 109 is formed that penetrates the p-type base region 106 and the n + -type source region 107 and reaches the current diffusion layer 104. The above-mentioned p-type base region 106 and n + -type source region 107 are arranged in contact with the side surface of this gate trench 109. The gate trench 109 is formed in a linear layout with the left-right direction of the paper surface of FIG. 3 as the width direction, one direction normal to the paper surface as the longitudinal direction, and the up-down direction of the paper surface as the depth direction. Also, although only two are shown in FIG. 3, a plurality of gate trenches 109 are arranged at equal intervals in the left-right direction of the paper surface and are respectively arranged to be sandwiched between the second deep layers 105 and are in a stripe shape.

[0044] Also, the portion of the p-type base region 106 located on the side surface of the gate trench 109 serves as a channel region connecting the n + type source region 107 and the current diffusion layer 104 during the operation of the vertical MOSFET. A gate insulating film 110 is formed on the inner wall surface of the gate trench 109 including this channel region. A gate electrode 111 made of doped Poly-Si is formed on the surface of the gate insulating film 110, and these gate insulating film 110 and gate electrode 111 are embedded in the gate trench 109. Thereby, a trench gate structure is configured.

[0045] Note that, as shown in FIG. 4, the trench gate structure extends along the left-right direction of the paper surface of FIG. 2, and as shown in FIG. 3, a plurality of trench gate structures are arranged in the up-down direction of the paper surface of FIG. 2. And although not shown, in the left-right direction of the paper surface of FIG. 2, the trench gate structure is formed so as to protrude beyond the active region Rb. Also, an n + type source region 107 is formed on the side surface of the gate trench 109, but the n + type source region 107 is formed in the active region Rb and is not formed outside thereof. For this reason, the channel region is formed only within the active region Rb.

[0046] n + type source region 107, p + type contact region 108, and an interlayer insulating film 112 are formed on the surface of the trench gate structure. And in the active region Rb, a source electrode 113 corresponding to a surface electrode is formed on the interlayer insulating film 112. The source electrode 113 is formed by patterning a lower layer wiring electrode made of a first layer of wiring electrode material, and the upper layer wiring electrode made of a second layer of wiring electrode material is removed to form a single-layer wiring structure.

[0047] Among the interlayer insulating film 112, the n + type source region 107, p+ A contact hole 112a is formed at a position corresponding to the type contact region 108. As a result, as shown in FIG. 3, the source electrode 113 passes through the contact hole 112a to the n + type source region 107 and the p + type contact region 108 are in electrical contact.

[0048] Also, on the back side of the n + type substrate 101, that is, on the side opposite to the side where the source electrode 113 is formed, a drain electrode 114 corresponding to a back electrode electrically connected to the n + type substrate 101 is formed. With such a structure, a vertical MOSFET having an n-channel type inversion-type trench gate structure is configured, and an active region Rb is configured by arranging a plurality of vertical MOSFETs. Then, as shown in FIG. 3, the surface of the semiconductor chip 10 is covered with a passivation film 115, and a portion corresponding to the source electrode 113 in the passivation film 115 is removed and opened. The portion where the passivation film 115 is opened in the portion corresponding to the source electrode 113 is the internal region Ra, and the exposed portion of the source electrode 113 becomes the source pad 11.

[0049] Also, in the portion of the active region Rb that overlaps with the pad arrangement region Re, as shown in FIG. 4, it has substantially the same configuration as the portion of the active region Rb that does not overlap with the pad arrangement region Re. However, in the portion of the active region Rb that overlaps with the pad arrangement region Re, a separation insulating film 116 is disposed on the surface of the source electrode 113, and pads 12a to 12e are formed on this separation insulating film 116. FIG. 4 shows a cross section of the portion where the gate pad 12c is disposed, but the other pads 12a, 12b, 12d, and 12e are also formed on the source electrode 113 via the separation insulating film 116. The pads 12a to 12e are formed by patterning the upper wiring electrode, which is the second-layer wiring electrode. Therefore, as shown in FIG. 2B, in the portion of the active region Rb that overlaps with the pad arrangement region Re, a two-layer wiring electrode structure in which the source electrode 113 and the pads 12a to 12e are stacked is formed.

[0050] Also, the portions of the passivation film 115 corresponding to the respective pads 12a to 12e provided in the pad arrangement region Re are also removed and opened. Therefore, the connection portion 33b can be connected to each of the pads 12a to 12e.

[0051] Also, in the temperature-sensitive element region 13 disposed overlapping the active region Rb, a temperature-sensitive diode, for example, is formed as the temperature-sensitive element. The temperature-sensitive diode is configured, for example, by ion-implanting p-type impurities and n-type impurities into polysilicon to form a plurality of stages of PN diodes. Then, by connecting the cathode of the temperature-sensitive diode to the cathode pad 12a and the anode to the anode pad 12b, an electrical signal corresponding to the temperature of the semiconductor chip 10 is output.

[0052] Regarding the other pads 12c to 12e provided in the pad arrangement region Re, they are electrically connected to each part of the vertical MOSFET. For the gate pad 12c, it is electrically connected to the gate electrode 111 via a gate wiring layer 120 (described later) that constitutes a gate liner. Thus, a gate voltage is applied to the gate electrode 111 through the gate pad 12c. The gate wiring layer 120 is formed, for example, in a rectangular frame shape surrounding the active region Rb within the connection region Rc, that is, near the outer edge of the semiconductor chip 10, and is structured to be routed to the vicinity of the gate pad 12c. The first sense pad 12d and the second sense pad 12e are connected to the source electrode 113 of the vertical MOSFET. Specifically, most of the vertical MOSFETs formed by a plurality of cells in the active region Rb are main cells that supply current to a load such as a motor through the source-drain, while some are sense cells for measuring the current flowing through the main cells. The first sense pad 12d is connected to the source electrode 113 on the sense cell side, and by outputting the current flowing between the source and drain of the vertical MOSFET on the sense cell side to the outside, the current flowing through the main cells can be measured. The second sense pad 12e is connected to the source electrode 113 on the main cell side, and outputs the source potential to the outside through the second sense pad 12e.

[0053] 〔Configuration of the connection region Rc〕 As shown in FIG. 3, also in the connection region Rc, up to a position near the outer peripheral region Rd, an n - -type low concentration layer 102 has a JFET portion 102a and a first deep layer 103 formed thereon. However, the current diffusion layer 104 is not present thereon, and only the second deep layer 105 is formed. Also, a trench gate structure is not formed, and only a p-type base region 106 and a p + -type contact region 108 are formed on the second deep layer 105.

[0054] Also, the p-type base region 106 and p +On the gate insulating film 110 formed on the type contact region 108, a gate lead portion 111a made of doped Poly-Si drawn from the gate electrode 111 is formed. And an interlayer insulating film 112 is formed so as to cover the gate lead portion 111a, and further, a gate wiring layer 120 is formed on the interlayer insulating film 112. This gate wiring layer 120 constitutes a gate liner and is routed in a rectangular frame shape so as to surround, for example, the active region Rb and is connected to the gate pad 12c. Also, a contact hole 112b is formed at a position corresponding to the gate wiring layer 120 in the interlayer insulating film 112, and the gate wiring layer 120 and the gate lead portion 111a are electrically connected through the contact hole 112b.

[0055] Furthermore, on the outer peripheral region Rd side rather than the gate wiring layer 120, a via pull-out layer 130 is formed on the interlayer insulating film 112. A contact hole 112c is formed at a position corresponding to the via pull-out layer 130 in the interlayer insulating film 112, and the via pull-out layer 130 is electrically connected to the p + type contact region 108 through the contact hole 112c.

[0056] Regarding the gate wiring layer 120 and the via pull-out layer 130 formed in the connection region Rc, as shown in FIGS. 2B and 3, they are configured by patterning the lower wiring electrode which is the first-layer wiring electrode and the upper wiring electrode which is the second-layer wiring electrode. And in the case of this embodiment, the gate wiring layer 120 and the via pull-out layer 130 have a two-layer wiring electrode structure of a lower wiring electrode and an upper wiring electrode.

[0057] In addition, in order to electrically isolate the pads 12a to 12e from the source electrode 113, the above-described separation insulating film 116 is formed between the lower-layer wiring electrode and the upper-layer wiring electrode. For this reason, with respect to the gate wiring layer 120 and the via hole extraction layer 130, the separation insulating film 116 formed between the lower-layer wiring electrode and the upper-layer wiring electrode is removed so that the lower-layer wiring electrode and the upper-layer wiring electrode are electrically connected. In this way, by adopting a two-layer wiring electrode structure for the gate wiring layer 120 and the via hole extraction layer 130, it becomes possible to reduce the wiring resistance.

[0058] In addition, in a cross section different from FIGS. 3 and 4, the gate wiring layer 120 is connected to the gate pad 12c, and the via hole extraction layer 130 is connected to a portion having a ground potential, for example, the second sense pad 12e.

[0059] 〔Configuration of the outer peripheral region Rd〕 In the outer peripheral region Rd, the p-type base region 106 and the second deep layer 105 are removed, and a recess 140 is formed. A plurality of p-type guard rings 150 are arranged so as to surround the active region Rb at the position of the bottom surface of the recess 140. By providing the p-type guard rings 150, equipotential lines can be extended further outside the active region Rb and terminated, thereby alleviating electric field concentration and ensuring the breakdown voltage in the outer peripheral region Rd.

[0060] Then, the entire outer peripheral region Rd is covered with the passivation film 115, and the surface is protected. In this way, a power module provided with the semiconductor chip 10 corresponding to the semiconductor device of the present embodiment is configured.

[0061] This power module operates, for example, by applying a voltage of about 10 V to the drain electrode 114 via the metal layer 23, setting the source electrode 113 to the ground potential via the connection portion 33a, and applying a predetermined voltage to the gate electrode 111 via the connection portion 33b. That is, when a gate voltage is applied to the gate electrode 111, a channel region is formed in a portion of the p-type base region 106 that contacts the trench gate structure. As a result, the vertical MOSFET is turned on, and an operation of flowing a current between the source and the drain is performed.

[0062] And even when a high voltage is applied to the drain electrode 114, etc., since the first deep layer 103 is fixed to the source potential through the second deep layer 105 and the p-type base region 106, the rise of the equipotential line up to the trench gate structure is suppressed. Also, in the outer peripheral region Rd, an outer peripheral breakdown voltage structure such as the p-type guard ring 150 is provided, so that the equipotential line is led to the more outer peripheral side, and the electric field concentration is alleviated. As a result, it is possible to realize a vertical MOSFET with a high breakdown voltage.

[0063] Here, when the vertical MOSFET is operated as described above, the semiconductor chip 10 becomes hot. Therefore, if the thickness of each part constituted by the wiring electrodes in the semiconductor chip 10 is large, the warpage will increase at high temperatures. However, in the present embodiment, the source pad 11, which is a pad configured by opening the passivation film 115 with the largest area, that is, the thickness of the source electrode 113 is made thin. For this reason, it is possible to suppress the increase in warpage at high temperatures.

[0064] Specifically, the above-described source electrode 113, gate wiring layer 120, hole extraction layer 130, and pads 12a to 12e are formed by patterning the lower wiring electrode which is the wiring electrode of the first layer and the upper wiring electrode which is the wiring electrode of the second layer. In the case of this embodiment, the gate wiring layer 120 and the hole extraction layer 130 have a two-layer wiring electrode structure of a lower wiring electrode and an upper wiring electrode, but the source electrode 113 has a one-layer wiring electrode structure in which the upper wiring electrode is removed and the lower wiring electrode remains. Also, the pads 12a to 12e have a one-layer wiring electrode structure formed by the upper wiring electrode.

[0065] In this way, on the surface side of the semiconductor chip 10, the source electrode 113, which has the largest area among the portions formed of the wiring electrode material, has a one-layer wiring structure. That is, even at the positions where the pads 12a to 12e are arranged, a two-layer wiring electrode structure in which the pads 12a to 12e are stacked on the source electrode 113 is adopted, but at the positions where only the source electrode 113 is arranged, a one-layer wiring electrode structure is adopted without a stacked structure. For this reason, it is possible to suppress an increase in the warpage of the semiconductor chip 10 at high temperatures.

[0066] Therefore, by forming a semiconductor element below the pad arrangement region Re, a wide range of the semiconductor chip 10 can be made into the active region Rb to reduce the on-resistance, and it is possible to suppress an increase in the warpage of the semiconductor chip 10. And by suppressing an increase in the warpage of the semiconductor chip 10, it is possible to suppress deterioration of the semiconductor element characteristics due to the warpage, and it is also possible to further reduce the on-resistance. Also, since heat can be dissipated through the connection portion 33b, even if the active region Rb is laid out so as to overlap the pad arrangement region Re, the heat generated in that portion can be dissipated through the connection portion 33b.

[0067] The structure of this embodiment was actually fabricated, and the change in on-resistance was examined for the case of adopting the structure of this embodiment and a comparative example in which the source electrode 113 also has a two-layer wiring electrode structure. The fabricated structure of this embodiment is the structure shown in FIGS. 3 and 4. Also, for the comparative example, the structure shown in FIGS. 5 and 6 is adopted. That is, as shown in FIGS. 5 and 6, not only the pads 12a to 12e, but also the source electrode 113, the gate wiring layer 120, and the via hole extraction layer 130 all have a two-layer wiring electrode structure.

[0068] FIG. 7 shows the evaluation results of the on-resistance. Specifically, while applying 10 V to the drain electrode 114, the source electrode 113 was set to the ground potential, and the gate voltage was adjusted so that a current with a predetermined current value flowed between the source and the drain, and the on-resistance in each case was measured. Here, for each case, vertical MOSFETs with four different characteristics were fabricated. As a result, regardless of the characteristics of the vertical MOSFET, the on-resistance was reduced by about 5% when the structure of this embodiment was adopted compared to the case where the source electrode 113 also has a two-layer wiring electrode structure. From this evaluation result, it can be seen that further reduction of the on-resistance can be achieved by adopting the structure of this embodiment. This is presumably due to the following reasons. That is, in the case of a two-layer wiring electrode structure, an oxide layer is formed on the surface of the lower-layer wiring electrode, and the contact resistance between the lower-layer wiring electrode and the upper-layer wiring electrode increases, resulting in an increase in the on-resistance. On the other hand, in the case of the structure of this embodiment, even if an oxide layer is formed on the source electrode 113 when the isolation insulating film 116 is formed as described later, the oxide layer can be removed when the upper-layer wiring electrode formed thereon is removed. Therefore, it is considered that the contact resistance of the source electrode 113 is reduced and the on-resistance is decreased.

[0069] Next, a method for manufacturing a semiconductor chip 10 configured as described above, that is, a semiconductor device, will be described. However, for the method of manufacturing a semiconductor device, known techniques may be used for forming semiconductor elements, forming an interlayer insulating film 112, forming contact holes 112a to 112c, etc., and any technique may be used. Therefore, only the post-process of the forming process of the contact holes 112a to 112c will be described.

[0070] First, as shown in the flowchart of FIG. 8, after forming a semiconductor element, an interlayer insulating film 112 is formed and contact holes 112a to 112c are formed in the interlayer insulating film 112. Then, by performing each of the subsequent steps, a source electrode 113, a gate wiring layer 120, a gate lead-out portion 111a, and pads 12a to 12e are formed.

[0071] Specifically, a lower-layer wiring electrode is formed on the interlayer insulating film 112 including inside the contact holes 112a to 112e. For example, as the lower-layer wiring electrode, a wiring electrode material mainly made of AlSi or the like is formed by sputtering. At this time, instead of directly forming the wiring electrode material on the semiconductor layer, in order to form a barrier metal layer as an underlying layer, it is preferable to form, for example, a laminated structure of Ti / TiN by sputtering and then form the lower-layer wiring electrode. Next, after applying a resist on the lower-layer wiring electrode, exposure and development processes are performed to form a resist mask. Then, the lower-layer wiring electrode is wet-etched using the resist mask, and if an underlying layer is formed, the underlying layer is dry-etched. After that, after peeling and cleaning the resist mask, sintering is performed. As a result, the patterning of the lower-layer wiring electrode is completed, the source electrode 113 is formed, and a portion constituted by the lower-layer wiring electrode among the gate wiring layer 120 and the hole extraction layer 130 is formed.

[0072] Subsequently, a separation insulating film 116 is formed. For example, a silicon oxide film or a silicon nitride film such as USG (Undoped Silicate Glass), which constitutes the separation insulating film 116, is deposited. By using a silicon oxide film or a silicon nitride film, the lower layer wiring electrode and the upper layer wiring electrode can be accurately insulated. Also, when using a silicon nitride film, an effect of suppressing the oxidation of the portion of the lower layer wiring electrode covered with the silicon nitride film can be obtained. Further, after applying a resist on the separation insulating film 116, exposure and development processes are performed to form a resist mask. Then, the separation insulating film 116 is patterned by performing dry etching using the resist mask. At this time, the separation insulating film 116 is left in the formation planned regions of the pads 12a to 12e, and the separation insulating film 116 is not left on the surface of the source electrode 113 and the surface of the portion constituted by the lower layer wiring electrode among the gate wiring layer 120 and the via hole extraction layer 130. Thereafter, by performing the peeling and cleaning processes of the resist mask, the separation insulating film 116 with the desired pattern is formed.

[0073] Furthermore, an upper layer wiring electrode is formed so as to cover the portion constituted by the lower layer wiring electrode such as the source electrode 113 including the upper part of the separation insulating film 116. For example, as the upper layer wiring electrode, a wiring electrode material such as AlSi is formed by sputtering. Also at this time, instead of directly forming the wiring electrode material, it is preferable to form a barrier metal layer as the underlayer, for example, by sputtering a stacked structure such as Ti / TiN and then forming the upper layer wiring electrode. Next, after applying a resist on the upper layer wiring electrode, exposure and development processes are performed to form a resist mask. Then, the upper layer wiring electrode is wet-etched using the resist mask, and if an underlayer is formed, the underlayer is dry-etched. Thereafter, after performing the peeling and cleaning processes of the resist mask, sintering is performed. As a result, the patterning of the upper layer wiring electrode is completed, the portion constituted by the upper layer wiring electrode among the gate wiring layer 120 and the via hole extraction layer 130 is formed, and the pads 12a to 12e are formed.

[0074] Regarding the patterning of the upper-layer wiring electrodes, the removal of the lower-layer wiring electrodes can be prevented by controlling the etching time when removing the upper-layer wiring electrodes. When forming the barrier metal layer serving as the underlying layer, it may be used as an etch stopper. Further, an oxide layer may be formed on the surface of the source electrode 113 when forming the isolation insulating film 116, but the oxide layer can be removed simultaneously when removing the upper-layer wiring electrodes. Therefore, the contact resistance of the source electrode 113 can be reduced, and it becomes possible to reduce the on-resistance.

[0075] Thereafter, the semiconductor chip 10 can be manufactured through, for example, a step of forming a passivation film 115 made of PIQ (Polyimide isoindoloquinazolinedione) or the like, a step of forming a drain electrode 114 as a back surface electrode, and a step of dicing to form chips.

[0076] (Second Embodiment) The second embodiment will be described. This embodiment is different from the first embodiment in that the region having a two-layer wiring electrode structure is changed, and since the other aspects are the same as those of the first embodiment, only the differences from the first embodiment will be described.

[0077] As shown in FIG. 9, in this embodiment, only the positions of the pads 12a to 12e in the pad arrangement region Re have a two-layer wiring electrode structure, and all other regions have a single-layer wiring electrode structure. Specifically, as shown in FIG. 10, in this embodiment, not only the source electrode 113 at a position in the active region Rb that does not overlap with the pad arrangement region Re, but also the gate wiring layer 120 and the via extraction layer 130 have a single-layer wiring electrode structure.

[0078] With such a structure, the gate wiring layer 120 and the via hole extraction layer 130 can also be made thin, so that it is possible to suppress an increase in warpage at higher temperatures. Further, when the gate wiring layer 120 and the via hole extraction layer 130 are formed into a two-layer wiring electrode structure as in the first embodiment, it is necessary to remove the separation insulating film 116 formed between the lower layer wiring electrode and the upper layer wiring electrode. However, when only the lower layer wiring electrode is used, the separation insulating film 116 does not need to be removed except for the portion of the gate wiring layer 120 connected to the gate pad 12c and the portion of the via hole extraction layer 130 connected to the second sense pad 12e. Therefore, if the separation insulating film 116 is made of a silicon nitride film, oxidation of the gate wiring layer 120 and the via hole extraction layer 130 can be more effectively suppressed.

[0079] (Third Embodiment) The third embodiment will be described. In this embodiment, the ratio of the area of the region having a two-layer wiring electrode structure is set with respect to the first and second embodiments, and since the other aspects are the same as those of the first and second embodiments, only the differences from the first and second embodiments will be described.

[0080] As described above, in the first embodiment, the region where the pads 12a to 12e are arranged, the gate wiring layer 120, and the via hole extraction layer 130 have a two-layer wiring electrode structure. Further, in the second embodiment, the region where the pads 12a to 12e are arranged has a two-layer wiring electrode structure. The area of the region having the two-layer wiring electrode structure is preferably 30% or less of the area of the active region Rb. Specifically, the warpage of the semiconductor chip 10 at high temperatures increases as the area of the region having the two-layer wiring electrode structure increases. Also, the area of the active region Rb is the area of the portion that generates heat. There is a correlation between the area of the active region Rb and the area of the region having the two-layer wiring electrode structure, and when the ratio of the area of the region having the two-layer wiring electrode structure to the area of the active region Rb is 30% or less, the increase in warpage of the semiconductor chip 10 can be kept within a more preferable range.

[0081] Therefore, by setting each layout such that the ratio of the area of the region with the two-layer wiring electrode structure to the area of the active region Rb is 30% or less, it becomes possible to further suppress an increase in the warpage of the semiconductor chip 10.

[0082] (Fourth Embodiment) The fourth embodiment will be described. This embodiment defines the pad layout in the semiconductor chip 10 with respect to the first to third embodiments, and since the other aspects are the same as those of the first to third embodiments, only the parts different from the first to third embodiments will be described.

[0083] As shown in FIG. 11, in this embodiment, the layout of the internal region Ra that constitutes the pads 12a to 12e and the source pad 11 formed on the semiconductor chip 10 is made line-symmetric about the straight line L. The straight line L is the center line among the center lines of the semiconductor chip 10 that passes through the center of the internal region Ra that constitutes the square source pad 11. With this straight line L as the center, the source pad 11 itself is line-symmetric, and the pads 12a to 12e are line-symmetric.

[0084] With such a configuration, the warpage of the semiconductor chip 10 becomes uniform about the straight line L. Therefore, it becomes easier to predict the warpage, and the design considering the warpage becomes easier.

[0085] (Fifth Embodiment) The fifth embodiment will be described. This embodiment defines the number of pads in the semiconductor chip 10 with respect to the first to fourth embodiments, and since the other aspects are the same as those of the first to fourth embodiments, only the parts different from the first to fourth embodiments will be described.

[0086] As shown in FIG. 12, in this embodiment, in addition to the internal region Ra that constitutes the source pad 11, the gate pad 12c is provided, but the other pads 12a, 12b, 12d, and 12e are not provided, and the number of pads with the two-layer wiring electrode structure is set to only one.

[0087] The warp of the semiconductor chip 10 increases according to the area of the region having a two-layer wiring electrode structure. Therefore, it is preferable to reduce the number of pads of the two-layer wiring electrode structure, and it is desirable to set it to 5 or less. Furthermore, in the first to fourth embodiments, the number of pads of the two-layer wiring electrode structure is set to 5, but it is more preferable to set the number of pads to be less than that. Therefore, as in this embodiment, by setting the number of pads to be less than 5, particularly the smallest one, it is possible to further suppress the increase in the warp of the semiconductor chip 10.

[0088] In this embodiment, the gate pad 12c is arranged along the center of one side of the semiconductor chip 10 having a rectangular shape, and the internal region Ra that constitutes the source pad 11 so as to surround the gate pad 12c is configured in a concave shape with an opening at the lower side of the paper surface. Also, as in the fourth embodiment, the source pad 11 itself is line-symmetric, and the pads 12a to 12e are line-symmetric with respect to the straight line L. However, this shows an example of the layout of the semiconductor chip 10 when the number of pads of the two-layer wiring electrode structure is 5 or less, and other layouts may be used as long as the number of pads satisfies the conditions.

[0089] (Other Embodiments) This disclosure has been described in accordance with the above-described embodiments, but is not limited to the embodiments, and includes various modifications and modifications within an equivalent range. In addition, various combinations and forms, and further, other combinations and forms including only one element, more than one element, or less than one element thereof, are within the scope and spirit of this disclosure.

[0090] For example, in each of the above embodiments, a vertical MOSFET is exemplified as the semiconductor element provided in the active region Rb, but other elements such as a vertical IGBT or a diode may be used, or a combination of multiple types of elements may be provided.

[0091] Also, although an example of the semiconductor chip 10 constituting the semiconductor device has been given, a semiconductor device having a structure different from that in FIG. 3A may be used. That is, in addition to the surface electrodes such as the source electrode 113 provided in the active region Rb, it has pads 12a to 12e arranged in the pad arrangement region Re, and while the pads 12a to 12e have a two-layer wiring electrode structure, the surface electrodes may have a one-layer wiring electrode structure.

[0092] Also, in each of the above embodiments, the case where the entire area of the pad arrangement region Re overlaps with the active region Rb has been described. However, a structure in which at least a part, rather than the entire area of the pad arrangement region Re, overlaps with the active region Rb may also be used.

[0093] Also, in each of the above embodiments, the one-layer wiring electrode structure and the two-layer wiring electrode structure indicate the number of stacked layers of wiring electrode materials such as AlSi. The number of stacked layers referred to here does not include metal layers that are not wiring electrode materials such as barrier metal layers.

Explanation of Reference Numerals

[0094] 10... semiconductor chip, 11... source pad, 12a to 12e... pads 112... interlayer insulating film, 113... source electrode, 116... isolation insulating film 120... gate wiring layer, Ra... internal region, Rb... active region, Rc... connecting region Rd... outer peripheral region, Re... pad arrangement region

Claims

1. A semiconductor device composed of a semiconductor chip (10), wherein a semiconductor element is formed, and on one surface side of the semiconductor chip, an active region (Ra) is provided where a surface electrode (113) composed of a wiring electrode material and connected to the semiconductor element is disposed, and a pad arrangement region (Re) is provided overlapping the active region in the normal direction to one surface of the semiconductor chip, where pads (12a to 12e) composed of the wiring electrode material are disposed, in a region where the pad arrangement region and the active region overlap, the pads are disposed on the surface electrode via a separation insulating film (116), so that a two-layer wiring electrode structure in which two layers of the wiring electrode material are stacked is formed, in a region of the active region that does not overlap the pad arrangement region, the surface electrode is exposed from the separation insulating film, and this exposed portion serves as a pad (11) of the surface electrode, and the surface electrode has a single-layer wiring electrode structure composed of one layer of the wiring electrode material, a semiconductor device.

2. A wiring layer (120, 130) composed of the wiring electrode material and connected to the semiconductor element is connected to the pads, and the wiring layer also has a single-layer wiring electrode structure composed of one layer of the wiring electrode material, the semiconductor device according to claim 1.

3. The semiconductor device according to claim 1 or 2, wherein the area of the region having the two-layer wiring electrode structure is 30% or less with respect to the area of the active region.

4. The semiconductor device according to any one of claims 1 to 3, wherein the surface electrode and the pads are laid out in line symmetry with respect to a straight line (L) that is a center line of the semiconductor chip passing through the center of the surface electrode.

5. The semiconductor device according to any one of claims 1 to 4, wherein the number of the pads is 5 or less.

6. The semiconductor device according to any one of claims 1 to 5, wherein the separation insulating film is made of a silicon oxide film.

7. The semiconductor device according to any one of claims 1 to 5, wherein the separation insulating film is made of a silicon nitride film.

8. The semiconductor device according to any one of claims 1 to 7, wherein the wiring electrode material is made of AlSi.

9. The semiconductor device according to any one of claims 1 to 8, wherein the semiconductor chip is formed by forming the semiconductor element on a semiconductor substrate made of silicon carbide.

10. A method of manufacturing a semiconductor device including a semiconductor chip (10) in which a semiconductor element is formed on a semiconductor substrate, comprising: after forming the semiconductor element on the semiconductor substrate, forming an interlayer insulating film (112) on one surface side of the semiconductor substrate and forming contact holes (112a to 112c) in the interlayer insulating film; forming and patterning a lower wiring electrode made of a first-layer wiring electrode material on the interlayer insulating film including the inside of the contact holes to form a surface electrode (113) connected to the semiconductor element in an active region (Rb) where the semiconductor element is formed; forming a separation insulating film (116) on the surface electrode; forming and patterning an upper wiring electrode made of a second-layer wiring electrode material on the separation insulating film to form pads (12a to 12e) in a pad arrangement region (Re) overlapping the active region; By forming the pads, in a region of the active region that does not overlap the pad arrangement region, the upper wiring electrode formed on the surface electrode is removed to expose the surface electrode from the separation insulating film, and the exposed portion constitutes a pad (11) of the surface electrode, and the surface electrode is formed as a single-layer wiring electrode structure constituted by the lower wiring electrode, and in a region of the active region that overlaps the pad arrangement region, the pads are arranged on the surface electrode to form a two-layer wiring electrode structure of the lower wiring electrode and the upper wiring electrode. A method of manufacturing a semiconductor device.

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