Method of manufacturing a semiconductor device

Abstract

To suppress reduction of pressure resistance while suppressing destruction of a gate insulating film and further suppress enlargement of a size in a lamination direction of a drift layer and a base layer.SOLUTION: A first deep layer 15 includes: a high concentration region 15a having a high concentration peak, in which an impurity concentration becomes maximum, in a concentration profile in a depth direction and including a region which is not depleted in an OFF state; and a low concentration region 15b having a region, in which an inclination of a change of the impurity concentration in the depth direction is less than a predetermined value, closer to a high concentration layer than the high concentration region 15a and being depleted in the OFF state. When a position closest to a base layer in the first deep layer 15 is defined as a first position P1, a position to be the high concentration peak is defined as a second position P2 and a position closest to the base layer in the low concentration region 15b is defined as a third position P3, a first length L1 between the first position P1 and the second position P2 is made shorter than a second length L2 between the second position P2 and the third position P3.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor device having a trench gate structure. arrangement

Background Art

[0002] Conventionally, semiconductor devices in which semiconductor elements such as MOSFETs (abbreviation for metal oxide semiconductor field effect transistors) are formed have been proposed (see, for example, Patent Document 1). Specifically, this semiconductor device includes a semiconductor substrate having a drift layer, a base layer is formed on one surface side of the semiconductor substrate, and a source region is formed in a surface layer portion of the base layer. Further, a trench is formed in the semiconductor substrate so as to penetrate the source region and the base layer. Then, a gate insulating film and a gate electrode are disposed in the trench to form a trench gate structure.

[0003] A drain region is disposed on the other surface side of the semiconductor substrate. An upper electrode is disposed on one surface side of the semiconductor substrate so as to be electrically connected to the source region and the base layer. A lower electrode is disposed on the other surface side of the semiconductor substrate so as to be electrically connected to the drain region.

[0004] Also, in this semiconductor device, a deep layer connected to the base layer in a state separated from the trench is formed at a position below the trench in the drift layer. Thereby, in this semiconductor device, it is possible to suppress the gate insulating film from being broken by the depletion layer formed between the deep layer and the drift layer.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] By the way, in the semiconductor device as described above, while suppressing the destruction of the gate insulating film, suppressing the reduction in breakdown voltage, and further, there is a desire to suppress an increase in the size along the stacking direction of the drift layer and the base layer.

[0007] In view of the above points, the present invention can suppress the destruction of the gate insulating film, suppress the reduction in breakdown voltage, and further suppress an increase in the size along the stacking direction of the drift layer and the base layer. arrangement It is an object of the present invention to provide a manufacturing method.

Means for Solving the Problems

[0010] To achieve the above object Claim 1 is A drift layer (19) of a first conductivity type, a base layer (21) of a second conductivity type formed on the surface layer portion of the drift layer, a first conductivity type impurity region (22) formed on the surface layer portion of the base layer and having a higher impurity concentration than the drift layer, a gate insulating film (26) formed on the wall surface of a trench (25) that penetrates the base layer and the impurity region and reaches the drift layer, a gate electrode (27) formed on the gate insulating film, a trench gate structure, a first deep layer (15) of a second conductivity type formed below the trench in the drift layer and separated from the trench, a second deep layer (18) of a second conductivity type connecting the base layer and the first deep layer, a high concentration layer (11) of a first conductivity type or a second conductivity type formed on the side opposite to the base layer with the drift layer interposed therebetween and having a higher impurity concentration than the drift layer, a first electrode (29) electrically connected to the base layer and the impurity region, and a second electrode (30) electrically connected to the high concentration layer. When a gate voltage equal to or higher than a predetermined voltage is applied to the gate electrode, a current flows between the first electrode and the second electrode to enter an on state, and when a gate voltage lower than the predetermined voltage is applied to the gate electrode, it enters an off state. The first deep layer has a high concentration peak where the impurity concentration is maximum in the concentration profile of the impurity concentration along the depth direction when the stacking direction of the drift layer and the base layer is the depth direction, and includes a high concentration region (15a) that does not deplete in the off state, and on the high concentration layer side from the high concentration region, there is a region where the slope of the change in the impurity concentration along the depth direction is less than a predetermined value and that depletes in the off state, a low concentration region (15b). Let the position closest to the base layer side in the first deep layer be the first position (P1), the position where the high concentration peak is located be the second position (P2), and the position closest to the base layer side in the low concentration region be the third position (P3). Then, a high concentration region is arranged between the first position and the third position, and the first length (L1) between the first position and the second position is shorter than the second length (L2) between the second position and the third position. A semiconductor device of a manufacturing method, including preparing a constituent substrate (100) including a portion on the high-concentration layer side of the drift layer, performing ion implantation on the constituent substrate to form a first deep layer, and epitaxially growing a constituent layer (17a) on the first deep layer to form a drift layer having the first deep layer inside.

[0011] According to this, a first deep layer having a concentration profile including a high-concentration region having a high-concentration peak with an impurity concentration that does not deplete at off-state and a low-concentration region with an impurity concentration that depletes at off-state is formed. For this reason, a semiconductor device is manufactured while suppressing the destruction of the gate insulating film and suppressing the reduction in breakdown voltage. Further, the first deep layer is formed such that the first length is shorter than the second length. For this reason, compared with the case where a semiconductor device having the same breakdown voltage and a first length equal to or longer than the second length is manufactured, the length of the first deep layer in the stacking direction can be shortened. Therefore, a semiconductor device that suppresses an increase in size in the stacking direction can be manufactured.

[0012] Note that the reference signs in parentheses attached to each component etc. indicate an example of the correspondence relationship between the component etc. and the specific components etc. described in the embodiments described later.

Brief Description of the Drawings

[0013]

Figure 1

Figure 2

Figure 3A

Figure 3B

Figure 3C

Figure 3D

Figure 3E

Figure 3F

Figure 4A

Figure 4B

Modes for Carrying Out the Invention

[0014] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other are denoted by the same reference signs and will be described.

[0015] (First Embodiment) The semiconductor device of the first embodiment will be described with reference to the drawings. The semiconductor device of this embodiment is suitably applied, for example, as a device mounted on a vehicle such as an automobile and for driving various electronic devices for the vehicle. Further, in this embodiment, a silicon carbide (hereinafter also referred to as SiC) semiconductor device in which an inversion-type MOSFET having a trench gate structure is formed will be described. In this embodiment, the configuration of the cell region in which the MOSFET is formed will be described, but in an actual SiC semiconductor device, an outer peripheral region in which an FLR (abbreviation for Field Limiting Ring) structure or the like is formed is provided so as to surround the cell region.

[0016] Hereinafter, one direction in the plane direction of the substrate 11 to be described later will be referred to as the X-axis direction, a direction intersecting one direction in the plane direction of the substrate will be referred to as the Y-axis direction, and a direction orthogonal to the X-axis direction and the Y-axis direction will be referred to as the Z-axis direction for explanation. In this embodiment, the X-axis direction and the Y-axis direction are orthogonal. Further, the Z-axis direction in this embodiment corresponds to the depth direction of the semiconductor substrate 10 to be described later, and also corresponds to the stacking direction of the drift layer 19 and the base layer 21 to be described later.

[0017] As shown in FIG. 1, the SiC semiconductor device is configured using a semiconductor substrate 10. Specifically, the SiC semiconductor device includes an n-type substrate 11 made of SiC. In this embodiment, as the substrate 11, for example, it has an off-angle of 0 to 8° with respect to the (0001) Si plane, and the n-type impurity concentration such as nitrogen or phosphorus is 1.0×10 + / cm 19 / cm 3 and the thickness is about 300 μm. The substrate 11 constitutes the drain region in this embodiment and corresponds to the high-concentration layer.

[0018] On the surface of the substrate 11, an n-type made of SiC -A buffer layer 12 of a certain type is formed. The buffer layer 12 is formed by performing epitaxial growth on the surface of the substrate 11. And the buffer layer 12 has an n-type impurity concentration that is the same as the impurity concentration between the substrate 11 and the low-concentration layer 13 described later, and a thickness of about 1 μm.

[0019] On the surface of the buffer layer 12, for example, an n-type impurity concentration is 5.0 - 10.0×10 15 / cm 3 and a thickness of about 10 - 15 μm, and an n - -type low-concentration layer 13 made of SiC is formed. This low-concentration layer 13 may have a constant impurity concentration in the Z-axis direction, but it is preferably given a concentration gradient such that the side of the low-concentration layer 13 closer to the substrate 11 has a higher concentration than the side farther from the substrate 11. For example, in the low-concentration layer 13, the impurity concentration in a portion about 3 - 5 μm from the surface of the substrate 11 is preferably made higher than that of other portions by about 2.0×10 15 / cm 3 . By adopting such a configuration, the internal resistance of the low-concentration layer 13 can be reduced, and the on-resistance can be reduced.

[0020] A JFET part 14 and a first deep layer 15 are formed in the surface layer part of the low-concentration layer 13. In this embodiment, the JFET part 14 and the first deep layer 15 each have a linear portion extending along the X-axis direction and arranged alternately and repeatedly in the Y-axis direction. That is, the JFET part 14 and the first deep layer 15 are each in a stripe shape extending along the X-axis direction in the normal direction to the surface of the substrate 11, and they are configured in a layout where they are arranged alternately along the Y-axis direction. Note that the normal direction to the surface of the substrate 11 can also be described as when viewed from the normal direction to the surface of the substrate 11. Also, the normal direction to the surface of the substrate 11 is also the direction along the stacking direction of the drift layer 19 and the base layer 21 described later.

[0021] The JFET section 14 is of an n-type with a higher impurity concentration than the low-concentration layer 13, and has a depth of 0.3 to 1.5 μm. In this embodiment, the JFET section 14 has an n-type impurity concentration of 7.0×10 16 ~5.0×10 17 / cm 3 . The impurity concentration of the first deep layer 15 will be specifically described later.

[0022] Also, the first deep layer 15 of this embodiment is formed shallower than the JFET section 14. That is, the first deep layer 15 is formed such that its bottom is located within the JFET section 14. In other words, the first deep layer 15 is formed such that the JFET section 14 is located between it and the low-concentration layer 13.

[0023] On the JFET section 14 and the first deep layer 15, a current dispersion layer 17, a second deep layer 18, a base layer 21, a source region 22, a contact region 23, etc. are formed.

[0024] The current dispersion layer 17 is of an n-type and is formed to be connected to the JFET section 14. For this reason, in this embodiment, the low-concentration layer 13, the JFET section 14, and the current dispersion layer 17 are connected, and these constitute a drift layer 19. And the first deep layer 15 is in a state of being formed within the drift layer 19.

[0025] The second deep layer 18 is of a p-type and has the same thickness as the current dispersion layer 17. Also, the second deep layer 18 is formed to be connected to the first deep layer 15.

[0026] Then, the current dispersion layer 17 and the second deep layer 18 extend in a direction intersecting with the longitudinal direction of the striped portion of the JFET section 14 or the first deep layer 15. In the present embodiment, the current dispersion layer 17 and the second deep layer 18 extend with the Y-axis direction as the longitudinal direction and are arranged in a layout in which a plurality of layers are alternately arranged in the X-axis direction. Note that the formation pitch of the current dispersion layer 17 and the second deep layer 18 is adjusted to the formation pitch of the trench gate structure described later, and the second deep layer 18 is formed so as to sandwich the trench 25 described later.

[0027] The base layer 21 is of p-type and is formed on the current dispersion layer 17 and the second deep layer 18. Therefore, the first deep layer 15 is connected to the base layer 21 via the second deep layer 18.

[0028] The source region 22 is of n + -type and is formed in the surface layer portion of the base layer 21. The contact region 23 is of p + -type and is formed in the surface layer portion of the base layer 21. Specifically, the source region 22 is formed so as to be in contact with the side surface of the trench 25 described later, and the contact region 23 is formed on the opposite side of the trench 25 described later with the source region 22 interposed therebetween. Note that in the present embodiment, the source region 22 corresponds to an impurity region.

[0029] The base layer 21 has, for example, a p-type impurity concentration of 3.0×10 17 / cm 3 or less. Also, the base layer 21 of the present embodiment is formed by, for example, ion implantation or the like. The source region 22 has an n-type impurity concentration in the surface layer portion, that is, a surface concentration of, for example, 1.0×10 21 / cm 3 or more. The contact region 23 has a p-type impurity concentration in the surface layer portion, that is, a surface concentration of, for example, 1.0×10 21 / cm 3 or more.

[0030] In this embodiment, as described above, the semiconductor substrate 10 is composed of the substrate 11, the buffer layer 12, the low-concentration layer 13, the JFET section 14, the first deep layer 15, the current dispersion layer 17, the second deep layer 18, the base layer 21, the source region 22, the contact region 23, etc. And since the semiconductor substrate 10 is configured as described above, it can be said that the semiconductor substrate 10 is made of SiC. Further, in this embodiment, one surface 10a of the semiconductor substrate 10 is composed of the source region 22 and the contact region 23, and the other surface 10b of the semiconductor substrate 10 is composed of the substrate 11.

[0031] In the semiconductor substrate 10, for example, trenches 25 having a width of 1.4 to 2.0 μm are formed so as to penetrate through the source region 22, the base layer 21, etc. and reach the current dispersion layer 17, and the bottom surface is located within the current dispersion layer 17. Note that the trenches 25 are formed so as not to reach the JFET section 14 and the first deep layer 15. That is, the trenches 25 are formed such that the JFET section 14 and the first deep layer 15 are located in a state separated from the trenches 25 below the bottom surface.

[0032] Also, although only one trench 25 is shown in FIG. 1, actually, a plurality of trenches 25 are extended along the Y-axis direction and arranged at equal intervals in the X-axis direction so as to form a stripe shape. That is, in this embodiment, the trenches 25 are formed such that the longitudinal direction is orthogonal to the longitudinal direction of the first deep layer 15. Further, the trenches 25 are formed so as to be sandwiched by the second deep layer 18 in the stacking direction of the drift layer 19 and the base layer 21.

[0033] In the trench 25, a gate insulating film 26 is formed on the inner wall surface, and a gate electrode 27 composed of doped Poly-Si or the like is formed on the gate insulating film 26. Thereby, a trench gate structure is configured. Although not particularly limited, the gate insulating film 26 is formed by thermally oxidizing the inner wall surface of the trench 25 or by performing a CVD (Chemical Vapor Deposition) method. And the gate insulating film 26 has a thickness of about 100 nm on both the side surface side and the bottom surface side of the trench 25.

[0034] In addition, the gate insulating film 26 is also formed on the surfaces other than the inner wall surface of the trench 25. Specifically, the gate insulating film 26 is formed so as to cover a part of one surface 10a of the semiconductor substrate 10. More specifically, the gate insulating film 26 is formed so as to cover a part of the surface of the source region 22. In other words, in a portion of the gate insulating film 26 different from the portion where the gate electrode 27 is disposed, a contact hole 26a for exposing the source region 22 and the contact region 23 is formed.

[0035] On one surface 10a of the semiconductor substrate 10, an interlayer insulating film 28 is formed so as to cover the gate electrode 27, the gate insulating film 26, and the like. The interlayer insulating film 28 is composed of BPSG (Borophosphosilicate Glass) or the like.

[0036] In the interlayer insulating film 28, a contact hole 28a is formed which communicates with the contact hole 26a to expose the source region 22 and the contact region 23. Note that the contact hole 28a formed in the interlayer insulating film 28 is formed so as to communicate with the contact hole 26a formed in the gate insulating film 26, and together with the contact hole 26a, it functions as one contact hole. For this reason, hereinafter, the contact hole 26a and the contact hole 28a are also collectively referred to as the contact hole 26b. And the pattern of the contact hole 26b is arbitrary, and examples thereof include a pattern in which a plurality of square ones are arranged, a pattern in which rectangular line-shaped ones are arranged, or a pattern in which line-shaped ones are arranged side by side. In the present embodiment, the contact hole 26b is in a line shape along the longitudinal direction of the trench 25.

[0037] On the interlayer insulating film 28, an upper electrode 29 is formed which is electrically connected to the source region 22 and the contact region 23 through the contact hole 26b. Note that in the present embodiment, the upper electrode 29 corresponds to the first electrode.

[0038] The upper electrode 29 of the present embodiment is composed of, for example, a plurality of metals such as Ni / Al. And the portion that contacts the portion constituting the n-type SiC (that is, the source region 22) among the plurality of metals is composed of a metal capable of forming an ohmic contact with the n-type SiC. Also, at least the portion that contacts the p-type SiC (that is, the base layer 21) among the plurality of metals is composed of a metal capable of forming an ohmic contact with the p-type SiC.

[0039] On the other surface 10b side of the semiconductor substrate 10, a lower electrode 30 is formed which is electrically connected to the substrate 11. Note that in the present embodiment, the lower electrode 30 corresponds to the second electrode.

[0040] In the SiC semiconductor device of the present embodiment, with such a structure, a MOSFET having a trench gate structure of an n-channel type inversion mode is configured. Note that in the present embodiment, n - type, n-type, n+ type corresponds to the first conductivity type, p-type, p + type corresponds to the second conductivity type.

[0041] And such a SiC semiconductor device, although specifically described later, when the gate voltage applied to the gate electrode 27 is equal to or higher than the threshold voltage of the insulated gate structure, it enters an on-state where current flows between the upper electrode 29 and the lower electrode 30. Also, such a SiC semiconductor device enters an off-state where no current flows between the upper electrode 29 and the lower electrode 30 when the gate voltage applied to the gate electrode 27 is less than the threshold voltage.

[0042] Next, the concentration profile along the Z-axis direction (i.e., the depth direction) of the first deep layer 15 in the present embodiment will be described with reference to FIG. 2. Hereinafter, the interface between the first deep layer 15 and the current dispersion layer 17 will be simply referred to as the interface. Also, in the semiconductor substrate 10, the position where the interface is formed is defined as the first position P1. Note that the interface between the first deep layer 15 and the current dispersion layer 17 can also be said to be the portion of the first deep layer 15 that is located closest to the base layer 21 side.

[0043] First, as shown in FIG. 2, the first deep layer 15 has a concentration profile including a high-concentration region 15a with a high-concentration peak where the impurity concentration is maximum on the first position P1 side of the interface side and is set to an impurity concentration that does not deplete in the off-state. Also, the first deep layer 15 has a low-concentration region 15b on the substrate 11 side from the high-concentration region 15a, where the slope of the change in impurity concentration along the Z-axis direction is less than a predetermined value and depletes in the off-state. In other words, the first deep layer 15 has a region where the impurity concentration hardly changes along the Z-axis direction on the substrate 11 side from the high-concentration region 15a and has a low-concentration region 15b that depletes in the off-state. Note that the portion of the first deep layer 15 on the substrate 11 side has a large slope of the change in impurity concentration but is a low-concentration region 15b because it is a region that depletes.

[0044] The high-concentration peak has an impurity concentration higher than the maximum impurity concentration of the current dispersion layer 17. For example, it has an impurity concentration of 1.0×10 18 / cm 3 or higher. The current dispersion layer 17 is configured such that, for example, the maximum impurity concentration is about 3.0×10 17 / cm 3 . The low-concentration region 15b has an impurity concentration such that the slope of the change in impurity concentration along the Z-axis direction is less than a predetermined value (i.e., the region where the impurity concentration is substantially constant) and is about the same as the maximum impurity concentration of the current dispersion layer 17, for example, about 3.0×10 17 / cm 3 .

[0045] Here, in the semiconductor substrate 10, the position (i.e., depth) serving as the boundary surface as described above is defined as the first position P1. Also, in the semiconductor substrate 10, the position where the high-concentration peak occurs is defined as the second position P2, and the position closest to the base layer 21 side in the low-concentration region 15b is defined as the third position P3. In other words, the third position P3 can also be said to be the boundary between the high-concentration region 15a and the low-concentration region 15b, or the position where the impurity concentration rapidly increases steeply from the low-concentration region 15b toward the high-concentration peak. Furthermore, the third position P3 can also be said to be the intersection of the region where the slope of the change in impurity concentration is greater than or equal to a predetermined value and the region where it is less than the predetermined value. Also, it can be said that the first deep layer 15 is formed to have a concentration profile in which the region between the first position P1 and the third position P3 is the high-concentration region 15a, and the low-concentration region 15b is provided in the portion on the substrate 11 side from the third position P3.

[0046] In this embodiment, the first length L1 between the first position P1 and the second position P2 is shorter than the second length L2 between the second position P2 and the third position P3. In other words, since the region between the first position P1 and the third position P3 is the high-concentration region 15a, it can also be said that the second position P2 is located closer to the first position P1 side than the center in the Z-axis direction in the high-concentration region 15a.

[0047] The above is the configuration of the SiC semiconductor device in this embodiment. Next, the operation and effects of the above SiC semiconductor device will be described.

[0048] First, in the SiC semiconductor device, in the off state before a gate voltage equal to or higher than the threshold voltage is applied to the gate electrode 27, an inversion layer is not formed in the base layer 21. Therefore, even if a positive voltage, for example, 1600 V, is applied to the lower electrode 30, electrons do not flow from the source region 22 into the base layer 21, and the SiC semiconductor device is in an off state where no current flows between the upper electrode 29 and the lower electrode 30.

[0049] Also, when the SiC semiconductor device is in the off state, an electric field is applied between the drain and the gate, and electric field concentration may occur at the bottom of the gate insulating film 26. However, in the above SiC semiconductor device, the first deep layer 15 and the JFET portion 14 are provided at a position deeper than the trench 25. And the first deep layer 15 has an impurity concentration at which the high-concentration peak is not depleted. Therefore, the upward rise of the equipotential line due to the influence of the drain voltage is suppressed by the depletion layer formed between the first deep layer 15 and the JFET portion 14, and it becomes difficult for a high electric field to enter the gate insulating film 26. Therefore, in this embodiment, it is possible to suppress the gate insulating film 26 from being broken.

[0050] Also, the low-concentration region 15b in the first deep layer 15 has an impurity concentration at which it is depleted. Therefore, when the SiC semiconductor device is in the off state, the portion including the low-concentration region 15b in the first deep layer 15 is also depleted. Therefore, it is possible to suppress a decrease in the breakdown voltage of the SiC semiconductor device due to the formation of the first deep layer 15.

[0051] In this case, in this embodiment, the first length L1 is shorter than the second length L2. Therefore, when a SiC semiconductor device having the same breakdown voltage is configured as compared with the case where the first length L1 is equal to or longer than the second length L2, the length of the first deep layer 15 in the Z-axis direction can be shortened. Therefore, it is possible to suppress the SiC semiconductor device from becoming large in the Z-axis direction.

[0052] Then, when a gate voltage equal to or higher than the threshold voltage, for example, 20 V, is applied to the gate electrode 27, an inversion layer is formed on the surface of the base layer 21 in contact with the trench 25. As a result, a current flows between the upper electrode 29 and the lower electrode 30, and the SiC semiconductor device is turned on. In this embodiment, since electrons passing through the inversion layer flow through the current dispersion layer 17, the JFET section 14, and the low-concentration layer 13 to the substrate 11, it can be said that the drift layer 19 having the current dispersion layer 17, the JFET section 14, and the low-concentration layer 13 is configured.

[0053] Subsequently, a method for manufacturing the SiC semiconductor device of this embodiment will be described with reference to FIGS. 3A to 3G. FIGS. 3A to 3G are cross-sectional views with the Y-axis direction in FIG. 1 as the normal direction.

[0054] First, as shown in FIG. 3A, a constituent substrate 100 formed with a buffer layer 12, a low-concentration layer 13, and a JFET section 14 made of SiC is prepared on the surface of the substrate 11. In other words, a constituent substrate 100 including a portion of the drift layer 19 on the substrate 11 side is prepared.

[0055] Then, as shown in FIG. 3B, a first deep layer 15 is formed by ion-implanting p-type impurities using a mask (not shown) on the constituent substrate 100. Specifically, by performing ion implantation a plurality of times while changing the acceleration energy, as shown in FIG. 2 above, a first deep layer 15 having a high-concentration region 15a and a low-concentration region 15b and having a concentration profile in which the first length L1 is shorter than the second length L2 is formed.

[0056] Subsequently, as shown in FIG. 3C, a constituent layer 17a for forming a current dispersion layer 17 or the like is epitaxially grown on the JFET section 14 and the first deep layer 15 to form the semiconductor substrate 10. In this way, by arranging the constituent layer 17a after forming the first deep layer 15, it is possible to suppress the p-type impurities constituting the first deep layer 15 from affecting the constituent layer 17a (i.e., the current dispersion layer 17). Therefore, it is possible to suppress a decrease in the effective concentration of the current dispersion layer 17 when the current dispersion layer 17 is formed, and it is possible to suppress an increase in the on-resistance.

[0057] Next, as shown in FIG. 3D, n-type impurities are ion-implanted using a mask (not shown) on the constituent layer 17a to form the current dispersion layer 17 and constitute the drift layer 19. That is, the impurity concentration of the portion constituting the interface with the first deep layer 15 is adjusted. Also, p-type impurities are ion-implanted using a mask (not shown) on the constituent layer 17a to form the second deep layer 18.

[0058] Subsequently, as shown in FIG. 3E, impurities are appropriately ion-implanted again using a mask (not shown) on the constituent layer 17a to form the base layer 21, the source region 22, and the contact region 23.

[0059] Thereafter, as shown in FIG. 3F, although the detailed process is omitted, a predetermined semiconductor manufacturing process is performed to form a trench gate structure, an interlayer insulating film 28, an upper electrode 29, a lower electrode 30, etc. Thereby, the SiC semiconductor device of the present embodiment is manufactured.

[0060] According to the present embodiment described above, the first deep layer 15 has a concentration profile including a high-concentration region 15a having a high-concentration peak with an impurity concentration that does not deplete when off, and a low-concentration region 15b having an impurity concentration that depletes when off. Therefore, it is possible to suppress the breakdown of the gate insulating film 26 and suppress the decrease in breakdown voltage. Further, the first deep layer 15 is formed such that the first length L1 is shorter than the second length L2. Therefore, when a SiC semiconductor device having the same breakdown voltage is configured as compared with the case where the first length L1 is equal to or greater than the second length L2, the length of the first deep layer 15 in the Z-axis direction can be shortened. Therefore, it is possible to suppress the SiC semiconductor device from increasing in size in the Z-axis direction.

[0061] (1) In the present embodiment, after forming the first deep layer 15 on the constituent substrate 100, the constituent layer 17a is disposed on the constituent substrate 100 to form the semiconductor substrate 10. Therefore, it is possible to suppress the p-type impurities constituting the first deep layer 15 from affecting the constituent layer 17a (that is, the current dispersion layer 17). Therefore, it is possible to suppress the effective concentration of the current dispersion layer 17 from decreasing when the current dispersion layer 17 is formed, and suppress the increase in on-resistance.

[0062] (Modification of the First Embodiment) A modification of the first embodiment will be described. In the first embodiment, if the first deep layer 15 has a concentration profile in which the first length L1 is shorter than the second length L2, the shape of the detailed concentration profile can be appropriately changed. For example, as shown in FIG. 4A, the first deep layer 15 may have a concentration profile in which the second position P2 coincides with the first position P1 and the first length L1 is 0. Further, as shown in FIG. 4B, the first deep layer 15 may have a concentration profile having a step C between the second position P2 and the first position P1.

[0063] (Other Embodiments) Although this disclosure has been described in accordance with the embodiments, it is understood that the disclosure is not limited to such embodiments or structures. The disclosure also includes various modifications and variations within the equivalent scope. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element thereof, are within the scope and spirit of the disclosure.

[0064] For example, in the above-described first embodiment, an n-channel type trench gate structure MOSFET with the first conductivity type being n-type and the second conductivity type being p-type was described as an example of a semiconductor switching element. However, this is merely an example, and a semiconductor switching element with another structure, for example, a p-channel type trench gate structure MOSFET in which the conductivity type of each component is inverted with respect to the n-channel type, may also be used. Furthermore, the semiconductor device may be configured such that, in addition to the MOSFET, an IGBT with a similar structure is formed. In the case of the IGBT, it is the same as the vertical MOSFET described in the above-described first embodiment except that the n-type substrate 11 in the first embodiment is changed to a P-type collector layer. + type substrate 11 to a P + type collector layer.

[0065] Also, in the above-described first embodiment, an example in which the semiconductor substrate 10 is made of SiC was described. However, the semiconductor substrate 10 may be configured using a silicon substrate, another compound semiconductor substrate, or the like.

[0066] Furthermore, in the above-described first embodiment, an example in which the first deep layer 15 extends along the X-axis direction was described, but the first deep layer 15 may extend along the Y-axis direction.

[0067] And in the above-described first embodiment, an example in which the current dispersion layer 17 is formed by performing ion implantation after forming the constituent layer 17a has been described. However, the current dispersion layer 17 may be formed by arranging the constituent layer 17a while adjusting the impurity concentration when arranging the constituent layer 17a by epitaxial growth. That is, the current dispersion layer 17 may be formed simultaneously in the process of arranging the constituent layer 17a instead of by ion implantation.

[0068] Furthermore, in the above-described first embodiment, the semiconductor substrate 10 may be configured by arranging the constituent layer 17a before forming the first deep layer 15, and the first deep layer 15 may be formed by performing ion implantation on the semiconductor substrate 10.

Description of Reference Numerals

[0069] 11 Substrate (high-concentration layer) 15 Deep layer 15a High-concentration region 15b Low-concentration region 19 Drift layer 21 Base layer 22 Source region (impurity region) 25 Trench 26 Gate insulating film 27 Gate electrode 29 Upper electrode (first electrode) 30 Lower electrode (second electrode) P1 First position P2 Second position P3 Third position

Claims

1. A drift layer (19) of a first conductivity type, a base layer (21) of a second conductivity type formed on the surface layer portion of the drift layer, a first conductivity type impurity region (22) formed on the surface layer portion of the base layer and having a higher impurity concentration than the drift layer, a trench gate structure having a gate insulating film (26) formed on the wall surface of a trench (25) that penetrates the base layer and the impurity region to reach the drift layer, and a gate electrode (27) formed on the gate insulating film, a first deep layer (15) of a second conductivity type formed below the trench in the drift layer and separated from the trench, a second deep layer (18) of a second conductivity type connecting the base layer and the first deep layer, a high concentration layer (11) of a first conductivity type or a second conductivity type formed on the opposite side of the base layer with the drift layer interposed therebetween and having a higher impurity concentration than the drift layer, a first electrode (29) electrically connected to the base layer and the impurity region, a second electrode (30) electrically connected to the high concentration layer, and when a gate voltage equal to or higher than a predetermined voltage is applied to the gate electrode, a current flows between the first electrode and the second electrode to be in an on state, and when a gate voltage lower than the predetermined voltage is applied to the gate electrode, it is configured to be in an off state, the first deep layer has a high concentration peak where the impurity concentration is maximum in a concentration profile of the impurity concentration along the depth direction when the stacking direction of the drift layer and the base layer is the depth direction, and includes a high concentration region (15a) that does not deplete in the off state, and on the high concentration layer side of the high concentration region, there is a region where the slope of the change in the impurity concentration along the depth direction is less than a predetermined value, and a low concentration region (15b) that depletes in the off state, assuming the position closest to the base layer side in the first deep layer as a first position (P1), the position where the high concentration peak is located as a second position (P2), and the position closest to the base layer side in the low concentration region as a third position (P3), the high concentration region is arranged between the first position and the third position, a manufacturing method of a semiconductor device in which a first length (L1) between the first position and the second position is shorter than a second length (L2) between the second position and the third position Prepare a constituent substrate (100) including a portion on the high-concentration layer side of the drift layer. Perform ion implantation on the constituent substrate to form the first deep layer. Form the drift layer having the first deep layer inside by epitaxially growing a constituent layer (17a) on the first deep layer. A method for manufacturing a semiconductor device comprising performing the above steps.

2. The method for manufacturing a semiconductor device according to claim 1, wherein, in forming the drift layer, the impurity concentration of a portion constituting the interface with the first deep layer in the drift layer is adjusted by performing ion implantation on the constituent layer.

3. The method for manufacturing a semiconductor device according to claim 1, wherein, in forming the drift layer, the impurity concentration of a portion constituting the interface with the first deep layer in the constituent layer is adjusted when epitaxially growing the constituent layer.

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