Switching Device and Method of Manufacturing the Same

Abstract

To form electric field relaxation regions with high position accuracy.SOLUTION: A method for manufacturing a switching device (10) includes the steps of: forming source regions (30) and a body region (34) on a semiconductor substrate (12) having a drift region (38); forming a mask (50) having openings (52) on a top face of the semiconductor substrate having the drift region; injecting a p-type impurity into the semiconductor substrate through the openings after forming the mask to form electric field relaxation regions (36) in the drift region; forming gate trenches (14) inside the openings after forming the electric field relaxation regions so that the electric field relaxation regions remain below the gate trenches; and forming gate insulator films (16) and gate electrodes (18) after forming the gate trenches.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The technology disclosed in this specification relates to a switching device and a method for manufacturing the same.

[0002] Patent Document 1 discloses a switching device having a trench-type gate electrode. This switching device has a p-type electric field relaxation region at a position in contact with the bottom surface of the gate trench. The electric field relaxation region is surrounded by an n-type drift region. The electric field relaxation region suppresses the electric field concentration in the vicinity of the lower end of the gate trench.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the manufacturing method of the switching device of Patent Document 1, an electric field relaxation region is formed by implanting p-type impurities into a part of the drift region. Next, an n-type layer and a p-type layer are sequentially epitaxially grown on the semiconductor substrate. Next, a gate trench is formed on the upper surface of the semiconductor substrate. Here, the gate trench is formed so that the lower end of the gate trench is located within the electric field relaxation region. After that, a gate electrode is formed in the gate trench. In this manufacturing method, it is necessary to align the gate trench with respect to the electric field relaxation region so that the bottom surface of the gate trench is located within the electric field relaxation region. However, since the alignment accuracy of photolithography is not so high, the gate trench may be laterally displaced with respect to the electric field relaxation region. For example, as shown in FIG. 12, the gate trench 120 may be laterally displaced with respect to the electric field relaxation region 130, and the corner portion 120c at the lower end of the gate trench 120 may protrude outward from the electric field relaxation region 130. When the corner portion 120c of the gate trench 120 protrudes from the electric field relaxation region 130 in this way, the electric field tends to concentrate in the vicinity of the corner portion 120c, and the breakdown voltage of the switching device decreases. Therefore, in the manufacturing method of Patent Document 1, even when the gate trench is laterally displaced with respect to the electric field relaxation region, it is necessary to make the width of the electric field relaxation region significantly wider than the width of the gate trench so that the bottom surface of the gate trench is located within the electric field relaxation region. When the width of the electric field relaxation region is widened, problems such as an increase in the on-resistance of the switching device or an increase in the size of the switching device occur.

[0005] There is also a method of forming a gate trench before the electric field relaxation region and implanting p-type impurities into the bottom surface of the gate trench to form the electric field relaxation region. However, in this manufacturing method, there is a problem that the vertical position of the lower end of the electric field relaxation region (i.e., the position in the thickness direction of the semiconductor substrate) is likely to vary. That is, when forming a gate trench on the upper surface of the semiconductor substrate, generally, a large variation occurs in the depth of the gate trench. For this reason, when p-type impurities are implanted into the bottom surface of the gate trench to form the electric field relaxation region, the position of the lower end of the electric field relaxation region varies greatly in the vertical direction. For example, as shown in FIG. 13, when there is a variation in the depth D140 of the gate trench 140, when p-type impurities are implanted into the bottom surface of the gate trench 140 to form the electric field relaxation region 130, the position D130 of the lower end of the electric field relaxation region 130 also varies due to the influence of the variation in the depth D140 of the gate trench. When the position of the lower end of the electric field relaxation region varies in the vertical direction, the characteristics of the switching device vary.

[0006] Therefore, in this specification, a technique for forming an electric field relaxation region with high positional accuracy is proposed.

Means for Solving the Problem

[0007] This specification proposes a method for manufacturing a switching device. The switching device includes a semiconductor substrate having a gate trench on its upper surface, a gate electrode disposed in the gate trench and insulated from the semiconductor substrate by a gate insulating film, an n-type source region in contact with the gate insulating film on the side surface of the gate trench, a p-type body region in contact with the gate insulating film on the side surface of the gate trench below the source region, a p-type electric field relaxation region in contact with the gate insulating film on the bottom surface of the gate trench, and an n-type drift region in contact with the gate insulating film on the side surface of the gate trench below the body region and in contact with the side surface and bottom surface of the electric field relaxation region. The manufacturing method includes a step of forming the source region and the body region on the semiconductor substrate having the drift region, a step of forming a mask having an opening on the upper surface of the semiconductor substrate having the drift region, a step of forming the electric field relaxation region in the drift region by implanting p-type impurities into the semiconductor substrate through the opening after forming the mask, a step of forming the gate trench by etching the upper surface of the semiconductor substrate in the opening after forming the electric field relaxation region, the gate trench being formed such that the electric field relaxation region remains below the gate trench, and a step of forming the gate insulating film and the gate electrode after forming the gate trench.

[0008] Note that the step of forming the source region and the body region may be performed at any time. For example, the step of forming the source region and the body region may be performed before the step of forming the mask, or may be performed after the step of forming the gate electrode.

[0009] In this manufacturing method, after forming an electric field relaxation region by implanting p-type impurities into a semiconductor substrate through an opening of a mask, a gate trench is formed by etching the upper surface of the semiconductor substrate within the opening of the same mask. Therefore, misalignment in the lateral direction between the electric field relaxation region and the gate trench can be suppressed. Also, in this manufacturing method, since the gate trench is formed after forming the electric field relaxation region, the position of the lower end of the electric field relaxation region is not affected by the depth variation of the gate trench. For this reason, variation in the vertical direction of the position of the lower end of the electric field relaxation region is suppressed. Thus, according to this manufacturing method, misalignment in the lateral direction of the electric field relaxation region with respect to the gate trench can be suppressed, and variation in the vertical direction of the position of the lower end of the electric field relaxation region can be suppressed. That is, the electric field relaxation region can be formed with high positional accuracy.

Brief Description of the Drawings

[0010]

Figure 1

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Figure 13

Embodiments for Carrying Out the Invention

[0011] In an example manufacturing method disclosed in this specification, in the step of forming the electric field relaxation region, the electric field relaxation region may be formed such that the width of the electric field relaxation region becomes wider toward the lower side.

[0012] According to this configuration, since the width of the electric field relaxation region becomes wider near the bottom surface of the gate trench, the entire bottom surface of the gate trench is easily covered by the electric field relaxation region, and electric field concentration near the lower end of the gate trench can be effectively suppressed.

[0013] In an example manufacturing method disclosed in this specification, in the step of forming the gate trench, the gate trench may be formed such that the width of the gate trench becomes narrower toward the lower side.

[0014] According to this configuration, since the width of the bottom surface of the gate trench becomes narrower, the entire bottom surface of the gate trench is easily covered by the electric field relaxation region, and electric field concentration near the lower end of the gate trench can be effectively suppressed.

[0015] In an example manufacturing method disclosed in this specification, after the step of forming the gate trench, the method may further include a step of etching the side surface of the gate trench.

[0016] According to this configuration, the width of the portion where the drift region contacts the gate insulating film becomes wider above the electric field relaxation region, and variations in the mirror capacitance of the switching element are suppressed.

[0017] In an example manufacturing method disclosed in this specification, the width of the bottom surface of the gate trench may be narrower than the width of the electric field relaxation region. In the step of forming the gate trench, the gate trench may be formed such that the electric field relaxation region is in contact with each corner portion between the bottom surface of the gate trench and the side surface of the gate trench.

[0018] According to this configuration, the electric field concentration in the vicinity of the lower end of the gate trench can be effectively suppressed.

[0019] In an example manufacturing method disclosed in this specification, the drift region may have a low-concentration region and a high-concentration region that has an n-type impurity concentration higher than that of the low-concentration region and is disposed above the low-concentration region. In the step of forming the electric field relaxation region, the electric field relaxation region may be formed in the high-concentration region such that the lower end of the electric field relaxation region is located within the high-concentration region.

[0020] According to this configuration, since the position of the lower end of the electric field relaxation region is less likely to vary in the depth direction, it is easy to position the lower end of the electric field relaxation region above the lower end of the high-concentration region. By positioning the lower end of the electric field relaxation region above the lower end of the high-concentration region, the on-resistance of the switching element can be reduced.

[0021] This specification proposes a switching device. This switching device includes a semiconductor substrate having a plurality of gate trenches on its upper surface, a plurality of gate electrodes disposed within the plurality of gate trenches and insulated from the semiconductor substrate by a gate insulating film, an n-type source region in contact with the gate insulating film on the side surfaces of the plurality of gate trenches, a p-type body region in contact with the gate insulating film on the side surfaces of the plurality of gate trenches below the plurality of source regions, a plurality of p-type electric field relaxation regions in contact with the gate insulating film on the bottom surfaces of the plurality of gate trenches, and an n-type drift region in contact with the gate insulating film on the side surfaces of the plurality of gate trenches below the body region and in contact with the side surfaces and bottom surfaces of the plurality of electric field relaxation regions. In each of the plurality of gate trenches, the deviation between the center in the width direction of the gate trench and the center in the width direction of the electric field relaxation region below the gate trench may be 0.1 μm or less. Between the plurality of electric field relaxation regions, the variation in the distance in the thickness direction of the semiconductor substrate from the upper surface of the semiconductor substrate to the lower end of the electric field relaxation region may be ±2% or less.

[0022] In this switching element, since the lateral deviation between the gate trench and the electric field relaxation region is small, electric field concentration can be preferably suppressed in the vicinity of the lower end of the gate trench. Also, in this switching element, the variation in the depth direction (i.e., the thickness direction of the semiconductor substrate) of the position of the lower end of the electric field relaxation region is small. Therefore, in this switching element, variations in characteristics are less likely to occur. Further, such a switching element with high positional accuracy of the electric field relaxation region can be manufactured by any of the manufacturing methods described above.

[0023] In an example of a switching device disclosed in this specification, in each of the plurality of gate trenches, the width of the bottom surface of the gate trench may be narrower than the width of the electric field relaxation region below the gate trench. In each of the plurality of gate trenches, the electric field relaxation region may be in contact with each corner portion between the bottom surface of the gate trench and the side surface of the gate trench.

[0024] According to this configuration, the electric field concentration near the lower end of the gate trench can be effectively suppressed.

Example

[0025] FIG. 1 shows a MOSFET (metal oxide semiconductor field effect transistor) 10 of an example. The MOSFET 10 has a semiconductor substrate 12. The semiconductor substrate 12 is made of SiC (that is, silicon carbide). However, the semiconductor substrate 12 may be made of other materials such as silicon. Hereinafter, the thickness direction of the semiconductor substrate 12 is referred to as the z direction, one direction parallel to the upper surface 12a of the semiconductor substrate 12 is referred to as the x direction, and a direction parallel to the upper surface 12a of the semiconductor substrate 12 and orthogonal to the x direction is referred to as the y direction.

[0026] A plurality of gate trenches 14 are provided on the upper surface 12a of the semiconductor substrate 12. Each gate trench 14 is arranged at intervals in the x direction. Each gate trench 14 extends long in the y direction. The inner surface of each gate trench 14 is covered with a gate insulating film 16. A gate electrode 18 is arranged in each gate trench 14. Each gate electrode 18 is insulated from the semiconductor substrate 12 by a corresponding gate insulating film 16. The upper surface of each gate electrode 18 is covered with an interlayer insulating film 20.

[0027] The MOSFET 10 has a source electrode 22 and a drain electrode 24. The source electrode 22 covers the upper surface 12a of the semiconductor substrate 12 and the interlayer insulating film 20. The source electrode 22 is in contact with the semiconductor substrate 12 on the upper surface 12a. The source electrode 22 is insulated from the gate electrode 18 by the interlayer insulating film 20. The drain electrode 24 covers the entire lower surface 12b of the semiconductor substrate 12.

[0028] The semiconductor substrate 12 has a plurality of source regions 30, a plurality of contact regions 32, a body region 34, a plurality of electric field relaxation regions 36, a drift region 38, and a drain region 40.

[0029] Each source region 30 is an n-type region having a high n-type impurity concentration. Each source region 30 is provided in a range facing the upper surface 12a of the semiconductor substrate 12. Each source region 30 makes an ohmic contact with the source electrode 22. Each source region 30 is in contact with the gate insulating film 16 at the upper end of the side surface of the gate trench 14.

[0030] Each contact region 32 is a p-type region having a high p-type impurity concentration. Each contact region 32 is provided in a range sandwiched by the source regions 30 and facing the upper surface 12a of the semiconductor substrate 12. Each contact region 32 makes an ohmic contact with the source electrode 22.

[0031] The body region 34 is a p-type region having a lower p-type impurity concentration than the contact region 32. The body region 34 is disposed below the plurality of source regions 30 and the plurality of contact regions 32. The body region 34 is in contact with the plurality of source regions 30 and the plurality of contact regions 32 from below. The body region 34 is in contact with the gate insulating film 16 at the side surface of each gate trench 14 below each source region 30.

[0032] Each electric field relaxation region 36 is a p-type region having a p-type impurity concentration lower than that of the contact region 32. Each electric field relaxation region 36 is disposed below the corresponding gate trench 14. Each electric field relaxation region 36 extends long in the y direction along the bottom surface of the corresponding gate trench 14. Each electric field relaxation region 36 is in contact with the gate insulating film 16 over the entire bottom surface of the corresponding gate trench 14. Note that each electric field relaxation region 36 is connected to the body region 34 by a p-type region provided at a position not shown. However, in other embodiments, each electric field relaxation region 36 may not be connected to the body region 34 and may be floating with respect to the body region 34.

[0033] The drift region 38 is an n-type region having a relatively low n-type impurity concentration. The drift region 38 is provided below the body region 34. The drift region 38 is in contact with the gate insulating film at the side surfaces of each gate trench 14 below the body region 34. The drift region 38 is in contact with the side surfaces and the bottom surface of each electric field relaxation region 36. The drift region 38 has a high concentration region 38a and a low concentration region 38b. The high concentration region 38a has an n-type impurity concentration lower than that of the source region 30. The low concentration region 38b has an n-type impurity concentration lower than that of the high concentration region 38a.

[0034] The high concentration region 38a is distributed from the position of the lower surface of the body region 34 to a position below the lower end of each electric field relaxation region 36. The high concentration region 38a is in contact with the body region 34 from below. The high concentration region 38a is in contact with the gate insulating film 16 at the side surfaces of each gate trench 14 below the body region 34. That is, the high concentration region 38a is in contact with the gate insulating film 16 in the range between the electric field relaxation region 36 and the body region 34 (that is, the range of the width W38 shown in FIG. 1) of the side surfaces of each gate trench 14. The high concentration region 38a is in contact with the side surfaces and the bottom surface of each electric field relaxation region 36. That is, the lower end of each electric field relaxation region 36 is located within the high concentration region 38a.

[0035] The low-concentration region 38b is disposed below the high-concentration region 38a. The low-concentration region 38b is in contact with the high-concentration region 38a from below. The low-concentration region 38b is separated from each electric field relaxation region 36 by the high-concentration region 38a. That is, the low-concentration region 38b is not in contact with each electric field relaxation region 36.

[0036] The drain region 40 is an n-type region having an n-type impurity concentration higher than that of the drift region 38 (that is, higher than both the high-concentration region 38a and the low-concentration region 38b). The drain region 40 is disposed below the low-concentration region 38b. The drain region 40 is in contact with the low-concentration region 38b from below. The drain region 40 is disposed in a range facing the lower surface 12b of the semiconductor substrate 12. The drain region 40 is in ohmic contact with the drain electrode 24.

[0037] In FIG. 1, the center C14 indicates the center of the gate trench 14 in the width direction (i.e., the x direction) of the gate trench 14. Also, in FIG. 1, the center C36 indicates the center of the electric field relaxation region 36 in the width direction (i.e., the x direction) of the electric field relaxation region 36. In all the gate trenches 14 of the MOSFET 10, the deviation between the center C14 of the gate trench 14 and the center C36 of the electric field relaxation region 36 is 0.1 μm or less. That is, in the x direction, the center C14 of the gate trench 14 and the center C36 of the electric field relaxation region 36 substantially coincide. Also, in all the gate trenches 14 of the MOSFET 10, the width W14 of the bottom surface of the gate trench 14 is narrower than the width W36 of the electric field relaxation region 36 at the position of the bottom surface of the gate trench 14. Therefore, each corner portion 14c connecting the bottom surface of the gate trench 14 and the side surface of the gate trench 14 is covered by the electric field relaxation region 36. That is, at each corner portion 14c of the gate trench 14, the electric field relaxation region 36 is in contact with the gate insulating film 16.

[0038] In FIG. 1, the distance L36 indicates the distance in the z direction from the upper surface 12a of the semiconductor substrate 12 to the lower end of the electric field relaxation region 36. Between the plurality of electric field relaxation regions 36 of the MOSFET 10, the variation in the distance L36 is ±2% or less. That is, the variation in the distance L36 is extremely small.

[0039] Next, a method for manufacturing the MOSFET 10 of the embodiment will be described. First, a semiconductor substrate 12 (that is, the semiconductor substrate 12 before processing) shown in FIG. 2 is prepared. The semiconductor substrate 12 shown in FIG. 2 is made of SiC. However, the semiconductor substrate 12 may be made of other materials such as silicon. The semiconductor substrate 12 shown in FIG. 2 has a drain region 40, a low-concentration region 38b, and a high-concentration region 38a. The low-concentration region 38b is disposed above the drain region 40, and the high-concentration region 38a is disposed above the low-concentration region 38b. The low-concentration region 38b and the high-concentration region 38a may be regions formed by epitaxial growth or regions formed by ion implantation. Electrodes, insulating films, etc. are not provided on the upper surface 12a and the lower surface 12b of the semiconductor substrate 12 in FIG. 2.

[0040] First, epitaxial growth, ion implantation, etc. are performed on the semiconductor substrate 12 in FIG. 2 to form a source region 30, a contact region 32, and a body region 34 as shown in FIG. 3.

[0041] Next, as shown in FIG. 4, a mask 50 made of silicon oxide is formed on the upper surface 12a of the semiconductor substrate 12. Next, a plurality of openings 52 are formed in the mask 50 by photolithography, etching, etc. Here, the mask 50 is formed such that each opening 52 is located above each part of the semiconductor substrate 12 where the gate trench 14 and the electric field relaxation region 36 are to be formed. The upper surface 12a of the semiconductor substrate 12 is exposed within each opening 52.

[0042] Next, as shown in FIG. 5, p-type impurities are ion-implanted into the semiconductor substrate 12 through the mask 50. In the portions where the mask 50 exists, the p-type impurities are shielded by the mask 50. Therefore, the p-type impurities are implanted into the semiconductor substrate 12 through each opening 52. Here, by adjusting the implantation energy of the p-type impurities, the p-type impurities are implanted so that the implanted p-type impurities reach the high-concentration region 38a and do not reach the low-concentration region 38b. That is, the p-type impurities are implanted within the hatched range shown in FIG. 5. In the implantation range of the p-type impurities in the high-concentration region 38a, the p-type impurities are implanted at a higher concentration than in the high-concentration region 38a. Therefore, a p-type electric field relaxation region 36 is formed within the high-concentration region 38a. In this way, a p-type electric field relaxation region 36 is formed below the opening 52. The electric field relaxation region 36 is formed such that the lower end of the electric field relaxation region 36 is located within the high-concentration region 38a (that is, the lower end of the electric field relaxation region 36 does not contact the low-concentration region 38b). In the implantation range 30x of the p-type impurities in the source region 30, the n-type impurity concentration in the source region 30 is higher than the concentration of the implanted p-type impurities. Therefore, the implantation range 30x of the p-type impurities in the source region 30 is maintained as n-type. In the implantation range 34x of the p-type impurities in the body region 34, the p-type impurity concentration in the body region 34 increases.

[0043] The implantation depth of the p-type impurities can be controlled with relatively high accuracy. Therefore, between the electric field relaxation regions 36, the variation in the depth direction of the lower end of the electric field relaxation region 36 is extremely small. That is, between the electric field relaxation regions 36, the variation in the distance L36 is extremely small. That is, according to this manufacturing method, the position of the lower end of the electric field relaxation region 36 in the z direction can be accurately controlled.

[0044] Also, when the p-type impurities travel in the z direction in the semiconductor substrate 12, the p-type impurities are scattered and diffuse in the x direction. Therefore, the width in the x direction of the implantation range of the p-type impurities shown in FIG. 5 (that is, the hatched range) is larger at the lower side. Therefore, the width W36 of the lower portion of the electric field relaxation region 36 is slightly wider than the width W52 of the opening 52.

[0045] Next, using the mask 50 as it is which was used for p-type impurity implantation, the upper surface 12a of the semiconductor substrate 12 is etched. That is, the upper surface 12a of the semiconductor substrate 12 is etched within the opening 52 of the mask 50. As a result, as shown in FIG. 6, a gate trench 14 is formed on the upper surface 12a of the semiconductor substrate 12. Here, the semiconductor substrate 12 is etched in the z direction within the opening 52 by anisotropic etching such as reactive ion etching to form the gate trench 14. Here, a gate trench 14 is formed that penetrates the source region 30 and the body region 34 and reaches the electric field relaxation region 36. Here, the gate trench 14 is formed so that the electric field relaxation region 36 remains below the gate trench 14. By forming the gate trench 14, most of the p-type impurity implantation range 30x in the source region 30 and the p-type impurity implantation range 34x in the body region 34 shown in FIG. 5 are removed. Since the ion implantation shown in FIG. 5 and the etching shown in FIG. 6 are carried out using the same mask 50, the gate trench 14 is accurately formed at a position overlapping the electric field relaxation region 36. For this reason, the center C14 of the gate trench 14 can be made to coincide with the center C36 of the electric field relaxation region 36 with high accuracy. That is, according to this manufacturing method, the displacement in the x direction between the center C14 of the gate trench 14 and the center C36 of the electric field relaxation region 36 can be made 0.1 μm or less.

[0046] Also, in the step of forming the gate trench 14, by adjusting the etching conditions, the gate trench 14 is formed so that the width in the x direction of the gate trench 14 becomes narrower toward the lower side. For this reason, the width W14k in the x direction of the bottom surface of the gate trench 14 is slightly narrower than the width W52 of the opening 52. As described above, the width W36 of the lower portion of the electric field relaxation region 36 is slightly wider than the width W52 of the opening 52. Therefore, the electric field relaxation region 36 exists on both sides in the x direction of the bottom surface of the gate trench 14. That is, the corner portion 14c of the gate trench 14 is covered by the electric field relaxation region 36.

[0047] Next, the mask 50 is removed. Next, a carbon film is formed to cover the upper surface 12a of the semiconductor substrate 12 and the inner surface of the gate trench 14. Next, the semiconductor substrate 12 is annealed to activate the p-type impurities implanted in the semiconductor substrate 12. Note that the carbon film prevents silicon atoms from diffusing outside the semiconductor substrate 12 during the annealing process. After the annealing process, the carbon film is removed.

[0048] Next, as shown in FIG. 7, the upper surface 12a of the semiconductor substrate 12 and the inner surface of the gate trench 14 are etched by isotropic etching (e.g., CDE (chemical dry etching) or the like). Thereby, the damage layer (that is, the layer damaged by ion implantation, etching, etc.) existing on the upper surface 12a and the inner surface of the gate trench 14 is removed. Further, by etching the side surface of the gate trench 14 in this manner, the width of the gate trench 14 slightly expands. For example, the width of the bottom surface of the gate trench 14 expands from the width W14k shown in FIG. 6 to the width W14 shown in FIG. 7. Since the amount of expansion of the width of the gate trench 14 is slight, an electric field relaxation region 36 remains at a position adjacent to the side surface of the gate trench 14 in the vicinity of the bottom surface of the gate trench 14. Further, by slightly expanding the width of the gate trench 14, the upper portion of the electric field relaxation region 36 (that is, the portion 36u in FIG. 6) is removed. Therefore, as shown in FIG. 7, a high-concentration region 38a is exposed on the side surface of the gate trench 14 at the upper portion of the electric field relaxation region 36.

[0049] Next, as shown in FIG. 8, a gate insulating film 16 is formed to cover the inner surface of the gate trench 14. As a result, the source region 30 is in contact with the gate insulating film 16 at the upper end portion of the side surface of the gate trench 14. Also, the body region 34 is in contact with the gate insulating film 16 at the side surface of the gate trench 14 below the source region 30. Further, the high-concentration region 38a is in contact with the gate insulating film 16 below the body region 34 (that is, in the range between the body region 34 and the electric field relaxation region 36). Also, the electric field relaxation region 36 is in contact with the gate insulating film 16 at the bottom surface of the gate trench 14 and the side surface in the vicinity of the bottom surface. Next, as shown in FIG. 8, a gate electrode 18 is formed in the gate trench 14.

[0050] Thereafter, as shown in FIG. 1, an interlayer insulating film 20 is formed so as to cover the upper surface of the gate electrode 18. Next, a source electrode 22 is formed so as to cover the upper surface 12a of the semiconductor substrate 12 and the interlayer insulating film 20. Next, a drain electrode 24 is formed so as to cover the lower surface 12b of the semiconductor substrate 12. As a result, the MOSFET 10 shown in FIG. 1 is completed.

[0051] Next, the operation of the MOSFET 10 will be described. The MOSFET 10 is used in a state where a higher potential than the source electrode 22 is applied to the drain electrode 24. When a potential higher than the gate threshold is applied to the gate electrode 18, a channel is formed in a portion near the gate insulating film 16 in the body region 34. As a result, as shown by the arrow 92 in FIG. 9, electrons flow from the drain region 40 through the low-concentration region 38b, the high-concentration region 38a, and the channel in the body region 34 to the source region 30. That is, the MOSFET 10 is turned on. When the potential of the gate electrode 18 is lowered to a potential below the gate threshold, the channel disappears and the flow of electrons stops. That is, the MOSFET 10 is turned off.

[0052] When MOSFET 10 turns off, a depletion layer spreads from the body region 34 to the drift region 38. By depleting the drift region 38, MOSFET 10 can hold the high voltage applied between the drain electrode 24 and the source electrode 22. Also, when MOSFET 10 turns off, a depletion layer spreads from the electric field relaxation region 36 to the high-concentration region 38a around the lower end of the gate trench 14. The depletion layer that spreads from the electric field relaxation region 36 to the high-concentration region 38a suppresses the electric field concentration around the lower end of the gate trench 14. Therefore, MOSFET 10 has a high breakdown voltage. As shown in FIG. 12, when the corner portion of the gate trench is located outside the electric field relaxation region due to misalignment between the gate trench and the electric field relaxation region, electric field concentration occurs around the corner portion. In contrast, in the above manufacturing method, since the electric field relaxation region 36 and the gate trench 14 are formed using the common mask 50, misalignment of the electric field relaxation region 36 with respect to the gate trench 14 (more specifically, misalignment of the center C36 of the electric field relaxation region 36 with respect to the center C14 of the gate trench 14) can be suppressed. Therefore, it is possible to suppress the corner portion 14c from protruding outside the electric field relaxation region 36. Therefore, according to the above manufacturing method, electric field concentration in the vicinity of the lower end of the gate trench 14 can be more reliably prevented. Also, in the above manufacturing method, since almost no misalignment of the electric field relaxation region 36 with respect to the gate trench 14 occurs, even if the width W36 of the electric field relaxation region 36 is not so wide, it is possible to suppress the corner portion 14c from protruding outside the electric field relaxation region 36. Since the width W36 of the electric field relaxation region 36 can be made relatively narrow, MOSFET 10 can be miniaturized. Also, since the width W36 of the electric field relaxation region 36 can be made relatively narrow, electrons can flow through a relatively short path as shown by the arrow 92 in FIG. 9. For this reason, the on-resistance of MOSFET 10 can be lowered.

[0053] The dashed line 90 in FIG. 9 indicates the depletion layer that spreads from the electric field relaxation region 36 to its periphery due to the built-in potential when the MOSFET 10 is on. Also, as described above, the arrow 92 in FIG. 9 indicates the path along which electrons flow when the MOSFET 10 is on. As shown in FIG. 9, when the MOSFET 10 is on, electrons flow avoiding the depletion layer 90. Since the n-type impurity concentration in the high-concentration region 38a adjacent to the electric field relaxation region 36 is relatively high, the range over which the depletion layer 90 spreads is narrow. Therefore, as indicated by the arrow 92, electrons can flow along a relatively short path. Therefore, the on-resistance of the MOSFET 10 is low. Further, FIG. 10 shows, as a comparative example, the current path in a MOSFET in which the electric field relaxation region 36 protrudes from the high-concentration region 38a to the low-concentration region 38b. When the electric field relaxation region 36 contacts the low-concentration region 38b as shown in FIG. 10, since the n-type impurity concentration in the low-concentration region 38b is low, when the MOSFET 10 is on, the depletion layer 90 spreads widely from the high-concentration region 38a into the low-concentration region 38b due to the built-in potential. When the depletion layer 90 spreads widely into the low-concentration region 38b in this way, as indicated by the arrow 94, electrons flow in a large detour to avoid the depletion layer 90. As a result, the path along which electrons flow becomes long, and the on-resistance of the MOSFET becomes high. For example, in the method of forming an electric field relaxation region by implanting p-type impurities into the bottom surface of the gate trench shown in FIG. 13, the position of the lower end of the electric field relaxation region varies greatly due to the influence of the variation in the depth of the gate trench. As a result, when attempting to form the electric field relaxation region 36 within the high-concentration region 38a as shown in FIG. 9, the electric field relaxation region 36 may contact the low-concentration region 38b as shown in FIG. 10. Therefore, when forming the electric field relaxation diffusion region by the method of implanting p-type impurities into the bottom surface of the gate trench, the variation in the on-resistance of the MOSFET becomes large. In contrast, in the manufacturing method of the above-described embodiment, since the gate trench 14 is formed after forming the electric field relaxation region 36, the position of the lower end of the electric field relaxation region 36 (i.e., the distance L36) is not affected by the variation in the depth of the gate trench 14. Therefore, according to the manufacturing method of the embodiment, the variation in the position of the lower end of the electric field relaxation region 36 can be suppressed, and it can be prevented that the electric field relaxation region 36 is formed in contact with the low-concentration region 38b.Therefore, by manufacturing the MOSFET 10 according to the manufacturing method of the embodiment, variations in the on-resistance of the MOSFET 10 can be suppressed.

[0054] Also, in the manufacturing method of the above-described embodiment, the electric field relaxation region 36 is formed such that the width becomes wider toward the lower side, and the gate trench 14 is formed such that the width becomes narrower toward the lower side. Therefore, at the position of the bottom surface of the gate trench 14, the width W36 of the electric field relaxation region 36 can be made wider than the width W14 of the gate trench 14. As a result, the gate trench 14 and the electric field relaxation region 36 can be arranged such that the corner portion 14c of the gate trench 14 is surely covered by the electric field relaxation region 36. For this reason, electric field concentration in the vicinity of the lower end of the gate trench 14 can be more surely prevented. In other embodiments, it is not necessary to form the electric field relaxation region 36 such that the width becomes wider toward the lower side, nor is it necessary to form the gate trench 14 such that the width becomes narrower toward the lower side. For example, when forming the electric field relaxation region 36 such that the width becomes wider toward the lower side, it is not necessary to form the gate trench 14 such that the width becomes narrower toward the lower side. Also, when forming the gate trench 14 such that the width becomes narrower toward the lower side, it is not necessary to form the electric field relaxation region 36 such that the width becomes wider toward the lower side. As long as the corner portion 14c of the gate trench 14 can be covered by the electric field relaxation region 36, the shapes of the electric field relaxation region 36 and the gate trench 14 can be any shape.

[0055] Also, according to the manufacturing method of the above-described embodiment, since the electric field relaxation region 36 can be formed with high precision, variations in the z-direction width W38 of the portion where the high-concentration region 38a contacts the gate insulating film 16 (i.e., the portion between the body region 34 and the electric field relaxation region 36) are suppressed. The width W38 affects the mirror capacitance of the MOSFET 10. According to the manufacturing method of the above-described embodiment, since variations in the width W38 are suppressed, variations in the mirror capacitance of the MOSFET 10 can be suppressed. In particular, in the manufacturing method of the above-described embodiment, after the gate trench 14 is formed, the side surface of the gate trench 14 is etched. When the side surface of the gate trench 14 is etched, a wider width W38 can be ensured. When a wider width W38 is ensured, variations in the width W38 are suppressed, and variations in the mirror capacitance are more effectively suppressed.

[0056] In the above-described embodiment, the drift region 38 had the high-concentration region 38a and the low-concentration region 38b. However, as shown in FIG. 11, the drift region 38 may be composed of an n-type region having a single concentration. Even in this case, variations in the characteristics of the MOSFET can be suppressed by suppressing variations in the position of the lower end of the electric field relaxation region 36 (i.e., the distance L36).

[0057] Also, in the manufacturing method of the above-described embodiment, the source region 30, the contact region 32, and the body region 34 were formed before forming the electric field relaxation region 36 and the gate trench 14. However, after forming the electric field relaxation region 36 and the gate trench 14, the source region 30, the contact region 32, and the body region 34 may be formed by ion implantation or the like.

[0058] Also, in the above-described embodiment, the MOSFET was described. However, the technology disclosed in this specification may be applied to other switching devices (e.g., IGBT (insulated gate bipolar transistor), etc.).

[0059] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Also, the technology illustrated in this specification or the drawings achieves multiple purposes simultaneously, and achieving one of those purposes itself has technical utility.

Explanation of Reference Numerals

[0060] 12: Semiconductor substrate, 14: Gate trench, 16: Gate insulating film, 18: Gate electrode, 30: Source region, 32: Contact region, 34: Body region, 36: Electric field relaxation region, 38: Drift region, 38a: High concentration region, 38b: Low concentration region, 40: Drain region

Claims

1. A method for manufacturing a switching device (10), comprising: wherein the switching device includes: a semiconductor substrate (12) having a gate trench (14) on its upper surface; a gate electrode (18) disposed within the gate trench and insulated from the semiconductor substrate by a gate insulating film (16); an n-type source region (30) in contact with the gate insulating film on a side surface of the gate trench; a p-type body region (34) in contact with the gate insulating film on the side surface of the gate trench below the source region; a p-type electric field relaxation region (36) in contact with the gate insulating film on a bottom surface of the gate trench; an n-type drift region (38) in contact with the gate insulating film on the side surface of the gate trench below the body region and in contact with side and bottom surfaces of the electric field relaxation region; and having: wherein the manufacturing method includes: a step of forming the source region and the body region in the semiconductor substrate having the drift region; a step of forming a mask (50) having an opening (52) on the upper surface of the semiconductor substrate having the drift region; a step of forming the electric field relaxation region in the drift region by implanting p-type impurities into the semiconductor substrate through the opening after forming the mask; a step of forming the gate trench by etching the upper surface of the semiconductor substrate within the opening after forming the electric field relaxation region, the gate trench being formed such that the electric field relaxation region remains below the gate trench; a step of forming the gate insulating film and the gate electrode after forming the gate trench; and having: in the step of forming the electric field relaxation region, the electric field relaxation region is formed such that the width thereof becomes wider toward the lower side; a manufacturing method.

2. The manufacturing method according to claim 1, wherein in the step of forming the gate trench, the gate trench is formed such that the width thereof becomes narrower toward the lower side.

3. The manufacturing method according to claim 1 or 2, further comprising a step of etching a side surface of the gate trench after the step of forming the gate trench.

4. The width of the bottom surface of the gate trench is narrower than the width of the electric field relaxation region. In the step of forming the gate trench, the gate trench is formed such that the electric field relaxation region contacts each corner portion (14c) between the bottom surface of the gate trench and the side surface of the gate trench. The manufacturing method according to any one of claims 1 to 3.

5. The drift region has a low concentration region (38b) and a high concentration region (38a) that has an n-type impurity concentration higher than that of the low concentration region and is disposed above the low concentration region. In the step of forming the electric field relaxation region, the electric field relaxation region is formed in the high concentration region such that the lower end of the electric field relaxation region is located within the high concentration region. The manufacturing method according to any one of claims 1 to 4.

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