Silicon carbide semiconductor device and method for manufacturing the same

Abstract

Provided is a method for producing a silicon carbide semiconductor device, the method making is possible to suppress degradation of a built-in diode due to charging, and to suppress any variation in on-resistances of active elements. The method includes: a step for epitaxially growing a first-electroconductivity-type drift layer (2) on the upper-surface side of a first-electroconductivity-type silicon carbide substrate (1s); a step for forming a second-electroconductivity-type base region on the upper-surface side of the drift layer (2); a step for forming a first-electroconductivity-type main region on the upper-surface side of the drift layer (2) such that the main region is in contact with the base region; a step for forming a gate insulation film so as to be in contact with the base region and the main region; a step for forming a gate electrode so as to be in contact with the base region and the main region with the gate insulation film interposed therebetween; and a step for irradiating the drift layer (2) with a lifetime killer from the upper-surface side of the drift layer (2) to form a lifetime killer region (23) at a depth that includes the lower surface of the drift layer (2), said step being carried out after the step for epitaxially growing the drift layer (2) and before the step for forming the gate insulation film.

Description

Technical Field

[0001] The present invention relates to a silicon carbide (SiC) semiconductor device and a method for manufacturing the same.

Background Art

[0002] Commercially available silicon carbide (SiC) single crystal substrates contain a large number of dislocations including basal plane dislocations (BPDs). Such dislocations are inherited by epitaxial substrates on which SiC single crystals are epitaxially grown. Therefore, it is known that the characteristics of semiconductor devices formed on the epitaxial substrates are adversely affected.

[0003] In semiconductor devices (SiC semiconductor devices) such as MOS field effect transistors (FETs) using SiC as a semiconductor material, a built-in diode having a pn junction is provided on an epitaxial substrate. The basal plane dislocation causes deterioration of the forward characteristics of the built-in diode that performs bipolar operation during turn-off. For example, minority carriers generated by forward conduction during bipolar operation, such as holes in an n-type semiconductor, diffuse through the epitaxial substrate. When the minority carriers recombine at the basal plane dislocation and give recombination energy to the basal plane dislocation, stacking faults expand in the epitaxial substrate starting from the basal plane dislocation. When the stacking faults expand, when a forward current is passed through the built-in diode, the forward voltage (on-voltage) increases and the forward resistance (on-resistance) increases. Thus, when the device characteristics deteriorate, the generated loss increases over time and the amount of heat generation also increases, which causes a failure of the semiconductor device.

[0004] The stacking faults expand from the interface between an n-type substrate and a drift layer which is an n-type epitaxial growth layer. Therefore, a high concentration of n +By disposing a recombination promoting layer, holes injected from the surface electrode side into the drift layer can be recombined. Further, it is also known that by irradiating a lifetime killer such as a proton instead of the recombination promoting layer to form a lifetime killer region, the expansion of stacking defects can be prevented. The irradiation of the lifetime killer is generally performed after forming the metal on the surface side, in the same manner as in the case of a semiconductor device (Si semiconductor device) using silicon (Si) as a semiconductor material.

[0005] Patent Document 1 discloses injecting a proton or the like as a lifetime killer near the interface between an SiC semiconductor substrate and an n-type boundary layer. Patent Document 2 discloses injecting a proton or the like inside a p-type epitaxial layer on an n-type drift layer to form a lifetime killer region.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0007] When forming a recombination promoting layer, since the recombination promoting layer is required to have a thickness of about 10 μm, the manufacturing cost increases. On the other hand, when forming a lifetime killer region, in the case of an Si semiconductor device, the lifetime killer generally affects minority carriers but hardly affects majority carriers and hardly affects the on-resistance of a MOSFET. However, in an SiC semiconductor device, the lifetime killer also affects majority carriers, and particularly when irradiating the lifetime killer in the drift layer, the on-resistance of the MOSFET increases.

[0008] In addition, in a Si semiconductor device, in order to reduce the influence on the gate insulating film, a lifetime killer is irradiated from the back side of the Si substrate to a depth that does not affect the gate insulating film. On the other hand, in a SiC semiconductor device, since the thickness of the SiC substrate is thicker than that of the Si substrate, the thickness varies, and the thickness of the drift layer epitaxially grown on the SiC substrate is thinner than the thickness of the drift layer of the Si semiconductor device. Therefore, when irradiating the lifetime killer from the back side of the SiC substrate, the lifetime killer varies and is distributed within the drift layer, resulting in variations in the on-resistance of the MOSFET.

[0009] In view of the above problems, an object of the present invention is to provide a SiC semiconductor device and a method for manufacturing the same that can suppress the conduction degradation of a built-in diode and variations in the on-resistance of active elements.

Means for Solving the Problems

[0010] To achieve the above object, one aspect of the present invention is a SiC semiconductor device including: (a) a first-conductivity-type drift layer provided on the upper surface side of a silicon carbide substrate of a first conductivity type; (b) a second-conductivity-type base region provided on the upper surface side of the drift layer; (c) a first-conductivity-type main region provided in contact with the base region on the upper surface side of the drift layer; (d) an insulated gate type electrode structure provided in contact with the main region and the base region; and (e) a lifetime killer region provided so as to include the lower surface of the drift layer.

[0011] Another aspect of the present invention is a method for manufacturing a SiC semiconductor device, including: (a) a step of epitaxially growing a drift layer of a first conductivity type on the upper surface side of a silicon carbide substrate of the first conductivity type; (b) a step of forming a base region of a second conductivity type on the upper surface side of the drift layer; (c) a step of forming a main region of the first conductivity type on the upper surface side of the drift layer so as to be in contact with the base region; (d) a step of forming a gate insulating film so as to be in contact with the base region and the main region; (e) a step of forming a gate electrode so as to be in contact with the base region and the main region via the gate insulating film; and (f) a step of irradiating a lifetime killer from the upper surface side of the drift layer after the step of epitaxially growing the drift layer and before the step of forming the gate insulating film to form a lifetime killer region at a depth including the lower surface of the drift layer.

Advantages of the Invention

[0012] According to the present invention, it is possible to provide a SiC semiconductor device and a method for manufacturing the same that can suppress the conduction degradation of the built-in diode and the variation in the on-resistance of the active element.

Brief Description of the Drawings

[0013]

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Embodiments for Carrying Out the Invention

[0014] Hereinafter, the first to third embodiments of the present invention will be described with reference to the drawings. In the description of the drawings, the same or similar parts are denoted by the same or similar reference numerals, and duplicate explanations are omitted. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thicknesses of the respective layers, etc. may be different from the actual ones. Also, there may be parts where the dimensional relationships and ratios are different even between the drawings. Further, the first to third embodiments shown below are examples of devices and methods for embodying the technical idea of the present invention, and the technical idea of the present invention does not specify the material, shape, structure, arrangement, etc. of the constituent parts as the following ones.

[0015] In this specification, the source region of a MOS transistor is the "one main region (first main region)" that can be selected as the emitter region of an insulated gate bipolar transistor (IGBT). Also, in a thyristor such as a MOS controlled static induction thyristor (SI thyristor), the "one main region" can be selected as the cathode region. The drain region of a MOS transistor is the "other main region (second main region)" of a semiconductor device that can be selected as the collector region in an IGBT and as the anode region in a thyristor. When simply referred to as the "main region" in this specification, it means either the first main region or the second main region that is reasonable from the common technical knowledge of those skilled in the art.

[0016] Also, the definitions of directions such as up and down in the following description are merely for convenience of explanation and do not limit the technical idea of the present invention. For example, if the object is rotated 90° and observed, up and down are read as left and right, and if it is rotated 180° and observed, up and down are read in reverse, which goes without saying.

[0017] In the following description, the case where the first conductivity type is n-type and the second conductivity type is p-type will be exemplified. However, the conductivity types may be selected in the reverse relationship, i.e., the first conductivity type may be p-type and the second conductivity type may be n-type. Also, the + and - attached to n and p respectively mean that the semiconductor regions have relatively higher or lower impurity concentrations compared to the semiconductor regions without the + and - notations. However, even for semiconductor regions with the same n attached, it does not necessarily mean that the impurity concentrations of the respective semiconductor regions are exactly the same.

[0018] In addition, SiC crystals have crystal polymorphs, and the main ones are cubic 3C, and hexagonal 4H, 6H. The reported values of the bandgap at room temperature are 2.23 eV for 3C-SiC, 3.26 eV for 4H-SiC, and 3.02 eV for 6H-SiC. In the following description, the case of using 4H-SiC will be exemplified.

[0019] (First Embodiment) <Structure of SiC Semiconductor Device> The SiC semiconductor device according to the first embodiment is manufactured using a SiC semiconductor substrate (substrate) 100 as shown in FIG. 1. The substrate 100 consists of a plurality of chip regions 101 and dicing lines 102. For example, the chip region 101 has a rectangular planar shape and is provided on the substrate 100 in a matrix. The dicing lines 102 are provided in a grid pattern so as to surround each of the chip regions 101.

[0020] As shown in FIG. 2, the chip region 101 is provided with an active region 101a containing active elements and a termination region (outer peripheral portion) 101b provided around the active region 101a and having a breakdown voltage structure. In FIG. 2, in the active region 101a, it includes a MOSFET with a trench gate structure provided on top of a drift layer 2 of the first conductivity type (n-type), and in the termination region 101b, it exemplifies the case of including electric field relaxation regions 20a, 20b as the breakdown voltage structure. - type) and includes a MOSFET with a trench gate structure provided on the upper part of the drift layer 2, and in the termination region 101b, it exemplifies the case of including electric field relaxation regions 20a, 20b as the breakdown voltage structure.

[0021] The drift layer 2 is composed of an epitaxial growth layer made of SiC. The impurity concentration of the drift layer 2 is, for example, 1×10 15 cm -3 or more and 2×10 16 cm -3 or less, and the thickness is 1 μm or more and several 100 μm or less. The impurity concentration and thickness of the drift layer 2 can be appropriately adjusted according to the breakdown voltage specifications of the built-in diode described later.

[0022] On the upper surface of the drift layer 2, a base region 6 of the second conductivity type (p-type) is provided. The base region 6 is composed of an epitaxial growth layer made of SiC. The impurity concentration of the base region 6 is, for example, 1×10 17 cm -3 or more and 1×10 18 cm -3 or less.

[0023] On the upper part of the base region 6, a p + -type base contact region 8 with a higher impurity concentration than the base region 6 is selectively provided. The impurity concentration of the base contact region 8 is, for example, 5×10 18 cm -3 or more and 5×10 20 cm -3 or less.

[0024] On the upper part of the base region 6, an n + -type first main region (source region) 7 with a higher impurity concentration than the drift layer 2 is selectively provided so as to be in contact with the base contact region 8. The impurity concentration of the source region 7 is, for example, 5×10 18 cm -3 or more and 5×10 20 cm -3 or less.

[0025] A trench 9a is provided penetrating through the base region 6 from the upper surfaces of the source region 7 and the base region 6. The width of the trench 9a is, for example, about 1 μm or less. The source region 7 and the base region 6 are in contact with the side surfaces of the trench 9a. A gate insulating film 11 is provided on the bottom surface and the side surfaces of the trench 9a. A gate electrode 12a is embedded in the trench 9a via the gate insulating film 11. The gate insulating film 11 and the gate electrode 12a constitute an insulated gate type electrode structure (11, 12a).

[0026] As the gate insulating film 11, in addition to a silicon dioxide film (SiO2 film), a silicon oxynitride (SiON) film, a strontium oxide (SrO) film, a silicon nitride (Si3N4) film, an aluminum oxide (Al2O3) film, a magnesium oxide (MgO) film, a yttrium oxide (Y2O3) film, a hafnium oxide (HfO2) film, a zirconium oxide (ZrO2) film, a tantalum oxide (Ta2O5) film, a bismuth oxide (Bi2O3) film, any one of single-layer films or a composite film formed by laminating a plurality of these can be adopted. As the material of the gate electrode 12a, for example, a polysilicon layer (doped polysilicon layer) with impurities such as phosphorus (P) and boron (B) added at a high impurity concentration can be used.

[0027] On the upper part of the drift layer 2, an n-type current spreading layer (CSL) 3 with a higher impurity concentration than that of the drift layer 2 is selectively provided. The upper surface of the current spreading layer 3 is in contact with the lower surface of the base region 6. The impurity concentration of the current spreading layer 3 is, for example, 5×10 16 cm -3 or more and 5×10 17 cm -3 or less. The bottom of the trench 9a reaches the current spreading layer 3. Note that the current spreading layer 3 does not necessarily have to be provided. When the current spreading layer 3 is not provided, the bottom of the trench 9a reaches the drift layer 2.

[0028] Inside the current spreading layer 3, a p + -type gate bottom protection region 4b is provided in contact with the bottom of the trench 9a. The impurity concentration of the gate bottom protection region 4b is, for example, 1×10 17 cm-3 The above is at a level of 1×10 19 cm -3 or less.

[0029] Inside the current diffusion layer 3, below the base contact region 8, at a depth approximately the same as that of the gate bottom protection region 4b and spaced apart from the gate bottom protection region 4b, a p + -type first buried region 4a is provided. Above the current diffusion layer 3, a p + -type second buried region 5a is provided so as to contact the upper surface of the first buried region 4a and the lower surface of the base region 6. The second buried region 5a is also provided below the base contact region 8. The first buried region 4a and the second buried region 5a constitute a base bottom buried region (4a, 5a). Selectively in the depth direction of the trench 9a shown in FIG. 2, a p + -type connection portion 4d that connects the first buried region 4a and the gate bottom protection region 4b is provided. The impurity concentrations of the first buried region 4a, the second buried region 5a, and the connection portion 4d are, for example, 1×10 17 cm -3 or more and 1×10 19 cm -3 or less.

[0030] An interlayer insulating film 13 is provided on the upper surface of the gate electrode 12a. As the interlayer insulating film 13, a silicon oxide film (BPSG) doped with boron (B) and phosphorus (P) is used. As the interlayer insulating film 13, a silicon oxide film doped with phosphorus (PSG) (PSG), a non-doped SiO2 film called "NSG" that does not contain phosphorus (P) or boron (B), a silicon oxide film doped with boron (B) (BSG), an Si3N4 film, etc. may also be used. Also, a laminated film of these may be used.

[0031] A source contact layer 14 is provided on the source region 7 and the base contact region 8 exposed between the interlayer insulating films 13. A barrier metal layer 15a is provided so as to cover the interlayer insulating film 13 and the source contact layer 14. The first main electrode (source electrode) 16a is electrically connected to the source region 7 and the base contact region 8 through the barrier metal layer 15a and the source contact layer 14. For example, the source contact layer 14 can be a nickel silicide (NiSi x ) film, the barrier metal layer 15a can be a titanium nitride (TiN) film or a titanium (Ti) film, and the source electrode 16a can be made of an aluminum (Al) film or an aluminum-silicon (Al-Si) film. The source electrode 16a is provided separately from a gate surface electrode (not shown) that is electrically connected to the gate electrode 12a.

[0032] Below the drift layer 2, an n-type buffer layer (dislocation conversion layer) 22 having a higher impurity concentration than the drift layer 2 is provided. The dislocation conversion layer 22 has a function of converting basal plane dislocations that are the starting points of the expansion of stacking defects into through dislocations that do not expand into stacking defects. The impurity concentration of the dislocation conversion layer 22 is, for example, 5×10 17 cm -3 or more and 1×10 18 cm -3 or less, and the thickness is, for example, about 0.5 μm or more and 1 μm or less. A lifetime killer region 23 is provided between the drift layer 2 and the dislocation conversion layer 22. The lifetime killer region 23 will be described later.

[0033] On the lower surface of the dislocation conversion layer 22, an n + -type second main region (drain region) 1 having a higher impurity concentration than the dislocation conversion layer 22 is provided. The drain region 1 is composed of a SiC semiconductor substrate (substrate). The impurity concentration of the drain region 1 is, for example, 1×10 18 cm -3 or more and 1×10 19 cm -3 or less.

[0034] On the lower surface of the drain region 1, a second main electrode (drain electrode) 17 is provided. As the drain electrode 17, for example, a single-layer film made of gold (Au) or a metal film laminated in the order of Ti, nickel (Ni), and Au can be used. Further, a metal film such as molybdenum (Mo) or tungsten (W) may be laminated on the lowermost layer thereof. Also, a drain contact layer such as a nickel silicide (NiSi x ) film may be provided between the drain region 1 and the drain electrode 17.

[0035] On the terminal region 101b side of the active region 101a, a base contact region 8a is provided on the upper part of the base region 6. On the upper surface of the base contact region 8a, a wiring layer 12b is provided via a field oxide film 10. On the upper surface of the wiring layer 12b, a gate electrode pad 16b is provided via a barrier metal layer 15b. Although not shown, the gate electrode pad 16b is electrically connected to the gate electrode 12a via the wiring layer 12b. The interlayer insulating film 13 and the field oxide film 10 extend to the terminal region 101b side.

[0036] On the terminal region 101b side of the active region 101a, a base bottom embedded region (4c, 5b) composed of a first embedded region 4c and a second embedded region 5b extends so as to be in contact with the lower surface of the base region 6. The first embedded region 4c is provided so as to be in contact with the upper surface of the drift layer 2. The second embedded region 5b is provided so as to be in contact with the upper surface of the first embedded region 4c and the lower surface of the base region 6.

[0037] In the terminal region 101b, a mesa groove (recess) 9b is provided that penetrates the base region 6 from the upper surface of the base region 6 and reaches the first embedded region 4c. The width of the mesa groove 9b in one chip region 101 is, for example, about 5 μm or more and 200 μm or less.

[0038] In the terminal region 101b, electric field relaxation regions 20a and 20b are provided as a terminal structure so as to be exposed on the bottom surface of the mesa groove 9b. Each of the electric field relaxation regions 20a and 20b is, for example, a junction terminal extension (JTE) structure, and a plurality of p-type spatially modulated portions are provided. Each of the electric field relaxation regions 20a and 20b is not limited to the JTE structure, and a plurality of p-type guard rings may be provided in a concentric ring shape. At the outer end of the terminal region 101b, an n + -type or p + -type channel stopper may be provided in a concentric ring shape.

[0039] During the operation of the SiC semiconductor device according to the first embodiment, when a positive voltage is applied to the drain electrode 17 with the source electrode 16a at the ground potential and a positive voltage equal to or higher than the threshold value is applied to the gate electrode 12a, an inversion layer (channel) is formed on the side surface of the trench 9a in the base region 6, and the device is turned on. The inversion layer is formed on the surface of the base region 6 exposed on the side surface of the trench 9a, which is the interface between the gate insulating film 11 and the base region 6, with the base region 6 being sandwiched between the positions facing the gate electrode 12a. In the on state, current flows from the drain electrode 17 through the drain region 1, the dislocation conversion layer 22, the drift layer 2, the current diffusion layer 3, the inversion layer in the base region 6, and the source region 7 to the source electrode 16a. On the other hand, when the voltage applied to the gate electrode 12a is less than the threshold value, no inversion layer is formed in the base region 6, so the device is turned off and no current flows from the drain electrode 17 to the source electrode 16a.

[0040] FIG. 3 is an enlarged view of part B of the semiconductor device shown in FIG. 2. As shown in FIGS. 2 and 3, since the p-type base region 6 is formed on the upper part of the n - -type drift layer 2, a built-in diode (body diode) of the pn junction is formed. That is, the p + -type base contact region 8, the p-type base region 6, and the p + -type base bottom buried regions (4a, 5a) function as the anode region of the built-in diode, and the n + -type drain region 1 functions as the cathode region of the built-in diode. The n-type current diffusion layer 3 and the n -The drift layer 2 of the [type] functions as a traveling region where a large number of carriers (electrons) supplied from the drain region 1 drift and travel. Minority carriers (holes) are injected into the drift layer 2 from the base contact region 8 side through the base region 6.

[0041] The holes injected into the drift layer 2 can reach the drain region 1 through the dislocation conversion layer 22 at a sufficiently high density. Starting from the basal plane dislocations localized near the interface between the dislocation conversion layer 22 and the drain region 1, stacking defects will expand within the drift layer 2. Since the stacking defects become high-resistance regions, the current will flow through the regions without stacking defects. As a result, in the built-in diode, it causes deterioration of forward characteristics such as an increase in the forward voltage (on-voltage) and on-resistance.

[0042] Therefore, in the SiC semiconductor device according to the first embodiment, as shown in FIGS. 2 and 3, a lifetime killer region 23 is provided between the drift layer 2 and the dislocation conversion layer 22. The lifetime killer region 23 is provided so as to include the lower surface of the drift layer 2, that is, the interface between the drift layer 2 and the dislocation conversion layer 22. The lifetime killer region 23 has crystal defects as recombination centers for recombining minority carrier holes, and is a region where the lifetime of minority carrier holes is shorter than that of the drift layer 2. The crystal defects consist of point defects formed by ion-implanted protons (hydrogen) or helium. The surface density of hydrogen or helium is, for example, 5×10 10 cm -2 or more and 2×10 12 cm -2 or less. The thickness of the lifetime killer region 23 is, for example, about 0.2 μm or more and 5 μm or less.

[0043] Here, referring to FIG. 4, the formation position of the lifetime killer region 23 in the depth direction will be described. The left side of FIG. 4 schematically shows the positional relationship in the depth direction of the substrate 1s, the dislocation conversion layer 22, and the drift layer 2, which will become the drain region 1 before forming the lifetime killer region 23. As shown on the left side of FIG. 4, the lower surface of the dislocation conversion layer 22 is in contact with the upper surface of the substrate 1s, and the upper surface of the dislocation conversion layer 22 is in contact with the lower surface of the drift layer 2.

[0044] The right side of FIG. 4 schematically shows the concentration profile of point defects formed by hydrogen or helium that constitutes the lifetime killer region 23 in the depth direction corresponding to the left side of FIG. 4. When a dislocation conversion layer 22 is provided between the substrate 1s and the drift layer 2 as shown on the left side of FIG. 4, as shown on the right side of FIG. 4, the peak position in the depth direction of the concentration of point defects formed by hydrogen or helium is preferably at a position within the dislocation conversion layer 22 that is deeper than the interface between the dislocation conversion layer 22 and the drift layer 2. By adjusting to this position, it is possible to suppress hydrogen or helium from affecting the gate insulating film 11 while sufficiently maintaining the function of the lifetime killer region 23 to recombine holes.

[0045] The dashed line on the right side of FIG. 4 indicates the maximum allowable deviation width of the peak position in the depth direction of the concentration of point defects formed by hydrogen or helium that constitutes the lifetime killer region 23. That is, the peak position in the depth direction of the concentration of point defects formed by hydrogen or helium may be formed within the range from a position in the drift layer 2 that is shallower than the half-width at half-maximum (FWHM) a of the concentration of point defects formed by hydrogen or helium with respect to the interface between the dislocation conversion layer 22 and the drift layer 2 to a position in the substrate 1s that is 5 times the half-width a deeper with respect to the interface between the dislocation conversion layer 22 and the drift layer 2. The half-width a can be appropriately adjusted, for example, by adjusting the thickness of the shielding layer used when irradiating with hydrogen or helium and the acceleration voltage of hydrogen or helium.

[0046] <Method for manufacturing a semiconductor device> Next, with reference to FIGS. 5 to 15, an example of a method for manufacturing a SiC semiconductor device according to the first embodiment will be described. Note that the method for manufacturing a SiC semiconductor device described below is an example, and it goes without saying that it can be realized by various other manufacturing methods including this modification example as long as it is within the scope of the gist described in the claims.

[0047] First, an n-type impurity such as nitrogen (N) is added to the n +Prepare a SiC semiconductor substrate (substrate) 1s of a certain type. Then, as shown in FIG. 5, on the upper surface of the substrate 1s, an n-type impurity such as N is added, and a buffer layer (dislocation conversion layer) 22 made of n-type SiC with an impurity concentration lower than that of the substrate 1s is epitaxially grown. Further, on the upper surface of the dislocation conversion layer 22, an n-type impurity such as N is added, and an n - type drift layer 2 made of SiC is epitaxially grown.

[0048] Next, as shown in FIG. 6, from the upper surface side of the drift layer 2, protons (hydrogen (H) ions) or helium (He) ions are irradiated over the entire area of the upper surface of the drift layer 2. In FIG. 6, the irradiation of protons or helium ions is schematically shown by arrows. The dose of protons or helium ions is, for example, 1×10 10 cm -2 or more and 2×10 12 cm -2 or less, and the acceleration voltage is, for example, 0.1 MeV or more and 25 MeV or less. In the case of irradiation at low acceleration, multi-stage ion implantation is performed, and in the case of a high acceleration voltage, implantation is performed in one stage to adjust the depth direction distribution of the irradiated ions. When performing multi-stage implantation at low acceleration, the position of point defects can be accurately controlled. When performing one-stage implantation at high acceleration, the irradiation time can be shortened. As a result, a lifetime killer region 23 is uniformly and flatly formed so as to include the interface between the dislocation conversion layer 22 and the drift layer 2. The thickness of the drift layer 2 in the SiC semiconductor device is, for example, about 10 μm, which is thinner than the drift layer of about 100 μm in the Si semiconductor device. Therefore, protons or helium ions can be accurately irradiated from the upper surface side of the drift layer 2 to the interface between the dislocation conversion layer 22 and the drift layer 2.

[0049] Next, a photoresist film 130 (see FIG. 7) is applied onto the upper surface of the drift layer 2, and the photoresist film 130 is patterned using photolithography technology or the like. Using the patterned photoresist film 130 as a mask for ion implantation, n-type impurity ions such as nitrogen (N) are selectively implanted into the active region 101a of the drift layer 2 in multiple stages from the upper surface side of the drift layer 2. As a result, as shown in FIG. 7, an n-ion implantation layer 3p is formed on the upper part of the drift layer 2 in the active region 101a. Thereafter, the photoresist film 130 is removed.

[0050] Next, an oxide film 140 (see FIG. 8) is deposited on the upper surfaces of the n-ion implantation layer 3p and the drift layer 2 by chemical vapor deposition (CVD) technology or the like. A photoresist film is applied onto the upper surface of the oxide film 140, and the oxide film 140 is patterned using photolithography technology and dry etching technology or the like. Using the patterned oxide film 140 as a mask for ion implantation, p-type impurity ions such as aluminum (Al) are implanted into the n-ion implantation layer 3p in multiple stages. As a result, as shown in FIG. 8, p + -type first embedded regions 4a, 4c and p + -type gate bottom protection region 4b are selectively formed. Although not shown in FIG. 8, the connection portion 4d shown in FIG. 2 is also formed simultaneously. Thereafter, the oxide film 140 is removed.

[0051] Next, an epitaxial growth layer 5e (see FIG. 9) made of n-type SiC is grown on the upper surfaces of the first embedded regions 4a, 4c, the gate bottom protection region 4b, and the drift layer 2. A photoresist film is applied onto the upper surface of the epitaxial growth layer 5e, and the photoresist film is patterned using photolithography technology or the like. Using the patterned photoresist film as a mask for ion implantation, n-type impurity ions such as nitrogen (N) are selectively implanted into the upper part of the epitaxial growth layer 5e in the active region 101a in multiple stages from the upper surface side of the epitaxial growth layer 5e to form an n-ion implantation layer 5p (see FIG. 9). Thereafter, the photoresist film used as a mask for ion implantation is removed.

[0052] Next, an oxide film 150 (see FIG. 9) is deposited on the upper surfaces of the n-ion implantation layer 5p and the epitaxial growth layer 5e by means of CVD technology or the like. A photoresist film is applied to the upper surface of the oxide film 150, and the oxide film 150 is patterned using photolithography technology, dry etching technology, or the like. Using the patterned oxide film 150 as a mask for ion implantation, p-type impurity ions such as aluminum (Al) are selectively implanted into the n-ion implantation layer 5p in multiple stages. As a result, as shown in FIG. 9, second implanted regions 5a and 5b are selectively formed at positions corresponding to the first implanted regions 4a and 4c of the n-ion implantation layer 5p. Thereafter, the oxide film 150 is removed.

[0053] Next, a p-type epitaxial growth layer 6p (see FIG. 10) is epitaxially grown on the upper surfaces of the second implanted regions 5a and 5b, the n-ion implantation layer 5p, and the epitaxial growth layer 5e. An oxide film is deposited on the surface of the grown epitaxial growth layer 6p by means of CVD technology or the like. A photoresist film is applied to the upper surface of the oxide film, and the oxide film is patterned using photolithography technology, dry etching technology, or the like. Using the patterned oxide film as an etching mask, the epitaxial growth layer 6p, a part of the second implanted region 5b, and the epitaxial growth layer 5e are selectively etched in the termination region 101b by means of dry etching technology or the like. Thereafter, the oxide film used as the etching mask is removed.

[0054] As a result, as shown in FIG. 10, a mesa groove (recess) 9b is formed in the termination region 101b. The end portion of the first implanted region 4c and the upper surface of the drift layer 2 are exposed on the bottom surface of the mesa groove 9b. On the other hand, the epitaxial growth layer 6p, the second implanted region 5a, the n-ion implantation layer 5p, and the second implanted region 5b remain in the active region 101a.

[0055] Next, an oxide film is deposited on the upper surface of the epitaxial growth layer 6p and the bottom surface of the mesa groove 9b by means of CVD technology or the like. A photoresist film is applied to the upper surface of the oxide film, and the oxide film is patterned using photolithography technology, dry etching technology, or the like. Using the patterned oxide film as a mask for ion implantation, n-type impurity ions such as phosphorus (P) are multi-step ion implanted into the epitaxial growth layer 6p from the upper surface side of the epitaxial growth layer 6p. As a result, an n-ion implantation layer is formed on the upper part of the epitaxial growth layer 6p in the active region 101a.

[0056] After removing the oxide film used as a mask for ion implantation, an oxide film is deposited on the upper surface of the n-ion implantation layer and the bottom surface of the mesa groove 9b by means of CVD technology or the like. A photoresist film is applied to the upper surface of this oxide film, and the oxide film is patterned using photolithography technology, dry etching technology, or the like. Using the patterned oxide film as a mask for ion implantation, p-type impurity ions such as aluminum (Al) are selectively multi-step ion implanted into the n-ion implantation layer from the upper surface side of the n-ion implantation layer. Then, the oxide film used as a mask for ion implantation is removed. Here, the region into which the p-type impurity ions are implanted becomes the base contact region 8 and the base contact region 8a, and the n-ion implantation layer remaining without the p-type impurity ions being implanted becomes the source region 7.

[0057] Next, a photoresist film is applied to the upper surfaces of the source region 7, the base contact region 8, the base contact region 8a, and the bottom surface of the mesa groove 9b, and the photoresist film is patterned using photolithography technology or the like. Using the patterned photoresist film as a mask for ion implantation, p-type impurity ions such as aluminum (Al) are selectively multi-step ion implanted into the bottom surface of the mesa groove 9b from the upper surface side of the mesa groove 9b. Then, the photoresist film used as a mask for ion implantation is removed. As a result, as shown in FIG. 11, the source region 7 and the base contact regions 8 and 8a are formed on the upper part of the base region 6. Further, the electric field relaxation regions 20a and 20b are formed as a termination structure so as to be exposed on the bottom surface of the mesa groove 9b.

[0058] Next, in the state shown in FIG. 11, by performing activation annealing (heat treatment), the p-type impurity ions or n-type impurity ions ion-implanted into the first implanted regions 4a and 4c, the gate bottom protection region 4b, the second implanted regions 5a and 5b, the source region 7, the base contact regions 8 and 8a, the electric field relaxation regions 20a and 20b, etc. are simultaneously activated. The temperature of the activation annealing is, for example, about 1600° C. or higher and 1800° C. or lower, which is the highest temperature in the manufacturing method of the SiC semiconductor device according to the first embodiment. Here, the case where activation annealing is performed once collectively after all the ion implantation steps is exemplified, but multiple activation annealings may be performed individually after each ion implantation step.

[0059] Even after the activation annealing, the defects constituting the lifetime killer region 23 are not sufficiently recovered, and the lifetime killer region 23 is maintained. That is, SiC has a larger bandgap than Si, and levels are formed by irradiation with protons or helium ions. Therefore, focusing on the principle that the levels formed in the forbidden band do not recover at a temperature of about 1600° C. or higher and 1800° C. or lower during activation annealing, this is utilized.

[0060] Next, an oxide film is deposited on the upper surfaces of the source region 7, the base contact regions 8 and 8a, and the bottom surface of the mesa groove 9b by CVD technology or the like. A photoresist film is applied on the upper surface of the oxide film, and the oxide film is patterned using photolithography technology, dry etching technology, etc. Using the patterned oxide film as an etching mask, a part of the source region 7, the base region 6, and the n-ion implantation layer 5p is selectively removed by dry etching technology. Then, the oxide film is removed. As a result, as shown in FIG. 12, a trench 9a that penetrates the source region 7 and the base region 6 and reaches the gate bottom protection region 4b is selectively formed. Also, an n-type current diffusion layer 3 composed of the n-ion implantation layer 3p and the n-ion implantation layer 5p is formed on the upper surface of the drift layer 2.

[0061] Next, an oxide film is deposited by a CVD technique or the like. A photoresist film is applied onto the upper surface of the oxide film, and the photoresist film is patterned using a photolithography technique or the like. Using the patterned photoresist film as an etching mask, the oxide film is selectively removed to form a field oxide film 10 (see FIG. 13) so as to extend from the bottom surface of the mesa groove 9b to the upper surface of the base contact region 8a.

[0062] Next, a gate insulating film 11 (see FIG. 13) such as an SiO2 film is formed on the bottom surface and side surfaces of the trench 9a, and the upper surfaces of the source region 7 and the base contact region 8 by a thermal oxidation method or a chemical vapor deposition (CVD) technique or the like. The temperature at the time of forming the gate insulating film 11 is, for example, about 1300 ° C, which is the second highest temperature at the time of activation annealing. Next, a polysilicon layer (doped polysilicon layer) doped with a high concentration of impurities such as phosphorus (P) or boron (B) is deposited by a CVD technique or the like so as to fill the trench 9a. Thereafter, a part of the polysilicon layer and a part of the gate insulating film are selectively removed by a photolithography technique and dry etching. As a result, as shown in FIG. 13, an insulated gate type electrode structure (11, 12a) composed of the gate insulating film 11 and the gate electrode 12a of the polysilicon layer is formed. Also, in the vicinity of the mesa groove 9b, a wiring layer 12b electrically connected to the gate electrode 12a is formed on the upper surface of the field oxide film 10.

[0063] Next, an interlayer insulating film 13 (see FIG. 14) is deposited on the upper surface of the insulated gate type electrode structure (11, 12a) by a CVD technique or the like. A part of the interlayer insulating film 13 is selectively removed by a photolithography technique, a dry etching technique, or the like to open a source electrode contact hole, a gate electrode pad contact hole, and a gate contact hole.

[0064] Next, a metal layer such as a Ni film is deposited by a sputtering method, an evaporation method, or the like, and the metal layer is patterned using photolithography technology, RIE technology, or the like. Thereafter, by performing a rapid thermal treatment (RTA), for example, heat treatment at about 1000 ° C., a source contact layer 14 (see FIG. 14) is formed on the upper surfaces of the source region 7 and the base contact region 8. Next, a metal layer such as a TiN film is deposited by a sputtering technique or the like, and the metal layer is patterned using photolithography technology, RIE technology, or the like, so that a barrier metal layer 15a (see FIG. 14) is formed so as to cover the interlayer insulating film 13, and a barrier metal layer 15b (see FIG. 14) is formed on the upper surface of the wiring layer 12b exposed from the interlayer insulating film 13.

[0065] Next, a metal layer such as an Al film is deposited by a sputtering method or the like. The metal layer such as the Al film is patterned using photolithography technology, RIE technology, or the like. As a result, as shown in FIG. 14, patterns of the source electrode 16a, the gate electrode pad 16b, and the gate surface electrode (not shown) are formed.

[0066] Next, an adhesive 200 is applied to the upper surface side of the substrate 1s on which the element structure is formed and bonded to a glass plate 210. The lower surface of the substrate 1s is polished by chemical mechanical polishing (CMP) or the like to adjust the thickness to 100 μm or less, for example, about 50 μm, whereby a drain region 1 is formed as shown in FIG. 15. Thereafter, the adhesive 200 is removed to separate the element structure from the glass plate 210.

[0067] Next, a drain electrode 17 made of Au or the like is formed on the entire lower surface of the drain region 1 by a sputtering method, an evaporation method, or the like. In this way, the SiC semiconductor device shown in FIG. 2 is completed.

[0068] <Example> Figures 16 and 17 show the measurement results of the lifetime by the microwave detection photoconductance decay (μ-PCD) method for SiC under four conditions of "1750 °C + 1300 °C", "1300 °C", "immediately after irradiation", and "unirradiated". "1750 °C + 1300 °C" is the case where after irradiating SiC with helium (He) ions, it is heated at 1750 °C which is the temperature during activation annealing, and further heated at 1300 °C which is the temperature during the formation of the gate insulating film 11, assuming that He ions are irradiated before activation annealing. "1300 °C" is the case where after irradiating with He ions, it is heated at 1300 °C, assuming that He ions are irradiated after activation annealing and before the formation of the gate insulating film 11. "Immediately after irradiation" is the case where no heat treatment is performed after irradiating with He ions. "Unirradiated" is the case where no He ions are irradiated. The acceleration voltage during the irradiation of He ions under each condition is 23 MeV, and the dose is 1.5×10 11 cm -2 is.

[0069] The horizontal axis of Fig. 16 indicates time, and the vertical axis of Fig. 16 indicates the microwave reflection intensity. Fig. 17 shows the effective lifetime which is the time until the microwave reflection intensity decays to 1 / e. From Figs. 16 and 17, it can be confirmed that the lifetime is the shortest under the condition of "immediately after irradiation", and the lifetime is also sufficiently short under the conditions of "1750 °C + 1300 °C" and "1300 °C".

[0070] <Effect> According to the method for manufacturing a SiC semiconductor device according to the first embodiment, by irradiating protons or helium ions from the upper surface side of the drift layer 2 as lifetime killers, it is possible to accurately irradiate the interface between the dislocation conversion layer 22 and the drift layer 2, and accurately form the lifetime killer region 23. Therefore, the lifetime killer region 23 can efficiently recombine and eliminate holes which are minority carriers, and suppress the expansion of stacking defects. Thus, even when a large current is applied, the conduction degradation of the built-in diode can be suppressed.

[0071] Furthermore, by performing the irradiation process of the lifetime killer shown in FIG. 6 before the formation process of the gate insulating film 11 shown in FIG. 13, it is possible to prevent affecting the gate insulating film 11 as compared with the case of performing it after the formation process of the gate insulating film 11 shown in FIG. 13, and it is possible to suppress variations in the on-resistance of the MOSFET.

[0072] Furthermore, the irradiation process of the lifetime killer shown in FIG. 6 is performed immediately after the growth process of the drift layer 2 shown in FIG. 5 and before the ion implantation process for forming the n-ion implantation layer 3p in the drift layer 2 shown in FIG. 7. Thereby, as compared with the case of performing it after the ion implantation process for forming the n-ion implantation layer 3p in the drift layer 2 shown in FIG. 7, it is possible to suppress affecting the interaction with defects generated by ion implantation and the variation in the concentration of ion implantation in the ion implantation process for forming the n-ion implantation layer 3p in the drift layer 2 shown in FIG. 7.

[0073] Furthermore, by performing the irradiation process of the lifetime killer shown in FIG. 6 before the formation process of the mesa groove 9b of the termination region 101b shown in FIG. 10, as compared with the case of performing it after the formation process of the mesa groove 9b of the termination region 101b shown in FIG. 10, the lifetime killer region 23 can be formed flat with a uniform depth in the entire regions of the active region 101a and the termination region 101b, so that a more accurate deterioration suppression effect can be expected.

[0074] Furthermore, by performing the irradiation process of the lifetime killer shown in FIG. 6 before the formation process of the trench 9a shown in FIG. 12, as compared with the case of performing it after the formation process of the trench 9a shown in FIG. 12, the lifetime killer region 23 in the active region 101a can be accurately formed flat without being affected by the unevenness due to the trench 9a.

[0075] <Modification Example of the First Embodiment> In the method for manufacturing a SiC semiconductor device according to the first embodiment, the case where the irradiation step of the lifetime killer shown in FIG. 6 is performed immediately after the growth step of the drift layer 2 shown in FIG. 5 was exemplified. However, the irradiation step of the lifetime killer shown in FIG. 6 may be performed at any stage after the growth step of the drift layer 2 shown in FIG. 5 and before the formation step of the gate insulating film 11 shown in FIG. 13.

[0076] For example, the irradiation step of the lifetime killer shown in FIG. 6 may be performed after the growth step of the epitaxial growth layer 5e shown in FIG. 9 and before the growth step of the epitaxial growth layer 6p shown in FIG. 10. When the irradiation step of the lifetime killer shown in FIG. 6 is performed before the growth step of the epitaxial growth layer 5e shown in FIG. 9, during the growth of the epitaxial growth layer 5e shown in FIG. 9, since a thermal history is introduced while supplying an element that recovers defects, the amount of defect recovery increases, and the recovery amount is affected by variations in the growth conditions. On the other hand, by performing the irradiation step of the lifetime killer shown in FIG. 6 after the growth step of the epitaxial growth layer 5e shown in FIG. 9, the amount of defect recovery due to the growth step of the epitaxial growth layer 5e shown in FIG. 9 can be reduced, and the influence of variations in the growth conditions of the recovery amount can be excluded.

[0077] Also, the irradiation step of the lifetime killer shown in FIG. 6 may be performed after the growth step of the epitaxial growth layer 6p shown in FIG. 10. Thereby, compared with the case of performing it before the growth step of the epitaxial growth layer 6p shown in FIG. 10, the amount of defect recovery due to the growth steps of the epitaxial growth layer 5e shown in FIG. 9 and the epitaxial growth layer 6p shown in FIG. 10 can be reduced, and the influence of variations in the growth conditions of the recovery amount can be excluded.

[0078] Also, the irradiation process of the lifetime killer shown in FIG. 6 may be performed before the mesa groove 9b forming process of the terminal region 101b shown in FIG. 10. As a result, compared with the case of performing after the mesa groove 9b forming process of the terminal region 101b shown in FIG. 10, the lifetime killer region 23 can be formed flat with a uniform depth in the entire regions of the active region 101a and the terminal region 101b, so that a more accurate deterioration suppression effect can be expected.

[0079] Also, the irradiation process of the lifetime killer shown in FIG. 6 may be performed after the ion implantation process for forming the source region 7 and the base contact regions 8, 8a shown in FIG. 11 and before the activation annealing process after the ion implantation process. As a result, compared with the case of performing before the ion implantation process for forming the source region 7 and the base contact regions 8, 8a shown in FIG. 11, the possibility of defects flowing due to photolithography technology or ion implantation in the ion implantation process shown in FIG. 11 can be excluded by the warpage generated during the irradiation of the lifetime killer. Further, compared with the case of performing after the activation annealing process after the ion implantation process shown in FIG. 11, since the stress is relaxed by the activation annealing, the influence of the warpage generated during the irradiation of the lifetime killer can be reduced.

[0080] Also, the irradiation process of the lifetime killer shown in FIG. 6 may be performed before the trench 9a forming process shown in FIG. 12. As a result, compared with the case of performing after the trench 9a forming process shown in FIG. 12, the lifetime killer region 23 in the active region 101a can be accurately formed flat without being affected by the unevenness due to the trench 9a.

[0081] Also, the irradiation process of the lifetime killer shown in FIG. 6 may be performed after the trench 9a forming process shown in FIG. 12 and before the gate insulating film 11 forming process shown in FIG. 13. As a result, compared with the case of performing after the gate insulating film 11 forming process shown in FIG. 13, it is possible to prevent the gate insulating film 11 from being affected and to prevent the gate threshold voltage from fluctuating.

[0082] (Second Embodiment) As shown in FIG. 18, the SiC semiconductor device according to the second embodiment is different from the SiC semiconductor device according to the first embodiment shown in FIG. 2 in that the lifetime killer regions 23a and 23b are not uniformly flat from the active region 101a to the termination region 101b. The lifetime killer region 23a in the active region 101a is provided flat and uniformly at the same depth as the lifetime killer region 23 shown in FIG. 2.

[0083] On the other hand, the lifetime killer region 23b in the termination region 101b is provided flat and uniformly at a position deeper than the lifetime killer region 23a in the active region 101a. For example, the lifetime killer region 23b in the termination region 101b is provided inside the drain region 1. Since the other configurations of the SiC semiconductor device according to the second embodiment are substantially the same as those of the SiC semiconductor device according to the first embodiment shown in FIG. 2, duplicate descriptions are omitted.

[0084] As a method for manufacturing the SiC semiconductor device according to the second embodiment, after the step of forming the mesa groove 9b in the termination region 101b shown in FIG. 10 and before the step of forming the gate insulating film 11 shown in FIG. 13 in the method for manufacturing the SiC semiconductor device according to the first embodiment, protons or helium ions are irradiated as lifetime killers from the upper surface side of the drift layer 2 to form the lifetime killer regions 23a and 23b.

[0085] For example, as shown in FIG. 19, immediately after the formation step of the mesa groove 9b in the terminal region 101b and before the ion implantation step for forming the source region 7, base contact regions 8, 8a, and field relaxation regions 20a, 20b shown in FIG. 11, protons or helium ions may be irradiated as lifetime killers from the upper surface side of the drift layer 2. At this time, the mesa groove 9b is formed in the terminal region 101b, and the bottom of the mesa groove 9b is at a position lower than the upper surface of the active region 101a. Therefore, corresponding to the shape of the mesa groove 9b, the lifetime killer region 23b in the terminal region 101b is formed at a deeper position than the lifetime killer region 23a in the active region 101a.

[0086] As shown in FIG. 20, after the ion implantation step for forming the source region 7, base contact regions 8, 8a, and field relaxation regions 20a, 20b, or after the subsequent activation annealing, protons or helium ions may be irradiated as lifetime killers from the upper surface side of the drift layer 2. Also in this case, the lifetime killer region 23b in the terminal region 101b is formed at a deeper position than the lifetime killer region 23a in the active region 101a. Other procedures of the manufacturing method of the SiC semiconductor device according to the second embodiment are substantially the same as those of the manufacturing method of the SiC semiconductor device according to the first embodiment, and thus duplicate explanations are omitted.

[0087] According to the SiC semiconductor device and its manufacturing method according to the second embodiment, by accurately forming the lifetime killer region 23a so as to include the interface between the dislocation conversion layer 22 and the drift layer 2 in the active region 101a, similar to the SiC semiconductor device and its manufacturing method according to the first embodiment, it is possible to suppress the conduction degradation of the built-in diode and the variation in the on-resistance of the active element. Also, similar to the case of irradiating after the growth step of the epitaxial growth layer 6p in the first embodiment, it is possible to reduce the amount of defect recovery due to the growth step and exclude the influence of the variation in the growth conditions of the recovery amount.

[0088] (Third Embodiment) As shown in FIG. 21, the SiC semiconductor device according to the third embodiment is different from the SiC semiconductor device according to the first embodiment shown in FIG. 2 in that a dislocation conversion layer 22 is not provided between the drain region 1 and the drift layer 2. A lifetime killer region 23 is provided between the drain region 1 and the drift layer 2. The lifetime killer region 23 is provided so as to include the lower surface of the drift layer 2, that is, the interface between the drift layer 2 and the drain region 1.

[0089] The left side of FIG. 22 schematically shows the positional relationship in the depth direction between the substrate 1s, which becomes the drain region 1 before forming the lifetime killer region 23, and the drift layer 2. As shown on the left side of FIG. 22, the lower surface of the drift layer 2 is in contact with the upper surface of the substrate 1s.

[0090] The right side of FIG. 22 schematically shows the concentration profile of point defects formed by hydrogen or helium constituting the lifetime killer region 23 in the depth direction corresponding to the left side of FIG. 22. When no dislocation conversion layer is provided between the substrate 1s and the drift layer 2 as shown on the left side of FIG. 22, as shown on the right side of FIG. 22, the peak position in the depth direction of the concentration of point defects formed by hydrogen or helium constituting the lifetime killer region 23 is preferably on the upper surface side within the substrate 1s. By forming at this position, it is possible to suppress hydrogen or helium from affecting the gate insulating film 11 while sufficiently maintaining the function of the lifetime killer region 23 to recombine holes.

[0091] The dashed line on the right side of FIG. 22 indicates the maximum allowable deviation width in the depth direction of the peak position of the concentration of point defects formed by hydrogen or helium that constitutes the lifetime killer region 23. The peak position in the depth direction of the concentration of point defects formed by hydrogen or helium that constitutes the lifetime killer region 23 may be within the range from a position in the drift layer 2 that is shallower than the half-value full width a of the concentration of point defects formed by hydrogen or helium with respect to the interface between the substrate 1s and the drift layer 2 to a position in the substrate 1s that is 5 times the half-value full width a deeper with respect to the interface between the substrate 1s and the drift layer 2. Since other configurations of the SiC semiconductor device according to the third embodiment are substantially the same as those of the SiC semiconductor device according to the first embodiment shown in FIG. 2, duplicate descriptions are omitted.

[0092] As a method for manufacturing the SiC semiconductor device according to the third embodiment, in the method for manufacturing the SiC semiconductor device according to the first embodiment, the drift layer 2 is epitaxially grown on the substrate 1s without epitaxially growing the dislocation conversion layer 22 shown in FIG. 5 on the substrate 1s. Then, in the same manner as the method for manufacturing the SiC semiconductor device according to the first embodiment, after the growth process of the drift layer 2 and before the formation process of the gate insulating film 11 shown in FIG. 13, protons or helium ions are irradiated from the upper surface side of the drift layer 2 to form the lifetime killer region 23. Since other procedures of the method for manufacturing the SiC semiconductor device according to the third embodiment are substantially the same as those of the method for manufacturing the SiC semiconductor device according to the first embodiment, duplicate descriptions are omitted.

[0093] According to the SiC semiconductor device and its manufacturing method according to the third embodiment, even when the dislocation conversion layer 22 is not provided between the drain region 1 and the drift layer 2, by accurately forming the lifetime killer region 23 so as to include the interface between the drain region 1 and the drift layer 2, it is possible to suppress the conduction degradation of the built-in diode and the variation in the on-resistance of the active element, similar to the SiC semiconductor device and its manufacturing method according to the first embodiment.

[0094] (Other Embodiments) As described above, the first to third embodiments of the present invention have been described. However, the discussions and drawings that form part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments, examples, and operation techniques will become apparent to those skilled in the art from this disclosure.

[0095] For example, as the SiC semiconductor device according to the first to third embodiments, a trench gate type SiC semiconductor device has been exemplified. However, it is also applicable to a planar gate type SiC semiconductor device. Further, it is also applicable to a semiconductor device made of a wide bandgap semiconductor other than SiC.

[0096] Also, the configurations disclosed in the first to third embodiments can be appropriately combined within a range where no contradiction occurs. Thus, the present invention naturally includes various embodiments and the like not described herein. Therefore, the technical scope of the present invention is defined only by the invention specific matters according to the appropriate claims based on the above description.

Explanation of Reference Numerals

[0097] 1... Drain region 1s, 100... SiC semiconductor substrate (substrate) 2... Drift layer 3... Current diffusion layer 3p... n - ion implantation layer 4a, 4c... First buried region 4b... Gate bottom protection region 4d... Connection part 5a, 5b... Second buried region 5e... Epitaxial growth layer 5p... n - ion implantation layer 6... Base region 6p... Epitaxial growth layer 7... Source region 8, 8a... Base contact region 9a... Trench 9b... Mesa groove (recess) 10... Field oxide film 11... Gate insulating film 12a... Gate electrode 12b... Wiring layer 13…Interlayer insulating film 14…Source contact layer 15a, 15b…Barrier metal layer 16a…Source electrode 16b…Gate electrode pad 17…Drain electrode 20a, 20b…Electric field relaxation region 22…Buffer layer (dislocation conversion layer) 23, 23a, 23b…Lifetime killer region 101…Chip region 101a…Active region 101b…Terminal region (outer periphery) 102…Dicing line 130…Photoresist film 140, 150…Oxide film 200…Adhesive 210…Glass plate

Claims

1. A first conductivity type drift layer provided on the upper surface side of a silicon carbide substrate of the first conductivity type, a second conductivity type base region provided on the upper surface side of the drift layer, a first conductivity type main region provided on the upper surface side of the drift layer in contact with the base region, an insulated gate type electrode structure provided in contact with the main region and the base region, a lifetime killer region provided so as to include the lower surface of the drift layer, comprising: a mesa groove is provided in a termination region provided around an active region where the insulated gate type electrode structure is provided, a silicon carbide semiconductor device, wherein the lifetime killer region in the termination region is provided at a position deeper than the lifetime killer region in the active region.

2. A step of epitaxially growing a first conductivity type drift layer on the upper surface side of a silicon carbide substrate of the first conductivity type, a step of forming a second conductivity type base region on the upper surface side of the drift layer, a step of forming a first conductivity type main region on the upper surface side of the drift layer in contact with the base region, a step of forming a gate insulating film in contact with the base region and the main region, a step of forming a gate electrode in contact with the base region and the main region via the gate insulating film, a step of irradiating a lifetime killer from the upper surface side of the drift layer after the step of epitaxially growing the drift layer and before the step of forming the gate insulating film to form a lifetime killer region at a depth including the lower surface of the drift layer, A method for manufacturing a silicon carbide semiconductor device, comprising:

3. The method for manufacturing a silicon carbide semiconductor device according to claim 2, wherein the lifetime killer is a proton or a helium ion.

4. Further comprising a step of forming a trench penetrating the base region and the main region, The step of forming the lifetime killer region is performed before the step of forming the trench. The method for manufacturing a silicon carbide semiconductor device according to claim 2 or 3, characterized in that:

5. Further comprising an activation anneal for activating impurity ions implanted into the base region and the main region, The step of forming the lifetime killer region is performed before the activation anneal. The method for manufacturing a silicon carbide semiconductor device according to claim 2 or 3, characterized in that:

6. The method for manufacturing a silicon carbide semiconductor device according to claim 2 or 3, wherein the step of forming the lifetime killer region is performed immediately after the step of epitaxially growing the drift layer.

7. The method further includes a step of forming a mesa groove in a termination region provided around an active region provided with the gate electrode, The method for manufacturing a silicon carbide semiconductor device according to claim 2 or 3, wherein the step of forming the lifetime killer region is performed before the step of forming the mesa groove.

8. The method further includes a step of forming a mesa groove in a termination region around an active region where the gate insulating film and the gate electrode are formed, The method for manufacturing a silicon carbide semiconductor device according to claim 2 or 3, wherein the step of forming the lifetime killer region is performed after the step of forming the mesa groove.

9. The method for manufacturing a silicon carbide semiconductor device according to claim 2 or 3, further including a step of forming a buffer layer of a first conductivity type having a higher impurity concentration than the drift layer on the silicon carbide substrate before the step of epitaxially growing the drift layer.

10. The dose amount of the protons or helium ions is 1×10 １０ cm －２ or more and 2×10 １２ cm －２ or less, and the method for manufacturing a silicon carbide semiconductor device according to claim 3 is characterized by this.

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