Semiconductor device

Abstract

Provided is a semiconductor device comprising a semiconductor substrate provided with a drift region of a first conductivity type. The semiconductor substrate has an active part and trench portions provided in the active part in the upper surface of the semiconductor substrate. The active part includes a first region in which trench portions are arrayed at a first trench interval in the array direction and a second region in which trench portions are arrayed at a second trench interval larger than the first trench interval in the array direction. The first region has a second-conductivity type first bottom region extending over the bottoms of at least two of the trench portions, and the second region has a second-conductivity type second bottom region provided at the bottom of one of the trench portions.

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] Conventionally, in a semiconductor device such as an IGBT (Insulated Gate Bipolar Transistor), a configuration in which an impurity region is provided at the bottom of a trench portion is known (see, for example, Patent Documents 1 and 2). [Prior Art Documents] [Patent Documents] [Patent Document 1] Japanese Patent Application Laid-Open No. 2019-91892 [Patent Document 2] Japanese Patent Application Laid-Open No. 2019-110288 Problems to be Solved

[0003] In a semiconductor device such as an IGBT device, it is preferable to reduce the withstand voltage imbalance. General Disclosure

[0004] In order to solve the above problems, in a first aspect of the present invention, there is provided a semiconductor device including a semiconductor substrate provided with a drift region of a first conductivity type. The semiconductor substrate may have an active portion. The semiconductor substrate may have a trench portion. The trench portion may be provided in the active portion on the upper surface of the semiconductor substrate. The active portion may have a first region. In the first region, the trench portions may be arranged at a first trench interval in the arrangement direction. The active portion may have a second region. In the second region, the trench portions may be arranged at a second trench interval that is larger than the first trench interval. The first region may have a first bottom region of a second conductivity type. The first bottom region may be provided across the bottoms of at least two trench portions. The second region may have a second bottom region of a second conductivity type. The second bottom region may be provided at the bottom of one trench portion.

[0005] The second trench interval may be 2 times or more and 4 times or less the first trench interval.

[0006] The second region may include a gate trench portion. The second bottom region may be provided at the bottom of the gate trench portion.

[0007] The semiconductor substrate may have a peripheral well region of the second conductivity type. The peripheral well region may surround the active portion in a top view.

[0008] At least a part of the second region may be sandwiched between two first regions in the arrangement direction.

[0009] The first bottom region provided in one of the two first regions may be electrically connected to the peripheral well region.

[0010] The second region may include at least two trench portions. The second bottom regions may be respectively provided at the bottoms of the two trench portions. The second bottom region may not be provided at the center of the mesa portion sandwiched between the two trench portions.

[0011] A part of the drift region may be provided between two adjacent second bottom regions in the arrangement direction.

[0012] The semiconductor substrate may have an accumulation region of the first conductivity type. A part of the accumulation region may be provided between two adjacent second bottom regions in the arrangement direction.

[0013] The doping concentration of the accumulation region provided in the second region may be lower than the doping concentration of the accumulation region provided in the first region.

[0014] The upper end of the second bottom region and the lower end of the accumulation region may be in contact in the depth direction of the semiconductor substrate.

[0015] The second trench interval may be larger than 1.6 times the length of the second bottom region in the arrangement direction.

[0016] The semiconductor device may include an interlayer insulating film. The interlayer insulating film may be provided above the semiconductor substrate. The interlayer insulating film may have contact holes. The opening width of the contact hole provided above the second region may be larger than the opening width of the contact hole provided above the first region.

[0017] Note that the above summary of the invention does not enumerate all the features of the present invention. Also, sub-combinations of these feature groups can also be inventions.

Brief Description of the Drawings

[0018]

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Mode for Carrying Out the Invention

[0019] Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the claims. Also, not all combinations of features described in the embodiments are essential for the solution means of the invention.

[0020] In this specification, one side in the direction parallel to the depth direction of the semiconductor substrate is referred to as "upper", and the other side is referred to as "lower". Of the two main surfaces of the substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction at the time of mounting the semiconductor device.

[0021] In this specification, when explaining technical matters, orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis may be used. The orthogonal coordinate axes only specify the relative positions of the components and do not limit a specific direction. For example, the Z-axis does not limit and indicate the height direction with respect to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When described as the Z-axis direction without specifying positive or negative, it means the directions parallel to the +Z-axis and -Z-axis.

[0022] In this specification, the orthogonal axes parallel to the upper surface and the lower surface of the semiconductor substrate are defined as the X-axis and the Y-axis. Also, the axis perpendicular to the upper surface and the lower surface of the semiconductor substrate is defined as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. Also, in this specification, the directions parallel to the upper surface and the lower surface of the semiconductor substrate, including the X-axis and the Y-axis, may be referred to as the horizontal direction.

[0023] Also, the region from the center in the depth direction of the semiconductor substrate to the upper surface of the semiconductor substrate may be referred to as the upper surface side. Similarly, the region from the center in the depth direction of the semiconductor substrate to the lower surface of the semiconductor substrate may be referred to as the lower surface side.

[0024] In this specification, when referred to as "identical" or "equal", it may include cases having errors due to manufacturing variations or the like. The error is, for example, within 10%.

[0025] In this specification, the conductivity type of the doped region doped with impurities is described as P-type or N-type. In this specification, the impurity may particularly mean either an N-type donor or a P-type acceptor, and may be described as a dopant. In this specification, doping means introducing a donor or an acceptor into the semiconductor substrate to form a semiconductor showing an N-type conductivity type or a semiconductor showing a P-type conductivity type.

[0026] In this specification, the doping concentration means the concentration of donors or acceptors in the thermal equilibrium state. In this specification, the net doping concentration means the net concentration obtained by adding up including the polarity of charges, taking the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions. As an example, if the donor concentration is N D , and the acceptor concentration is N A , then the net doping concentration at any position is N D - N A . In this specification, the net doping concentration may sometimes be simply referred to as the doping concentration.

[0027] A donor has the function of supplying electrons to a semiconductor. An acceptor has the function of receiving electrons from a semiconductor. Donors and acceptors are not limited to the impurities themselves. For example, a VOH defect in which a vacancy (V), oxygen (O), and hydrogen (H) existing in a semiconductor are combined functions as a donor that supplies electrons. In this specification, the VOH defect may sometimes be referred to as a hydrogen donor.

[0028] When described as P+ type or N+ type in this specification, it means that the doping concentration is higher than that of P type or N type. When described as P- type or N- type, it means that the doping concentration is lower than that of P type or N type. Also, when described as P++ type or N++ type in this specification, it means that the doping concentration is higher than that of P+ type or N+ type. The unit system of this specification is the SI unit system unless otherwise specified. Although the unit of length may be expressed in cm, various calculations may be performed after converting to meters (m).

[0029] In this specification, the chemical concentration refers to the atomic density of impurities measured regardless of the state of electrical activation. The chemical concentration (atomic density) can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration described above can be measured by voltage-capacitance measurement (CV method). Also, the carrier concentration measured by the spreading resistance measurement method (SR method) may be used as the net doping concentration. The carrier concentration measured by the CV method or the SR method may be a value in the thermal equilibrium state. Further, in the N-type region, since the donor concentration is sufficiently larger than the acceptor concentration, the carrier concentration in the region may be used as the donor concentration. Similarly, in the P-type region, the carrier concentration in the region may be used as the acceptor concentration. In this specification, the doping concentration in the N-type region may be referred to as the donor concentration, and the doping concentration in the P-type region may be referred to as the acceptor concentration.

[0030] Also, when the concentration distribution of donors, acceptors, or net doping has a peak, the peak value may be used as the concentration of donors, acceptors, or net doping in the region. In cases where the concentration of donors, acceptors, or net doping is substantially uniform, etc., the average value of the concentration of donors, acceptors, or net doping in the region may be used as the concentration of donors, acceptors, or net doping. In this specification, for the concentration representation per unit volume, atoms / cm 3 , or, / cm 3 is used. This unit is used for the donor or acceptor concentration or the chemical concentration in the semiconductor substrate. The atoms notation may be omitted.

[0031] The carrier concentration measured by the SR method may be lower than the concentration of donors or acceptors. In the range where current flows when measuring the spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state. The decrease in carrier mobility occurs due to the scattering of carriers caused by the disorder of the crystal structure (disorder) such as lattice defects.

[0032] The concentration of donors or acceptors calculated from the carrier concentration measured by the CV method or the SR method may be lower than the chemical concentration of the element indicating the donor or acceptor. As an example, in a silicon semiconductor, the donor concentration of phosphorus or arsenic that acts as a donor, or the acceptor concentration of boron that acts as an acceptor, is about 99% of these chemical concentrations. On the other hand, the donor concentration of hydrogen that acts as a donor in a silicon semiconductor is about 0.1% to 10% of the chemical concentration of hydrogen. Each concentration in this specification may be a value at room temperature. As an example, a value at room temperature may use a value at 300 K (Kelvin) (about 26.9 °C).

[0033] FIG. 1 is a top view showing an example of a semiconductor device 100 according to an embodiment. In FIG. 1, the position where each member is projected onto the upper surface of the semiconductor substrate 10 is shown. In FIG. 1, only some members of the semiconductor device 100 are shown, and some members are omitted.

[0034] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate, but the material of the semiconductor substrate 10 is not limited to silicon.

[0035] The semiconductor substrate 10 has end sides 162 in a top view. When simply referred to as a top view in this specification, it means looking from the upper surface side of the semiconductor substrate 10. The semiconductor substrate 10 in this example has two sets of end sides 162 facing each other in a top view. In FIG. 1, the X-axis and the Y-axis are parallel to any of the end sides 162. Also, the Z-axis is perpendicular to the upper surface of the semiconductor substrate 10.

[0036] An active portion 160 is provided on the semiconductor substrate 10. The active portion 160 is a region where a main current flows in the depth direction between the upper surface and the lower surface of the semiconductor substrate 10 when the semiconductor device 100 operates. An emitter electrode is provided above the active portion 160 but is omitted in FIG. 1.

[0037] In this example, a transistor section 70 including a transistor element such as an IGBT is provided in the active section 160. In other examples, a diode section including a transistor section 70 and a diode element such as an FWD (Free Wheel Diode) may be alternately arranged along a predetermined arrangement direction on the upper surface of the semiconductor substrate 10. In this specification, the arrangement direction is the X-axis direction.

[0038] The transistor section 70 has a P+-type collector region in a region in contact with the lower surface of the semiconductor substrate 10. Further, the transistor section 70 has a gate structure including an N++-type emitter region, a P--type base region, a gate conductive portion, and a gate insulating film periodically arranged on the upper surface side of the semiconductor substrate 10.

[0039] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 of this example has a gate pad 164. The semiconductor device 100 may have pads such as an anode pad, a cathode pad, and a current detection pad. Each pad is arranged in the vicinity of the end side 162. The vicinity of the end side 162 refers to the region between the end side 162 in a top view and the emitter electrode. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via a wiring such as a wire.

[0040] A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to the conductive portion of the gate trench portion of the active section 160. The semiconductor device 100 includes a gate wiring 130 that connects the gate pad 164 and the gate trench portion. In FIG. 1, the gate wiring 130 is hatched with oblique lines.

[0041] The gate wiring 130 is disposed between the active portion 160 and the edge 162 of the semiconductor substrate 10 in a top view. The gate wiring 130 in this example surrounds the active portion 160 in a top view. The region surrounded by the gate wiring 130 in a top view may be regarded as the active portion 160. Also, the gate wiring 130 is connected to the gate pad 164. The gate wiring 130 is disposed above the semiconductor substrate 10. The gate wiring 130 may be a metal wiring containing aluminum or the like.

[0042] The outer peripheral well region 11 is provided overlapping with the gate wiring 130. That is, similar to the gate wiring 130, the outer peripheral well region 11 surrounds the active portion 160 in a top view. The outer peripheral well region 11 is also provided to extend with a predetermined width in a range where it does not overlap with the gate wiring 130. The outer peripheral well region 11 is a region of a second conductivity type. The outer peripheral well region 11 in this example is of P+ type (see FIG. 2). The impurity concentration of the outer peripheral well region 11 is 5.0×10 17 atoms / cm 3 or more and 5.0×10 19 atoms / cm 3 or less. The impurity concentration of the outer peripheral well region 11 may be 2.0×10 18 atoms / cm 3 or more and 2.0×10 19 atoms / cm 3 or less.

[0043] Further, the semiconductor device 100 may include a temperature sensing portion (not shown) which is a PN junction diode formed of polysilicon or the like, and a current detecting portion (not shown) for simulating the operation of the transistor portion 70 provided in the active portion 160.

[0044] In the semiconductor device 100 of this example, in a top view, an edge termination structure portion 90 is provided between the active portion 160 and the end side 162. The edge termination structure portion 90 of this example is disposed between the outer peripheral gate wiring 130 and the end side 162. The edge termination structure portion 90 alleviates the electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure portion 90 may include at least one of a guard ring, a field plate, and RESURF provided annularly surrounding the active portion 160.

[0045] FIG. 2 is an enlarged view of region D in FIG. 1. Region D is a region including the transistor portion 70. The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, an outer peripheral well region 11, an emitter region 12, and a contact region 15 provided inside the upper surface side of the semiconductor substrate 10. The gate trench portion 40 and the dummy trench portion 30 are each an example of a trench portion.

[0046] The semiconductor device 100 of this example includes an emitter electrode and a gate wiring 130 provided above the upper surface of the semiconductor substrate 10. The emitter electrode and the gate wiring 130 are provided separately from each other. Also, an interlayer insulating film is provided between the emitter electrode and the gate wiring 130 and the upper surface of the semiconductor substrate 10. In FIG. 2, the emitter electrode, the gate wiring 130, and the interlayer insulating film are omitted.

[0047] The emitter electrode is provided above the gate trench portion 40, the dummy trench portion 30, the outer peripheral well region 11, the emitter region 12, and the contact region 15. The emitter electrode contacts the emitter region 12 and the contact region 15 on the upper surface of the semiconductor substrate 10 through a contact hole. Also, the emitter electrode is connected to a dummy conductive portion in the dummy trench portion 30 through a contact hole provided in the interlayer insulating film. The emitter electrode may be connected to the dummy conductive portion of the dummy trench portion 30 at the tip portion 31 of the dummy trench portion 30 in the Y-axis direction.

[0048] The gate wiring 130 is connected to the gate trench portion 40 through a contact hole provided in the interlayer insulating film. The gate wiring 130 may be connected to the gate conductive portion of the gate trench portion 40 at the tip portion 41 of the gate trench portion 40 in the Y-axis direction. The gate wiring 130 is not connected to the dummy conductive portion in the dummy trench portion 30.

[0049] The emitter electrode is formed of a material containing metal. For example, at least a part of the emitter electrode is formed of aluminum or an aluminum-silicon alloy, such as a metal alloy like AlSi, AlSiCu, etc. The emitter electrode may have a barrier metal formed of titanium, a titanium compound, etc. under the region formed of aluminum or the like. Further, in the contact hole, a plug formed by embedding tungsten or the like so as to be in contact with the barrier metal and aluminum or the like may be provided.

[0050] The transistor portion 70 has a plurality of trench portions arranged in the array direction. In this example, the trench portions are provided in the active portion 160 and the outer peripheral well region 11 on the upper surface of the semiconductor substrate 10. The trench portions are provided in a stripe shape in a top view in the transistor portion 70. In the transistor portion 70, one or more gate trench portions 40 and one or more dummy trench portions 30 are alternately provided along the array direction. One gate trench portion 40 and two dummy trench portions 30 may be alternately provided. Note that in at least a part of the region, two gate trench portions 40 may be provided adjacent to each other.

[0051] The gate trench portion 40 in this example may have two straight portions 39 (portions of the trench that are linear along the extending direction) extending along the extending direction perpendicular to the array direction, and a tip portion 41 connecting the two straight portions 39. In this specification, the extending direction is the Y-axis direction.

[0052] At least a part of the tip portion 41 is preferably provided in a curved shape in a top view. By connecting the ends of the two linear portions 39 in the Y-axis direction with the tip portion 41, the electric field concentration at the ends of the linear portion 39 can be alleviated.

[0053] In the transistor portion 70, the dummy trench portion 30 is provided between the respective linear portions 39 of the gate trench portion 40. One dummy trench portion 30 may be provided between the respective linear portions 39, or a plurality of dummy trench portions 30 may be provided. In this example, two dummy trench portions 30 are provided between the respective linear portions 39. Note that in at least a part of the region, the dummy trench portion 30 may not be provided between the linear portions 39. The dummy trench portion 30 may have a linear shape extending in the extending direction, and similar to the gate trench portion 40, may have a linear portion 29 and a tip portion 31. In this example, each dummy trench portion 30 has a linear portion 29 and a tip portion 31.

[0054] The diffusion depth of the outer peripheral well region 11 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. The Y-axis direction ends of the gate trench portion 40 and the dummy trench portion 30 are provided in the outer peripheral well region 11 in a top view. That is, at the Y-axis direction ends of each trench portion, the bottom in the depth direction of each trench portion is covered by the outer peripheral well region 11. Thereby, the electric field concentration at the bottom of each trench portion can be alleviated. Further, the semiconductor device 100 may include a gate trench portion 40 or a dummy trench portion 30 that is entirely provided in the outer peripheral well region 11 in a top view.

[0055] In the array direction, mesa portions are provided between the respective trench portions. The mesa portion refers to the region sandwiched by the trench portions inside the semiconductor substrate 10. As an example, the upper end of the mesa portion is the upper surface of the semiconductor substrate 10. The depth position of the lower end of the mesa portion is the same as the depth position of the lower end of the trench portion. The mesa portion of this example is provided to extend in the extending direction (Y-axis direction) along the trench on the upper surface of the semiconductor substrate 10. In this example, the mesa portion 60 and the wide mesa portion 62 are provided in the transistor portion 70.

[0056] At least one of the emitter region 12 of the first conductivity type and the contact region 15 of the second conductivity type may be provided in each mesa portion 60. The emitter region 12 of this example is of N++ type, and the contact region 15 is of P++ type. The emitter region 12 and the contact region 15 may be provided between the base region and the upper surface of the semiconductor substrate 10 in the depth direction.

[0057] The mesa width of the wide mesa portion 62 is larger than the mesa width of the mesa portion 60. The mesa width is the interval between the trench portions in the array direction (X-axis direction). In this specification, the mesa width of the mesa portion 60 is expressed as the first trench interval, and the mesa width of the wide mesa portion 62 is expressed as the second trench interval. The contact region 15 of the second conductivity type may be provided in each wide mesa portion 62.

[0058] The mesa portion 60 of the transistor portion 70 has an emitter region 12 exposed on the upper surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. A contact region 15 exposed on the upper surface of the semiconductor substrate 10 may be provided in the mesa portion 60 in contact with the gate trench portion 40. In this example, in the mesa portion 60, the region exposed on the upper surface of the semiconductor substrate 10 and arranged closest to the gate wiring 130 is the contact region 15. Also in the wide mesa portion 62, the emitter region 12 and the contact region 15 may be provided. In FIG. 2, the contact region 15 is provided in the wide mesa portion 62.

[0059] Each of the contact region 15 and the emitter region 12 in the mesa portion 60 is provided from one trench portion in the X-axis direction to the other trench portion. As an example, the contact region 15 and the emitter region 12 of the mesa portion 60 are alternately arranged along the extending direction (Y-axis direction) of the trench portion. Further, the contact region 15 in the wide mesa portion 62 is provided from one trench portion in the X-axis direction to the other trench portion.

[0060] In other examples, the contact region 15 and the emitter region 12 of the mesa portion 60 may be provided in a stripe shape along the extending direction (Y-axis direction) of the trench portion. For example, the emitter region 12 is provided in a region in contact with the trench portion, and the contact region 15 is provided in a region sandwiched by the emitter regions 12.

[0061] In FIG. 2, a guard ring 92 is provided in the edge termination structure portion 90. A plurality of guard rings 92 may be provided in the edge termination structure portion 90. The guard ring 92 is a region of the second conductivity type. The impurity concentration of the guard ring 92 may be the same as that of the outer peripheral well region 11.

[0062] The active portion 160 has a central portion 170 and an outer peripheral portion 180. The central portion 170 has the emitter region 12. The outer peripheral portion 180 surrounds the central portion 170. In this example, the outer peripheral portion 180 surrounds the central portion 170 in a top view. The boundary between the central portion 170 and the outer peripheral portion 180 may be the emitter region 12 closest to the outer peripheral well region 11 in the X-axis direction or the Y-axis direction.

[0063] Contact holes are provided above each of the mesa portions 60 and the wide mesa portions 62 of the central portion 170. The contact holes in this example are provided above each of the contact region 15 and the emitter region 12. The contact holes may be arranged at the center in the arrangement direction (X-axis direction) of the mesa portions 60. The contact holes may be arranged at the center in the arrangement direction (X-axis direction) of the wide mesa portions 62. In this example, the contact holes are omitted.

[0064] In FIG. 2, the arrangement of the first bottom region 182 and the second bottom region 184 provided in the semiconductor substrate 10 is shown by a dotted line. The first bottom region 182 is a P-type region provided across at least two trench portions. The second bottom region 184 is a P-type region provided at the bottom of one trench portion. In this example, the second bottom region 184 is provided in the trench portion sandwiched by the wide mesa portion 62. The first bottom region 182 is provided in the trench portion sandwiched by the mesa portion 60 and in the trench portion sandwiched by the mesa portion 60 and the wide mesa portion 62. As shown in FIG. 2, the first bottom region 182 and the second bottom region 184 are provided separately. That is, the first bottom region 182 and the second bottom region 184 are not electrically connected.

[0065] FIG. 3 is a view showing an example of the e-e cross section in FIG. 2. The e-e cross section is the XZ plane passing through the emitter region 12 of the central portion 170. Note that the dimensions in FIG. 3 do not necessarily match the dimensions in FIG. 2. The semiconductor device 100 in this example has, in this cross section, the semiconductor substrate 10, the interlayer insulating film 38, the emitter electrode 52, and the collector electrode 24.

[0066] The interlayer insulating film 38 is provided on the upper surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 is a film including at least one layer of an insulating film such as a silicate glass to which impurities such as boron or phosphorus are added, a thermal oxide film, and other insulating films. The contact hole 54 described in FIG. 2 is provided in the interlayer insulating film 38. The contact hole 54 is partially provided above the outer peripheral well region 11, and thereby the outer peripheral well region 11 is connected to the emitter electrode 52.

[0067] The emitter electrode 52 is provided above the interlayer insulating film 38. The emitter electrode 52 is in contact with the upper surface 21 of the semiconductor substrate 10 through the contact hole 54 of the interlayer insulating film 38. Note that the emitter electrode 52 does not necessarily need to be provided above the outer peripheral well region 11. The gate wiring 130 may be provided above the outer peripheral well region 11. The gate polysilicon 46 may be provided under the gate wiring 130.

[0068] The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum. In this specification, the direction (Z-axis direction) connecting the emitter electrode 52 and the collector electrode 24 is referred to as the depth direction.

[0069] A base region 14 of the second conductivity type is provided in each mesa portion 60 and the wide mesa portion 62. The emitter region 12 and the contact region 15 are provided between the upper surface 21 of the semiconductor substrate 10 and the base region 14. The base region 14 in this example is of P-type.

[0070] The semiconductor substrate 10 has a drift region 18 of the first conductivity type. The drift region 18 in this example is of N-type or N--type.

[0071] In the mesa portion 60 of the central portion 170, an N++-type emitter region 12 and a P-type base region 14 are provided in order from the upper surface 21 side of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. An N+-type accumulation region 16 may be provided in the mesa portion 60. The accumulation region 16 is disposed between the base region 14 and the drift region 18.

[0072] The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10 and is provided in contact with the gate trench portion 40. The emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 60. The doping concentration of the emitter region 12 is higher than that of the drift region 18.

[0073] The base region 14 is provided below the emitter region 12. The base region 14 in this example is provided in contact with the emitter region 12. The base region 14 may be in contact with the trench portions on both sides of the mesa portion 60. The peak of the impurity concentration of the base region 14 is, as an example, 2.5×10 17 atoms / cm 3 and is. The impurity concentration of the base region 14 is 5.0×10 16 atoms / cm3 or less than and 1.0×10 18 atoms / cm 3 The following may be satisfied. Also, the base region 14 may be in contact with the trench portions on both sides of the wide mesa portion 62.

[0074] The accumulation region 16 is provided below the base region 14. The accumulation region 16 is an N+-type region with a higher doping concentration than the drift region 18. The accumulation region 16 may have a concentration peak of donors such as phosphorus or hydrogen donors. By providing the high-concentration accumulation region 16 between the drift region 18 and the base region 14, the carrier injection promotion effect (IE effect) can be enhanced and the on-voltage can be reduced. The accumulation region 16 may be provided so as to cover the entire lower surface of the base region 14 in each mesa portion 60.

[0075] In the mesa portion 60 of the outer peripheral portion 180, a P++-type contact region 15 and a P-type base region 14 are provided in order from the upper surface 21 side of the semiconductor substrate 10. Similarly, in the wide mesa portion 62 of the outer peripheral portion 180, a P++-type contact region 15 and a P-type base region 14 may be provided in order from the upper surface 21 side of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. The accumulation region 16 may be provided in the mesa portion 60 of the outer peripheral portion 180. The accumulation region 16 may be provided in the wide mesa portion 62 of the outer peripheral portion 180.

[0076] An N+-type buffer region 20 may be provided below the drift region 18. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may have a concentration peak with a higher doping concentration than the drift region 18. The doping concentration of the concentration peak refers to the doping concentration at the apex of the concentration peak. Also, the doping concentration of the drift region 18 may use the average value of the doping concentration in a region where the doping concentration distribution is substantially flat.

[0077] The buffer region 20 may be formed by ion-implanting an N-type dopant such as hydrogen (proton) or phosphorus. The buffer region 20 in this example is formed by ion-implanting hydrogen. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower end of the base region 14 from reaching the P+-type collector region 22.

[0078] A P+-type collector region 22 is provided below the buffer region 20. The acceptor concentration of the collector region 22 is higher than that of the base region 14. The collector region 22 may contain the same acceptor as the base region 14 or may contain a different acceptor. The acceptor of the collector region 22 is, for example, boron. The element serving as the acceptor is not limited to the above-described example.

[0079] The collector region 22 is exposed on the lower surface 23 of the semiconductor substrate 10 and is connected to the collector electrode 24. The collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum.

[0080] On the upper surface 21 side of the semiconductor substrate 10, one or more gate trench portions 40 and one or more dummy trench portions 30 are provided. Each trench portion penetrates from the upper surface 21 of the semiconductor substrate 10 through the base region 14 and reaches the drift region 18. In a region where at least any one of the emitter region 12, the contact region 15, and the accumulation region 16 is provided, each trench portion also penetrates these doping regions and reaches the drift region 18. The fact that the trench portion penetrates the doping region is not limited to the case where the trench portion is formed in the order of forming the doping region first and then the trench portion. Even in the case where the doping region is formed between the trench portions after the trench portions are formed, it is included in the case where the trench portion penetrates the doping region.

[0081] The gate trench portion 40 has a gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate insulating film 42 within the gate trench. That is, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0082] The gate conductive portion 44 may be provided longer than the base region 14 in the depth direction. The gate trench portion 40 in the cross section is covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring 130. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is formed in the surface layer of the interface of the base region 14 that contacts the gate trench portion 40.

[0083] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross section. The dummy trench portion 30 has a dummy trench provided on the upper surface 21 of the semiconductor substrate 10, a dummy insulating film 32, and a dummy conductive portion 34. The dummy conductive portion 34 is electrically connected to the emitter electrode 52. The dummy insulating film 32 is provided to cover the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and inside the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction.

[0084] In this example, the gate trench portion 40 and the dummy trench portion 30 are covered by the interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. Note that the bottoms of the dummy trench portion 30 and the gate trench portion 40 may be convex downward curved surfaces (curved in cross-section).

[0085] In the semiconductor device 100 according to this example, a bottom region of the second conductivity type is provided at the bottom of the trench portion. In this example, in the central portion 170, a first bottom region 182-1 of the second conductivity type is provided at the bottom of the trench portion. The first bottom region 182-1 is the first bottom region 182 provided closer to the central portion 170 side than the first bottom region 182-2. The first bottom region 182-1 of this example is of P-type. The first bottom region 182-1 covers the bottom of the trench portion. The first bottom region 182-1 is provided over the bottoms of at least two trench portions. The first bottom region 182-1 may be provided below the base region 14. By providing the first bottom region 182-1 of the second conductivity type, it becomes easier to control the slope of the reverse recovery voltage of the FWD. Therefore, the turn-on loss can be reduced. Also, by providing the first bottom region 182-1, the breakdown voltage can be improved.

[0086] Also, in the outer peripheral portion 180, a first bottom region 182-2 of the second conductivity type is provided at the bottom of the trench portion. The first bottom region 182-2 is the first bottom region 182 provided closer to the outer peripheral portion 180 side than the first bottom region 182-1. The first bottom region 182-2 of this example is of P-type. The first bottom region 182-2 covers the bottom of the trench portion. The first bottom region 182-2 may be provided toward the first bottom region 182-1. That is, the first bottom region 182-2 may be provided at the same depth as the first bottom region 182-1 in the depth direction of the semiconductor substrate 10. The first bottom region 182-2 is electrically connected to the outer peripheral well region 11. In this example, the first bottom region 182-2 is directly connected to the outer peripheral well region 11. Therefore, the electric field concentration at the boundary between the outer peripheral well region 11 and the first bottom region 182-2 can be alleviated, and the avalanche withstand capacity at turn-off can be improved.

[0087] The first bottom regions 182-1 and 182-2 are provided separately. That is, in at least a part of the outer peripheral portion 180, no bottom region is provided. Since the first bottom regions 182-1 and 182-2 are provided separately, it is possible to prevent the first bottom region 182-1 and the outer peripheral well region 11 from having the same electric potential. The first bottom region 182-1 may be electrically floating. The fact that the first bottom region 182-1 is electrically floating means that it is not electrically connected to any electrode.

[0088] The impurity concentrations of the first bottom region 182-1 and the first bottom region 182-2 may be the same. By making the impurity concentrations of the first bottom region 182-1 and the first bottom region 182-2 the same, the manufacturing processes can be made the same. Also, the impurity concentration of the first bottom region 182-2 may be greater than the impurity concentration of the first bottom region 182-1. By making the impurity concentration of the first bottom region 182-2 greater than the impurity concentration of the first bottom region 182-1, the effect of relaxing local electric field concentration becomes greater. The impurity concentration of the outer peripheral well region 11 may be greater than the impurity concentration of the first bottom region 182-2. By making the impurity concentration of the outer peripheral well region 11 greater than the impurity concentration of the first bottom region 182-2, it is possible to prevent the electric field distribution from becoming steep. The peak of the impurity concentration of each bottom region is, as an example, 4.0×10 15 atoms / cm 3 It is. The peak of the impurity concentration of each bottom region is 3.0×10 14 atoms / cm 3 or more and 3.0×10 16 atoms / cm 3 or less may be. The dose amount of ions implanted into each bottom region is, as an example, 5.0×10 11 ion / cm 2 or more and 5.0×10 13 ion / cm 2 or less may be.

[0089] In the semiconductor device 400 (see FIG. 16) according to the comparative example, in the active portion 160, in the region where the trench portion has a bottom region (referred to as region 202) and the region where the trench portion does not have a bottom region (region 204), an imbalance occurs in the static breakdown voltage of the IGBT due to the presence or absence of the bottom region. According to the simulation performed by the inventor, the static breakdown voltage of region 204 is about 5% lower than that of region 202. Depending on the breakdown voltage of the IGBT, the difference in the static breakdown voltage is estimated to be several tens to 100 V. For the same reason, it is estimated that the clamp breakdown voltage of region 204 is also lower than that of region 202. Due to the breakdown voltage imbalance, the possibility that the IGBT undergoes switching breakdown intensively in region 204 increases.

[0090] In FIG. 3, the active portion 160 has a first region 192 and a second region 194. The first region 192 is a region where the trench portions are arranged at a first trench interval L1 in the arrangement direction. The second region 194 is a region where the trench portions are arranged at a second trench interval L2 that is larger than the first trench interval L1 in the arrangement direction. In this example, the first region 192 is provided in the central portion 170 and the outer peripheral portion 180. In this example, the second region 194 is provided in the outer peripheral portion 180.

[0091] When forming a bottom region in the first region 192, impurities such as boron are implanted into the trench portions. Thereafter, a heat treatment is performed to diffuse the boron. The first region 192 has a smaller trench interval than the second region 194. Therefore, when the boron is diffused, the bottom regions provided in the adjacent trench portions are connected. Therefore, in the first region 192, a first bottom region 182 is formed that extends over at least two trench portions. In this example, the first region 192 corresponds to the mesa portion 60, and the second region 194 corresponds to the wide mesa portion 62.

[0092] On the other hand, when forming the bottom region in the second region 194, since the trench pitch in the second region 194 is larger than that in the first region 192, when boron is diffused, the bottom regions provided in adjacent trench portions do not connect. Therefore, in the second region 194, a second bottom region 184 provided at the bottom of one trench portion is formed. By providing the second bottom region 184, the withstand voltage imbalance in the active portion 160 can be reduced. Further, since the second bottom region 184 is provided at the bottom of one trench portion, it is possible to prevent the first bottom region 182-1 and the outer peripheral well region 11 from having the same potential. Therefore, the turn-on loss can be reduced.

[0093] The second trench pitch L2 may be 1.3 times or more and 8 times or less the first trench pitch L1. The second trench pitch L2 may be 1.5 times or more and 6 times or less the first trench pitch L1. The second trench pitch L2 may be 2 times or more and 4 times or less the first trench pitch L1. The first trench pitch L1 is, for example, 0.4 μm or more and 2.0 μm or less. The second trench pitch L2 is, for example, 0.8 μm or more and 8.0 μm or less. By setting the first trench pitch L1 and the second trench pitch L2 in this way, the withstand voltage imbalance can be reduced.

[0094] In this example, the second region 194 includes the gate trench portion 40. Further, the second bottom region 184 is provided at the bottom of the gate trench portion 40. Since the second region 194 includes the gate trench portion 40, current easily flows through the wide mesa portion 62.

[0095] Also, in this example, the second region 194 includes the dummy trench portion 30. Further, the second bottom region 184 is provided at the bottom of the dummy trench portion 30. Even with such a configuration, the withstand voltage imbalance can be eliminated.

[0096] In the second region 194, at least two trench portions may be provided. The second bottom region 184 may be provided at the bottom of each of the two trench portions. In this example, the second region 194 includes one gate trench portion 40 and one dummy trench portion 30, but is not limited to this example. For example, the second region 194 may include only one gate trench portion 40. The second region 194 may include only one dummy trench portion 30. The second region 194 may include one or more gate trench portions 40 and one or more dummy trench portions 30.

[0097] In this example, at least a part of the second region 194 is sandwiched between two first regions 192 in the arrangement direction. The second region 194 is sandwiched between two first regions 192 in the X-axis direction. Since the second region 194 is sandwiched between two first regions 192, it is possible to prevent the first bottom region 182-1 and the first bottom region 182-2 from being electrically connected. Further, the first bottom region 182-2 provided in one of the two first regions 192 may be electrically connected to the outer peripheral well region 11.

[0098] In this example, the second bottom region 184 is not provided at the center C of the wide mesa portion 62 in the arrangement direction. Since the second bottom region 184 is not provided at the center C of the wide mesa portion 62 in the arrangement direction, it is possible to prevent the second bottom region 184 from being connected to another adjacent second bottom region 184. In this example, a part of the drift region 18 is provided between two adjacent second bottom regions 184 in the arrangement direction. Therefore, two adjacent second bottom regions 184 in the arrangement direction are not connected.

[0099] The second trench interval L2 may be larger than the length W1 of the second bottom region 184 in the arrangement direction. The second trench interval L2 may be larger than 1.6 times the length W1 of the second bottom region 184 in the arrangement direction. With such a configuration, it is possible to prevent two adjacent second bottom regions 184 in the arrangement direction from being connected.

[0100] In this example, the second bottom region 184 covers the bottom of the trench portion. That is, the length W1 in the arrangement direction of the second bottom region 184 may be larger than the length W2 in the arrangement direction of the trench portion. The length W2 in the arrangement direction of the trench portion may be the length in the arrangement direction of the bottom of the trench portion. Since the second bottom region 184 covers the bottom of the trench portion, the hole current is dispersed and current concentration can be prevented.

[0101] The impurity concentrations of the second bottom region 184 and the first bottom region 182 may be the same. By making the impurity concentrations of the first bottom region 182 and the second bottom region 184 the same, the manufacturing process can be made the same. The impurity concentrations of the second bottom region 184 and the first bottom region 182 may be different. Also, the second bottom region 184 may be provided toward the first bottom region 182. That is, the second bottom region 184 may be provided at the same depth as the first bottom region 182 in the depth direction of the semiconductor substrate 10.

[0102] The distance L7 between adjacent second bottom regions 184 in the arrangement direction may be 0.1 μm or more and 10 μm or less. Similarly, the distance between the adjacent second bottom region 184 and the first bottom region 182 in the arrangement direction may be 0.1 μm or more and 10 μm or less.

[0103] FIG. 4 is a diagram showing an example of the f-f cross section in FIG. 2. The f-f cross section is the YZ plane passing through the tip 41 of the gate trench portion 40 and the tip 31 of the dummy trench portion 30. Note that the dimensions in FIG. 4 do not necessarily match the dimensions in FIG. 2. The semiconductor device 100 of this example has, in this cross section, the semiconductor substrate 10, the interlayer insulating film 38, the emitter electrode 52, the collector electrode 24, and the gate wiring 130.

[0104] In this cross-section, the gate trench portion 40 is connected to the gate wiring 130. Gate polysilicon 46 may be provided under the gate wiring 130. In this cross-section, the dummy trench portion 30 is connected to the emitter electrode 52 via the contact hole 56. Dummy polysilicon 36 may be provided under the emitter electrode 52. Also, in FIG. 4, similar to FIG. 3, the first bottom region 182-2 may be provided at the same depth as the first bottom region 182-1 in the depth direction of the semiconductor substrate 10.

[0105] FIG. 5 is a diagram showing an example of the g-g cross-section in FIG. 2. The g-g cross-section is It is the YZ plane passing through the straight portion 29 of the dummy trench portion 30. Note that the dimensions in FIG. 5 do not necessarily match the dimensions in FIG. 2. The semiconductor device 100 in this example has, in this cross-section, the semiconductor substrate 10, the interlayer insulating film 38, the emitter electrode 52, the collector electrode 24, and the gate wiring 130. In FIG. 5, an interlayer insulating film 38 is provided between the emitter electrode 52 and the dummy trench portion 30. Also, in FIG. 5, similar to FIG. 3, the first bottom region 182-2 may be provided at the same depth as the first bottom region 182-1 in the depth direction of the semiconductor substrate 10.

[0106] FIGS. 6 and 7 are diagrams showing an example of the manufacturing method of the semiconductor device 100. The manufacturing method of the semiconductor device 100 includes a trench formation step S301, a resist formation step S302, an ion implantation step S303, a resist removal step S304, a gate conductive portion formation step S305, and a heat treatment step S306. In FIG. 6, the trench formation step S301, the resist formation step S302, and the ion implantation step S303 are described. In FIG. 7, the resist removal step S304, the gate conductive portion formation step S305, and the heat treatment step S306 are described.

[0107] In the trench formation step S301, a trench 43 is formed in the semiconductor substrate 10. The trench 43 may be formed by a known method. The trench 43 may be formed by etching. In this example, by forming the trench 43, a mesa portion 60 and a wide mesa portion 62 are formed. A sacrificial oxide film 206 may be provided on the trench 43, the mesa portion 60, and the wide mesa portion 62.

[0108] In the resist formation step S302, a resist 208 is formed above the semiconductor substrate 10. The resist 208 may be formed by a known method such as photolithography. In the resist formation step S302, the resist 208 may be exposed and developed. Although the resist 208 is not provided in the ion implantation step S303 in this cross-section, the resist 208 may be provided in other cross-sections.

[0109] In the ion implantation step S303, ions are implanted into the semiconductor substrate 10. In this example, boron is implanted into the semiconductor substrate 10. The acceleration energy of the ion implantation is, for example, 100 keV. By performing the ion implantation, an implantation region 210 is formed at the bottom of the trench 43. By heat-treating the implantation region 210, a bottom region can be formed.

[0110] In the resist removal step S304, the resist 208 is removed. In the resist removal step S304, the resist 208 may be ashed. In the resist removal step S304, the sacrificial oxide film 206 may be removed.

[0111] In the gate conductive portion formation step S305, a gate conductive portion 44 is formed inside the trench 43. The gate conductive portion 44 may be polysilicon or the like. A gate insulating film 42 may be provided between the gate conductive portion 44 and the trench 43. The gate insulating film 42 may be provided on the mesa portion 60 and the wide mesa portion 62.

[0112] In the heat treatment step S306, the semiconductor substrate 10 is heat-treated. In this example, after ion implantation into the regions where the emitter region 12, the base region 14, the storage region 16, and a contact region 15 (not shown) are formed, the semiconductor substrate 10 is heat-treated. When heat-treated, in the mesa portion 60, since the bottom regions provided in the adjacent trench portions are connected when boron is diffused, a first bottom region 182 is formed. On the other hand, in the wide mesa portion 62, since the bottom regions provided in the adjacent trench portions are not connected when boron is diffused, a second bottom region 184 is formed.

[0113] FIG. 8 is a diagram showing an example of the arrangement of the resist 208 provided in the resist formation step S302. In FIG. 8, the resist 208 is arranged in the region D of FIG. 1. The resist 208 may have a longitudinal direction in the arrangement direction. The resist 208 may be provided at the outer peripheral portion 180.

[0114] FIG. 9 is a diagram showing an example of the arrangement of the resist 208 provided in the resist formation step S302. In FIG. 9, the resist 208 is arranged in the region E of FIG. 1. The arrangement of each component in the region E may be a reverse of the arrangement of each component in the region D with respect to the Y axis. Similar to FIG. 8, the resist 208 may have a longitudinal direction in the arrangement direction. The resist 208 may be provided at the outer peripheral portion 180.

[0115] The resist 208 may be provided so as not to connect the first bottom region 182 (the first bottom region 182-1 in FIG. 3) provided on the central portion 170 side and the first bottom region 182 (the first bottom region 182-2 in FIG. 3) provided on the outer peripheral portion 180 side. The resist 208 may terminate at the wide mesa portion 62. In this example, the resist 208 is continuously provided from the wide mesa portion 62 in FIG. 8 to the wide mesa portion 62 in FIG. 9.

[0116] FIG. 10 is a diagram showing another example of the e-e cross-section in FIG. 2. FIG. 10 is different from FIG. 3 in that the first bottom region 182-2 is provided wider than the first bottom region 182-1 in the depth direction of the semiconductor substrate 10. Other configurations of FIG. 10 may be the same as those of FIG. 3. In this example, the first bottom region 182-2 is provided wider on the lower surface 23 side than the first bottom region 182-1 and has substantially the same depth as the outer peripheral well region 11. By providing the first bottom region 182-2 wider than the first bottom region 182-1, the electric field distribution can be adjusted. Also, the first bottom region 182-2 may be provided wider than the second bottom region 184 in the depth direction of the semiconductor substrate 10.

[0117] FIG. 11 is a diagram showing another example of the e-e cross-section in FIG. 2. FIG. 11 is different from FIG. 3 in the configuration of the storage region 16. Other configurations of FIG. 11 may be the same as those of FIG. 3.

[0118] In this example, a part of the storage region 16 is provided between two adjacent second bottom regions 184 in the array direction. Even with such a configuration, the withstand voltage imbalance in the active portion 160 can be reduced. The upper end of the second bottom region 184 and the lower end of the storage region 16 may be in contact with each other in the depth direction of the semiconductor substrate 10. By bringing the upper end of the second bottom region 184 into contact with the lower end of the storage region 16, the withstand voltage of the semiconductor device 100 can be improved. Note that the upper end of the first bottom region 182-1 and the lower end of the storage region 16 may be in contact with each other in the depth direction of the semiconductor substrate 10.

[0119] FIG. 12 is a diagram showing another example of the e-e cross-section in FIG. 2. FIG. 12 is different from FIG. 11 in the configuration of the storage region 16. Other configurations of FIG. 12 may be the same as those of FIG. 11.

[0120] In this example, the storage region 16 provided in the first region 192 is defined as the storage region 16-1, and the storage region 16 provided in the second region 194 is defined as the storage region 16-2. The doping concentration of the storage region 16-2 provided in the second region 194 may be lower than the doping concentration of the storage region 16-1 provided in the first region 192. Since the breakdown voltage tends to decrease when the doping concentration of the storage region 16 is high, the breakdown voltage imbalance can be eliminated by reducing the doping concentration of the storage region 16-2 provided in the second region 194 where the breakdown voltage is likely to decrease.

[0121] FIG. 13 is a diagram showing another example of the e-e cross-section in FIG. 2. In FIG. 13, the configuration of the contact hole 54 is different from that in FIG. 3. Other configurations in FIG. 13 may be the same as those in FIG. 3.

[0122] In this example, the contact hole 54 provided above the first region 192 is defined as the contact hole 54-1, and the contact hole 54 provided above the second region 194 is defined as the contact hole 54-2. The opening width W3 of the contact hole 54-2 provided above the second region 194 may be larger than the opening width W4 of the contact hole 54-1 provided above the first region 192. In the contact hole 54-2 provided above the second region 194, since the contact region 15 is exposed, by increasing the opening width W3 of the contact hole 54-2, the hole extraction can be improved. Therefore, the latch-up of the semiconductor device 100 can be suppressed. In this example, the opening width W3 of the contact hole 54-2 is the same as the second trench pitch L2 (see FIG. 3).

[0123] FIG. 14 is a top view showing an example of a semiconductor device 200 according to another embodiment. FIG. 14 is different from FIG. 2 in that the wide mesa portion 62 is provided in the central portion 170. Other configurations in FIG. 14 may be the same as those in FIG. 2.

[0124] In this example, the wide mesa portion 62 is provided in the central portion 170. Accordingly, a second bottom region 184 can be formed in the central portion 170. Thus, the withstand voltage imbalance of the semiconductor device 200 can be adjusted. In this example, the trench portion where the second bottom region 184 is provided is the dummy trench portion 30. The trench portion where the second bottom region 184 is provided may be the gate trench portion 40. Also, a plurality of second bottom regions 184 may be formed in the central portion 170. The trench pitch of the wide mesa portion 62 provided in the central portion 170 may be the same as or different from the trench pitch of the wide mesa portion 62 provided in the outer peripheral portion 180.

[0125] In this example, the area ratio of the emitter region 12 to the contact region 15 in the wide mesa portion 62 provided in the central portion 170 is the same as the area ratio of the emitter region 12 to the contact region 15 in the mesa portion 60 provided in the central portion 170. The area ratio of the emitter region 12 to the contact region 15 is, for example, the area of the emitter region 12 / the area of the contact region 15 per unit length in the extending direction. In this example, since the emitter region 12 and the contact region 15 are provided from one trench portion to the other trench portion in the X-axis direction in the mesa portion 60 and the wide mesa portion 62, the area ratio of the emitter region 12 to the contact region 15 is the length of one emitter region 12 in the extending direction / the length of one contact region 15 in the extending direction.

[0126] FIG. 15 is a top view showing an example of a semiconductor device 300 according to another embodiment. In FIG. 15, the configurations of the emitter region 12 and the contact region 15 provided in the wide mesa portion 62 are different from those in FIG. 14. Other configurations in FIG. 15 may be the same as those in FIG. 14.

[0127] In this example, the area ratio between the emitter region 12 and the contact region 15 in the wide mesa portion 62 provided in the central portion 170 is different from the area ratio between the emitter region 12 and the contact region 15 in the mesa portion 60 provided in the central portion 170. In FIG. 15, the area ratio between the emitter region 12 and the contact region 15 in the wide mesa portion 62 provided in the central portion 170 is smaller than the area ratio between the emitter region 12 and the contact region 15 in the mesa portion 60 provided in the central portion 170. Let the length of one emitter region 12 in the extending direction in the wide mesa portion 62 be L3, and the length of one contact region 15 in the extending direction in the wide mesa portion 62 be L4. Also, let the length of one emitter region 12 in the extending direction in the mesa portion 60 be L5, and the length of one contact region 15 in the extending direction in the mesa portion 60 be L6. L3 / L4 may be smaller than L5 / L6. That is, in the wide mesa portion 62 provided in the central portion 170, compared with the mesa portion 60 provided in the central portion 170, the contact region 15 even if the ratio of is good. Even with such a configuration, the extraction of holes can be improved and the latch-up of the semiconductor device 300 can be suppressed.

[0128] FIG. 16 is a diagram showing an example of a semiconductor device 400 according to a comparative example. FIG. 16 is different from FIG. 3 in that the wide mesa portion 62 and the second bottom region 184 are not provided. Other configurations in FIG. 16 may be the same as those in FIG. 3.

[0129] FIG. 17 is a diagram showing an example of a semiconductor device 500 according to a comparative example. FIG. 17 is different from FIG. 16 in that the first bottom region 182 is not provided. Other configurations in FIG. 17 may be the same as those in FIG. 16.

[0130] FIG. 18 is a diagram showing an example of a semiconductor device 600 according to a comparative example. FIG. 18 is different from FIG. 16 in that the first bottom region 182-1 and the first bottom region 182-2 are connected. Other configurations in FIG. 18 may be the same as those in FIG. 16. In the case of this example, the boundary between the first bottom region 182-1 and the first bottom region 182-2 may be the boundary between the central portion 170 and the outer peripheral portion 180.

[0131] Figure 19 is a diagram showing the relationship between the forward current of the FWD at room temperature and the slope of the reverse recovery voltage. The forward current is shown as a ratio when the rated current is set to 1. For the semiconductor device 100 and the semiconductor device 500 in Figure 19, an external gate resistor is adjusted so that the slope of the reverse recovery voltage is the same (about 5 kV / μsec) when the forward current is 5 to 10% (low current). From Figure 19, the semiconductor device 100 can keep the slope of the reverse recovery voltage of the FWD at the same level even when the forward current is changed, compared with the semiconductor device 500. Therefore, since the turn-on speed on the IGBT side does not slow down at 100% of the forward current (rated current) and can be kept as fast as at 5 to 10% of the forward current (low current), the turn-on loss can be reduced.

[0132] Figure 20 is a diagram showing the relationship between the maximum value of the slope of the reverse recovery voltage of the FWD (at low current at room temperature) and the turn-on loss (at rated current at high temperature). Figure 20 can be obtained by plotting one-to-one the maximum value of the slope of the reverse recovery voltage on the FWD side and the turn-on loss on the IGBT side while changing the external gate resistor. From Figure 20, when comparing the semiconductor device 100 and the semiconductor device 500 with the maximum value of the slope of the reverse recovery voltage of the FWD being 5 kV / μsec, the turn-on loss can be reduced by about 50 percent.

[0133] Figure 21 is a diagram showing the IV characteristics of the collector current and the collector voltage when the gate voltage of the semiconductor device 100 and the semiconductor device 500 is 0 V (OFF). The collector voltage is shown as a ratio when the semiconductor device 500 the pressure resistance of is set to 1. As shown in Figure 21, since the semiconductor device 100 has a bottom region, the breakdown voltage can be improved compared with the semiconductor device 500.

[0134] Figure 22 is a diagram showing the IV characteristics of the collector current and the collector voltage when the gate voltage of the semiconductor device 100 and the semiconductor device 600 is 15 V (ON). As shown in Figure 22, when the first bottom region 182-1 and the first bottom region 182-2 are connected, the semiconductor device 600 does not operate.

[0135] FIG. 23 is a diagram showing the IV characteristics of the collector current and collector voltage of the semiconductor device 500 and the semiconductor device 600. As shown in FIG. 23, when the first bottom regions 182-1 and 182-2 are connected in the semiconductor device 600, jumps occur in the IV characteristics. By preventing the first bottom regions 182-1 and 182-2 from being connected, the jumps can be prevented.

[0136] As described above, the present invention has been described using embodiments. However, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. It is clear from the claims that forms with such changes or improvements can also be included in the technical scope of the present invention.

[0137] It should be noted that the execution order of each process such as operations, procedures, steps, and stages in the devices, systems, programs, and methods shown in the claims, the specification, and the drawings is not explicitly indicated as "earlier" or "preceding" etc., and unless the output of the previous process is used in the subsequent process, it can be realized in any order. Regarding the operation flow in the claims, the specification, and the drawings, even if it is described using "first," "next," etc. for convenience, it does not mean that it is essential to be implemented in this order.

Explanation of Reference Numerals

[0138] 10··Semiconductor substrate, 11··Peripheral well region, 12··Emitter region, 14··Base region, 15··Contact region, 16··Accumulation region, 18··Drift region, 20··Buffer region, 21··Upper surface, 22··Collector region, 23··Lower surface, 24··Collector electrode, 29··Straight portion, 30··Dummy trench portion, 31··Tip portion, 32··Dummy insulating film, 34··Dummy conductive portion, 36··Dummy polysilicon, 38··Interlayer insulating film, 39··Straight portion, 40··Gate trench portion, 41··Tip portion, 42··Gate insulating film, 43··Trench, 44··Gate conductive portion, 46··Gate polysilicon, 52··Emitter electrode, 54··Contact hole, 56··Contact hole, 60··Mesa portion, 62··Wide mesa portion, 70··Transistor portion, 90··Edge termination structure portion, 92··Guard ring, 100··Semiconductor device, 130··Gate wiring, 160··Active portion, 162··Side edge, 164··Gate pad, 170··Central portion, 180··Peripheral portion, 182··First bottom region, 184··Second bottom region, 192··First region, 194··Second region, 200··Semiconductor device, 202··Region, 204··Region, 206··Sacrificial oxide film, 208··Resist, 210··Implantation region, 300··Semiconductor device, 400··Semiconductor device, 500··Semiconductor device, 600··Semiconductor device

Claims

1. A semiconductor device comprising a semiconductor substrate provided with a drift region of a first conductivity type, wherein the semiconductor substrate has an active portion, and a trench portion provided in the active portion on the upper surface of the semiconductor substrate, and has, wherein the active portion has a first region in which the trench portions are arranged at a first trench interval in the arrangement direction, and a second region in which the trench portions are arranged at a second trench interval greater than the first trench interval in the arrangement direction, and has, wherein the first region has a first bottom region of a second conductivity type provided across the bottoms of at least two of the trench portions, and the second region has a second bottom region of a second conductivity type provided at the bottom of one of the trench portions semiconductor device.

2. The second trench interval is 2 times or more and 4 times or less the first trench interval The semiconductor device according to claim 1.

3. The second region includes a gate trench portion, and the second bottom region is provided at the bottom of the gate trench portion The semiconductor device according to claim 1.

4. The semiconductor substrate further has a second conductivity type outer peripheral well region surrounding the active portion in a top view The semiconductor device according to claim 1.

5. At least a part of the second region is sandwiched between two of the first regions in the arrangement direction The semiconductor device according to claim 4.

6. The first bottom region provided in one of the two first regions is electrically connected to the outer peripheral well region The semiconductor device according to claim 5.

7. The second region includes at least two of the trench portions, wherein the second bottom region is provided at the bottoms of the two trench portions respectively, and is not provided at the center of the mesa portion sandwiched between the two trench portions The semiconductor device according to claim 1.

8. A part of the drift region is provided between two adjacent second bottom regions in the arrangement direction The semiconductor device according to claim 7.

9. The semiconductor substrate further has a first conductivity type accumulation region, and a part of the accumulation region is provided between two adjacent second bottom regions in the arrangement direction The semiconductor device according to claim 7.

10. The semiconductor substrate further has a first conductivity type accumulation region, and the doping concentration of the accumulation region provided in the second region is lower than the doping concentration of the accumulation region provided in the first region The semiconductor device according to claim 1.

11. The upper end of the second bottom region and the lower end of the storage region are in contact with each other in the depth direction of the semiconductor substrate. The semiconductor device according to claim 9.

12. The second trench interval is larger than 1.6 times the length of the second bottom region in the arrangement direction. The semiconductor device according to claim 1.

13. Further provided above the semiconductor substrate, and further comprising an interlayer insulating film having contact holes. The opening width of the contact hole provided above the second region is larger than the opening width of the contact hole provided above the first region. The semiconductor device according to any one of claims 1 to 12.

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