Silicon carbide semiconductor device and method of manufacturing the same

Abstract

To provide a silicon carbide semiconductor device enabling the on-resistance thereof to be reduced, and a manufacturing method of the silicon carbide semiconductor device.SOLUTION: A main semiconductor element 11 is a vertical MOSFET with trench gate structure, and includes first and second p+ type regions 61a and 62a for an electro field relaxation of a bottom surface of a trench 37a. The first p+ type regions 61a are opposite to the bottom surface of the trench 37a in a depth direction Z, and are scattered in a first direction X similar to a direction where a gate electrode 39a extend. The second p+ type region 62a extends in a liner shape with an appropriate length similar to the trench 37a in the first direction X between the adjacent trenches 37a. A p++ type contact region 36a scatters in the first direction. The main semiconductor element 11 includes: a first cross section vertical to the first direction X in which a n+ type source region 35a between the adjacent two p++ type contact regions 36a in the first direction X; and an n-type current diffusion region 33a between the adjacent two first p+ type regions 61a in the first direction X.SELECTED DRAWING: Figure 5B

Description

Technical Field

[0001] This invention relates to a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device.

Background Art

[0002] Conventionally, for power semiconductor devices that control high voltages and large currents, there are, for example, multiple types such as bipolar transistors, IGBTs (Insulated Gate Bipolar Transistors), and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and these are used appropriately according to the application.

[0003] For example, bipolar transistors and IGBTs have a higher current density than MOSFETs and can handle larger currents, but cannot be switched at high speeds. Specifically, the use of bipolar transistors is limited to a switching frequency of about several kHz, and the use of IGBTs is limited to a switching frequency of about several tens of kHz. On the other hand, MOSFETs have a lower current density than bipolar transistors and IGBTs and it is difficult to handle large currents, but can perform high-speed switching operations up to about several MHz.

[0004] Also, different from IGBTs, MOSFETs have a parasitic diode formed by a pn junction between a p-type base region and an n - type drift region inside the semiconductor substrate (semiconductor chip), and this parasitic diode can be used as a freewheeling diode for self-protection. Therefore, when a MOSFET is used as an inverter device, it can be used without adding and connecting an external freewheeling diode, and it is attracting attention in terms of economy.

[0005] Silicon (Si) is used as a constituent material of power semiconductor devices. In the market, there is a strong demand for power semiconductor devices that combine high current and high speed. Efforts are being made to improve IGBTs and MOSFETs, and currently, development has advanced to almost the material limit. Therefore, semiconductor materials to replace silicon are being considered from the perspective of power semiconductor devices, and silicon carbide (SiC) has attracted attention as a semiconductor material capable of fabricating (manufacturing) next-generation power semiconductor devices with excellent low on-voltage, high-speed characteristics, and high-temperature characteristics.

[0006] Silicon carbide is a chemically very stable semiconductor material with a wide bandgap of 3 eV and can be used extremely stably as a semiconductor even at high temperatures. Also, since the maximum electric field strength of silicon carbide is more than one order of magnitude larger than that of silicon, it is expected as a semiconductor material that can sufficiently reduce the on-resistance. Such features of silicon carbide are also possessed by not only silicon carbide but all semiconductors with a wider bandgap than silicon (hereinafter referred to as wide-bandgap semiconductors).

[0007] In addition, in MOSFETs, when increasing the current, compared with the planar gate structure in which a channel (inversion layer) is formed along the front surface of the semiconductor chip, it is cost-effective to adopt a trench gate structure in which a channel is formed in a direction perpendicular to the front surface of the semiconductor chip along the sidewalls of the trench. The reason is that the trench gate structure can increase the unit cell (the constituent unit of the element) density per unit area, so the current density per unit area can be increased.

[0008] Since the rate of temperature rise corresponding to the occupied volume of the unit cell increases as the current density per unit area increases, a double-sided cooling structure is required to improve the discharge efficiency and stabilize the reliability. Furthermore, a highly functional structure has been proposed in which high-functional parts such as a current sense part, a temperature sense part, and an overvoltage protection part are arranged as circuit parts for protecting and controlling the main semiconductor element on the same semiconductor substrate as the main semiconductor element that performs the main operation of the power semiconductor device, thereby improving the reliability of the power semiconductor device.

[0009] The structure of a conventional semiconductor device will be described. FIG. 13 is a cross-sectional view showing the structure of a conventional semiconductor device. FIG. 13 shows the cross-sectional structure taken along the cutting line AA-AA' of FIG. 14. FIG. 14 is a plan view showing the layout of a part of a conventional semiconductor device as viewed from the front side of a semiconductor substrate. In FIG. 14, the layout of the first and second p + type regions 261 and 262 (hatched portions) that relax the electric field applied to the bottom surface of the trench 237 of the main semiconductor element is shown.

[0010] The conventional semiconductor device 220 shown in FIGS. 13 and 14 includes, as a main semiconductor element, a vertical MOSFET having a MOS gate with a general trench gate structure on the front surface side of a semiconductor substrate (semiconductor chip) 210 made of silicon carbide. The semiconductor substrate 210 is an n + type starting substrate 271, and n - type drift region 232 and p-type base region 234 are formed by epitaxially growing silicon carbide layers 272 and 273 in this order.

[0011] Taking the main surface on the p-type silicon carbide layer 273 side of the semiconductor substrate 210 as the front surface and the main surface on the n + type starting substrate 271 side as the back surface. The MOS gate is composed of a p-type base region 234, an n + type source region 235, a p ++ type contact region 236, a trench 237, a gate insulating film 238, and a gate electrode 239. The trench 237 is arranged in a stripe shape extending in a first direction X (the vertical direction in FIG. 14) parallel to the front surface of the semiconductor substrate 210.

[0012] Inside the semiconductor substrate 210, at a position closer to the n + type drain region 231 than the p-type base region 234, first and second p + type regions 261 and 262 that relax the electric field applied to the bottom surface of the trench 237 are provided. The first p +The p-type region 261 is provided apart from the p-type base region 234, linearly extends in the first direction X which is the same as the extending direction of the trench 237, and faces the entire bottom surface of the trench 237 in the depth direction Z.

[0013] Second p + The p-type region 262 is provided between adjacent trenches 237, apart from the first p + type region 261 and the trench 237, and is in contact with the p-type base region 234. The second p + type region 262 linearly extends in the first direction X which is the same as the extending direction of the trench 237. The metal silicide film 241, barrier metal 246, and source pad 221 that function as source electrodes are sequentially stacked on the front surface of the semiconductor substrate 210.

[0014] A double-sided cooling structure is constituted by the wiring structure on the source pad 221 and a cooling fin (not shown) joined to the drain electrode 251 on the back surface of the semiconductor substrate 210. Reference numerals 233, 240, and 240a are an n-type current diffusion region, an interlayer insulating film, and a contact hole, respectively. Reference numerals 242 to 245 are metal films constituting the barrier metal 246. Reference numerals 247 to 250 are respective parts constituting the wiring structure on the source pad 221.

[0015] As a conventional vertical MOSFET with a trench gate structure, an apparatus has been proposed in which the depth of a trench (gate trench) is made shallower than the depth of a p-type base region, and an n-type region reaching an n-type drift region is provided on the bottom surface of the trench (see, for example, Patent Document 1 below). In Patent Document 1 below, a pn junction between a p-type base region and an n-type drift region is formed at a position deeper than the trench, an electric field is concentrated on the pn junction, and the electric field is not concentrated on the bottom corner portion of the trench, thereby improving the breakdown voltage tolerance of the gate insulating film and achieving high voltage resistance.

[0016] As a conventional vertical MOSFET with a trench gate structure, a device has been proposed in which a p-type base region is composed of a first region with a low impurity concentration and a narrow width and a second region with a high impurity concentration and a wide width (see, for example, Patent Document 2 below). In Patent Document 2 below, the p-type base region is made to have a lower on-resistance by narrowing the width and lowering the impurity concentration in the first region, and punch-through is prevented and the breakdown voltage is maintained by narrowing the width in the first region and widening the width in the second region, and ohmic contact is made between the source electrode and the second region with a high impurity concentration and a wide width.

[0017] As a conventional vertical MOSFET with a trench gate structure, a device has been proposed in which a region where no parasitic transistor exists is provided between some adjacent trenches (gate trenches) arranged with a short pitch (see, for example, Patent Document 3 below). In Patent Document 3 below, the pitch between some adjacent trenches is shortened to concentrate the hole current flowing at the time of avalanche generation in the p-type floating region at the bottom of the trench, and by making this current concentration location a region where no parasitic transistor exists, the avalanche withstand voltage is improved.

[0018] As a conventional vertical MOSFET with a trench gate structure, n - A device has been proposed that has n-type regions between a plurality of p-type regions that relax the electric field applied to the bottom surface of a trench (gate trench) provided between an n-type drift region and a p-type base region (see, for example, Patent Document 4 below). In Patent Document 4 below, the n-type region between the p-type regions is made deeper on the drain side than the p-type regions, and the path of the current flowing through the channel between adjacent p-type regions is made less likely to narrow, thereby reducing the on-resistance while maintaining the breakdown voltage. + As a conventional vertical MOSFET with a trench gate structure, n + type regions between p + type regions, and the n-type region between the p-type regions is made deeper on the drain side than the p-type regions, and the path of the current flowing through the channel between adjacent p-type regions is made less likely to narrow, thereby reducing the on-resistance while maintaining the breakdown voltage. + By making the path of the current flowing through the channel between adjacent p-type regions less likely to narrow, the on-resistance is reduced while maintaining the breakdown voltage.

[0019] As a conventional vertical MOSFET with a trench gate structure, n - A plurality of p-type regions that relax the electric field applied to the bottom surface of a trench (gate trench) are provided between an n-type drift region and a p-type base region. +having a p-type region, and connecting a part of the p-type region between adjacent trenches to the p-type base region has been proposed (see, for example, Patent Document 5 below). In Patent Document 5 below, by partially thinning the p-type region between adjacent trenches, the hole current flowing during avalanche generation is made easier to discharge to the source electrode. + As a conventional vertical MOSFET with a trench gate structure, between the n-type drift region and the p-type base region, a plurality of p-type regions are provided to relax the electric field applied to the bottom surface of the trench (gate trench). + Among these p-type regions, the p-type regions between adjacent trenches all extend linearly in the same direction as the trenches, and a stripe-shaped p-type region extending in a direction orthogonal to the trenches is disposed at a position deeper on the drain side than the bottom surface of the trench. An apparatus has been proposed (see, for example, Patent Document 6 below).

[0020] In Patent Document 6 below, between a trench and a p-type region adjacent in a direction parallel to the front surface of the semiconductor substrate, and between p-type regions disposed apart from the trench and adjacent to each other at a position deeper on the drain side than the bottom surface of the trench, an n-type region having a higher impurity concentration than the n-type drift region is disposed. By this n-type region, even if a p-type region is partially disposed between the n-type drift region and the p-type base region, the current path flowing through the channel is less likely to become narrow, and the on-resistance is reduced while maintaining the breakdown voltage. -

Prior Art Documents

Patent Documents

Patent Document 1

Patent Document 2

[0021] In Patent Document 6 below, between a trench and a p-type region adjacent in a direction parallel to the front surface of the semiconductor substrate, and between p-type regions disposed apart from the trench and adjacent to each other at a position deeper on the drain side than the bottom surface of the trench, an n-type region having a higher impurity concentration than the n-type drift region is disposed. By this n-type region, even if a p-type region is partially disposed between the n-type drift region and the p-type base region, the current path flowing through the channel is less likely to become narrow, and the on-resistance is reduced while maintaining the breakdown voltage. +

Prior Art Documents

Patent Documents

Patent Document 1

Patent Document 2

Prior Art Documents

Patent Documents

[0022]

Patent Document 1

Patent Document 2

[0023] However, in the main semiconductor element (see FIGS. 13 and 14) of the conventional semiconductor device 220, as the unit cell is miniaturized, the width w101 between the first and second p-type regions 261 and 262 of the n-type drift region 232 becomes narrow. At the portion where this width w101 becomes narrow, the JFET (Junction FET) resistance increases, and the on-resistance increases, resulting in a large operating loss (power loss). In particular, when the semiconductor device 220 has a high-functional structure, it is necessary to reduce the on-resistance of the main semiconductor element to reduce the total operating loss of the semiconductor device 220. - type drift region 232, between the first and second p + type regions 261, 262 becomes narrow. At the portion where this width w101 becomes narrow, the JFET (Junction FET) resistance increases, and the on-resistance increases, resulting in a large operating loss (power loss). In particular, when the semiconductor device 220 has a high-functional structure, it is necessary to reduce the on-resistance of the main semiconductor element to reduce the total operating loss of the semiconductor device 220.

[0024] When the semiconductor device 220 has a high-functional structure, the main semiconductor element is operationally controlled by an external circuit based on the output signals of high-functional parts (not shown) such as a current sense part and a temperature sense part so as not to exceed the short-circuit withstand capacity and the like. For the main semiconductor element alone, it is sufficient if the applied voltage at which a current about four times the rated current of the main semiconductor element flows is defined as the allowable applied voltage (actual performance value). This is because when the total operating loss of the semiconductor device 220 becomes large, a voltage exceeding the actual performance value is applied to the main semiconductor element, causing the main semiconductor element to be damaged or malfunction.

[0025] An object of the present invention is to provide a silicon carbide semiconductor device capable of reducing the on-resistance and a method for manufacturing the silicon carbide semiconductor device in order to solve the problems caused by the above-described conventional technologies.

Means for Solving the Problems

[0026] In order to solve the above-described problems and achieve the object of the present invention, this invention has the following features. A silicon carbide semiconductor device having a trench gate structure, comprising: a semiconductor substrate made of silicon carbide; a trench extending in a first direction parallel to the front surface of the semiconductor substrate on the front surface of the semiconductor substrate; a source electrode provided on the front surface of the semiconductor substrate; a source region of a first conductivity type provided adjacent to the side wall of the trench on the front surface side of the semiconductor substrate and connected to the source electrode; a contact region of a second conductivity type selectively provided in the first direction on the front surface side of the semiconductor substrate and connected to the source electrode; a bottom region of the second conductivity type provided at a predetermined interval in the first direction and facing the bottom surface of the trench in the depth direction, having a width wider than that of the bottom surface of the trench and parallel to the front surface of the semiconductor substrate and orthogonal to the first direction. And A first region between two adjacent contact regions in the first direction and a second region between two adjacent bottom regions in the first direction and are provided, including a portion where current flows when on a first cross-section perpendicular to the first direction and a second cross-section perpendicular to the first direction, including a portion where current flows when on, provided with the contact region and the bottom surface region is included then and the source region is forms a ladder-like planar shape surrounding the periphery of the contact region, or a first cross-section perpendicular to the first direction, including a portion where current flows when on, provided with a first region between two adjacent contact regions in the first direction and a second region between two adjacent bottom surface regions in the first direction a second cross-section perpendicular to the first direction in which the contact region and the bottom region are provided is included, and the JFET resistance in the first cross-section is lower than the JFET resistance in the second cross-section, or including a portion where current flows when on the width of the contact region in the first direction including a first cross-section perpendicular to the first direction, provided with a first region between two adjacent contact regions in the first direction and a second region between two adjacent bottom surface regions in the first direction, including a portion where current flows when on is wider than the width of the bottom region in the first direction. is

[0027] Alternatively, to solve the above-described problems and achieve the object of the present invention, this invention has the following features. A semiconductor substrate made of silicon carbide, a trench extending in a first direction parallel to the front surface of the semiconductor substrate on the front surface of the semiconductor substrate, a source electrode provided on the front surface of the semiconductor substrate, a source region of a first conductivity type connected to the source electrode, a contact region of a second conductivity type connected to the source electrode, and a bottom region of the second conductivity type parallel to the front surface of the semiconductor substrate and orthogonal to the first direction, facing the bottom surface of the trench in the depth direction, and a method for manufacturing a silicon carbide semiconductor device having a trench gate structure, which has the following features. A step of ion-implanting impurities of the second conductivity type into the semiconductor substrate to form the bottom region at a predetermined interval in the first direction inside the semiconductor substrate, a first region between two adjacent contact regions in the first direction, and a second region between two adjacent bottom regions in the first direction and provided including a portion where current flows when on a first cross-section perpendicular to the first direction, and the contact region and the bottom region are provided including a portion where current flows when on a second cross-section perpendicular to the first direction, and ion-implanting impurities of the second conductivity type into the semiconductor substrate so as to include the above, and forming the contact region selectively in the first direction on the front surface side of the semiconductor substrate. The JFET resistance in the first cross-section is lower than the JFET resistance in the second cross-section.

Effects of the Invention

[0028] According to the silicon carbide semiconductor device and the method for manufacturing a silicon carbide semiconductor device according to the present invention, there is an effect that the on-resistance can be reduced.

Brief Description of the Drawings

[0029]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5A

Figure 5B

Figure 5C

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Embodiments for Carrying Out the Invention

[0030] With reference to the accompanying drawings, preferred embodiments of a silicon carbide semiconductor device and a method of manufacturing the silicon carbide semiconductor device according to the present invention will be described in detail. In this specification and the accompanying drawings, in layers and regions denoted by n or p, it means that electrons or holes are majority carriers, respectively. Also, + and - attached to n and p mean higher impurity concentration and lower impurity concentration than layers and regions to which they are not attached, respectively. In the following description of the embodiments and the accompanying drawings, the same reference numerals are assigned to the same configurations, and redundant descriptions are omitted.

[0031] (Embodiment) The semiconductor device according to the embodiment is configured using a semiconductor (wide bandgap semiconductor) having a wider bandgap than silicon (Si) as a semiconductor material. Here, the structure of the semiconductor device according to the embodiment will be described by taking the case where silicon carbide (SiC) is used as the wide bandgap semiconductor material constituting the semiconductor device according to the embodiment as an example. FIG. 1 is a plan view showing a layout of the semiconductor device according to the embodiment as viewed from the front side of the semiconductor substrate.

[0032] The semiconductor device 20 according to the embodiment shown in FIG. 1 includes a main semiconductor element 11 and one or more circuit portions for protecting and controlling the main semiconductor element 11 in an active region 1 of the same semiconductor substrate (semiconductor chip) 10 made of silicon carbide. The active region 1 is provided substantially at the center (chip center) of the semiconductor substrate 10. The main semiconductor element 11 is a vertical MOSFET that performs the main operation of the semiconductor device 20, and is composed of a plurality of unit cells (functional units of the element) connected in parallel to each other by a source pad 21a described later.

[0033] The main semiconductor element 11 is disposed in the effective region of the active region 1 (hereinafter referred to as the main effective region) 1a. The main effective region 1a is a region in which the main current (drift current) of the main semiconductor element 11 flows in a direction from the back surface to the front surface of the semiconductor substrate 10 (the direction opposite to the depth direction Z) when the main semiconductor element 11 is turned on. The main effective region 1a has, for example, a substantially rectangular planar shape and occupies most of the surface area of the active region 1. Three sides of the main effective region 1a having a substantially rectangular planar shape are adjacent to the edge termination region 2 described later.

[0034] The circuit section for protecting and controlling the main semiconductor element 11 is a high-functional section such as a current sense section 12, a temperature sense section 13, an overvoltage protection section (not shown), and an arithmetic circuit section (not shown), and is disposed in the main ineffective region 1b of the active region 1. The main ineffective region 1b is a region in which the unit cells of the main semiconductor element 11 are not disposed and does not function as the main semiconductor element 11. The main ineffective region 1b has, for example, a substantially rectangular planar shape and is disposed between the remaining one side of the main effective region 1a having a substantially rectangular planar shape and the edge termination region 2.

[0035] The edge termination region 2 is a region between the active region 1 and the end portion (chip end portion) of the semiconductor substrate 10, is adjacent to the active region 1, surrounds the periphery of the active region 1, and has a function of relaxing the electric field on the front surface side of the semiconductor substrate 10 and maintaining the breakdown voltage. In the edge termination region 2, a general breakdown voltage structure (not shown) such as a field limiting ring (FLR) or a junction termination extension (JTE) structure is disposed. The breakdown voltage is the limit voltage at which the semiconductor device does not malfunction or break down.

[0036] The source pad (electrode pad) 21a of the main semiconductor element 11 is disposed on the front surface of the semiconductor substrate 10 in the main active region 1a. The source pad 21a of the main semiconductor element 11 is disposed apart from the electrode pads other than the source pad 21a. The main semiconductor element 11 has a larger current capacity than other circuit portions. For this reason, the source pad 21a of the main semiconductor element 11 has substantially the same planar shape as the main active region 1a and covers substantially the entire surface of the main active region 1a.

[0037] The electrode pads other than the source pad 21a are disposed apart from each other on the front surface of the semiconductor substrate 10 in the main inactive region 1b. The electrode pads other than the source pad 21a are the gate pad 21b of the main semiconductor element 11, the electrode pad (OC pad) 22 of the current sense section 12, the electrode pads (anode pad and cathode pad) 23a, 23b of the temperature sense section 13, the electrode pad of the overvoltage protection section (hereinafter referred to as OV pad: not shown), and the electrode pad of the arithmetic circuit section (not shown), etc.

[0038] The electrode pads other than the source pad 21a have, for example, a substantially rectangular planar shape and have a surface area necessary for bonding to the terminal pins 48b to 48d (see FIGS. 3 and 4) and wires (not shown) described later. FIG. 1 shows a case where the electrode pads other than the source pad 21a are arranged in a single row in the first direction X along the boundary between the main inactive region 1b and the edge termination region 2. In FIG. 1, the source pad 21a, the gate pad 21b, the OC pad 22, the anode pad 23a, and the cathode pad 23b are illustrated in a rectangular shape denoted by S, G, OC, A, and K, respectively.

[0039] The current sense section 12 is connected in parallel to the main semiconductor element 11, operates under the same conditions as the main semiconductor element 11, and has a function of detecting an overcurrent (OC: Over Current) flowing through the main semiconductor element 11. The current sense section 12 is arranged separately from the main semiconductor element 11. The current sense section 12 is a vertical MOSFET having unit cells with the same configuration as those of the main semiconductor element 11, with a number of unit cells (e.g., about 10) less than the number of unit cells of the main semiconductor element 11 (e.g., 1,000 or more), and has a smaller surface area than the main semiconductor element 11.

[0040] The unit cells of the current sense section 12 are arranged in a part of the region covered by the OC pad 22 on the semiconductor substrate 10 (hereinafter referred to as the sense effective region) 12a. The unit cells of the current sense section 12 are arranged adjacent to each other in a direction parallel to the front surface of the semiconductor substrate 10. The direction in which the unit cells of the current sense section 12 are adjacent to each other is, for example, the same as the direction in which the unit cells of the main semiconductor element 11 are adjacent to each other. The unit cells of the current sense section 12 are connected in parallel to each other by the OC pad 22.

[0041] Also, among the regions covered by the OC pad 22 on the semiconductor substrate 10, the region excluding the sense effective region 12a is a sense ineffective region 12b that does not function as the current sense section 12. No unit cells of the current sense section 12 are arranged in the sense ineffective region 12b. In almost the entire region of the main ineffective region 1b excluding the sense effective region 12a, a p-type base region 34b (see FIGS. 2 and 3), which will be described later, extends from the sense effective region 12a on the surface region of the front surface of the semiconductor substrate 10.

[0042] The temperature sensing unit 13 has a function of detecting the temperature of the main semiconductor element 11 (semiconductor substrate 10) by utilizing the temperature characteristics of a diode. The temperature sensing unit 13 is disposed directly below the anode pad 23a and the cathode pad 23b. The temperature sensing unit 13 may be, for example, a polysilicon diode composed of a polysilicon (poly-Si) layer provided on the interlayer insulating film 40 on the front surface of the semiconductor substrate 10, or may be a diffusion diode formed by a pn junction between a p-type region and an n-type region formed inside the semiconductor substrate 10.

[0043] The overvoltage protection unit (not shown) is, for example, a diode that protects the main semiconductor element 11 from an overvoltage (OV: Over Voltage) such as a surge. The current sensing unit 12, the temperature sensing unit 13, and the overvoltage protection unit are controlled by an arithmetic circuit unit. The arithmetic circuit unit controls the main semiconductor element 11 based on the output signals of the current sensing unit 12, the temperature sensing unit 13, and the overvoltage protection unit. The arithmetic circuit unit is composed of a plurality of semiconductor elements such as a CMOS (Complementary MOS) circuit.

[0044] Next, the cross-sectional structure of the semiconductor device 20 according to the embodiment will be described. FIGS. 2 to 4 are cross-sectional views showing the cross-sectional structure of the active region in FIG. 1. FIG. 5A is a plan view showing the layout of a part of the active region in FIG. 1 as viewed from the front surface side of the semiconductor substrate. FIGS. 5B and 5C are plan views showing another example of the layout of a part of the active region in FIG. 1 as viewed from the front surface side of the semiconductor substrate. FIG. 2 shows the cross-sectional structure of the main active region 1a and the current sensing unit 12 (the cross-sectional structure along the cutting lines X1 - X2 - X3 - X4 in FIG. 1). FIG. 3 shows the cross-sectional structure of the main active region 1a, the sense active region 12a, and the temperature sensing unit 13 (the cross-sectional structures along the cutting lines X1 - X2, the cutting lines X3 - X4, and the cutting line Y1 - Y2 in FIG. 1).

[0045] The main effective region 1a and the sense effective region 12a in FIGS. 2 and 3 each show a part of the unit cells. The cross-sectional structure of the main effective region 1a in FIGS. 2 and 3 corresponds to the cross-sectional structure along the cutting line A-A' in FIG. 5A. FIGS. 2 and 3 show the unit cell closest to the Y side in the second direction of the main effective region 1a. Outside the outermost trench 37a, which is the outer peripheral part of the main effective region 1a, there is no n + -type source region 35a. Also, as shown in FIG. 5A, the cross-sectional structure in the main effective region 1a has an n + -type source region 35a between all adjacent trenches 37a.

[0046] FIG. 4 shows the cross-sectional structure along the cutting line B-B' in FIG. 5A. FIGS. 5A to 5C show a first p + -type region 61a (first high-concentration region: hatched portion surrounded by a broken-line rectangle) and a second p + -type region 62a (second high-concentration region: hatched portion between broken-line vertical lines) in terms of layout for relaxing the electric field applied to the bottom surface of the trench 37a of the main semiconductor element 11. FIGS. 5A to 5C clearly show the planar arrangement of the first and second p + -type regions 61a and 62a. In addition to the first and second p + -type regions 61a and 62a, FIGS. 5A to 5C also illustrate an n + -type source region 35a, a p ++ -type contact region 36a, a trench 37a, etc.

[0047] The main semiconductor element 11 has a trench gate structure MOS gate (insulated gate composed of a three-layer structure of metal-oxide-semiconductor) including a p-type base region 34a, an n + -type source region 35a, a p ++ -type contact region 36a, a trench 37a, a gate insulating film 38a, and a gate electrode 39a on the front surface side of the semiconductor substrate 10 in the main effective region 1a. The semiconductor substrate 10 is formed by sequentially epitaxially growing an n + -type starting substrate 71 made of silicon carbide, an n - -type drift region (first semiconductor region) 32 and a p-type base region (second semiconductor region) 34a, each silicon carbide layer 72 and 73, on the front surface.

[0048] n + The starting substrate 71 is a semiconductor device including the main semiconductor element 11 and the current sensing portion 12. + The main surface of the semiconductor substrate 10 on the p-type silicon carbide layer 73 side is the front surface, and the n + The main surface (n + The back surface is the back surface of mold starting substrate 71. Here, an example will be described in which main semiconductor element 11 and a circuit section that protects and controls main semiconductor element 11 have the same wiring structure using pin-shaped wiring members (terminal pins 48a to 48d, described later), but a wiring structure using wires instead of the pin-shaped wiring members may also be used.

[0049] The trench 37a penetrates the p-type silicon carbide layer 73 in the depth direction Z from the front surface of the semiconductor substrate 10. - The trenches 37a are disposed in a stripe shape extending in a direction (here, a first direction X) parallel to the front surface of the semiconductor substrate 10. The width of the trenches 37a in the short direction (here, a second direction Y) is, for example, about 1.0 μm. A gate electrode 39a is provided inside the trench 37a via a gate insulating film 38a. The gate electrode 39a extends linearly inside the trench 37a in the first direction X in which the trench 37a extends.

[0050] Between the adjacent trenches 37a, p-type base regions 34a and n-type base regions 34b are formed in the surface region of the front surface of the semiconductor substrate 10. + type source region (third semiconductor region) 35a and p ++ The contact regions 36a are selectively provided. + type source region 35a and p ++ The n-type contact regions 36a are selectively provided between the front surface of the semiconductor substrate 10 and the p-type base region 34a and in contact with the p-type base region 34a. + type source region 35a and p ++ The mold contact region 36 a is exposed on the front surface of the semiconductor substrate 10 .

[0051] n + type n source region 35a and p ++ type contact region 36a being exposed on the front surface of the semiconductor substrate 10 means that the n + type source region 35a and p ++ type contact region 36a is in contact with the NiSi film 41a described later inside the first contact hole 40a of the interlayer insulating film 40 described later. n + type n source region 35a and p ++ type contact region 36a are alternately and repeatedly arranged in the same first direction X as the direction in which the gate electrode 39a extends between adjacent trenches 37a.

[0052] n + type n source region 35a is in contact with the gate insulating film 38a on the side wall of the trench 37a, and p ++ type contact region 36a is at a position away from the trench 37a and is in contact with the n + type n source region 35a. n + type n source region 35a has a ladder-shaped planar shape surrounding the p ++ type contact region 36a between adjacent trenches 37a. Therefore, n + type n source region 35a has a portion extending in the first direction X along the side wall of the trench 37a and a portion sandwiched between p ++ type contact regions 36a adjacent to each other in the first direction X.

[0053] p ++ type contact region 36a may not be provided. In this case, instead of the p ++ type contact region 36a, a p-type base region 34a reaches and is exposed on the front surface of the semiconductor substrate 10, and the n + type n source region 35a surrounds the peripheral surface region of the p-type base region 34a exposed on the front surface of the semiconductor substrate 10. Inside the semiconductor substrate 10, between the p-type base region 34a and the n + type drain region 31 (n + type starting substrate 71), there is a p-type base region 34a and an n + type drain region 31 in contact with the n -The type drift region 32 is provided.

[0054] Between the p-type base region 34a and the n - type drift region 32, an n-type current diffusion region (current path region) 33a may be provided in contact with these regions. The n-type current diffusion region 33a is a so-called current spreading layer (Current Spreading Layer: CSL) that reduces the spreading resistance of carriers. Also, inside the semiconductor substrate 10, at a position closer to the n + type drain region 31 than the bottom surface of the trench 37a, first and second p + type regions 61a, 62a are provided to relax the electric field applied to the bottom surface of the trench 37a.

[0055] The first and second p + type regions 61a, 62a may terminate inside the n-type current diffusion region 33a and may be surrounded by the n-type current diffusion region 33a (not shown). The first and second p + type regions 61a, 62a may terminate at the same position as the n-type current diffusion region 33a on the drain side and may be in contact with the n - type drift region 32 (not shown). Or, the first and second p + type regions 61a, 62a may extend to the drain side of the n-type current diffusion region 33a and may terminate inside the n - type drift region 32 (see FIGS. 2 to 4). In other words, the n-type current diffusion region 33a may be formed deeper or shallower than the first and second p + type regions 61a, 62a.

[0056] The first p + type region 61a is provided away from the p-type base region 34a and faces the bottom surface of the trench 37a in the depth direction Z. The first p + type region 61a may or may not be in contact with the bottom surface of the trench 37a. The first p + type region 61a is scattered in the same first direction X as the direction in which the gate electrode 39a extends (see FIG. 5A). In the portion facing the bottom surface of the trench 37a in the depth direction Z, in the first direction X, the first p +The p-type regions 61a and the n-type current diffusion regions 33a are alternately and repeatedly arranged. Thereby, an electric field relaxation effect at the bottom surface of the trench 37a due to the p-type region 61a can be obtained, and a low on-resistance can be achieved. + The p-type region 61a has, for example, a substantially rectangular planar shape. The interval w2 between the p-type regions 61a adjacent to each other in the first direction X is, for example, about 1.0 μm or less.

[0057] The p-type + region 61a. The width w12 of the p-type region 61a in the first direction X is, for example, not less than the processing limit value by ion implantation and about 1.0 μm or less, and preferably substantially the same as the interval w2 between the p-type regions 61a adjacent to each other in the first direction X. + The width w12 of the p-type region 61a in the first direction X is, for example, preferably narrower than the width w21 of the p-type region 61a in the second direction Y. + By setting the arrangement and dimensions of the p-type region 61a in this way, a predetermined breakdown voltage and a predetermined low on-resistance can be satisfied as described later (see FIG. 12). In order to maintain the predetermined breakdown voltage, the width w21 of the p-type region 61a in the second direction Y needs to be at least 50% or more, and more preferably 100% or more, with respect to the width in the short side direction of the trench 37a. + Also, in order to achieve a low on-resistance, the width w21 of the p-type region 61a in the second direction Y is preferably 150% or less with respect to the width in the short side direction of the trench 37a. The widths w21 and w22 of the first and second p-type regions 61a and 62a in the second direction Y are substantially the same. + The width w12 of the p-type region 61a in the first direction X is, for example, the width w12 of the p-type region 61a in the first direction X. + The width w21 of the p-type region 61a in the second direction Y is preferably narrower than the width w21 of the p-type region 61a in the second direction Y.

[0058] As described above, by setting the arrangement and dimensions of the p-type region 61a, a predetermined breakdown voltage and a predetermined low on-resistance can be satisfied as described later (see FIG. 12). + In order to maintain the predetermined breakdown voltage, the width w21 of the p-type region 61a in the second direction Y needs to be at least 50% or more, and more preferably 100% or more, with respect to the width in the short side direction of the trench 37a. + Also, in order to achieve a low on-resistance, the width w21 of the p-type region 61a in the second direction Y is preferably 150% or less with respect to the width in the short side direction of the trench 37a. The widths w21 and w22 of the first and second p-type regions 61a and 62a in the second direction Y are substantially the same. + The width w21 of the p-type region 61a in the second direction Y is preferably 150% or less with respect to the width in the short side direction of the trench 37a. The widths w21 and w22 of the first and second p-type regions 61a and 62a in the second direction Y are substantially the same. + The widths w21 and w22 of the first and second p-type regions 61a and 62a in the second direction Y are substantially the same. Having substantially the same width means having the same width within a range including an allowable error due to process variations.

[0059] The second p-type + region 62a is disposed between adjacent trenches 37a, and the first p-type +The type region 61a is provided away from the trench 37a and is in contact with the p-type base region 34a. The second p + type region 62a extends linearly in the first direction X, which is the same direction as the extension direction of the trench 37a, with substantially the same length as the trench 37a (see Fig. 5A). The second p + type region 62a faces the first p + type region 61a in the second direction Y via the n-type current diffusion region 33a, and faces the trench 37a via the n-type current diffusion region 33a at a portion that does not face the first p + type region 61a.

[0060] Therefore, the n-type current diffusion region 33a has a width w11 in the second direction Y that is wider at the second portion 64a between the type region 62a and the trench 37a than at the first portion 63a between the type region 62a and the first p + type regions 61a, 62a at the same depth position (w11 > w1). Thereby, when the main semiconductor element 11 is on, the JFET resistance of the main semiconductor element 11 can be lowered at the second portion 64a of the n-type current diffusion region 33a compared to the first portion 63a. + type region 62a and the first p + type region 61a. + Also, as described above, the second p

[0061] type region 62a extends in the first direction X with substantially the same length as the trench 37a between adjacent trenches 37a. For this reason, even if the first p + type region 61a facing the bottom surface of the trench 37a is partially thinned out, in the portion where the first p + type region 61a does not exist, the electric field applied to the bottom surface of the trench 37a can be relaxed by the second p + type region 62a. Thereby, it is possible to suppress the partial application of a high electric field to the bottom surface of the trench 37a. + type region 62a.

[0062] In Fig. 5A, all of the first p + type regions 61a are at a floating potential, but by electrically connecting to the second p + type region 62a, the first p+ The type region 61a may be fixed to the potential of the source pad 21a. + By fixing the potential of the mold region 61a to the potential of the source pad 21a, the electric field applied to the bottom surface of the trench 37a can be reliably relaxed. Such a modified example is shown in Figures 5B and 5C. For example, as shown in Figure 5B, the first and second p + p that connects the mold regions 61a and 62a + Type area 65 (1st, 2p + A hatched portion (connecting area) different from the mold areas 61a and 62a may be selectively provided. + For every three mold regions 61a, + Mold region 61a and second p + The p + A mold area 65 is provided.

[0063] Also, as shown in FIG. 5C, + The mold region 61a is extended in the second direction Y to form the first p + The end of the mold region 61a is + By connecting the first and second mold regions 62a and 62b, + The mold regions 61a and 62a may be arranged in a lattice pattern. Such a configuration has the advantage of widening the safe operating area. + Since the entire type region 61a is fixed to the potential of the source pad 21a, + The first p regions adjacent to each other in the first direction X are closer to each other than when the type regions 61a are at a floating potential (see FIG. 5A). + The distance w2 between the first p-type regions 61a may be increased to increase the area in which the JFET resistance is reduced. + The interval w2 between the mold regions 61a is, for example, about 0.5 μm or more and 1.5 μm or less.

[0064] The interlayer insulating film 40 is provided on substantially the entire front surface of the semiconductor substrate 10 and covers the gate electrode 39a in the main active region 1a. The gate electrodes 39a of all the unit cells are electrically connected to the gate pad 21b (see FIG. 1). A first contact hole 40a penetrating the interlayer insulating film 40 in the depth direction Z is provided in the main active region 1a. In the first contact hole 40a, an n + -type source region 35a and a p ++ -type contact region 36a are exposed.

[0065] The nickel silicide (NiSi, Ni2Si, or thermally stable NiSi2; hereinafter collectively referred to as NiSi) film 41a makes an ohmic contact with the semiconductor substrate 10 inside the first contact hole 40a and is electrically connected to the n + -type source region 35a and the p ++ -type contact region 36a. When the p ++ -type contact region 36a is not provided, instead of the p ++ -type contact region 36a, the p-type base region 34a is exposed in the first contact hole 40a and is electrically connected to the NiSi film 41a.

[0066] On the entire surface of the interlayer insulating film 40 and the NiSi film 41a in the main active region 1a, a barrier metal 46a is provided along the surfaces of the interlayer insulating film 40 and the NiSi film 41a. The barrier metal 46a has a function of preventing mutual reaction between the respective metal films of the barrier metal 46a or between regions facing each other with the barrier metal 46a interposed therebetween. The barrier metal 46a may have, for example, a stacked structure in which a first titanium nitride (TiN) film 42a, a first titanium (Ti) film 43a, a second TiN film 44a, and a second Ti film 45a are stacked in this order.

[0067] The first TiN film 42a covers the entire surface of the interlayer insulating film 40. The first TiN film 42a is not provided on the front surface of the semiconductor substrate 10 in the portion where the NiSi film 41a is formed. The first Ti film 43a is provided on the surfaces of the first TiN film 42a and the NiSi film 41a. The second TiN film 44a is provided on the surface of the first Ti film 43a. The second Ti film 45a is provided on the surface of the second TiN film 44a. A source pad 21a is provided on the entire surface of the second Ti film 45a.

[0068] The source pad 21a is electrically connected to the n + -type source region 35a and the p ++ -type contact region 36a via the barrier metal 46a and the NiSi film 41a. The source pad 21a may be, for example, an aluminum (Al) film, an aluminum-silicon (Al-Si) film, or an aluminum-silicon-copper (Al-Si-Cu) film having a thickness of about 5 μm. The source pad 21a, the barrier metal 46a, and the NiSi film 41a function as the source electrode of the main semiconductor element 11.

[0069] One end of the terminal pin 48a is joined onto the source pad 21a via the plating film 47a and a solder layer (not shown). The other end of the terminal pin 48a is joined to a metal bar (not shown) arranged so as to face the front surface of the semiconductor substrate 10. Further, the other end of the terminal pin 48a is exposed outside a case (not shown) on which the semiconductor substrate 10 is mounted and is electrically connected to an external device (not shown). The terminal pin 48a is solder-joined to the plating film 47a in a state of standing substantially perpendicular to the front surface of the semiconductor substrate 10.

[0070] The terminal pin 48a is a rod-shaped (cylindrical) wiring member having a predetermined diameter, and is connected to an external ground potential (lowest potential). The terminal pin 48a is an external connection terminal that extracts the potential of the source pad 21a to the outside. The first and second protective films 49a, 50a are, for example, polyimide films. The first protective film 49a covers the surface of the source pad 21a except for the plating film 47a. The second protective film 50a covers the boundary between the plating film 47a and the first protective film 49a.

[0071] The drain electrode 51 is disposed on the rear surface (n + The drain electrode 51 is in ohmic contact with the entire surface of the insulating substrate 71 (the back surface of the mold starting substrate 71). On the drain electrode 51, a drain pad (electrode pad: not shown) is provided, for example, with a laminated structure in which a Ti film, a nickel (Ni) film, and a gold (Au) film are laminated in this order. The drain pad is solder-bonded to a metal base plate (not shown) of the insulating substrate, for example, made of copper (Cu) foil, and at least a portion of the drain pad is in contact with the base of a cooling fin (not shown) via the metal base plate.

[0072] In this way, by joining the terminal pin 48a to the source pad 21a on the front surface of the semiconductor substrate 10 and joining the drain pad on the back surface to the metal base plate of the insulating substrate, the semiconductor substrate 10 has a double-sided cooling structure with cooling structures on both main surfaces. Heat generated in the semiconductor substrate 10 is dissipated from the fins of the cooling fins via the metal base plate joined to the drain pad on the back surface of the semiconductor substrate 10, and is also dissipated from the metal bar to which the terminal pin 48a on the front surface of the semiconductor substrate 10 is joined.

[0073] The current sensing section 12 includes p-type base regions 34b and n-type + Type source region 35b, p ++ The current sensing section 12 includes a p-type contact region 36b, a trench 37b, a gate insulating film 38b, a gate electrode 39b, and an interlayer insulating film 40. Each portion of the MOS gate of the current sensing section 12 is provided in the sense effective region 12a of the main ineffective region 1b. The p-type base region 34b is an n-type base region of the surface region of the front surface of the semiconductor substrate 10. -The type region 32a is separated from the p-type base region 34a of the main semiconductor element 11.

[0074] The p-type base region 34b extends, for example, from the sense active region 12a to substantially the entire region of the main inactive region 1b. The current sense section 12 may have an n-type current diffusion region 33b and first and second p- + type regions 61b, 62b. In this case, the n-type current diffusion region 33b and the second p- + type region 62b are arranged in the same manner as the main semiconductor element 11. The first p- + type region 61b may be dotted in the first direction X in the same manner as the main semiconductor element 11, or may extend linearly in the first direction X in the same manner as the conventional structure (see reference numeral 261 in FIG. 14).

[0075] The first p- + type region 61b when dotted in the first direction X, the arrangement and dimensions of the first p- + type region 61b may be the same as those of the main semiconductor element 11. The p- ++ type contact region 36b may not be provided. In this case, in the same manner as the main semiconductor element 11, instead of the p- ++ type contact region 36b, the p-type base region 34b is exposed on the front surface of the semiconductor substrate 10. The gate electrodes 39b of all unit cells are electrically connected to the gate pad 21b (see FIG. 1). The gate electrodes 39b are covered with an interlayer insulating film 40.

[0076] In the sense active region 12a, the interlayer insulating film 40 is provided with a second contact hole 40b that penetrates in the depth direction Z and reaches the semiconductor substrate 10, and the n- + type source region 35b and the p- ++ type contact region 36b are exposed. On the front surface of the semiconductor substrate 10 in the sense active region 12a, in the same manner as the main semiconductor element 11, a NiSi film 41b and a barrier metal 46b are provided. Reference numerals 42b to 45b are the first TiN film, the first Ti film, the second TiN film, and the second Ti film that constitute the barrier metal 46b, respectively.

[0077] The NiSi film 41b makes an ohmic contact with the semiconductor substrate 10 inside the second contact hole 40b, and is electrically connected to the n + -type source region 35b and the p ++ -type contact region 36b. When the p ++ -type contact region 36b is not provided, instead of the p-type contact region 36b, the p-type base region 34b is exposed to the second contact hole 40b and is electrically connected to the NiSi film 41b. The barrier metal 46b extends on the interlayer insulating film 40 in the sense-invalid region 12b. ++ On the entire surface of the barrier metal 46b, apart from the source pad 21a, the OC pad 22 is provided. The OC pad 22 is electrically connected to the n

[0078] -type source region 35b and the p-type base region 34b through the barrier metal 46b and the NiSi film 41b. The OC pad 22 is made of, for example, the same material as the source pad 21a and is formed simultaneously with the source pad 21a. The OC pad 22, the barrier metal 46b, and the NiSi film 41b function as the source electrode of the current sense section 12. + On the OC pad 22, the terminal pin 48b is joined with the same wiring structure as the wiring structure on the source pad 21a. The terminal pin 48b is a round bar-shaped (cylindrical) wiring member having a diameter smaller than that of the terminal pin 48a. The terminal pin 48b is, for example, an external connection terminal for taking out the potential of the OC pad 22 to the outside, and connects the OC pad 22 to the ground potential through an external resistor (not shown). The reference numerals 47b, 49b, 50b are the plating film and the first and second protective films that constitute the wiring structure on the OC pad 22, respectively.

[0079] The p-type base region 34a in the main effective region 1a and the p-type base region 34b in the sense effective region 12a are the n of the surface region of the semiconductor substrate 10, which is not shown in the figure

[0080] -type impurity regions (not shown) are formed by the same process. -The type region is separated from a p-type region (not shown) for element isolation. The p-type region for element isolation is provided in a substantially rectangular shape surrounding the active region 1 in the edge termination region 2, and is a floating p-type region formed by a pn junction with the n-type drift region 32 to electrically isolate the active region 1 and the edge termination region 2. - It is a floating p-type region formed by a pn junction of the p-type polysilicon layer 81 which is a p-type anode region and the n-type polysilicon layer 82 which is an n-type cathode region, for example.

[0081] The temperature sense section 13 is, for example, a polysilicon diode formed by a pn junction of a p-type polysilicon layer 81 which is a p-type anode region and an n-type polysilicon layer 82 which is an n-type cathode region (FIG. 3). The p-type polysilicon layer 81 and the n-type polysilicon layer 82 are provided on the interlayer insulating film 40 in the main inactive region 1b. The temperature sense section 13 is electrically insulated from the semiconductor substrate 10, the main semiconductor element 11, and the current sense section 12 by the interlayer insulating film 40.

[0082] The anode pad 23a and the cathode pad 23b are in contact with the p-type polysilicon layer 81 and the n-type polysilicon layer 82 at the third and fourth contact holes 83a and 83b of the interlayer insulating film 83 covering them, respectively. The anode pad 23a and the cathode pad 23b are made of, for example, the same material as the source pad 21a and are formed simultaneously with the source pad 21a. Terminal pins 48c and 48d are joined on the anode pad 23a and the cathode pad 23b, respectively, with the same wiring structure as the wiring structure on the source pad 21a.

[0083] The terminal pins 48c and 48d are external connection terminals for taking out the potentials of the anode pad 23a and the cathode pad 23b to the outside, and are round bar-shaped wiring members having a predetermined diameter according to the current capacity of the temperature sense section 13. References 47c and 47d are plating films constituting the wiring structure on the anode pad 23a and the wiring structure on the cathode pad 23b, respectively. References 49c and 50c are the first and second protective films constituting the wiring structure on the temperature sense section 13, respectively. A barrier metal is not provided on the temperature sense section 13.

[0084] In addition, a gate pad portion 14 in which a gate pad 21b of the main semiconductor element 11 is disposed is provided in the main invalid region 1b (see FIG. 1). The gate pad 21b is provided separately from other electrode pads on the interlayer insulating film 40 in the main invalid region 1b. The gate pad 21b is formed of, for example, the same material as the source pad 21a and is formed simultaneously with the source pad 21a. A terminal pin (not shown) is joined to the gate pad 21b with the same wiring structure as the wiring structure on the source pad 21a.

[0085] The operation of the semiconductor device 20 according to the embodiment will be described. When a voltage equal to or higher than the gate threshold voltage is applied to the gate electrode 39a of the main semiconductor element 11 in a state where a positive voltage (forward voltage) is applied to the source electrode (source pad 21a) of the main semiconductor element 11 with respect to the drain electrode 51, a channel (n-type inversion layer) is formed in a portion along the trench 37a of the p-type base region 34a of the main semiconductor element 11. As a result, a current flows from the n-type drain region 31 of the main semiconductor element 11 through the channel toward the n-type source region 35a, and the main semiconductor element 11 is turned on. + The n-type drain region 31 to the n-type source region 35a through the channel, and the main semiconductor element 11 is turned on. + The n-type drain region 31 to the n-type source region 35a through the channel, and the main semiconductor element 11 is turned on.

[0086] The first and second portions 63a and 64a (JFET regions) of the n-type current diffusion region 33a serve as a path for the current flowing through the channel when the main semiconductor element 11 is turned on. When the main semiconductor element 11 is turned on, depletion layers spread from the pn junctions between the first and second p-type regions 61a and 62a and the n-type current diffusion region 33a to the first and second portions 63a and 64a of the n-type current diffusion region 33a. However, a wider portion (a portion where the depletion layer of the n-type current diffusion region 33a has not spread) serving as a current path can be left in the second portion 64a than in the first portion 63a of the n-type current diffusion region 33a. + The reason for this is that the first p

[0087] The reason for this is that the first p +This is because in the region where there is no type region 61a, the width w11 in the second direction Y of a part (the second part 64a) of the first and second parts 63a and 64a of the n-type current diffusion region 33a is wide. Since the region through which current flows expands by the amount by which the width w11 in the second direction Y of the second part 64a of the n-type current diffusion region 33a expands, it becomes easier for current to flow through the second part 64a of the n-type current diffusion region 33a. Furthermore, as the unit cells of the main semiconductor element 11 are miniaturized, even if the width (the width w1 in the second direction Y of the first part 63a of the n-type current diffusion region 33a) between the mutually adjacent first and second p + type regions 61a and 62a becomes narrow up to the processing limit (for example, about 0.2 μm), the JFET resistance of the main semiconductor element 11 can be reduced. Also, since the interval w2 between the first p + type regions 61a adjacent to each other in the first direction X is suppressed within 1.0 μm, holes do not reach the gate insulating film 38a during switching. Therefore, the ability to relax the electric field applied to the bottom surface of the trench 37a can be maintained.

[0088] Under the same conditions as the main semiconductor element 11, when a voltage equal to or higher than the gate threshold voltage is applied to the gate electrode 39b of the current sense section 12 in a state where a positive voltage (forward voltage) is applied to the drain electrode 51 with respect to the source electrode (OC pad 22) of the current sense section 12, a channel (n-type inversion layer) is formed in a portion along the trench 37b of the p-type base region 34b of the current sense section 12. Thereby, current (hereinafter referred to as sense current) flows from the n + type drain region 31 to the n + type source region 35b, and the current sense section 12 is turned on.

[0089] When the main semiconductor element 11 is turned on, the current sense section 12 is turned on. When sense current flows through the current sense section 12, the n +A voltage drop occurs across a resistor (not shown) connected between the type-source region 35b and the ground point. Since the sense current of the current sense section 12 increases according to the magnitude of the current flowing through the main semiconductor element 11, the voltage drop across the resistor also increases. Therefore, by monitoring the magnitude of the voltage drop across this resistor, it is possible to detect an overcurrent in the main semiconductor element 11.

[0090] On the other hand, when a voltage lower than the gate threshold voltage is applied to the gate electrode 39a of the main semiconductor element 11, the first and second p + type regions 61a, 62a and the p-type base region 34a, and the n-type current diffusion region 33a and the n - type drift region 32 are reverse-biased to maintain the off state. A voltage lower than the gate threshold voltage is also applied to the gate electrode 39b of the current sense section 12, and the current sense section 12 is configured such that the first and second p + type regions 61b, 62b and the p-type base region 34b, and the n-type current diffusion region 33b and the n - type drift region 32 are reverse-biased to maintain the off state.

[0091] The first and second p + type regions 61a, 62a and the n-type current diffusion region 33a and the n - type drift region 32 are located on the drain side of the bottom surface of the trench 37a, so that the electric field applied to the bottom surface of the trench 37a when the main semiconductor element 11 is off is relaxed. The first and second p + type regions 61b, 62b and the n-type current diffusion region 33b and the n - type drift region 32 are located on the drain side of the bottom surface of the trench 37b, so that the electric field applied to the bottom surface of the trench 37b when the current sense section 12 is off is relaxed.

[0092] Also, when the main semiconductor element 11 is off, by applying a negative voltage to the drain electrode 51 with respect to the source electrode (source pad 21a), the first and second p + type regions 61a, 62a and the n-type current diffusion region 33a and the n -A parasitic diode formed by a pn junction with the drift region 32 can have a forward current flowing through it. For example, a parasitic diode built into the semiconductor substrate 10 can be used as a reflux diode for protecting the main semiconductor element 11 itself.

[0093] During the operation of the main semiconductor element 11, a forward current continuously flows from the anode pad 23a through the pn junction between the anode region (p-type polysilicon layer 81) and the cathode region (n-type polysilicon layer 82) to the cathode pad 23b in the temperature sense section 13 at all times. The curve (forward voltage characteristic) showing the relationship between the forward current If and the forward voltage Vf of the temperature sense section 13 depends on temperature, and the forward voltage Vf becomes smaller as the temperature increases. Therefore, the forward voltage characteristic of the temperature sense section 13 is acquired in advance and stored, for example, in a storage section (not shown).

[0094] During the operation of the main semiconductor element 11, for example, the forward voltage Vf (voltage drop in the temperature sense section 13) generated between the anode pad 23a and the cathode pad 23b of the temperature sense section 13 at room temperature (for example, about 25°C) is continuously monitored by an arithmetic circuit section. When the forward voltage Vf of the temperature sense section 13 decreases, assuming that a high-temperature portion has occurred in the main semiconductor element 11 (semiconductor substrate 10), the supply of the gate voltage to the main semiconductor element 11 is stopped by the arithmetic circuit section to stop the operation of the main semiconductor element 11.

[0095] Next, a method for manufacturing the semiconductor device 20 according to the embodiment will be described. FIGS. 6 to 11 are cross-sectional views showing the state during the manufacture of the semiconductor device according to the embodiment. FIGS. 6 to 11 show only the state during the manufacture of the cross-sectional structure of the main semiconductor element 11 at the cut line A - A' in FIG. 5A, but each part of the semiconductor element (see FIGS. 1 to 3) formed on the same semiconductor substrate 10 is formed simultaneously with each part having the same impurity concentration and depth as each part of the main semiconductor element 11.

[0096] First, as shown in FIG. 6, n made of silicon carbide +As the p-type starting substrate (semiconductor wafer) 71, for example, a nitrogen (N)-doped silicon carbide single crystal substrate is prepared. Next, an n + -type epitaxial layer 72 doped with nitrogen at a lower concentration than the p-type starting substrate 71 is epitaxially grown on the front surface of the p-type starting substrate 71. When the main semiconductor element 11 is of a breakdown voltage of 3300 V class, the thickness t1 of the n + -type silicon carbide layer 72 may be, for example, about 30 μm. - - - +

[0097] Next, as shown in FIG. 7, by photolithography and ion implantation of p-type impurities such as Al, for example, in the main active region 1a, a first p - -type region 61a and a p + -type region 91 are selectively formed on the surface region of the n + -type silicon carbide layer 72, respectively. The first p + -type region 61a and the p + -type region 91 are alternately and repeatedly arranged in the second direction Y (see FIG. 5A). The first p + -type region 61a is arranged at predetermined intervals w2 in the first direction X (see FIG. 5A).

[0098] Next, by photolithography and ion implantation of n-type impurities such as nitrogen, for example, an n-type region 92 is formed over the entire surface region of the n - -type silicon carbide layer 72 in the main active region 1a. The n-type region 92 is formed in contact with these p + -type region 61a and the p + -type region 91 between the p + -type regions 61a, 91. The formation order of the n-type region 92 and the p + -type regions 61a, 91 may be interchanged.

[0099] The distance d2 between adjacent p + -type regions 61a, 91 is, for example, about 1.5 μm. The p + -type regions 61a, 91 have, for example, a depth d1 and an impurity concentration of about 0.5 μm and 5.0×10 18 / cm 3It is at this level. The depth d3 and the impurity concentration of the n-type region 92 are, for example, about 0.4 μm and 1.0×10 17 / cm 3 respectively. The non-ion-implanted portion of the n - -type silicon carbide layer 72 becomes the n - -type drift region 32.

[0100] Next, as shown in FIG. 8, an n - -type silicon carbide layer is further doped with an n-type impurity such as nitrogen, etc. on the n - -type silicon carbide layer 72, and epitaxially grown to a thickness t2 of about 0.5 μm, for example, to thicken the thickness of the n - -type silicon carbide layer 72. As a result, the thickness of the n - -type silicon carbide layer 72 becomes a predetermined thickness. The impurity concentration of the thickened portion 72a of the n - -type silicon carbide layer 72 may be, for example, 3×10 15 / cm 3 or the like.

[0101] Next, by photolithography and ion implantation of a p-type impurity such as Al, a p - -type region 93 reaching the p + -type region 91 is selectively formed in the thickened portion 72a of the n + -type silicon carbide layer 72. Next, by photolithography and ion implantation of an n-type impurity such as nitrogen, etc., an n-type region 94 reaching the n-type region 92 is selectively formed in the thickened portion 72a of the n - -type silicon carbide layer 72.

[0102] As a result, the p + -type regions 91 and 93 adjacent to each other in the depth direction Z are connected to form the second p + -type region 62a. The n-type regions 92 and 94 adjacent to each other in the depth direction Z are connected to form the n-type current diffusion region 33a. The conditions such as the impurity concentration of the p + -type region 93 and the n-type region 94 are, for example, the same as those of the p + -type region 91 and the n-type region 92 respectively. The formation order of the p + -type region 93 and the n-type region 94 may be interchanged.

[0103] Next, as shown in FIG. 9, n - On the n-type silicon carbide layer 72, a p-type silicon carbide layer 73 doped with a p-type impurity such as Al is epitaxially grown. The thickness t3 and the impurity concentration of the p-type silicon carbide layer 73 are, for example, about 1.3 μm and 4.0×10 17 / cm 3 respectively. Through the steps up to this point, a semiconductor substrate 10 (semiconductor wafer) in which an n-type silicon carbide layer 72 and a p-type silicon carbide layer 73 are sequentially stacked on an n-type starting substrate 71 is fabricated. + type starting substrate 71 with an n - type silicon carbide layer 72 and a p-type silicon carbide layer 73 is fabricated.

[0104] Next, a process consisting of photolithography and ion implantation is repeated under different conditions, and an n + type source region 35a and a p ++ type contact region 36a are selectively formed on the surface region of the p-type silicon carbide layer 73 in the main active region 1a, respectively. The portions between the n + type source region 35a and the p ++ type contact region 36a of the p-type silicon carbide layer 73 in the main active region 1a and the n - type silicon carbide layer 72 become a p-type base region 34a.

[0105] Next, for the diffusion regions (the first and second p + type regions 61a, 62a, the n-type current diffusion region 33a, the n + type source region 35a and the p ++ type contact region 36a) formed by ion implantation, impurity activation is performed by heat treatment (activation annealing) at a temperature of about 1700° C. for about 2 minutes, for example. The activation annealing may be performed once collectively after the formation of all the diffusion regions, or may be performed each time a diffusion region is formed by ion implantation.

[0106] Next, as shown in FIG. 10, by photolithography and etching, from the front surface of the semiconductor substrate 10, n +Reach the n-type current diffusion region 33a through the p-type source region 35a and the p-type base region 34a, and form a first p in the depth direction Z (see FIGS. 2 and 3). + Form a trench 37a facing the first p + type region 61a. The trench 37a may reach, for example, the first p + type region 61a and terminate inside the first p

[0107] Next, as shown in FIG. 11, form a gate insulating film 38a along the front surface of the semiconductor substrate 10 and the inner wall of the trench 37a. The gate insulating film 38a may be, for example, a thermal oxide film formed by thermally oxidizing the semiconductor surface at a temperature of about 1000 ° C. in an oxygen (O2) atmosphere, or may be a deposited film by high-temperature oxidation (HTO: High Temperature Oxide).

[0108] Next, deposit (form), for example, a phosphorus (P)-doped polysilicon layer on the front surface of the semiconductor substrate 10 so as to fill the inside of the trench 37a. Next, selectively remove the polysilicon layer by photolithography and etching, and leave only the portion of the polysilicon layer that will become the gate electrode 39a inside the trench 37a.

[0109] Also, when forming each part of the MOS gate of the main semiconductor element 11 as described above, for each part of the semiconductor elements (high-functional parts such as the current sense part 12, the overvoltage protection part (not shown), and the arithmetic circuit part (not shown): see FIGS. 2 and 3) fabricated on the same semiconductor substrate 10, they may be formed simultaneously with the parts of the main semiconductor element 11 having the same impurity concentration and depth.

[0110] The main semiconductor element 11 is arranged in the island-shaped p-type base region 34a formed in the surface region of the front surface of the semiconductor substrate 10, so that the p-type base region 34a and the n -It is separated from other semiconductor elements fabricated on the same semiconductor substrate 10 by pn junction isolation with the drift region 32 of type O. The current sense section 12 may have the same structure as the main semiconductor element 11 and may be disposed within the island-shaped p-type base region 34b formed in the surface region of the front surface of the semiconductor substrate 10.

[0111] Next, an interlayer insulating film 40 such as BPSG (Boro Phospho Silicate Glass) or PSG (Phospho Silicate Glass) is formed, for example, with a thickness of 1 μm over the entire front surface of the semiconductor substrate 10 so as to cover the gate electrode 39a. The temperature sense section 13 may form a p-type polysilicon layer 81 and an n-type polysilicon layer 82 (see FIG. 3) on the interlayer insulating film 40 and may be covered with an interlayer insulating film 83.

[0112] Next, first and second contact holes 40a and 40b penetrating the interlayer insulating film 40 and the gate insulating film 38a in the depth direction Z are formed by photolithography and etching. Third and fourth contact holes 83a and 83b penetrating the interlayer insulating film 83 in the depth direction Z are formed. In the first contact hole 40a, the n + -type source region 35a and p ++ -type contact region 36a are exposed.

[0113] In the second contact hole 40b, the n + -type source region 35b and p ++ -type contact region 36b are exposed. In the third and fourth contact holes 83a and 83b, the p-type polysilicon layer 81 and the n-type polysilicon layer 82 of the temperature sense section 13 are exposed, respectively. Next, the interlayer insulating films 40 and 83 are planarized (reflowed) by heat treatment.

[0114] Next, a first TiN film 42a that covers only the interlayer insulating film 40 is formed. Next, an NiSi film 41a is formed on the front surface of the semiconductor substrate 10 at the portion exposed in the first contact hole 40a. Next, a barrier metal 46a is formed by sequentially laminating a first Ti film 43a, a second TiN film 44a, and a second Ti film 45a so as to cover the NiSi film 41a and the first TiN film 42a. Next, a source pad 21a is deposited on the second Ti film 45a.

[0115] Also, in the second contact hole 40b as well, NiSi films 41b and barrier metals 46b are formed with the same configuration as these metal films simultaneously with the NiSi film 41a and the barrier metal 46a. In the second to fourth contact holes 40b, 83a, 83b as well, OC pads 22, anode pads 23a, and cathode pads 23b are formed with the same configuration as the source pad 21a simultaneously with the source pad 21a.

[0116] Also, a drain electrode 51 that makes an ohmic contact with the back surface of the semiconductor substrate 10 is formed, and a drain pad (not shown) is formed by sequentially laminating, for example, a Ti film, an Ni film, and a gold (Au) film on the surface of the drain electrode 51.

[0117] Next, first protective films 49a to 49c made of polyimide are selectively formed on the front surface of the semiconductor substrate 10, and the respective different electrode pads 21a, 22, 23a, 23b are exposed in the openings of these first protective films 49a to 49c. Next, after general plating pretreatment, plating films 47a to 47d are formed on the portions of the electrode pads 21a, 22, 23a, 23b exposed in the openings of the first protective films 49a to 49c by general plating treatment.

[0118] Next, the plating films 47a to 47d are dried by heat treatment (baking). Next, second protective films 50a to 50c made of polyimide are formed to cover the respective boundaries between the plating films 47a to 47d and the first protective films 49a to 49c. Next, the strength of the polyimide films (the first protective films 49a to 49c and the second protective films 50a to 50c) is improved by heat treatment (curing). Next, terminal pins 48a to 48d are joined to the plating films 47a to 47d by solder layers, respectively.

[0119] Although not shown, on the gate pad 21b as well, a wiring structure in which a first protective film, a plating film, and a second protective film are sequentially formed and a terminal pin is joined by a solder layer is formed simultaneously with the wiring structure on the electrode pads 21a, 22, 23a, and 23b. Thereafter, the semiconductor substrate 10 (semiconductor wafer) is diced (cut) into individual chip-like pieces, whereby the semiconductor device 20 shown in FIGS. 1 to 5 is completed.

[0120] As described above, according to the embodiment, among the first and second p-type regions that relax the electric field applied to the bottom surface of the trench, the first p-type regions facing the bottom surface of the trench in the depth direction are arranged in a scattered manner in the first direction, so that the first p-type regions are partially thinned compared to the conventional structure. As a result, since the current path flowing when the main semiconductor element is turned on becomes partially wider in the JFET region, along with the miniaturization of the unit cell of the main semiconductor element, even if the width between the adjacent first and second p-type regions becomes narrow, the JFET resistance of the main semiconductor element is reduced and the on-resistance is reduced. + Among the first p-type regions of the first and second p-type regions that relax the electric field applied to the bottom surface of the trench, + by arranging the first p-type regions facing the bottom surface of the trench in the depth direction in a scattered manner in the first direction, + the first p-type regions are partially thinned compared to the conventional structure. As a result, since the current path flowing when the main semiconductor element is turned on becomes partially wider in the JFET region, along with the miniaturization of the unit cell of the main semiconductor element, even if the width between the adjacent first and second p-type regions becomes narrow, the JFET resistance of the main semiconductor element is reduced and the on-resistance is reduced. + Among the first and second p-type regions that relax the electric field applied to the bottom surface of the trench, even if the width between the adjacent first and second p-type regions becomes narrow, the JFET resistance of the main semiconductor element is reduced and the on-resistance is reduced.

[0121] Also, according to the embodiment, among the first and second p-type regions that relax the electric field applied to the bottom surface of the trench, the second p-type regions arranged between adjacent trenches are extended in the first direction with substantially the same length as the trench. Further, the width of the portion where the first p-type region does not exist in the portion facing the bottom surface of the trench is limited to 1.0 μm or less. Thereby, in the portion facing the bottom surface of the trench, + Among the first and second p-type regions that relax the electric field applied to the bottom surface of the trench, the second p-type regions arranged between adjacent trenches are extended in the first direction with substantially the same length as the trench. + Also, the second p-type regions arranged between adjacent trenches among the first and second p-type regions that relax the electric field applied to the bottom surface of the trench are extended in the first direction with substantially the same length as the trench. + the width of the portion where the first p-type region does not exist in the portion facing the bottom surface of the trench is limited to 1.0 μm or less. Thereby, in the portion facing the bottom surface of the trench,+ Even if the mold region is partially absent, the first p + In the portion where the mold region does not exist, the second p + The mold region reduces the electric field applied to the bottom surface of the trench, making it possible to prevent a high electric field from being applied partially to the bottom surface of the trench.

[0122] Therefore, the first and second + The mold region protects the entire bottom surface of the trench to obtain a predetermined breakdown voltage. + By partially thinning out the type region, the on-resistance of the main semiconductor element can be reduced, and the current capacity of the main semiconductor element can be improved. In addition, by suppressing the application of a high electric field to the bottom of the trench, the n - This can suppress a decrease in the amount of hole current (cut-off current) flowing through the type drift region 32 toward the source electrode and discharged to the source electrode.

[0123] In addition, in MOSFETs using silicon as a semiconductor material, a trench gate structure is used to reduce the on-resistance by miniaturizing the unit cell and eliminating the JFET resistance. Even with the trench gate structure, the p-type base region and n - The electric field can be borne by the pn junction with the drift region, and a high electric field is not applied to the gate insulating film at the bottom of the trench. For this reason, unlike the conventional structure (see Figs. 13 and 14), the first and second p + There is no need to provide a mold area.

[0124] On the other hand, in MOSFETs using silicon carbide as the semiconductor material, the trench gate structure allows the unit cell to be miniaturized, the channel mobility to be increased, and the on-resistance to be reduced. In addition, the increased channel mobility allows the thickness of the epitaxial layer laminated on the semiconductor substrate to be reduced. On the other hand, the band gap of silicon is 3 eV wider than that of silicon, so the p-type base region and n-type - The pn junction with the type drift region cannot bear the electric field, and a high electric field is applied to the gate insulating film at the bottom of the trench.

[0125] Therefore, the first and second p structures that reduce the electric field applied to the bottom of the trench as in the conventional structure are + A structure has been proposed in which the type regions are provided in stripes extending on the front surface of the semiconductor substrate. + The JFET resistance is generated by the pn junction between the p-type region and the n-type current diffusion region, and the smaller the unit cell is, the higher the JFET resistance becomes. + Even if a type region is provided, the JFET resistance is reduced, realizing a low on-resistance, while providing the various characteristics due to the advantages of silicon carbide (low on-voltage, high-speed characteristics, high-temperature characteristics).

[0126] According to the embodiment, the first and second p-type insulating layers 11 and 12 are formed to reduce the electric field applied to the bottom surface of the trench. + By simply changing the pattern of the ion implantation mask for forming the mold region, the same manufacturing process as that of the conventional structure can be used, and therefore the main semiconductor element can be easily manufactured.

[0127] (Example) The breakdown voltage characteristics and on-resistance characteristics of the main semiconductor element 11 were examined. Fig. 12 is a characteristic diagram showing the breakdown voltage characteristics and on-resistance characteristics of the example. The horizontal axis of Fig. 12 represents the breakdown voltage characteristics and on-resistance characteristics of the first p + 12, the left vertical axis indicates the on-resistance, and the right vertical axis indicates the breakdown voltage.

[0128] FIG. 12 shows the results of measuring the breakdown voltage and on-resistance of a plurality of samples (hereinafter, referred to as examples) having the structure of the main semiconductor element 11 (see FIGS. 2 to 5) of the semiconductor device 20 according to the embodiment described above. The examples had a breakdown voltage of 1200 V class. The plurality of samples in the examples were first p + The intervals w2 between the mold regions 61a are different from one another.

[0129] For comparison, the results of measuring the breakdown voltage and on-resistance of the main semiconductor element of the conventional semiconductor device 220 (hereinafter referred to as the conventional example; see FIGS. 13 and 14) are also shown in FIG. 12. The difference between the conventional example and the embodiment is that the first p + -type region 261 extends linearly in the first direction X with the same length as the trench 237. The breakdown voltage class of the conventional example is the same as that of the embodiment. The sample with an interval of = 0 μm on the horizontal axis of FIG. 12 is the conventional example.

[0130] From the results shown in FIG. 12, it was confirmed that the embodiment can reduce the on-resistance compared with the conventional example. The reason is that the first p + -type region 61a facing the trench 37a in the depth direction Z is partially thinned, so that the path of the current flowing during conduction becomes wider in the portion where the first p + -type region 61a does not exist, and the channel resistance can be reduced.

[0131] Also, it was confirmed that the embodiment can reduce the on-resistance as the interval w2 between the first p + -type regions 61a adjacent to each other in the first direction X is widened. On the other hand, it was confirmed that the embodiment has a lower breakdown voltage than the conventional example as the interval w2 between the first p + -type regions 61a adjacent to each other in the first direction X is widened.

[0132] The reason is that as the interval w2 between the first p + -type regions 61a adjacent to each other in the first direction X is widened, a high electric field is more likely to be applied to the bottom surface of the trench 37a in the portion where the first p + -type region 61a does not exist. Also, at the location where the high electric field on the bottom surface of the trench 37a is concentrated, the hole current flowing toward the source electrode in the n - -type drift region 32 during turn-off concentrates.

[0133] As a result, the amount of the hole current ejected to the source electrode (cut-off current amount) decreases. Therefore, the interval w2 between the first p + -type regions 61a adjacent to each other in the first direction X is the first p +It is advisable to suppress the application of a high electric field to the bottom surface of the trench 37a in a portion where the type region 61a does not exist and to set an interval that can ensure a predetermined on-resistance.

[0134] Specifically, taking a relatively wide reverse bias safe operating area (RBSOA), the interval w2 between the first p-type regions 61a adjacent to each other in the first direction X is set to about 1.0 μm or less (on the left side of the vertical broken line), and it is advisable to ensure a breakdown voltage of about 1.2 times or more of the breakdown voltage class (for example, about 1500 V). + Although not shown in the figure, the results shown in FIG. 12 can be obtained in the same manner even when the predetermined breakdown voltage class of the embodiment is variously changed.

[0135] Although not shown in the figure, the results shown in FIG. 12 can be obtained in the same manner even when the predetermined breakdown voltage class of the embodiment is variously changed.

[0136] As described above, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. For example, even when a wide bandgap semiconductor other than silicon carbide is used instead of using silicon carbide as the semiconductor material, the present invention can be applied. Further, the present invention is similarly applicable even when the conductivity type (n-type, p-type) is reversed.

Industrial Applicability

[0137] As described above, the silicon carbide semiconductor device and the method of manufacturing the silicon carbide semiconductor device according to the present invention are useful for power semiconductor devices that control high voltages and large currents.

Explanation of Signs

[0138] 1 Active region 1a Main effective region 1b Main ineffective region 2 Edge termination region 10 Semiconductor substrate 11 Main semiconductor element 12 Current sense section 12a Sense effective region 12b Sense ineffective region 13 Temperature sense section 14 Gate pad section 20 Semiconductor device 21a Source pad (electrode pad) 21b Gate pad (electrode pad) 22 OC pad (electrode pad) 23a Anode pad (electrode pad) 23b Cathode pad (electrode pad) 31 n + -type drain region 32 n - -type drift region 32a n - -type region 33a, 33b n-type current diffusion region 34a, 34b p-type base region 35a, 35b n + -type source region 36a, 36b p ++ -type contact region 37a, 37b Trench 38a, 38b Gate insulating film 39a, 39b Gate electrode 40, 83 Interlayer insulating film 40a, 40b, 83a, 83b Contact hole 41a, 41b NiSi film 42a, 42b First TiN film 43a, 43b First Ti film 44a, 44b Second TiN film 45a, 45b Second Ti film 46a, 46b Barrier metal 47a~47d Plating film 48a~48d Terminal pin 49a~49c First protective film 50a~50c Second protective film 51 Drain electrode 61a, 61b First p for relaxing the electric field at the bottom of the trench + -type region 62a, 62b Second p for relaxing the electric field at the bottom of the trench + -type region 63a n-type current diffusion region's, second p +The first part between the p-type region and the first p + type region The second part between the 64a n-type current diffusion region and the second p + type region and the trench 65 The first and second p + type regions connecting the p + type region 71 n + type starting substrate 72 n - type silicon carbide layer 72a n - The part with an increased thickness of the n-type silicon carbide layer 73 p-type silicon carbide layer 81 p-type polysilicon layer 82 n-type polysilicon layer 91,93 p + type region 92,94 n-type region d1 p + The depth of the p-type region d2 The distance between adjacent p + type regions d3 The depth of the n-type region t1 n - Of the n-type silicon carbide layer, n + The thickness first deposited on the n-type starting substrate t2 n - The thickness of the part with an increased thickness of the n-type silicon carbide layer t3 The thickness of the p-type silicon carbide layer w1 The width in the second direction Y of the first part of the n-type current diffusion region w2 The distance between adjacent first p + type regions in the first direction w11 The width in the second direction Y of the second part of the n-type current diffusion region w12 The first p + The width of the p-type region in the first direction w21 The first p + The width of the p-type region in the second direction w22 The second p + The width of the p-type region in the second direction X, Y A direction parallel to the front surface of the semiconductor substrate Z Depth direction

Claims

1. A silicon carbide semiconductor device having a trench gate structure, comprising: a semiconductor substrate made of silicon carbide; a trench extending in a first direction parallel to the front surface of the semiconductor substrate on the front surface of the semiconductor substrate; a source electrode provided on the front surface of the semiconductor substrate; a source region of a first conductivity type provided adjacent to the side wall of the trench on the front surface side of the semiconductor substrate and connected to the source electrode; a contact region of a second conductivity type selectively provided in the first direction on the front surface side of the semiconductor substrate and connected to the source electrode; a bottom surface region of a second conductivity type provided at a predetermined interval in the first direction and facing the bottom surface of the trench in the depth direction, having a width wider than that of the bottom surface of the trench in a second direction parallel to the front surface of the semiconductor substrate and orthogonal to the first direction; and a first cross-section perpendicular to the first direction including a portion through which current flows during on-state, having a first region between two adjacent contact regions in the first direction and a second region between two adjacent bottom surface regions in the first direction; and a second cross-section perpendicular to the first direction including a portion through which current flows during on-state, having the contact region and the bottom surface region; wherein the source region has a ladder-shaped planar shape surrounding the periphery of the contact region. The silicon carbide semiconductor device is characterized by this.

2. A silicon carbide semiconductor device having a trench gate structure, comprising: a semiconductor substrate made of silicon carbide; a trench extending in a first direction parallel to the front surface of the semiconductor substrate on the front surface of the semiconductor substrate; a source electrode provided on the front surface of the semiconductor substrate; a source region of a first conductivity type provided adjacent to the side wall of the trench on the front surface side of the semiconductor substrate and connected to the source electrode; a contact region of a second conductivity type selectively provided in the first direction on the front surface side of the semiconductor substrate and connected to the source electrode; a bottom surface region of a second conductivity type provided at a predetermined interval in the first direction and facing the bottom surface of the trench in the depth direction, having a width wider than that of the bottom surface of the trench in a second direction parallel to the front surface of the semiconductor substrate and orthogonal to the first direction; and A first region between two of the contact regions adjacent in the first direction and a second region between two of the bottom surface regions adjacent in the first direction are provided, and a first cross section perpendicular to the first direction including a portion through which current flows when on, and a second cross section perpendicular to the first direction including a portion through which current flows when on, in which the contact region and the bottom surface region are provided, A silicon carbide semiconductor device, characterized in that the JFET resistance in the first cross section is lower than the JFET resistance in the second cross section.

3. The silicon carbide semiconductor device according to claim 1 or 2, further comprising a second conductivity type connection region selectively provided in the semiconductor substrate in the first direction for electrically connecting the bottom surface region to the contact region.

4. The silicon carbide semiconductor device according to claim 1, characterized in that the JFET resistance in the first cross section is lower than the JFET resistance in the second cross section.

5. A second conductivity type base region in which a channel is formed along the trench, A first conductivity type current path region provided on the side of the base region opposite to the source electrode side and constituting a current path of a main current flowing through the channel, Comprising The silicon carbide semiconductor device according to claim 1 or 2, characterized in that the bottom surface region narrows the current path in the second cross section more than in the first cross section.

6. The silicon carbide semiconductor device according to claim 5, characterized in that the current path region is provided in the second region and the current path region is in contact with the upper surface of the bottom surface region.

7. The silicon carbide semiconductor device according to any one of claims 1 to 6, characterized in that the source region is provided in the first region.

8. The silicon carbide semiconductor device according to claim 2, characterized in that the source region has a ladder-shaped planar shape surrounding the periphery of the contact region.

9. A silicon carbide semiconductor device having a trench gate structure, A semiconductor substrate made of silicon carbide, A trench extending in a first direction parallel to the front surface of the semiconductor substrate on the front surface of the semiconductor substrate, A source electrode provided on the front surface of the semiconductor substrate, A first conductivity type source region provided adjacent to the side wall of the trench on the front surface side of the semiconductor substrate and connected to the source electrode, A contact region of a second conductivity type, which is selectively provided in the front surface side of the semiconductor substrate in the first direction and is connected to the source electrode; A bottom surface region of a second conductivity type, which is provided at a predetermined interval in the first direction, faces the bottom surface of the trench in the depth direction, is parallel to the front surface of the semiconductor substrate, and is wider than the bottom surface of the trench in a second direction orthogonal to the first direction; Comprising; Including a first cross-section perpendicular to the first direction, in which a first region between two adjacent contact regions in the first direction and a second region between two adjacent bottom surface regions in the first direction are provided; A silicon carbide semiconductor device, wherein a width of the contact region in the first direction is wider than a width of the bottom surface region in the first direction.

10. A method for manufacturing a silicon carbide semiconductor device having a trench gate structure, comprising: a semiconductor substrate made of silicon carbide, a trench extending in a first direction parallel to the front surface of the semiconductor substrate on the front surface of the semiconductor substrate, a source electrode provided on the front surface of the semiconductor substrate, a source region of a first conductivity type provided adjacent to a side wall of the trench on the front surface side of the semiconductor substrate and connected to the source electrode, a contact region of a second conductivity type connected to the source electrode, and a bottom surface region of a second conductivity type facing the bottom surface of the trench in the depth direction, parallel to the front surface of the semiconductor substrate, and wider than the bottom surface of the trench in a second direction orthogonal to the first direction, A step of ion-implanting impurities of a second conductivity type into the semiconductor substrate to form the bottom surface regions at predetermined intervals in the first direction inside the semiconductor substrate; Ion-implanting impurities of a second conductivity type into the semiconductor substrate so as to include a first cross-section perpendicular to the first direction, which includes a portion where current flows when turned on and where a first region between two adjacent contact regions in the first direction and a second region between two adjacent bottom surface regions in the first direction are provided, and a second cross-section perpendicular to the first direction, which includes a portion where current flows when turned on and where the contact region and the bottom surface region are provided, and forming the contact region selectively in the first direction on the front surface side of the semiconductor substrate; Including; A method for manufacturing a silicon carbide semiconductor device, wherein a JFET resistance in the first cross-section is lower than a JFET resistance in the second cross-section.

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