Nitride semiconductor device

Abstract

To provide a manufacturing method of nitride semiconductor device, capable of improving an activation ratio of an n-type impurity, and provide a nitride semiconductor device.SOLUTION: A manufacturing method of a nitride semiconductor device, includes a step of preparing a gallium nitride semiconductor layer having a first surface and a second surface positioned to the opposite side of the first surface, and adjusting a donor concentration in an n-type region by performing an ion implantation of an n-type impurity to the gallium nitride semiconductor layer from the first surface side. Previously, a relation among a dislocation density of the gallium nitride semiconductor layer, a depth until an implantation peak position from the first surface of the n-type impurity in the n-type region, and a tale length to the second surface from the implantation peak position of the n-type impurity are calculated when an activation ratio of the n-type impurity in the n-type region becomes a preset value. In the step of performing the ion implantation of the n-type impurity, a processing condition of the ion implantation is set so as to form the n-type region satisfying this relation.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a nitride semiconductor device and a nitride semiconductor device.

Background Art

[0002] A nitride semiconductor device having a MOS (Metal Oxide Semiconductor) structure is known. For example, Patent Document 1 discloses a vertical GaN semiconductor device.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] As a method for controlling the donor concentration of an n-type GaN layer, there is ion implantation. For example, a vertical GaN semiconductor device has an n-type GaN layer and has a JFET region between a pair of source regions arranged apart from each other. The donor concentration of the JFET region can be controlled by ion implantation, for example, at 1E+17 / cm 3 It is desired to control it at a level. However, the activation rate due to annealing of n-type impurities in the GaN layer tends to be low. Therefore, for example, when the activation rate is less than 20%, ion implantation of n-type impurities needs to be performed at a high concentration of the latter half of 1E+18 / cm 3 or more. When ion implantation of n-type impurities is performed at a high concentration, many implantation defects may occur in the GaN layer. There is a possibility that characteristics of the semiconductor device may deteriorate, such as charge trapping due to implantation defects. The present invention has been made in view of such circumstances, and an object thereof is to provide a method for manufacturing a nitride semiconductor device and a nitride semiconductor device capable of improving the activation rate of n-type impurities.

Means for Solving the Problem

[0005] To solve the above problems, a method for manufacturing a nitride semiconductor device according to an aspect of the present invention includes preparing a gallium nitride-based semiconductor layer having a first surface and a second surface located on the opposite side of the first surface, and ion-implanting an n-type impurity into the gallium nitride-based semiconductor layer from the first surface side to adjust the donor concentration of the n-type region. The relationship between the dislocation density of the gallium nitride-based semiconductor layer, the depth from the first surface to the implantation peak position of the n-type impurity in the n-type region, and the tail length from the implantation peak position of the n-type impurity to the second surface side when the activation rate of the n-type impurity in the n-type region becomes a preset value is obtained in advance. In the step of ion-implanting the n-type impurity, the processing conditions of the ion implantation are set so that an n-type region satisfying this relationship is formed.

[0006] A nitride semiconductor device according to an aspect of the present invention includes a gallium nitride-based semiconductor layer having a first surface and a second surface located on the opposite side of the first surface, and an n-type region provided on the first surface side of the gallium nitride-based semiconductor layer. Let the common logarithm of the dislocation density of the gallium nitride-based semiconductor layer be β, the depth from the first surface to the implantation peak position of the n-type impurity in the n-type region be T, and the tail length from the implantation peak position of the n-type impurity to the second surface side be ΔT. Then, the following formula (1) holds. ΔT / T≧0.25β-0.73…(1)

Advantages of the Invention

[0007] According to the present invention, it is possible to provide a method for manufacturing a nitride semiconductor device and a nitride semiconductor device capable of improving the activation rate of an n-type impurity.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

DETAILED DESCRIPTION OF THE INVENTION

[0009] Embodiments of the present invention will be described below. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each device and each member, etc. are different from the actual ones. Therefore, the specific thickness and dimensions should be determined with reference to the following description. Also, it goes without saying that there are portions where the dimensional relationships and ratios are different between the drawings.

[0010] Also, in the following description, the directions may be described using the terms in the X-axis direction, Y-axis direction, and Z-axis direction. For example, the X-axis direction or the Y-axis direction is a direction parallel to the surface 12a of the GaN layer 12. The X-axis direction, the Y-axis direction, or both the X-axis direction and the Y-axis direction are also referred to as the horizontal direction. The Z-axis direction is the normal direction of the surface 12a. The Z-axis direction is also the thickness direction of the GaN layer 12. The X-axis direction, the Y-axis direction, and the Z-axis direction are perpendicular to each other.

[0011] In the following description, the direction of the arrow on the Z-axis may be referred to as "up", and the opposite direction of the arrow on the Z-axis may be referred to as "down". "Up" and "down" do not necessarily mean the vertical direction with respect to the ground. That is, the directions of "up" and "down" are not limited to the direction of gravity. "Up" and "down" are merely convenient expressions for specifying the relative positional relationship in a region, layer, film, substrate, etc., and do not limit the technical idea of the present invention. For example, if the paper surface is rotated 180 degrees, it goes without saying that "up" becomes "down" and "down" becomes "up".

[0012] In the following description, n or p means that there are a large number of electrons or holes, respectively. Also, + and - attached to p or n mean semiconductor regions with relatively high or low impurity concentrations compared to semiconductor regions without + and - attached, respectively. However, even for semiconductor regions with the same p attached, it does not mean that the impurity concentrations of the respective semiconductor regions are exactly the same.

[0013] <Configuration of MOS Transistor> FIG. 1 is a cross-sectional view showing a configuration example of a MOS (Metal Oxide Semiconductor) transistor 100 according to an embodiment of the present invention. The nitride semiconductor device according to the embodiment of the present invention is, for example, a power semiconductor device, and includes a gallium nitride-based semiconductor substrate 1 shown in FIG. 1 and a MOS transistor 100 provided on the gallium nitride-based semiconductor substrate 1. FIG. 1 shows the unit structure of the MOS transistor 100. The unit structure extends in the Y-axis direction and is repeatedly provided in the X-axis direction. A region where a plurality of unit structures are provided is called an active region. Although not shown, an edge termination structure having a function of preventing electric field concentration in the active region is provided around the active region. The edge termination structure may include one or more of a guard ring structure, a field plate structure, and a JTE (Junction Termination ExtenSiOn) structure.

[0014] As shown in FIG. 1, the MOS transistor 100 includes a gate insulating film 5 provided on a gallium nitride-based semiconductor substrate 1, a gate electrode 6 provided on the gate insulating film 5, and a source electrode 7 and a drain electrode 8 provided on the gallium nitride-based semiconductor substrate 1. The gallium nitride-based semiconductor substrate 1 includes, for example, a GaN substrate 11 and a GaN layer 12 (an example of the "gallium nitride-based semiconductor layer" of the present invention) provided on the GaN substrate 11. As shown in FIG. 1, the surface 12a of the GaN layer 12 (an example of the "first surface" of the present invention) is also the surface 1a of the gallium nitride-based semiconductor substrate 1. The back surface 12b (an example of the "second surface" of the present invention) located on the opposite side of the surface 12a of the GaN layer 12 is in contact with the GaN substrate 11. The back surface 11b of the GaN substrate 11 is also the back surface 1b of the gallium nitride-based semiconductor substrate 1.

[0015] The GaN substrate 11 is a GaN single crystal substrate. The conductivity type of the GaN substrate 11 is, for example, n+-type. The n-type impurity (dopant) contained in the GaN substrate 11 is one or more elements among Si (silicon), O (oxygen), and Ge (germanium), and an example is O. The impurity concentration of O in the GaN substrate 11 is 2E+18 / cm 3 or more. Here, E+ is exponential notation. For example, 2E+18 means 2×10 18 . The GaN substrate 11 may be a low-dislocation free-standing substrate with a dislocation density of less than 1E+7 / cm 2 . Since the GaN substrate 11 is a low-dislocation free-standing substrate, the dislocation density of the GaN layer 12 formed on the GaN substrate 11 also becomes low. Further, by using a low-dislocation free-standing substrate as the GaN substrate 11, even when a large-area power device is formed on the GaN substrate 11, the leakage current in the power device can be reduced. Thereby, the manufacturing apparatus can manufacture the power device with a high yield. Also, in heat treatment, it is possible to prevent the impurity implanted with ions from diffusing deeply along the dislocations.

[0016] The GaN layer 12 is provided on the GaN substrate 11. The GaN layer 12 is n -It is a GaN single crystal layer formed by an epitaxial growth method on a GaN substrate 11. The n-type impurities contained in the GaN layer 12 are one or more elements among Si (silicon), O (oxygen), and Ge (germanium), and for example, it is O.

[0017] On the surface 12a side of the GaN layer 12, a p-type well region 13 (an example of the "p-type region" of the present invention), an n+-type source region 14, and an n-type JFET region 15 (an example of the "n-type region" of the present invention) are provided. In the GaN layer 12, a region where the well region 13 and the source region 14 are not provided may be called a drift region. The drift region functions as a current path between the GaN substrate 11 and the well region 13. Note that the JFET region 15 is a part of the drift region. The JFET region 15 has a higher concentration of n-type impurities and a lower electrical resistance than other drift regions. By providing the JFET region 15, the on-resistance of the MOS transistor 100 is reduced.

[0018] The well region 13 is formed by ion implanting p-type impurities from the surface 12a side of the GaN layer 12 and activating the p-type impurities by heat treatment. The p-type impurity is, for example, magnesium. The well region 13 faces the surface 12a of the GaN layer 12. Further, the well region 13 has a first end portion located on the source region 14 side and a second end portion located on the JFET region 15 side. In the well region 13, a channel of the MOS transistor 100 is formed between the first end portion and the second end portion and at the contact interface with the gate insulating film 5 and in the vicinity thereof.

[0019] The source region 14 is formed by ion implanting n-type impurities from the surface 12a side of the GaN layer 12 and activating the n-type impurities by heat treatment. The n-type impurity is, for example, one or more elements among Si, O, and Ge. The source region 14 faces the surface 12a of the GaN layer 12 and is located inside the well region 13. The side portion and the bottom portion of the source region 14 are in contact with the well region 13. In the X-axis direction, Y-axis direction, and Z-axis direction, the source region 14 and the well region 13 are in contact with each other.

[0020] The JFET region 15 has a higher concentration of n-type impurities than the n-type GaN layer 12. The JFET region 15 is formed by ion-implanting n-type impurities from the surface 12a side of the GaN layer 12 and activating the n-type impurities by heat treatment. The n-type impurity is, for example, one or more elements among Si, O, and Ge, and in one example, it is O. The JFET region 15 faces the surface 12a of the GaN layer 12 and is in contact with the gate insulating film 5. Further, the JFET region 15 is sandwiched from both sides in the horizontal direction (for example, the X-axis direction) by the well region 13. The JFET region 15 faces the source region 14 with the well region 13 in between.

[0021] The gate insulating film 5 is provided on the well region 13. The gate insulating film 5 is, for example, a silicon oxide film (SiO2 film) or an aluminum oxide (Al2O3) film. The thickness of the gate insulating film 5 is, for example, 50 nm or more and 100 nm or less. The gate electrode 6 is provided on the gate insulating film 5. The gate electrode 6 is a planar electrode provided on the flat gate insulating film 5. The gate electrode 6 is formed of, for example, impurity-doped polysilicon.

[0022] The source electrode 7 is continuously provided from above the source region 14 over the well region 13 and is electrically connected to the source region 14 and the well region 13, respectively. Although not shown, the source electrode 7 may be provided to cover the gate electrode 6 via an interlayer insulating film. The source electrode 7 is made of, for example, Al or an Al-Si alloy. The drain electrode 8 is provided on the back surface 11b side of the GaN substrate 11 and is electrically connected to the GaN substrate 11. The drain electrode 8 is made of, for example, Al or an Al-Si alloy.

[0023] <Ion Implantation Process of n-Type Impurities> Figure 2 is a cross-sectional view showing an ion implantation process for forming the JFET region 15 in the manufacturing process of the MOS transistor 100 according to an embodiment of the present invention. As shown in Figure 2, a resist pattern RP is formed on the surface 12a of the GaN layer 12 during ion implantation. The resist pattern RP has a shape that opens above the planned region (hereinafter referred to as the JFET formation region) 15' where the JFET region 15 is to be formed and covers the other regions. The ion implantation apparatus uses the resist pattern RP as a mask to ion-implant n-type impurities into the GaN layer 12 from the surface 12a side of the GaN layer 12. The implantation angle of the n-type impurities with respect to a straight line CL (virtual line) perpendicular to the surface 12a of the GaN layer 12 is called the tilt angle θ. In the ion implantation process shown in Figure 2, the tilt angle θ is arbitrary, but for example, it is 7°. Also, the tilt angle θ is not limited to 7°, and it may be 0°, for example.

[0024] After the n-type impurities are ion-implanted into the JFET formation region 15', the resist pattern RP is removed. Thereafter, by subjecting the GaN layer 12 to heat treatment, the n-type impurities ion-implanted into the JFET formation region 15' are activated, and the JFET region 15 is formed. In the embodiment of the present invention, the implantation profile of the n-type impurities is defined in association with the transition density of the GaN layer 12 so that the activation rate of the n-type impurities by this heat treatment is 20% or more.

[0025] <Implantation profile of n-type impurities> (1) First example Figure 3 is a graph showing an example (first example) of the implantation profile of n-type impurities in the JFET region 15 shown in Figure 1. Figure 3 shows the concentration profile at the position overlapping the straight line CL shown in Figures 1 and 2. In Figure 3, the vertical axis represents the concentration of oxygen (oxygen concentration), which is an example of n-type impurities [ / cm 3 . The horizontal axis represents the depth [μm] from the surface 12a to the back surface 12b side of the GaN layer 12. In the first example shown in Figure 3, the type of n-type impurity (dopant) to be ion-implanted is oxygen (O). The tilt angle θ of the ion implantation is 0 [°], the implantation energy is 700 [keV], and the dose amount is 2.28E+13 [ / cm2 is as follows.

[0026] Also, in the first example, the dislocation density ρd of the GaN layer 12 is 1E+6 / cm 3 is as follows. For the n-type impurity in the JFET region 15, the depth (hereinafter referred to as the implantation depth) T from the surface 12a of the GaN layer 12 to the implantation peak position P1 is 1000 [nm]. For the n-type impurity in the JFET region 15, the tail length ΔT from the implantation peak position P1 of the n-type impurity to the back surface 12b side is 1100 [nm]. The tail length is the length from the implantation peak position P1 to the position P2 where the concentration of the n-type impurity becomes 1 / 10 of the concentration at the implantation peak position P1 (i.e., the implantation peak concentration). The first example satisfies the following formula (2). α≧0.25β - 0.73…(2) Formula (2) is a relational expression showing the relationship between α and β. In formula (2), α is the tail length parameter and is represented by α = ΔT / T. Also, β is the common logarithm of the dislocation density ρd of the GaN layer 12 and is represented by β = log 10 ρd. The common logarithm is the logarithm with base 10. When formula (2) is satisfied, the activation rate of the n-type impurity in the GaN layer 12 is 20% or more.

[0027] Since the first example satisfies formula (2), the activation rate of the n-type impurity in the GaN layer 12 is 20% or more. The derivation method of formula (2) will be described later with reference to FIG. 8. (2) Second example FIG. 4 is a graph showing an example (second example) of the implantation profile of the n-type impurity in the JFET region 15 shown in FIG. 1. FIG. 4 shows the concentration profile at the position overlapping with the straight line CL shown in FIGS. 1 and 2. In FIG. 4, the vertical axis represents the concentration of oxygen (oxygen concentration) as an example of the n-type impurity [ / cm 3is shown. The horizontal axis represents the depth [μm] from the front surface 12a to the back surface 12b of the GaN layer 12. In the second example shown in FIG. 4, the type of n-type impurity (dopant) to be ion-implanted is oxygen (O). The tilt angle θ of the ion implantation is 7 [°], the implantation energy is 700 [keV], and the dose amount is 6.03E+13 [ / cm 2 .

[0028] Also, in the second example, the dislocation density ρd of the GaN layer 12 is 1E+4 [ / cm 3 . The implantation depth T of the n-type impurity in the JFET region 15 is 650 [nm]. The tail length ΔT of the n-type impurity in the JFET region 15 is 310 [nm]. Similar to the first example, since the second example also satisfies the above formula (2), the activation rate of the n-type impurity in the GaN layer 12 is 20% or more.

[0029] (3) Preferred ranges of α and β FIG. 5 is a graph showing an example of the preferred ranges of α and β that satisfy formula (2). In FIG. 5, the vertical axis represents the tail length parameter α. The horizontal axis represents β, which is the common logarithm of the dislocation density ρd of the GaN layer 12. In FIG. 5, the range above the straight line indicating α = 0.25β - 0.73) is the range that satisfies the above formula (2). For example, ranges A to H shown in FIG. 5 are respectively the preferred ranges of α and β.

[0030] For example, range A is a range where α is 0.1 or more and less than 0.2, and β is 3.32 or more and less than 3.72. Range B is a range where α is 0.2 or more and less than 0.3, and β is 3.72 or more and less than 4.12. Range C is a range where α is 0.3 or more and less than 0.4, and β is 4.12 or more and less than 4.52. Range D is a range where α is 0.4 or more and less than 0.5, and β is 4.52 or more and less than 4.92. Range E is a range where α is 0.5 or more and less than 0.6, and β is 4.92 or more and less than 5.32. Range F is a range where α is 0.6 or more and less than 0.7, and β is 5.32 or more and less than 5.72. Range G is a range where α is 0.7 or more and less than 0.8, and β is 5.72 or more and less than 6.12. Range H is a range where α is 0.8 or more and less than 0.9, and β is 6.12 or more and less than 6.52.

[0031] Also, the tail length parameter α is preferably smaller in value. That is, the tail length ΔT is preferably smaller with respect to the implantation depth T. In FIG. 5, range A where the tail length parameter α is the smallest is the most preferable, range B is the next preferable, and range C is the next preferable after that. Similarly, range D is preferable after range C, range E is preferable after range D, range F is preferable after range E, range G is preferable after range F, and range H is preferable after range G. The smaller the tail length parameter α, the less it hinders the extension of the depletion layer from the p-type well region 13 to the back surface 12b side of the GaN layer 12. Thereby, a decrease in the off-state breakdown voltage of the MOS transistor 100 can be suppressed. This effect will be described with reference to FIGS. 6 and 7.

[0032] FIG. 6 is a cross-sectional view showing a configuration example of a MOS transistor 100A (when the tail length parameter α is small) according to an embodiment of the present invention. FIG. 7 is a cross-sectional view showing a configuration example of a MOS transistor 100B (when the tail length parameter α is large) according to an embodiment of the present invention. In FIGS. 6 and 7, the implantation depth T of the n-type impurity in the JFET region 15 is the same for each other. In FIGS. 6 and 7, the lengths of the tail lengths ΔT of the JFET region 15 are different from each other.

[0033] For example, if the tail length of the MOS transistor 100A shown in FIG. 6 is ΔT1 and the tail length of the MOS transistor 100B shown in FIG. 7 is ΔT2, then ΔT1 is smaller than ΔT2 (ΔT1 < ΔT2). As a result, the tail length parameter α of the MOS transistor 100A shown in FIG. 6 has a smaller value than the tail length parameter α of the MOS transistor 100B shown in FIG. 7. In FIGS. 6 and 7, the bottom of the JFET region 15 is illustrated as the position P2 of the tail length end portion.

[0034] Also, in FIGS. 6 and 7, the extensions of the depletion layer from the p-type well region 13 to the n-type drift region side are illustrated by DL and DH. DL illustrates the extension of the depletion layer when no electric field is applied between the drain electrode 8 and the source electrode 7. DH illustrates the extension of the depletion layer when a high electric field is applied between the drain electrode 8 and the source electrode 7. When a high electric field is applied between the drain electrode 8 and the source electrode 7, a reverse bias state is formed between the p-type region and the drift region, so that the extension of the depletion layer becomes large like DH.

[0035] As shown in FIG. 6, in the MOS transistor 100A with a short tail length ΔT1, when a high electric field is applied, the depletion layer extends so as to wrap around below the bottom of the JFET region 15. On the other hand, as shown in FIG. 7, in the MOS transistor 100B with a long tail length ΔT1, when a high electric field is applied, the depletion layer hardly wraps around below the bottom of the JFET region 15. The bottom corner portion 15E of the JFET region 15 and its vicinity are locations where the electric field is likely to concentrate. However, if the wrap-around of the depletion layer is small, dielectric breakdown is likely to occur at this location. In this way, the MOS transistor 100A is more likely to maintain the off-state breakdown voltage and is more likely to reduce the on-resistance while maintaining the off-state breakdown voltage compared to the MOS transistor 100B. The above is the reason why it is preferable that the tail length ΔT is short and the tail length parameter α is small.

[0036] <Derivation method of relational expression> Next, the method for deriving the above formula (2) showing the relationship between α and β will be described. FIG. 8 is a graph showing the relationship between the tail length parameter α and the activation rate. In FIG. 8, the vertical axis represents the activation rate [%], and the horizontal axis represents the tail length parameter. As shown in FIG. 8, the inventor investigated the relationship between the activation rate of n-type impurities in the n-type region and the tail length parameter α for each dislocation density ρd of the GaN layer, and found that there is a correlation between the activation rate and the tail length parameter α. Extract the combination of the tail length parameter α and the dislocation density ρd when the activation rate is 20% or more. Then, plot the extracted data on a graph with the vertical axis as the tail length parameter α and the horizontal axis as the common logarithm β of the dislocation density. Equation (2) was obtained by approximating the obtained plot by, for example, the least squares method. A part of the data obtained in the process of deriving Equation (2) is shown in Table 1.

[0037]

Table 1

[0038] <Effects of the Embodiment> As described above, the nitride semiconductor device according to the embodiment of the present invention includes a GaN layer 12 and a JFET region 15 provided on the surface 12a side of the GaN layer 12. Let the common logarithm of the dislocation density ρd of the GaN layer 12 be β, the depth (implantation peak depth) from the surface 12a of the n-type impurity (for example, oxygen (O)) in the JFET region 15 to the implantation peak position P1 be T, and the tail length from the implantation peak position P1 of the n-type impurity to the back surface 12b side be ΔT. Then, the above formula (2) holds.

[0039] According to this, in the JFET region 15, the activation rate of the n-type impurity can be improved, and the activation rate can be made 20% or more. As a result, the concentration of the n-type impurity contained in the JFET region 15 can be kept low. For example, in the JFET region 15, when the activation rate of the n-type impurity is less than 20%, the concentration of the n-type impurity is 1E+18 / cm 3It is necessary to be more than the latter half of the stage, but if the activation rate is 20% or more, the concentration of the n-type impurity can be suppressed to 1E+17 / cm 3 on the stage. Thus, in the step of forming the JFET region 15, the dose amount of the n-type impurity to be ion-implanted can be kept low, and the occurrence of crystal defects in the JFET region 15 due to ion implantation can be suppressed. In the JFE region 15, since the generation of charge traps caused by crystal defects can be suppressed, the degradation of the characteristics of the MOS transistor 100 can be suppressed.

[0040] The method for manufacturing a nitride semiconductor device according to an embodiment of the present invention includes a step of ion-implanting an n-type impurity into the GaN layer 12 from the surface 12a side of the GaN layer 12 to adjust the donor concentration of the JFET region 15. When the activation rate of the n-type impurity in the JFET region 15 reaches a preset value (for example, 20% or more), the dislocation density ρd of the GaN layer 12, the depth (implantation peak depth) T from the surface 12a of the n-type impurity in the JFET region 15 to the implantation peak position P1, and the tail length ΔT from the implantation peak position P1 of the n-type impurity to the back surface 12b side are obtained in advance. This relationship is represented by, for example, the above formula (2). In the step of ion-implanting the n-type impurity, the processing conditions of the ion implantation are set so that the JFET region 15 satisfying the above formula (2) is formed. Examples of the processing conditions of the ion implantation include parameters for controlling the implantation peak depth T and the tail length ΔT (for example, tilt angle θ and implantation energy). Further, the processing conditions of the ion implantation may include the selection of the dislocation density ρd of the substrate (for example, GaN layer 12) to be ion-implanted.

[0041] According to this, since the activation rate of the n-type impurity in the JFET region 15 can be made 20% or more, the dose amount of the n-type impurity to be ion-implanted can be kept low. Thereby, the occurrence of crystal defects in the JFET region 15 due to ion implantation can be suppressed. In the JFET region 15, since the generation of charge traps caused by crystal defects can be suppressed, the degradation of the characteristics of the MOS transistor 100 can be suppressed. In the embodiments of the present invention, the tail length ΔT may be limited to 100 nm or more. As a method for doping the n-type impurities into the JFET region 15, in addition to ion implantation, a method of doping in-situ during epitaxial growth can be considered. When doping the n-type impurities in-situ, since the switching between doping and undoping is performed in a short time by operating the valve of the pipe connected to the chamber, the tail length ΔT is short, usually less than 100 nm. Therefore, by limiting the tail length ΔT to 100 nm or more, the doping method of the n-type impurities can be substantially limited to ion implantation.

[0042] <Other Embodiments> As described above, the present invention has been described by way of embodiments and variations, but it should not be understood that the descriptions and drawings forming a part of this disclosure limit the present invention. Various alternative embodiments and variations will be apparent to those skilled in the art from this disclosure. For example, in the above embodiment, it has been described that oxygen (O) is ion-implanted as the n-type impurity when forming the JFET region 15, but the n-type impurity is not limited to oxygen. In the embodiments of the present invention, the n-type impurity to be ion-implanted may contain any one or more elements of oxygen, silicon (Si), and germanium (Ge). Even in such a case, the relationship among the dislocation density ρd of the GaN layer 12, the implantation peak depth T of the n-type impurity, and the tail length ΔT of the n-type impurity when the activation rate of the n-type impurity becomes equal to or higher than a preset value (for example, 20%) is obtained in advance, and the processing conditions of ion implantation are set so that the JFET region 15 satisfying this relationship is formed. Thereby, it is possible to suppress the occurrence of crystal defects while keeping the dose amount of ion implantation low and achieve an activation rate of 20% or more.

[0043] Also, in the above-described embodiment, it has been explained that the activation rate of the n-type impurities is set to 20% or more. However, the target value of the activation rate is not limited to 20% or more. The target value of the activation rate may be, for example, 25% or more. Even in such a case, as shown in FIG. 8, regarding the relationship between the activation rate of the n-type impurities and the tail length parameter α, for each dislocation density ρd of the GaN layer 12, an investigation is made, and when the activation rate becomes 25% or more, the combination of the tail length parameter α and the dislocation density ρd is extracted to obtain a relational expression such as Equation (2). Then, the processing conditions for ion implantation are set so that the JFET region 15 that satisfies this relational expression is formed. As a result, it becomes possible to achieve an activation rate of 25% or more while suppressing the occurrence of crystal defects while keeping the dose amount of ion implantation low.

[0044] Also, in the above-described embodiment, the JFET region 15 is exemplified as the "n-type region" of the present invention. However, the "n-type region" is not limited to the JFET region 15 and may be other regions. Also, in the above-described embodiment, the GaN layer 12 is exemplified as the "gallium nitride-based semiconductor layer" of the present invention. However, the "gallium nitride-based semiconductor layer" is not limited to the GaN layer. For example, the "gallium nitride-based semiconductor layer" may be a bulk GaN substrate. Further, the "gallium nitride-based semiconductor layer" may contain GaN as a main component and further contain at least one element selected from aluminum (Al) and indium (In).

[0045] Needless to say, the present invention includes various embodiments and the like not described herein. At least one of various omissions, substitutions, and changes of components can be made without departing from the gist of the above-described embodiments and modifications. Also, the effects described in this specification are merely examples and are not limiting, and there may be other effects. The technical scope of the present invention is defined only by the invention-specific matters according to the proper claims based on the above description.

Explanation of Reference Numerals

[0046] 1 Gallium nitride-based semiconductor substrate 1a, 12a Surfaces Inner surfaces of 1b, 11b, and 12b 5 Gate insulating film 6 Gate electrode 7 Source electrode 8 Drain electrode 11 GaN substrate 12 GaN layer 13 Well region 14 Source region 15 JFET region 15’ JFET formation region 15E Bottom corner 100, 100A, 100B MOS transistors Ranges A, B, C, D, E, F, G, H P1 Implantation peak position P2 Position RP Resist pattern α Tail length parameter ΔT, ΔT1, ΔT2 Tail lengths θ Tilt angle ρd Dislocation density

Claims

1. A gallium nitride-based semiconductor layer having a first surface and a second surface located on the opposite side of the first surface, and an n-type region provided on the first surface side of the gallium nitride-based semiconductor layer, wherein the common logarithm of the dislocation density of the gallium nitride-based semiconductor layer is β, the depth from the first surface to the implantation peak position of the n-type impurity in the n-type region is T, when the tail length from the implantation peak position of the n-type impurity to the second surface side is ΔT, the following formula (2) holds, ΔT / T ≧ 0.25β - 0.73…(2) a gate insulating film provided on the first surface of the gallium nitride-based semiconductor layer, a p-type region provided on the first surface side of the gallium nitride-based semiconductor layer and located below the gate insulating film, and an n-type source region further provided on the first surface side of the gallium nitride-based semiconductor layer and adjacent to the p-type region, wherein the n-type region faces the source region with the p-type region interposed therebetween, and the implantation peak position exists at a position deeper from the first surface than the lower surface of the source region. A nitride semiconductor device.

2. On the second surface side from the implantation peak position, the position where the concentration of the n-type impurity becomes 1 / 10 of the concentration at the implantation peak position is located on the second surface side from the lower surface of the p-type region. The nitride semiconductor device according to Claim 1.

3. The depth of the implantation peak position from the first surface side of the gallium nitride-based semiconductor layer is 650 nm or more and 1000 nm or less. The nitride semiconductor device according to Claim 1 or 2.

4. The activation rate of the n-type impurity in the n-type region is 20% or more. The nitride semiconductor device according to any one of Claims 1 to 3.

5. The gallium nitride-based semiconductor layer is a GaN layer. The nitride semiconductor device according to any one of Claims 1 to 4.

Images