Semiconductor device design system, semiconductor device design method, and program

Abstract

To provide a semiconductor device design system capable of accurately designing a semiconductor device in consideration of an actual manufacturing process. 【Solution means】A semiconductor device design system 1 according to an aspect of the present disclosure includes a design information storage unit 11 that stores design information of a semiconductor device, a process characteristic information storage unit 12 that stores information regarding process characteristics for manufacturing the semiconductor device, and a design information optimization unit 13 that optimizes the design information of the semiconductor device stored in the design information storage unit 11 using the information regarding the process characteristics stored in the process characteristic information storage unit 12. The design information optimization unit 13 optimizes the design information of the semiconductor device so that the difference between the dimensions of the semiconductor device based on the design information of the semiconductor device and the dimensions of the semiconductor device after performing a process for manufacturing the semiconductor device is reduced.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device design system, a method for designing a semiconductor device, and a program.

Background Art

[0002] In recent years, with the increasing integration and functionality of semiconductor devices, the development of microfabrication technologies for miniaturization and high density of semiconductor elements has been progressing. In the design of semiconductor devices, it is carried out in consideration of DFM (Design For Manufacturing). That is, the layout design is performed so as to satisfy the design (DFM) considering the manufacturing process of the semiconductor device.

[0003] Patent Document 1 discloses a technique related to a design apparatus for a semiconductor integrated circuit.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] As described above, in the design of a semiconductor device, the design is carried out in consideration of the manufacturing process of the semiconductor device (DFM). However, even when circuit design is carried out in consideration of DFM, the dimensions of the semiconductor device when the semiconductor device is actually manufactured may differ from the design values. For this reason, there is a need for a semiconductor device design system that can accurately design a semiconductor device in consideration of the actual manufacturing process.

[0006] In view of the above problems, an object of the present disclosure is to provide a semiconductor device design system, a method for designing a semiconductor device, and a program that can accurately design a semiconductor device in consideration of the actual manufacturing process.

Means for Solving the Problems

[0007] A semiconductor device design system, a method for designing a semiconductor device, and a program according to one aspect of the present disclosure are as follows.

[0008] [1] A design information storage unit that stores design information of a semiconductor device, A process characteristic information storage unit that stores information regarding process characteristics for manufacturing the semiconductor device, A design information optimization unit that optimizes the design information of the semiconductor device stored in the design information storage unit using the information regarding the process characteristics stored in the process characteristic information storage unit, The design information optimization unit optimizes the design information of the semiconductor device so that the difference between the dimensions of the semiconductor device based on the design information of the semiconductor device and the dimensions of the semiconductor device after performing a process for manufacturing the semiconductor device is reduced. Semiconductor device design system.

[0009] [2] The design information of the semiconductor device stored in the design information storage unit includes information regarding manufacturing conditions when manufacturing the semiconductor device, The design information optimization unit optimizes the information regarding manufacturing conditions when manufacturing the semiconductor device using the information regarding the process characteristics stored in the process characteristic information storage unit, the semiconductor device design system according to [1].

[0010] [3] The design information of the semiconductor device stored in the design information storage unit includes information regarding the layout of the semiconductor device, The design information optimization unit optimizes the information regarding the layout of the semiconductor device using the information regarding the process characteristics stored in the process characteristic information storage unit, the semiconductor device design system according to [1] or [2].

[0011] [4] The process characteristic information storage unit stores information regarding at least one process characteristic among photolithography, cleaning, CMP, film formation, etching, ion implantation, lamination, and dicing, as information regarding the process characteristics for manufacturing the semiconductor device. The semiconductor device design system according to any one of [1] to [3].

[0012] [5] The process characteristic information storage unit stores information regarding CMP as information regarding the process characteristics for manufacturing the semiconductor device. The design information optimization unit optimizes the design information of the semiconductor device stored in the design information storage unit by using the information regarding CMP stored in the process characteristic information storage unit. The semiconductor device design system according to any one of [1] to [3].

[0013] [6] The process characteristic information storage unit stores at least one of the basic characteristics of the polishing apparatus to be used, the relationship between the composition of the film to be polished and the polishing rate, the relationship between the slurry to be used and the polishing rate, the relationship between the wiring width of the layout and the polishing rate, the relationship between the composition of the film to be polished and the dishing amount, the relationship between the slurry to be used and the dishing amount, and the relationship between the wiring width of the layout and the dishing amount, as the information regarding CMP. The semiconductor device design system according to [5].

[0014] [7] The design information optimization unit optimizes the design information of the semiconductor device by arranging a dummy pattern at a predetermined position, changing the wiring width of the layout, changing the type of slurry used in CMP, or changing the composition of the film to be polished. The semiconductor device design system according to [5] or [6].

[0015] [8] The design information optimization unit includes an optimization model generation unit that performs machine learning using, as teacher data, the design information of the semiconductor device stored in the design information storage unit, the information on the process characteristics stored in the process characteristic information storage unit, and the information used when optimizing the design information of the semiconductor device, and generates an optimization model for optimizing the design information of the semiconductor device. The semiconductor device design system according to any one of [1] to [7].

[0016] [9] The design information optimization unit includes an optimization unit that optimizes the design information of the semiconductor device by inputting the design information of the semiconductor device stored in the design information storage unit into the optimization model generated by the optimization model generation unit. The semiconductor device design system according to [8].

[0017]

[10] A step of acquiring design information of a semiconductor device; A step of acquiring information on process characteristics for manufacturing the semiconductor device; And a step of optimizing the design information of the semiconductor device using the acquired information on the process characteristics, The design information of the semiconductor device is optimized so that the difference between the dimensions of the semiconductor device based on the design information of the semiconductor device and the dimensions of the semiconductor device after performing the process for manufacturing the semiconductor device is reduced. A method for designing a semiconductor device.

[0018]

[11] A process of acquiring design information of a semiconductor device; A process of acquiring information on process characteristics for manufacturing the semiconductor device; And a process of causing a computer to execute a process of optimizing the design information of the semiconductor device using the acquired information on the process characteristics, In the process of optimization, the design information of the semiconductor device is optimized so that the difference between the dimensions of the semiconductor device based on the design information of the semiconductor device and the dimensions of the semiconductor device after performing the process for manufacturing the semiconductor device is reduced. Program

Advantages of the Invention

[0019] According to the present disclosure, it is possible to provide a semiconductor device design system, a semiconductor device design method, and a program that can accurately design a semiconductor device in consideration of an actual manufacturing process.

Brief Description of the Drawings

[0020]

Fig. 1

Fig. 2A

Fig. 2B

Fig. 2C

Fig. 3A

Fig. 3B

Fig. 4A

Fig. 4B

Fig. 4C

Fig. 5

Fig. 6

Modes for Carrying Out the Invention

[0021] <Embodiment 1> Hereinafter, embodiments will be described with reference to the drawings. FIG. 1 is a block diagram for explaining a semiconductor device design system according to Embodiment 1. As shown in FIG. 1, a semiconductor device design system 1 according to the present embodiment includes a design information storage unit 11, a process characteristic information storage unit 12, a design information optimization unit 13, and an optimization information storage unit 14.

[0022] The design information storage unit 11 stores design information of a semiconductor device. Specifically, the design information storage unit 11 stores, as design information of the semiconductor device, information regarding the layout of the semiconductor device and information regarding manufacturing conditions when manufacturing the semiconductor device. In the present embodiment, the semiconductor device is a semiconductor integrated circuit such as a SoC (System on a Chip) or a system LSI (Large-Scale Integration).

[0023] The information regarding the layout of the semiconductor device is information regarding the layout of the semiconductor device created using a design tool such as TCAD (Technology Computer Aided Design). Specifically, the information regarding the layout of the semiconductor device is information regarding the wiring, power supply, and arrangement of each element (transistor, capacitor, etc.) of the semiconductor device.

[0024] The information regarding manufacturing conditions when manufacturing the semiconductor device is information regarding the process conditions of semiconductor manufacturing equipment used when manufacturing the semiconductor device. When manufacturing the semiconductor device, for example, photolithography, cleaning, CMP (Chemical Mechanical Polishing), film formation, etching, ion implantation, lamination, dicing, etc. are performed.

[0025] For example, the information regarding the process conditions of photolithography is information regarding the type of exposure apparatus, apparatus parameters, type of resist, type of light source, etc. The information regarding the process conditions of cleaning is information regarding the apparatus used for cleaning, cleaning time, type of cleaning, chemical solution used, etc. Information regarding the process conditions of CMP is information regarding the type of polishing apparatus to be used, the type of slurry, the type of polishing pad, the pressing load of the head, the rotation speed of the head, the polishing rate, and the like. Information regarding the process conditions of film formation is information regarding the type of film forming apparatus to be used, the film formation time, the type of raw material used for film formation, and the like. Information regarding the process conditions of etching is information regarding the type of etching apparatus to be used, the etching time, the type of raw material used for etching, and the like. Information regarding the process conditions of ion implantation is information regarding the type of ion implantation apparatus to be used, the ion implantation time, the type of raw material used for ion implantation, and the like. Information regarding the process conditions of lamination is information regarding the type of lamination apparatus to be used, the lamination time, the number of layers to be laminated, the temperature and pressure during lamination, and the like. Information regarding the process conditions of dicing is information regarding the type of dicing apparatus to be used, the dicing time, the dicing rate, and the like.

[0026] The process characteristic information storage unit 12 stores information regarding the process characteristics for manufacturing a semiconductor device. Specifically, the process characteristic information storage unit 12 stores, as information regarding the process characteristics for manufacturing a semiconductor device, information regarding at least one process characteristic among photolithography, cleaning, CMP, film formation, etching, ion implantation, lamination, and dicing.

[0027] For example, information regarding the process characteristics of photolithography is information regarding the change in exposure characteristics when parameters such as the type of exposure apparatus and apparatus parameters, the type of resist, and the type of light source are changed. Information regarding the process characteristics of cleaning is information regarding the change in cleaning characteristics when parameters such as the apparatus used for cleaning, the cleaning time, the type of cleaning, and the chemical solution used are changed. Information regarding the process characteristics of CMP is information regarding changes in polishing characteristics when parameters such as the type of polishing apparatus used, the type of slurry, the type of polishing pad, the pressing load of the head, the rotation speed of the head, and the polishing speed are changed. Information regarding the process characteristics of film formation is information regarding changes in film formation characteristics when parameters such as the type of film formation apparatus used, the film formation time, and the type of raw material used for film formation are changed. Information regarding the process characteristics of etching is information regarding changes in etching characteristics when parameters such as the type of etching apparatus used, the etching time, and the type of raw material used for etching are changed. Information regarding the process characteristics of ion implantation is information regarding changes in ion implantation characteristics when parameters such as the type of ion implantation apparatus used, the ion implantation time, and the type of raw material used for ion implantation are changed. Information regarding the process characteristics of lamination is information regarding changes in lamination characteristics when parameters such as the type of lamination apparatus used, the lamination time, the number of layers to be laminated, the temperature during lamination, and the pressure are changed. Information regarding the process characteristics of dicing is information regarding changes in dicing characteristics when parameters such as the type of dicing apparatus used, the dicing time, and the dicing speed are changed.

[0028] In other words, the process characteristic information storage unit 12 stores, as information regarding the process characteristics for manufacturing a semiconductor device, information regarding the results of basic condition setting of the apparatuses used in photolithography, cleaning, CMP, film formation, etching, ion implantation, lamination, and dicing. Information regarding the process characteristics for manufacturing a semiconductor device can be obtained by conducting experiments in advance using each apparatus.

[0029] The design information optimization unit 13 optimizes the design information of the semiconductor device stored in the design information storage unit 11 by using the information on the process characteristics stored in the process characteristic information storage unit 12. At this time, the design information optimization unit 13 optimizes the design information of the semiconductor device so that the difference between the dimensions of the semiconductor device based on the design information of the semiconductor device and the dimensions of the semiconductor device after performing the process for manufacturing the semiconductor device is reduced.

[0030] The design information of the semiconductor device stored in the design information storage unit 11 includes information on the manufacturing conditions when manufacturing the semiconductor device. The design information optimization unit 13 optimizes the information on the manufacturing conditions when manufacturing the semiconductor device by using the information on the process characteristics stored in the process characteristic information storage unit 12. That is, the design information optimization unit 13 optimizes the information on the manufacturing conditions (i.e., the information on the manufacturing conditions of photolithography, cleaning, CMP, film formation, etching, ion implantation, lamination, and dicing) among the design information of the semiconductor device stored in the design information storage unit 11.

[0031] In addition, the design information of the semiconductor device stored in the design information storage unit 11 includes information on the layout of the semiconductor device. The design information optimization unit 13 optimizes the information on the layout of the semiconductor device by using the information on the process characteristics stored in the process characteristic information storage unit 12. That is, the design information optimization unit 13 optimizes the layout information of the semiconductor device (such as the wiring of the semiconductor device, the power supply, the arrangement of each element (transistor, capacitor, etc.)) among the design information of the semiconductor device stored in the design information storage unit 11.

[0032] The optimization information storage unit 14 stores the design information of the semiconductor device optimized by the design information optimization unit 13. Note that the optimization information storage unit 14 may be omitted.

[0033] Next, the operation of the semiconductor device design system 1 according to the present embodiment will be specifically described with reference to FIGS. 2 to 5. Hereinafter, as an example, the case where the information regarding the manufacturing conditions when manufacturing a semiconductor device is the information regarding CMP will be described.

[0034] The process characteristic information storage unit 12 stores information regarding the process characteristics of CMP as information regarding the process characteristics for manufacturing a semiconductor device. The information regarding the process characteristics of CMP is information regarding the change in polishing characteristics when parameters such as the type of polishing apparatus to be used, the type of slurry, the type of polishing pad, the pressing load of the head, the rotation speed of the head, and the polishing speed are changed.

[0035] Furthermore, in the present embodiment, the process characteristic information storage unit 12 may store at least one of the basic characteristics of the polishing apparatus to be used, the relationship between the composition of the film to be polished and the polishing speed, the relationship between the slurry to be used and the polishing speed, the relationship between the wiring width of the layout and the polishing speed, the relationship between the composition of the film to be polished and the dishing amount, the relationship between the slurry to be used and the dishing amount, and the relationship between the wiring width of the layout and the dishing amount as information regarding CMP.

[0036] FIGS. 2A to 2C are diagrams showing an example of the information regarding the process characteristics of CMP. FIG. 2A shows the relationship between the wiring width of the layout and the dishing amount. As shown in FIG. 2A, in the CMP process, there is a relationship in which the dishing amount decreases as the wiring width becomes narrower. The process characteristic information storage unit 12 stores the relationship between the wiring width of the layout and the dishing amount as shown in FIG. 2A as information regarding the process characteristics of CMP.

[0037] FIG. 2B shows the relationship between the slurry used and the amount of dishing. As shown in FIG. 2B, in the CMP process, the amount of dishing changes depending on the slurry used. That is, when using slurry B, the amount of dishing is reduced compared to when using slurry A. The process characteristic information storage unit 12 stores the relationship between the slurry used and the amount of dishing as shown in FIG. 2B as information regarding the CMP process characteristics.

[0038] FIG. 2C shows the relationship between the composition of the film to be polished and the amount of dishing. As shown in FIG. 2C, in the CMP process, the amount of dishing changes depending on the composition of the film to be polished. That is, when using the stopper film B, the amount of dishing is reduced compared to when using the polishing film A. The process characteristic information storage unit 12 stores the relationship between the composition of the film to be polished and the amount of dishing as shown in FIG. 2C as information regarding the CMP process characteristics. Here, the composition of the film to be polished refers to the layer composition and the type of the film to be polished.

[0039] Note that the information regarding the CMP process characteristics shown in FIGS. 2A to 2C is an example, and the process characteristic information storage unit 12 may store information other than these as information regarding the CMP process characteristics. For example, the amount of dishing can be controlled by changing conditions such as the type of polishing pad, the pressing load of the head, and the rotation speed of the head. The process characteristic information storage unit 12 may store this information as information regarding the CMP process characteristics.

[0040] The design information optimization unit 13 (see FIG. 1) optimizes the design information of the semiconductor device stored in the design information storage unit 11 using the information regarding CMP stored in the process characteristic information storage unit 12. Hereinafter, the operation of the design information optimization unit 13 will be described in detail.

[0041] First, the design information optimization unit 13 performs an initial simulation using the design information of the semiconductor device stored in the design information storage unit 11. Specifically, as shown in the left diagram of FIG. 3A, after forming an insulating film 22 on a silicon substrate 21 on which a wiring pattern is formed, a state of polishing using CMP is simulated. As shown in the right diagram of FIG. 3, the silicon substrate 21 includes a region 31 with a wiring width W1 and a region 32 with a wiring width W2. As a result of the initial simulation, in the silicon substrate 21 (semiconductor device) after polishing using CMP, the polishing amount of the insulating film 22 is large in the region 31 with a wide wiring width, and the polishing amount of the insulating film 22 is small in the region 32 with a narrow wiring width. In other words, the dishing amount of the insulating film 22 is larger in the region 31 with a wide wiring width than in the region 32 with a narrow wiring width.

[0042] On the other hand, based on the design information of the semiconductor device stored in the design information storage unit 11, the dimensions (design values) of the semiconductor device are such that, as shown in FIG. 3B, the polishing amount of the insulating film 22 in the region 31 with a wide wiring width and the polishing amount of the insulating film 22 in the region 32 with a narrow wiring width are approximately the same.

[0043] Therefore, in the initial simulation state (the right figure in FIG. 3A), since the difference in the polishing amount between region 31 and region 32 is large, the design information optimization unit 13 optimizes the design information of the semiconductor device so that the difference between the dimensions of the semiconductor device based on the design information of the semiconductor device (FIG. 3B) and the dimensions of the semiconductor device after performing the process for manufacturing the semiconductor device (the right figure in FIG. 3A) is reduced. Specifically, the design information optimization unit 13 optimizes the CMP conditions when manufacturing the semiconductor device by using the information regarding the process characteristics of CMP stored in the process characteristic information storage unit 12. For example, the design information optimization unit 13 optimizes the design information of the semiconductor device by (1) arranging a dummy pattern at a predetermined position, (2) changing the wiring width of the layout, (3) changing the type of slurry used in CMP, or (4) changing the configuration of the film to be polished. By optimizing the design information of the semiconductor device in this way, the dishing amount of the insulating film can be reduced. Therefore, it is possible to suppress the deviation of the depth of focus in the next process of patterning or to suppress the disconnection of the wiring layer. Hereinafter, the case of optimizing the design information of the semiconductor device using the above (1) to (4) will be described in detail.

[0044] (1) When arranging a dummy pattern at a predetermined position In the process characteristic information storage unit 12, as information regarding the process characteristics of CMP, the relationship between the wiring width of the layout and the dishing amount as shown in FIG. 2A is stored. That is, when the wiring widths of the layout are about the same, the dishing amounts are about the same. The design information optimization unit 13 may optimize the design information of the semiconductor device by arranging the dummy pattern 24 in the region 31 of the silicon substrate 21 by using the relationship between the wiring width of the layout and the dishing amount stored in the process characteristic information storage unit 12 as shown in FIG. 4A. By arranging the dummy pattern 24 in this way, the wiring width of region 31 and the wiring width of region 32 can be made about the same. Therefore, the difference between the polishing amount of the insulating film 22 in the region 31 of the silicon substrate 21 and the polishing amount of the insulating film 22 in the region 32 can be reduced.

[0045] (2) When changing the wiring width of the layout In the example of (1) above, the dummy pattern 24 was arranged in the region 31, but the wiring width of the region 31 may be changed. That is, the design information optimization unit 13 may optimize the design information of the semiconductor device by changing the wiring width of the region 31 of the silicon substrate 21 using the relationship between the wiring width of the layout stored in the process characteristic information storage unit 12 and the dishing amount. That is, by changing the layout so that the wiring width of the region 31 is about the same as the wiring width of the region 32, the difference between the polishing amount of the insulating film 22 in the region 31 of the silicon substrate 21 and the polishing amount of the insulating film 22 in the region 32 can be reduced.

[0046] (3) When changing the type of slurry used in CMP In the process characteristic information storage unit 12, as information regarding the process characteristics of CMP, the relationship between the slurry to be used and the dishing amount as shown in FIG. 2B is stored. That is, even when the wiring widths of the layouts are different, there may be cases where the polishing amount of the insulating film 22 can be made about the same by changing the type of slurry to be used. As shown in FIG. 4B, the design information optimization unit 13 may optimize the design information of the semiconductor device by changing the slurry to be used using the relationship between the slurry to be used and the dishing amount stored in the process characteristic information storage unit 12. By changing the slurry to be used in this way, the difference between the polishing amount of the insulating film 22 in the region 31 of the silicon substrate 21 and the polishing amount of the insulating film 22 in the region 32 can be reduced.

[0047] (4) When changing the configuration of the film to be polished In the process characteristic information storage unit 12, as information regarding the process characteristics of CMP, the relationship between the structure of the film to be polished and the dishing amount as shown in FIG. 2C is stored. That is, even when the wiring widths of the layout are different, by changing the structure of the film to be polished, the polishing amount of the insulating film 22 can be made approximately the same. As shown in FIG. 4C, the design information optimization unit 13 may optimize the design information of the semiconductor device by changing the structure of the film to be polished using the relationship between the structure of the film to be polished and the dishing amount stored in the process characteristic information storage unit 12. That is, a film (stopper film) 25 that is difficult to polish is provided on the silicon substrate 21. By changing the structure of the film to be polished in this way, the difference between the polishing amount of the insulating film 22 in the region 31 of the silicon substrate 21 and the polishing amount of the insulating film 22 in the region 32 can be reduced.

[0048] The design information optimization unit 13 may determine the above (1) to (4) as candidates, and optimize the design information of the semiconductor device by using the optimal one among them. As described above, the operation of the design information optimization unit 13 has been explained, but the above operation is an example, and in the present embodiment, the design information optimization unit 13 may optimize the design information of the semiconductor device using other methods.

[0049] As described above, in the present embodiment, the design information optimization unit 13 optimizes the design information of the semiconductor device stored in the design information storage unit 11 using the information regarding the process characteristics stored in the process characteristic information storage unit 12. At this time, the design information optimization unit 13 optimizes the design information of the semiconductor device so that the difference between the dimensions of the semiconductor device based on the design information of the semiconductor device and the dimensions of the semiconductor device after performing the process for manufacturing the semiconductor device is reduced. Therefore, a semiconductor device design system capable of accurately designing a semiconductor device in consideration of the actual manufacturing process can be provided.

[0050] <Embodiment 2> Next, Embodiment 2 will be described. FIG. 5 is a block diagram for explaining a semiconductor device design system according to Embodiment 2. The semiconductor device design system 2 according to Embodiment 2 has a different configuration of the design information optimization unit 13a compared to the semiconductor device design system 1 according to Embodiment 1. For the rest, since it is the same as the semiconductor device design system 1 according to Embodiment 1, the same reference numerals are assigned to the same components, and duplicate explanations are omitted.

[0051] As shown in FIG. 5, in the semiconductor device design system 2 according to the present embodiment, the design information optimization unit 13a includes an optimization model generation unit 17 and an optimization unit 18. The optimization model generation unit 17 performs machine learning using, as teacher data, the design information of the semiconductor device stored in the design information storage unit 11, the information regarding the process characteristics stored in the process characteristic information storage unit 12, and the information used when optimizing the design information of the semiconductor device, and generates an optimization model for optimizing the design information of the semiconductor device.

[0052] For example, the optimization model generation unit 17 creates candidates (the above candidates (1) to (4)) for optimizing the design information of the semiconductor device using the method described in Embodiment 1, and determines the optimal candidate for optimizing the design information of the semiconductor device from among these candidates. The optimization model generation unit 17 performs machine learning using, as teacher data, the design information of the semiconductor device stored in the design information storage unit 11, the information regarding the process characteristics stored in the process characteristic information storage unit 12, and the information used when optimizing the design information of the semiconductor device (for example, any one of the above candidates (1) to (4)). By performing such machine learning, an optimization model for optimizing the design information of the semiconductor device is generated.

[0053] For example, the optimization model generation unit 17 can generate an optimization model by performing machine learning using a known machine learning algorithm such as a convolutional neural network (CNN), with the design information of the semiconductor device stored in the design information storage unit 11, the information regarding the process characteristics stored in the process characteristic information storage unit 12, and the information used when optimizing the design information of the semiconductor device as teacher data. As the known machine learning algorithms, VGG19, Inception V3, ResNet, etc. can be used.

[0054] The optimization unit 18 optimizes the design information of the semiconductor device by inputting the design information of the semiconductor device stored in the design information storage unit 11 into the optimization model generated by the optimization model generation unit 17.

[0055] Also in this embodiment, the design information optimization unit 13a optimizes the design information of the semiconductor device stored in the design information storage unit 11 using the information regarding the process characteristics stored in the process characteristic information storage unit 12. Therefore, a semiconductor device design system that can accurately design a semiconductor device in consideration of the actual manufacturing process can be provided.

[0056] <Other Embodiments> Hereinafter, the semiconductor device design method according to this embodiment will be described. The semiconductor device design method according to this embodiment includes a step of acquiring the design information of the semiconductor device, a step of acquiring the information regarding the process characteristics for manufacturing the semiconductor device, and a step of optimizing the design information of the semiconductor device using the acquired information regarding the process characteristics. And in this embodiment, the design information of the semiconductor device is optimized so that the difference between the dimensions of the semiconductor device based on the design information of the semiconductor device and the dimensions of the semiconductor device after performing the process for manufacturing the semiconductor device is reduced.

[0057] Next, with reference to FIG. 6, a hardware configuration example of the semiconductor device design systems 1 and 2 according to the present embodiment will be described. The semiconductor device design systems 1 and 2 include a processor 101 and a memory 102. The processor 101 may be, for example, a microprocessor, an MPU (Micro Processing Unit), or a CPU (Central Processing Unit). The processor 101 may include a plurality of processors. The memory 102 is configured by a combination of a volatile memory and a non-volatile memory. The memory 102 may include a storage disposed away from the processor 101. In this case, the processor 101 may access the memory 102 via an input / output interface (not shown).

[0058] Also, each device in the above-described embodiment is configured by hardware or software, or both, and may be configured by one piece of hardware or software, or may be configured by a plurality of pieces of hardware or software. The functions (processes) of each device in the above-described embodiment may be realized by a computer. For example, a program for performing the operations in the embodiment may be stored in the memory 102, and each function may be realized by the processor 101 executing the program stored in the memory 102.

[0059] The program according to the present embodiment is a program that causes a computer to execute a process of acquiring design information of a semiconductor device, a process of acquiring information regarding process characteristics for manufacturing the semiconductor device, and a process of optimizing the design information of the semiconductor device using the acquired information regarding the process characteristics. Then, in the optimization process, the program optimizes the design information of the semiconductor device so that the difference between the dimensions of the semiconductor device based on the design information of the semiconductor device and the dimensions of the semiconductor device after performing the process for manufacturing the semiconductor device is reduced.

[0060] The program includes a set of instructions (or software code) that cause a computer to perform one or more of the functions described in the embodiments when loaded into the computer. The program may be stored in a non-transitory computer-readable medium or a tangible storage medium. By way of example and not limitation, a computer-readable medium or a tangible storage medium includes random-access memory (RAM), read-only memory (ROM), flash memory, solid-state drive (SSD), or other memory technologies, CD-ROM, digital versatile disk (DVD), Blu-ray (registered trademark) disk, or other optical disk storage, magnetic cassette, magnetic tape, magnetic disk storage, or other magnetic storage devices. The program may also be transmitted on a transitory computer-readable medium or a communication medium. By way of example and not limitation, a transitory computer-readable medium or a communication medium includes electrical, optical, acoustic, or other forms of propagated signals.

[0061] As described above, the present invention has been described with reference to the above embodiments. However, the present invention is not limited only to the configurations of the above embodiments, and of course includes various modifications, corrections, and combinations that can be made by those skilled in the art within the scope of the invention of the claims of the present patent application.

Explanation of Reference Numerals

[0062] 1, 2 Semiconductor device design system 11 Design information storage unit 12 Process characteristic information storage unit 13, 13a Design information optimization unit 14 Optimization information storage unit 17 Optimization model generation unit 18 Optimization unit 21 Silicon substrate 22 Insulating film 24 Dummy pattern 25 Film 31, 32 Region 101 Processor 102 Memory

Claims

1. a design information storage unit that stores design information of a semiconductor device; a process characteristic information storage unit that stores information regarding process characteristics for manufacturing the semiconductor device; a design information optimization unit that optimizes the design information of the semiconductor device stored in the design information storage unit by using the information regarding the process characteristics stored in the process characteristic information storage unit; the design information optimization unit is configured to optimize the design information of the semiconductor device such that a difference between dimensions of the semiconductor device based on the design information of the semiconductor device and dimensions of the semiconductor device after performing a process for manufacturing the semiconductor device is reduced; the process characteristic information storage unit stores at least one of basic characteristics of a polishing apparatus used in a CMP process, a relationship between a configuration of a film to be polished and a polishing rate, a relationship between a slurry used and the polishing rate, a relationship between a wiring width of a layout and the polishing rate, a relationship between a configuration of a film to be polished and a dishing amount, a relationship between a slurry used and the dishing amount, and a relationship between a wiring width of a layout and the dishing amount as information regarding process characteristics for manufacturing the semiconductor device; the design information optimization unit is configured to optimize the design information of the semiconductor device by using an optimal candidate from among a first candidate of arranging a dummy pattern at a predetermined position, a second candidate of changing a wiring width of a layout, a third candidate of changing a type of slurry used in CMP, and a fourth candidate of changing a configuration of a film to be polished; the design information optimization unit performs machine learning using, as teacher data, the design information of the semiconductor device stored in the design information storage unit, the information regarding the process characteristics stored in the process characteristic information storage unit, and information used when optimizing the design information of the semiconductor device, to generate an optimization model for optimizing the design information of the semiconductor device; an optimization model generation unit; an optimization unit that optimizes the design information of the semiconductor device by inputting the design information of the semiconductor device stored in the design information storage unit into the optimization model generated by the optimization model generation unit; The optimization model generation unit creates the first to fourth candidates as candidates for optimizing the design information of the semiconductor device, determines the optimal candidate for optimizing the design information of the semiconductor device from among the first to fourth candidates, and uses the determined candidate as information used when optimizing the design information of the semiconductor device for machine learning. A semiconductor device design system. **Claim 2** The design information of the semiconductor device stored in the design information storage unit includes information regarding manufacturing conditions when manufacturing the semiconductor device. The design information optimization unit optimizes the information regarding manufacturing conditions when manufacturing the semiconductor device by using the information regarding process characteristics stored in the process characteristic information storage unit. The semiconductor device design system according to claim 1. **Claim 3** The design information of the semiconductor device stored in the design information storage unit includes information regarding the layout of the semiconductor device. The design information optimization unit optimizes the information regarding the layout of the semiconductor device by using the information regarding process characteristics stored in the process characteristic information storage unit. The semiconductor device design system according to claim 1 or 2. **Claim 4** The process characteristic information storage unit stores information regarding at least one process characteristic among photolithography, cleaning, CMP, film formation, etching, ion implantation, lamination, and dicing as information regarding process characteristics for manufacturing the semiconductor device. The semiconductor device design system according to claim 1 or 2. **Claim 5** The process characteristic information storage unit stores information regarding CMP as information regarding process characteristics for manufacturing the semiconductor device. The design information optimization unit optimizes the design information of the semiconductor device stored in the design information storage unit by using the information regarding CMP stored in the process characteristic information storage unit. The semiconductor device design system according to claim 1. **Claim 6** A design information acquisition step of acquiring design information of a semiconductor device; A process characteristic information acquisition step of acquiring information regarding process characteristics for manufacturing the semiconductor device; A design information optimization step of optimizing the design information of the semiconductor device by using the acquired information regarding process characteristics. The design information optimization process is a process of optimizing the design information of the semiconductor device so that the difference between the dimensions of the semiconductor device based on the design information of the semiconductor device and the dimensions of the semiconductor device after implementing the process for manufacturing the semiconductor device is reduced. The information regarding the process characteristics for manufacturing the semiconductor device is at least one of the basic characteristics of the polishing apparatus used in the CMP process, the relationship between the composition of the film to be polished and the polishing rate, the relationship between the slurry used and the polishing rate, the relationship between the wiring width of the layout and the polishing rate, the relationship between the composition of the film to be polished and the dishing amount, the relationship between the slurry used and the dishing amount, and the relationship between the wiring width of the layout and the dishing amount. The design information optimization process uses, as a first candidate, arranging a dummy pattern at a predetermined position, as a second candidate, changing the wiring width of the layout, as a third candidate, changing the type of slurry used in CMP, and as a fourth candidate, changing the composition of the film to be polished, and is a process of optimizing the design information of the semiconductor device using the optimal candidate from among the first to fourth candidates. The design information optimization process further includes an optimization model generation process of performing machine learning using the design information of the semiconductor device, the information regarding the process characteristics, and the information used when optimizing the design information of the semiconductor device as teacher data to generate an optimization model for optimizing the design information of the semiconductor device, and an optimization process of optimizing the design information of the semiconductor device by inputting the design information of the semiconductor device into the optimization model generated in the optimization model generation process. The optimization model generation process creates the first to fourth candidates as candidates for optimizing the design information of the semiconductor device, determines the optimal candidate for optimizing the design information of the semiconductor device from among the first to fourth candidates, and performs machine learning using the determined candidate as the information used when optimizing the design information of the semiconductor device. A method for designing a semiconductor device.

7. a design information acquisition process for acquiring the design information of the semiconductor device, a process characteristic information acquisition process for acquiring the information regarding the process characteristics for manufacturing the semiconductor device, and a design information optimization process for optimizing the design information of the semiconductor device using the acquired information regarding the process characteristics. In the design information optimization process, the design information of the semiconductor device is optimized so that the difference between the dimensions of the semiconductor device based on the design information of the semiconductor device and the dimensions of the semiconductor device after performing the process for manufacturing the semiconductor device is reduced. The information regarding the process characteristics for manufacturing the semiconductor device is at least one of the basic characteristics of the polishing apparatus used in the CMP process, the relationship between the composition of the film to be polished and the polishing rate, the relationship between the slurry used and the polishing rate, the relationship between the wiring width of the layout and the polishing rate, the relationship between the composition of the film to be polished and the dishing amount, the relationship between the slurry used and the dishing amount, and the relationship between the wiring width of the layout and the dishing amount. The design information optimization process is a process of optimizing the design information of the semiconductor device using the optimal candidate from among the first to fourth candidates, where the first candidate is to place a dummy pattern at a predetermined position, the second candidate is to change the wiring width of the layout, the third candidate is to change the type of slurry used in CMP, and the fourth candidate is to change the composition of the film to be polished. The design information optimization process further includes an optimization model generation process of performing machine learning using the design information of the semiconductor device, the information regarding the process characteristics, and the information used when optimizing the design information of the semiconductor device as teacher data to generate an optimization model for optimizing the design information of the semiconductor device, and an optimization process of optimizing the design information of the semiconductor device by inputting the design information of the semiconductor device into the optimization model generated in the optimization model generation process. The optimization model generation process creates the first to fourth candidates as candidates for optimizing the design information of the semiconductor device, determines the optimal candidate for optimizing the design information of the semiconductor device from among the first to fourth candidates, and uses the determined candidate as the information used when optimizing the design information of the semiconductor device for machine learning. Causes a computer to execute a process Program.

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