Power overlay structure having wire bonds and method of manufacturing the same

Abstract

To provide a power overlay (POL) structure that enables copper wire bonding of power devices regardless of material types of contact pads of the power devices.SOLUTION: A power overlay (POL) structure 134 includes: a power device (semiconductor device 38) having at least one upper contact pad 44, 46 disposed on an upper surface thereof; and a POL interconnect layer 88 having a dielectric layer 74 coupled to the upper surface of the power device and a metallization layer 80 having metal interconnects 144 extending through vias 138 formed through the dielectric layer and electrically coupled to the at least one upper contact pad of the power device. The POL structure also includes at least one copper wirebond 96 directly coupled to the metallization layer.SELECTED DRAWING: Figure 9

Description

Technical Field

[0001] Embodiments of the present invention generally relate to structures and methods for wire bonding of power devices, and more particularly, to a power overlay (POL) structure that enables copper wire bonding of power devices regardless of the type of material of the contact pads of the power devices.

[0002] Power semiconductor devices are semiconductor devices used as switches or rectifiers in power electronic circuits such as switching power supplies. In use, semiconductor devices are typically mounted on an external circuit as a package structure. At this time, the package structure provides an electrical connection to the external circuit, further removes heat generated by the device, and provides a method of protecting the device from the external environment. Power semiconductor devices are provided with several input / output (I / O) interconnects to electrically connect the device to an external circuit. These I / O connections can be provided in the form of solder balls, plated bumps, or wire bond connections. In the case of a wire bond package, a wire bond is provided to connect a bond pad or contact pad provided on a power semiconductor device to a corresponding pad or conductive element of the next level of package, which may be a circuit board or a lead frame. Most existing power device package structures use a combination of wire bonds and a substrate (e.g., a direct bonded copper (DBC) substrate) to provide I / O interconnects to both sides of each semiconductor device. The package structure may be wired (such as a lead frame), or may be provided with bolted terminals for electrical connection to the package structure. The wire bond forms an electrical connection from one side of the package structure to the package pins, then connects to an external circuit, and the DBC substrate electrically couples the other side of the package structure to the external circuit.

[0003] FIG. 1 shows a wire-bonded power package structure 10 according to known prior art having a semiconductor device 12 with a gate contact pad 14 and an emitter contact pad 16 coupled to an upper surface 18 of the semiconductor device 12. As shown, wire bonds 20, 22, 24 are directly bonded to the contact pads 14, 16 of the semiconductor device 12. To form a reliable connection between the wire bonds 20, 22, 24 and the upper contact pads 14, 16 of the semiconductor device 12, the material of the wire bonds 20, 22, 24 is typically selected to be compatible with the metal coating of the upper contact pads 14, 16.

[0004] Often, a collector pad 26 in the form of a nickel-gold coating or a nickel-silver coating is formed on the lower surface 28 of the semiconductor device 12. To bond the semiconductor device 12 to a DBC or direct bond aluminum (DBA) substrate 32, solder 30 or a sintered silver die attach material is used.

[0005] Power devices are typically manufactured with aluminum contact pads, so corresponding wire bonds are also formed of aluminum or an aluminum alloy in order to make a reliable electrical connection to the power device. Currently, in the industry, copper wire bonds, which have low electrical resistance and thus low losses and high efficiency, are trending. However, copper wire bonds do not form a reliable electrical connection to the aluminum coating of the contact pads.

[0006] During manufacturing, copper contact pads can be incorporated into power devices, but it is not easy to incorporate copper into the manufacturing process of power devices, and significant development costs and time are added. Also, manufacturers typically supply a single type of metal coating material to all of the power devices they produce. Considering that a power module may incorporate power devices from multiple manufacturers, the various power devices within a given module may contain dissimilar metal coating materials, making it difficult to form reliable wire bonds to these power devices.

[0007] Even when a power device is provided with a copper coating, bonding a copper wire bond to the copper metal coating is challenging. For example, bonding a copper wire bond, particularly a thick copper wire bond that can withstand temporarily high currents, to a metal coated pad or contact pad places greater stress on the power device than in the case of a thinner or aluminum wire bond. This is because bonding copper to copper requires higher energy for joining due to its material properties compared to bonding aluminum to aluminum. Due to these higher energies, the wire bonding process can damage the power device.

[0008] Another issue associated with wire bonding copper to copper is current constriction when current flows from the contact pad of the power device to the wire bond. The metal coating layer of the contact pad of the power device is thin (e.g., a few microns), and the current must pass through this thin metal coating until it reaches and flows through the wire bond. The wire bonds can only be placed at specific intervals due to device constraints, and thus each power device can only have a few wire bonds distributed across the contact pad. Providing several wire bonds to each contact pad helps distribute the current, but there are still inherent losses in the resistance within the interconnect structure.

[0009] Conventionally, attempts have been made to mitigate the above problems related to wire bonding copper to copper, such as optimizing the material properties of the copper of the contact pads or adjusting the thickness of the copper pads, but there is still room for improvement in this field.

[0010] Therefore, it is desirable to provide a POL structure that can use copper wire bonding without changing the metal coating of the contact pads of the power device to copper. It is also desirable to have a method for fabricating an I / O interconnect in the form of a wire bond that reduces device damage due to stress during the wire bond process, thereby increasing the process yield and providing efficient current distribution from the power device to the wire bond.

Prior Art Documents

Patent Documents

[0011]

Patent Document 1

Summary of the Invention

Means for Solving the Problems

[0012] According to one aspect of the present invention, a power over - lay (POL) structure includes a power device having at least one upper contact pad disposed on its upper surface, a dielectric layer bonded to the upper surface of the power device, and a POL interconnect layer having a metal interconnect that extends through a via formed through the dielectric layer and having a metal coating layer electrically coupled to at least one upper contact pad of the power device. The POL structure also includes at least one copper wire bond directly bonded to the metal coating layer.

[0013] According to another aspect of the invention, a method of fabricating a POL structure includes the steps of providing a wafer including a plurality of semiconductor devices, bonding a dielectric layer to a top surface of each of the plurality of semiconductor devices, forming a plurality of vias through the dielectric layer to expose at least one contact pad of the plurality of semiconductor devices, and forming a metallization layer on the top surface of the dielectric layer, the metallization layer having metal interconnects extending through the plurality of vias and electrically coupling with the at least one contact pad of the plurality of semiconductor devices. The method further includes bonding at least one wire bond to the top surface of the metallization layer.

[0014] According to yet another aspect of the present invention, the POL assembly includes a first semiconductor device, a second semiconductor device, and a first semiconductor device adhesively bonded to top contact pads of the first and second semiconductor devices. and a POL interconnect assembly having a bonded polyimide film and metallization pathways formed in the polyimide film, the metallization pathways including a plurality of metal interconnects extending through vias formed through the polyimide film and electrically coupled to the top contact pads of the first and second semiconductor devices. The POL assembly also includes a plurality of copper wirebonds bonded directly to the metallization pathways, where a first wirebond of the plurality of copper wirebonds is electrically coupled to the top contact pad of the first semiconductor device and a second wirebond of the plurality of copper wirebonds is electrically coupled to the top contact pad of the second semiconductor device.

[0015] These and other advantages and features will be more readily understood from the following detailed description of preferred embodiments of the invention, which are provided in conjunction with the accompanying drawings.

[0016] The figures illustrate embodiments presently contemplated for carrying out the invention. [Brief description of the drawings]

[0017]

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DETAILED DESCRIPTION OF THE INVENTION

[0018] Embodiments of the present invention provide a POL structure including a power over laminate (POL) interconnect layer and a method of forming such a POL structure. The term "POL" as used herein refers to a structure that enables copper wire bonding of a power device regardless of the type of material of the contact pad of the power device. With this POL interconnect layer, copper wire bonding can be reliably connected to the POL structure regardless of the materials of the gate pad and the emitter pad. In addition, the POL interconnect layer is designed to function as a stress relief material that reduces damage to the power device in the process of bonding the wire bond to the contact pad of the device. By providing a parallel path for the current to flow through the metal coating of the power device before entering the wire bond, the POL structure disclosed herein reduces the resistance and loss of the interconnect compared to prior art wire bond power devices.

[0019] Figures 2 to 6 illustrate techniques for manufacturing the POL structure 34 according to embodiments of the present invention, where each of Figures 2 to 6 shows a cross-section of the POL structure 34 during the build-up process. First, referring to Figure 2, a wafer 36 is shown. According to one embodiment, the wafer 36 includes a plurality of semiconductor dies or semiconductor devices 38, 40, 42. The semiconductor devices 38, 40, 42 are, by way of non-limiting example, insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs), bipolar junction transistors (BJTs), integrated gate-commutated thyristors (IGCTs), gate turn-off (GTO) thyristors, silicon controlled rectifiers (SCRs), diodes, or other devices or combinations of devices including materials such as silicon (Si), silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), etc., which are power devices. Figure 2 shows a wafer 36 having three semiconductor devices 38, 40, 42, but it is contemplated that the wafer 36 may include more or fewer than three semiconductor devices.

[0020] Each of the semiconductor devices 38, 40, 42 can include one or more upper contact pads 44, 46, 48, 50, 52, 54 disposed on the upper surfaces 56, 58, 60 of the respective semiconductor devices 38, 40, 42. These upper contact pads 44 - 54 provide conductive paths to internal contacts within each of the semiconductor devices 38, 40, 42. In the illustrated embodiment, each of the semiconductor devices 38, 40, 42 includes a pair of upper contact pads, which are coupled to the corresponding emitter and / or gate, or anode regions of the semiconductor devices 38, 40, 42. In one embodiment, the semiconductor devices 38, 40, 42 are IGBTs having contact pads 44 - 54 coupled to each emitter region and gate region of the respective semiconductor devices 38, 40, 42. Specifically, semiconductor device 38 includes gate pad 44 and emitter pad 46, semiconductor device 40 includes gate pad 48 and emitter pad 50, and semiconductor device 42 includes gate pad 52 and emitter pad 54. It is contemplated that the semiconductor dies 38, 40, 42 can be provided with a different number of contact pads and / or different combinations of contact pads than those described above. As one non - limiting example, semiconductor die 38 can be provided with a pair of emitter pads. In one example, contact pads 44, 46, 48 include aluminum. However, it is contemplated that contact pads 44, 46, 48 can be formed from other types of conductive materials, such as copper, for example. Each of the semiconductor devices 38, 40, 42 also includes at least one lower contact pad or collector pad 62, 64, 66 disposed on the lower surfaces 68, 70, 72 of the respective semiconductor devices 38, 40, 42.

[0021] As shown in FIG. 3, the manufacture of the POL structure 34 begins with coupling a dielectric layer 74 to the upper surfaces 56, 58, 60 of semiconductor devices 38, 40, 42 using an adhesive layer 76. According to various embodiments, the dielectric layer 74 can be in the form of a stable non-flowing thin layer or film and can be formed of one of a plurality of dielectric materials such as Kapton®, Ultem®, polytetrafluoroethylene (PTFE), Upilex®, polysulfone materials (e.g., Udel®, Radel®), or another polymer film such as a liquid crystal polymer (LCP) or a polyimide material. In one embodiment, the dielectric layer 74 may be stretched on a frame (not shown) to control distortion during the manufacturing process. The adhesive layer 76 can be applied to the dielectric layer 74 using a spin coating technique, and then the wafer 36 is placed on the adhesive layer 76 using conventional pick and place equipment and methods.

[0022] In FIG. 3, the POL structure 34 is depicted as having separate dielectric layer 74 and adhesive layer 76, but in an alternative embodiment, it is contemplated that layers 74, 76 can be replaced by a single adhesive dielectric layer. Non-limiting examples of such adhesive dielectric layers include spin-on dielectrics such as polyimide or polybenzoxazole (PBO).

[0023] Next, referring to FIG. 4, a plurality of vias 78 are formed through the dielectric layer 74 and the adhesive layer 76 so as to expose the contact pads 44, 46, 48 of the respective semiconductor devices 38, 40, 42. The vias 78 can be formed, for example, by laser drilling or dry etching, although not limited thereto. As shown in FIG. 5, in the next step of the manufacturing process, a metallized path or metallized layer 80 is formed on the upper surface 82 of the dielectric layer 74. The metallized layer 80 extends through the vias 78 and includes a first portion 84 of a metal interconnect that electrically couples to the contact pads 44, 48, 52 of the semiconductor devices 38, 40, 42, and a second portion 86 of a metal interconnect that extends through the vias 78 and electrically couples to the contact pads 46, 50, 54 of the semiconductor devices 38, 40, 42. In a preferred embodiment, the metallized path 80 includes a layer of copper. However, this manufacturing technique is believed to be extensible to use other conductive materials for the metallized path 80. In one embodiment, the metallized path 80 can be formed using sputtering and plating techniques, followed by a lithography process. The metallized path 80, the vias 78, the dielectric layer 74, and the adhesive layer 76 together form a POL interconnect layer 88.

[0024] Referring to FIG. 6, the POL structure 34 is cut or singulated into individual POL structures 90, 92, 94. Each POL structure 90, 92, 94 includes each semiconductor device 38, 40, 42, and each semiconductor device 38, 40, 42 has a portion of the POL interconnect layer 88 bonded thereto. Since the wafer 36 may include more or fewer semiconductor devices than the three semiconductor devices 38, 40, 42, it is contemplated that the POL structure 34 can be divided into more or fewer POL structures than the three POL structures 90, 92, 94.

[0025] Next, referring to FIG. 7, after the POL structure 34 is cut or separated into individual POL structures 90, 92, 94, in the next step of the manufacturing technique, one or more wire bonds are coupled to the metallized path 80. In the illustrated embodiment, by the wire bond process, wire bonds 96, 98 are coupled to the metal interconnect 86 of the metallized path 80, and wire bond 100 is joined to the metal interconnect 84. However, in alternative embodiments, more or fewer than two wire bonds may be incorporated into the second portion 86 of the metal interconnect, and / or more than one wire bond 100 may be joined to the first portion 84 of the metal interconnect. According to an exemplary embodiment of the present invention, wire bonds 96, 98, 100 are copper.

[0026] In one embodiment, wire bonds 96, 98 are thicker or Provided with a large diameter, whereby wire bonds 96, 98 can handle a larger amount of current passing through contact pad 46 with lower electrical resistance. As one non-limiting example, wire bonds 96, 98 can be provided as "heavy" copper wire bonds having a diameter of about 10 to 20 mils. On the other hand, wire bond 100 can be provided, for example, as a copper wire bond that is "thin" relative to wire bonds 96, 98 in the range of about 3 to 10 mils in diameter. In such non-limiting embodiments of the present invention, the surface contact area 102 between the heavy wire bonds 96, 98 and the metal-coated path 80 can be about 50 mils × 80 mils. On the other hand, the surface contact area 104 between the thin wire bond 100 and the metal-coated path 80 can be, for example, in the range of about 10 to 15 mils × 20 mils. In exemplary embodiments of the present invention, the width of the surface contact areas 102, 104 is 2 to 3 times the diameter of each of the wire bonds 96, 98, 100, and the length of the surface contact areas 102, 104 is 4 to 5 times the diameter of each of the wire bonds 96, 98, 100. However, embodiments of the present invention are not limited to the specific wire gauges used for wire bonds 96, 98, 100, and it will be recognized by those skilled in the art that the diameter or gauge of wire bonds 96, 98, 100 can be varied as desired for a given application, and the corresponding surface area can vary accordingly.

[0027] The multilayer substrate 106 is thermally and electrically coupled to the contact pad 62 of the semiconductor device 38 via solder 108. In one embodiment, the multilayer substrate 106 is a pre-fabricated direct-bonded copper (DBC) including, for example, an inorganic ceramic substrate 110 such as alumina, aluminum nitride, silicon nitride, etc., and having upper and lower copper sheets 112, 114 joined to both sides of the substrate via a direct-bonded copper interface or brazing layer. In another embodiment of the present invention, it is contemplated that the multilayer substrate 106 can be a direct-bonded aluminum (DBA) substrate having upper and lower aluminum sheets 112, 114.

[0028] FIG. 7 and the following figures show a multilayer substrate 106 thermally and electrically coupled to contact pad 62. However, alternative embodiments may include a single layer substrate, such as a lead frame, for example, instead of the multilayer substrate 106.

[0029] As shown in FIG. 7, semiconductor device 38 is provided having a thickness 116 of about 50 to 500 microns. Additionally, the thickness 118 of metal coated path 80 can range from about 5 to 150 microns, and the thickness 120 of dielectric layer 74 can be about 0.5 to 2 mils.

[0030] In the embodiment shown in FIG. 7, each wire bond 96, 98, 100 is coupled to respective portions 122, 124, 126 of POL interconnect layer 88 that include at least one metal interconnect 84, 86, or a portion thereof. Specifically, portion 126 of POL interconnect layer 88 under contact surface 128 of wire bond 100 includes one metal interconnect 84, and portions 122, 124 of POL interconnect layer 88 under respective contact surfaces 130, 132 of wire bonds 96, 98 each include portions of at least two metal interconnects 86. Thus, metal interconnect 86 forms multiple parallel paths for current from semiconductor device 38 through wire bonds 96, 98.

[0031] Figures 8 and 9 show the positioning of wire bond 96 within POL structure 134 according to another embodiment of the present invention. Elements and components common to POL structure 134 and POL structure 34 are referred to herein with like part numbers as appropriate. As shown, wire bond 96 is positioned within a recess or well 136 formed in dielectric layer 74. Well 136 is formed by creating a large via 138 within adhesive layer 76 and dielectric layer 74 that exposes a portion of contact pad 46 having a surface area 140 larger than the surface area 142 of wire bond 96. When metal-coated path 80 is created, metal-coated path 80 extends into via 138 and forms a metal interconnect 144 having a relatively flat upper contact surface 146. The surface area 148 of upper contact surface 146 is larger than the corresponding surface area 142 of wire bond 96. Accordingly, the contact surface 150 of wire bond 96 is positioned lower than the top surface 152 of metal-coated path 80. In this embodiment, metal-coated path 80 is in direct contact with contact pad 46 as shown in FIG. 9, and no portion of adhesive layer 76 or dielectric layer 74 is positioned therebetween. Accordingly, there is substantially no portion of dielectric layer 74 or adhesive layer 76 in portion 154 of POL structure 134 below contact surface 150 of wire bond 96. In this embodiment, the large surface areas of metal-coated path 80 and contact pad 46 reduce the resistance of the current path between contact pad 46 and wire bond 96.

[0032] In another embodiment, when metal-coated path 80 is created by extending into via 138 to form metal interconnect 144, flat upper contact surface 146 and surface 152 of metal-coated path 80 are considered to be in the same plane. Accordingly, wire bond 96 is positioned at the same height as the top surface 152 of metal-coated path 80. In this embodiment, there is still substantially no portion of dielectric layer 74 or adhesive layer 76 in portion 154 of POL structure 134 below contact surface 150 of wire bond 96.

[0033] Next, referring to FIGS. 10 and 11, a POL structure 156 according to an alternative embodiment of the present invention is shown. Also in this case, elements common to the POL structure 156 and the POL structure 34 are referred to by the same reference numerals as appropriate. As shown, the wire bonds 96, 100 are coupled to the metal-coated path 80 at a portion of the POL structure 156 without vias 78. Thus, in this embodiment, vias 78 are not disposed in portions 158, 160 of the dielectric layer 74 positioned directly below each contact position 162, 164 of the wire bonds 96, 100. The thickness 120 of the dielectric layer 74 is substantially uniform in the portion of the POL structure 156 under the wire bonds 96, 100 and serves as a stress-relieving material that reduces potential damage to the semiconductor device 38 during the wire bonding process.

[0034] The wire bonds 96, 98, 100 and the DBC substrate 106 were described above as being coupled to individual semiconductor devices 38 in FIGS. 7 - 11, but it is contemplated that the DBC substrate 106 and / or the wire bonds 96, 98, 100 can be adhered to each semiconductor device 38, 40, 42 at the wafer stage (i.e., before singulation).

[0035] In an alternative embodiment, the POL interconnect layer 166 may be formed simultaneously on a plurality of individual semiconductor devices provided within a package or a redistribution wafer. Referring now to FIG. 12, a redistribution wafer 168 is shown having a plurality of semiconductor devices 170, 172 coupled to a removable support structure 174. In an alternative embodiment, it will be appreciated by those skilled in the art that the redistribution wafer 168 may include more than two semiconductor devices 170, 172. Similar to the semiconductor devices 38, 40, 42 of FIGS. 2-6, the semiconductor devices 170, 172 include a plurality of upper contact pads 176, 178, 180, 182, and at least one lower contact pad or collector pad 184, 186. The upper contact pads 176-182 can include various combinations of emitter pads and / or gate pads. In a preferred embodiment, the upper contact pads 176-182 are aluminum or copper. However, it is contemplated that the upper contact pads 176-182 can include alternative metal cladding materials.

[0036] As shown in FIG. 12, the semiconductor devices 170, 172 are of various thicknesses 188, 190, and the thickness 188 of the semiconductor device 170 is greater than the thickness 190 of the semiconductor device 172. In view of this thickness difference, a shim 192 can be positioned between the thinner semiconductor device and the removable support structure 174 within the wafer 168 such that the upper surfaces 194 of the contact pads 176, 178 of the semiconductor device 170 are substantially coplanar with the upper surfaces 196 of the contact pads 180, 182 of the semiconductor device 172.

[0037] Once the upper surfaces 194-196 of the semiconductor devices 170, 172 are positioned in a substantially coplanar plane, the POL interconnect layer 166 is formed on top of the semiconductor devices 170, 172 in a manner similar to that described with respect to FIGS. 3-5. When adhering the dielectric layer 200 to the semiconductor devices 170, 172, a single adhesive layer can be spin-coated on top of the dielectric layer 200 in a manner similar to that described with respect to the dielectric layer 74 (FIG. 3), or as shown in FIG. 11, it is considered that individual layers 202, 204 of the adhesive can be formed on top of each of the semiconductor devices 170, 172. In any case, the dielectric layer 200 is positioned so as to span the gap 206 between the adjacent semiconductor devices 170, 172. According to various embodiments, the dielectric layer 200 can be in the form of a thin layer or film and can be formed of one of a plurality of dielectric materials, similar to the dielectric layer 74.

[0038] In an alternative embodiment of the present invention, the semiconductor devices 170, 172 are coupled to the dielectric layer 200 via each of the adhesive layers 202, 204 (or a single adhesive layer). Here, instead of adhering the dielectric layer 200 to the semiconductor devices 170, 172, the semiconductor devices 170, 172 are coupled to the dielectric layer 200 by placing the semiconductor devices 170, 172 on top of the adhesive layers 202, 204. Accordingly, the removable support structure 174 can be omitted.

[0039] In another embodiment of the present invention shown in FIG. 13, the POL interconnect layer 208 can be formed having a dielectric layer 210 constructed to correct for the difference in thicknesses 188, 190 of the semiconductor devices 170, 172. As shown, the first portion 212 of the dielectric layer 210 disposed in alignment with the semiconductor device 170 has a first thickness 214, and the second portion 216 of the dielectric layer 210 disposed in alignment with the semiconductor device 172 has a second thickness 218. A step 220 is positioned at the transition between the first portion 212 and the second portion 216. In yet another embodiment of the present invention, the difference in height of the semiconductor devices 170, 172 can be corrected by varying the thickness of the adhesive layers 202, 204.

[0040] Referring to FIGS. 12 and 13 together, a plurality of vias 222 are formed through dielectric layer 200 and adhesive layers 202, 204 to expose contact pads 176, 178, 180, 182 in order to complete each POL interconnect layer 166. Next, a metallized path 224 is formed on the upper surface 226 of dielectric layer 200. Metallized layer 224 includes metal interconnects 228 that extend through vias 222 and are electrically coupled to contact pads 176, 180, and metal interconnects 230 that extend through vias 222 and are electrically coupled to contact pads 178, 182. Metallized path 224 may include a layer of copper and can be formed using sputtering and plating techniques followed by a lithography process.

[0041] Following the formation of POL interconnect layer 166 or POL interconnect layer 208, support structure 174 and any shims 192 can be removed, if desired. Each resulting POL assembly 232, 234 can then be singulated or diced into individual POL structures each having one or more semiconductor devices. In the case where the resulting POL structure includes a plurality of semiconductor dies, the portions of dielectric layers 200, 210 within gap 206 can be removed, such as by laser ablation, or retained to provide additional structural rigidity to the POL structure. Wire bonds can be coupled to metal interconnects 228, 230 either before or after singulation in a manner similar to that described with respect to any of FIGS. 7 - 11.

[0042] Next, referring to FIG. 14, according to another embodiment of the present invention, within the POL assembly 238, the integrated POL structure 90 is shown electrically coupled to another POL structure 236. As shown, each POL structure 90, 236 includes a respective POL interconnect layer 88 to which wire bonds 96, 100, 240, 242 of each POL structure 90, 236 are coupled. Wire bonds 96, 240 electrically couple contact pad 46 of semiconductor device 38 to contact pad 244 of semiconductor device 246. FIG. 14 shows the POL structures 90, 236 as having different heights, although it is contemplated that the POL structures 90, 236 may have the same height.

[0043] In one embodiment, as shown in FIG. 14, the POL structures 90, 236 are thermally coupled to the same multilayer substrate 106. However, one of ordinary skill in the art will recognize that the POL structures 90, 236 can be thermally coupled to separate multilayer substrates 106. Additionally, in an alternative embodiment, the multilayer substrate 106 can be considered to be a DBC substrate or a DBA substrate.

[0044] Next, FIG. 15 shows an alternative embodiment of the POL assembly 238. Here, the integrated POL structures 90, 236 described with respect to FIG. 14 have been replaced by a redistribution wafer 232 having at least two semiconductor devices 170, 172. As shown, the POL interconnect layer 166 is formed across the upward-facing surfaces of both semiconductor devices 170, 172 and spans the gap between semiconductor devices 170, 172. FIG. 15 is depicted as if the semiconductor devices 170, 172 are thermally coupled to the same multilayer substrate 106, although it is contemplated that each semiconductor device 170, 172 can be coupled to a separate respective multilayer substrate 106.

[0045] Wire bonds 96, 100, 240, 242 are coupled to the POL interconnect layer 166. In this embodiment, the metal-coated path 224 electrically connects to the contact pads 176, 178, 180, 182 of the semiconductor devices 170, 172 of the POL assembly 238. As a result, the semiconductor devices 170, 172 can be electrically coupled to each other without a direct connection between the wire bonds 96, 240. Thus, the wire bonds 96, 240 can be used to electrically couple the POL assembly 238 to other POL assemblies.

[0046] Advantageously, embodiments of the present invention provide a POL structure that enables copper wire bonds regardless of the material of the contact pads of the semiconductor device. The POL interconnect layer provides a copper metal-coated path that is electrically connected to the contact pads of the semiconductor device and forms a contact surface to which a copper wire bond can be reliably adhered. Thereby, copper wire bonds can be used in POL modules including various types of power devices having different metal-coated layers such as, for example, copper and aluminum contact pads.

[0047] The resulting POL structure can also distribute current more efficiently from the semiconductor power device to the wire bond than prior art structures. The metal-coated interconnect structure provided within the POL interconnect layer provides a parallel path for current to flow from the thin metal coating of the contact pads of the power device before entering the wire bond.

[0048] Also, the thickness of the POL interconnect layer forms a protective buffer layer between the wire bond and the power device, protecting the power device from the higher energy associated with wire bonding copper to copper as compared to wire bonding aluminum to aluminum. The POL interconnect layer acts as a stress buffer for the power device during the wire bond process, so a thicker wire than that traditionally used for wire bonding copper to copper The bond can electrically couple to the power device without the risk of damaging the power device. These thick wire bonds further reduce the interconnect resistance between the power device and the wire bond and thus the associated losses.

[0049] Accordingly, according to one embodiment of the present invention, a power over - lay (POL) structure includes a power device having at least one upper contact pad disposed on its upper surface, a dielectric layer coupled to the upper surface of the power device, and a POL interconnect layer having a metal interconnect portion extending through vias formed through the dielectric layer and electrically coupled to at least one upper contact pad of the power device and having a metal - coated layer. The POL structure also includes at least one copper wire bond directly coupled to the metal - coated layer.

[0050] According to another aspect of the present invention, a method of manufacturing a POL structure includes providing a wafer including a plurality of semiconductor devices, coupling a dielectric layer to the upper surface of each of the plurality of semiconductor devices, forming a plurality of vias through the dielectric layer to expose at least one contact pad of the plurality of semiconductor devices, and forming a metal - coated layer on the upper surface of the dielectric layer, the metal - coated layer having a metal interconnect portion extending through the plurality of vias and electrically coupled to at least one contact pad of the plurality of semiconductor devices. The method further includes coupling at least one wire bond to the top surface of the metal - coated layer.

[0051] According to yet another aspect of the present invention, the POL assembly includes a first semiconductor device, a second semiconductor device, a polyimide film adhesively bonded to upper contact pads of the first and second semiconductor devices, and a metallized path formed on the polyimide film, the metallized path including a plurality of metal interconnects that extend through vias formed through the polyimide film and are electrically coupled to the upper contact pads of the first and second semiconductor devices. The POL assembly also includes a plurality of copper wire bonds directly coupled to the metallized path, wherein a first wire bond of the plurality of copper wire bonds is electrically coupled to an upper contact pad of the first semiconductor device and a second wire bond of the plurality of copper wire bonds is electrically coupled to an upper contact pad of the second semiconductor device.

[0052] Although the present invention has been described in detail with reference to only a limited number of embodiments, it should be readily understood that the invention is not limited to such disclosed embodiments. Rather, the invention can be modified to incorporate any number of variations, alterations, substitutions, and equivalent arrangements that have not been heretofore described, but which are commensurate with the spirit and scope of the invention. Further, although various embodiments of the invention have been described, it is to be understood that aspects of the invention may include only some of the described embodiments. Accordingly, the invention is not to be understood as being limited to the foregoing description, but is only limited by the scope of the appended claims.

Description of Reference Numerals

[0053] 10 Power package structure 12 Semiconductor device 14 Gate contact pad 16 Emitter contact pad 18 Upper surface of semiconductor device 20 Wire bond 22 Wire bond 24 Wire bond 26 Collector pad 28 Lower surface of semiconductor device 30 solder 32 substrate 34 POL structure 36 wafer 38 semiconductor device 40 semiconductor device 42 semiconductor device 44 upper contact pad 46 upper contact pad 48 upper contact pad 50 upper contact pad 52 upper contact pad 54 upper contact pad 56 top surface of semiconductor device 58 top surface of semiconductor device 60 top surface of semiconductor device 62 lower contact pad 64 lower contact pad 66 lower contact pad 68 bottom surface of semiconductor device 70 bottom surface of semiconductor device 72 bottom surface of semiconductor device 74 dielectric layer 76 adhesive layer 78 via 80 metal coating layer 82 top surface of dielectric layer 84 first part of metal interconnection 86 second part of metal interconnection 88 POL interconnection layer 90 POL structure 92 POL structure 94 POL structure 96 wire bond 98 wire bond 100 wire bond 102 surface contact area 104 surface contact area 106 multilayer substrate 108 solder 110 non-organic ceramic substrate 112 upper sheet 114 lower sheet 116 Thickness of the semiconductor device 118 Thickness of the metal coating path 120 Thickness of the dielectric layer 122 Portion of the POL interconnect layer 124 Portion of the POL interconnect layer 126 Portion of the POL interconnect layer 128 Contact surface of the wire bond 130 Contact surface of the wire bond 132 Contact surface of the wire bond 134 POL structure 136 Hole 138 Via 140 Surface area of a portion of the contact pad 142 Surface area of the wire bond 144 Metal interconnect 146 Upper contact surface 148 Surface area of the upper contact surface 150 Contact surface of the wire bond 152 Top surface of the metal coating path 154 Portion of the POL structure 156 POL structure 158 Portion of the dielectric layer 160 Portion of the dielectric layer 162 Contact position of the wire bond 164 Contact position of the wire bond 166 POL interconnect layer 168 Wafer 170 Semiconductor device 172 Semiconductor device 174 Support structure 176 Upper contact pad 178 Upper contact pad 180 Upper contact pad 182 Upper contact pad 184 Lower contact pad 186 Lower contact pad 188 Thickness of the semiconductor device 190 Thickness of the semiconductor device 192 Shim Upper surface of contact pad of semiconductor device 194 Upper surface of contact pad of semiconductor device 196 200 Dielectric layer 202 Adhesive layer 204 Adhesive layer 206 Gap 208 POL interconnect layer 210 Dielectric layer 212 First portion of dielectric layer 214 First thickness of first portion of dielectric layer 216 Second portion of dielectric layer 218 Second thickness of second portion of dielectric layer 220 Step 222 Via 224 Metallic coated path 226 Upper surface of dielectric layer 228 Metallic interconnect 230 Metallic interconnect 232 POL assembly, wafer 234 POL assembly 236 POL structure 238 POL assembly 240 Wire bond 242 Wire bond 244 Contact pad 246 Semiconductor device

Claims

1. A dielectric layer, A metal-coated path formed on the upper surface of the dielectric layer and having a first portion extending into a well formed in the dielectric layer, A semiconductor device coupled to the lower surface of the dielectric layer such that a first contact pad of the semiconductor device is disposed under the well, A first wire bond disposed in the well and electrically coupled to the first contact pad, A second wire bond coupled to a second portion of the metal-coated path and a second contact pad of the semiconductor device, A package structure comprising: The lower surface of the second wire bond is disposed above the upper surface of the dielectric layer, The lower surface of the first wire bond is disposed below the upper surface of the dielectric layer. A package structure.

2. The package structure according to claim 1, wherein the lower surface of the first wire bond is disposed below the upper surface of the dielectric layer.

3. The package structure according to claim 2, wherein the entire lower surface of the first wire bond is disposed within the well.

4. The package structure according to claim 1, wherein the first wire bond is made of a wire gauge heavier than that of the second wire bond.

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