Switching Element and Method for Manufacturing the Same

Abstract

To suppress a compressive stress applied to a channel in a gallium nitride switching element.SOLUTION: A switching element is provided, having a semiconductor substrate (12) constituted by a gallium nitride switching element. The semiconductor substrate includes: an n-type source region (20); a p-type body region (22); and an n-type drain region (24) in a range including an upper surface (12a) of the semiconductor substrate. A gate insulation film (42) covers the upper surface in each range (22as and 22bs) in the body region. A stress film (44) having a compressive stress is disposed in an upper portion of the upper surface within the range of the body region, the upper portion being the upper portion of the gate insulation film. The gate electrode (46) is arranged on the upper portion of the stress film that is the upper portion of the upper surface within the range of the body region.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The technology disclosed in this specification relates to a switching element and a method for manufacturing the same.

[0002] Patent Document 1 discloses an n-channel type switching element. This switching element has a gate insulating film and a gate electrode provided so as to cover the upper surface of a semiconductor substrate. When a potential equal to or higher than the gate threshold is applied to the gate electrode, a channel is formed along the upper surface of the semiconductor substrate in the p-type body region, and the switching element is turned on.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Compressive stress that compresses the upper surface of the semiconductor substrate is generated during the manufacturing process of the switching element, and the compressive stress may remain in the switching element. In a switching element of the type in which a channel is formed along the upper surface of the semiconductor substrate as in Patent Document 1, when compressive stress that compresses the upper surface is applied to the semiconductor substrate, compressive stress is applied to the region where the channel is formed in the body region.

[0005] Also, a switching element having a semiconductor substrate composed of a gallium nitride-based semiconductor (hereinafter sometimes referred to as a gallium nitride-based switching element) is known. Also in the gallium nitride-based switching element, a structure in which a channel is formed along the upper surface of the semiconductor substrate can be adopted as in Patent Document 1. Therefore, also in the gallium nitride-based switching element, compressive stress may be applied to the region where the channel is formed within the body region. In the gallium nitride-based switching element, it has been experimentally found that when compressive stress is applied to the region where the channel is formed, problems such as a decrease in the gate threshold and an increase in the leakage current occur. Therefore, in this specification, a technique for suppressing the compressive stress applied to the channel in the gallium nitride-based switching element is proposed.

Means for Solving the Problems

[0006] The first switching element disclosed in this specification includes a semiconductor substrate (12) composed of a gallium nitride-based semiconductor, a gate insulating film (42), a gate electrode (46), and a stress film (44) having compressive stress. The semiconductor substrate has an n-type source region (20), a p-type body region (22), and an n-type drain region (24). The source region is provided in a range including the upper surface (12a) of the semiconductor substrate. The body region is provided in a range including the upper surface and is in contact with the source region. The drain region is provided in a range including the upper surface, is in contact with the body region, and is separated from the source region by the body region. The gate insulating film covers the upper surface within the range (22as, 22bs) of the body region. The stress film is disposed above the upper surface within the range of the body region and above the gate insulating film. The gate electrode is disposed above the upper surface within the range of the body region and above the stress film.

[0007] In this switching element, a stress film is provided between the gate insulating film and the gate electrode. Since the stress film has a compressive stress, the stress film exerts a force in a direction to expand the surrounding members. That is, a tensile stress acts on the surrounding members from the stress film. For this reason, the stress film exerts a tensile stress on the body region (i.e., the region where the channel is formed) in contact with the gate insulating film below the stress film. As a result, the compressive stress applied to the region where the channel is formed is relaxed. Therefore, according to the structure of this switching element, a decrease in the gate threshold and an increase in the leakage current can be suppressed.

[0008] Also, this specification discloses a first manufacturing method for manufacturing a switching element from a semiconductor substrate (12X) composed of a gallium nitride-based semiconductor. The semiconductor substrate has an n-type source region, a p-type body region, and an n-type drain region. The source region is provided in a range including the upper surface of the semiconductor substrate. The body region is provided in a range including the upper surface and is in contact with the source region. The drain region is provided in a range including the upper surface, is in contact with the body region, and is separated from the source region by the body region. The first manufacturing method includes a step of forming a gate insulating film covering the upper surface within the range of the body region, a step of forming a stress film having a compressive stress on the upper part of the upper surface within the range of the body region and above the gate insulating film, and a step of forming a gate electrode on the upper part of the upper surface within the range of the body region and above the stress film.

[0009] According to this manufacturing method, a decrease in the gate threshold and an increase in the leakage current can be suppressed.

[0010] The second switching element disclosed in this specification includes a semiconductor substrate (12) composed of a gallium nitride-based semiconductor, a gate insulating film (402), a gate electrode (406), and a stress film (444) having compressive stress. The semiconductor substrate has an n-type source region (20), a p-type body region (22), and an n-type drain region (24). The source region is provided in a range including the upper surface of the semiconductor substrate. The body region is provided in a range including the upper surface and is in contact with the source region. The drain region is provided in a range including the upper surface, is in contact with the body region, and is separated from the source region by the body region. The gate insulating film covers the upper surface within the range of the body region (22as, 22bs). The gate electrode is disposed above the upper surface within the range of the body region and above the gate insulating film. The stress film is disposed above the upper surface within the range of the body region and above the gate electrode. The stress film does not contact the side surface of the gate electrode.

[0011] In this switching element, a stress film is provided above the gate electrode. Since the stress film has compressive stress, the stress film exerts a force in a direction to expand the surrounding members. That is, a tensile stress acts on the surrounding members from the stress film. Therefore, the stress film exerts a tensile stress on the body region (i.e., the region where the channel is formed) in contact with the gate insulating film below the stress film. As a result, the compressive stress applied to the region where the channel is formed is relaxed. Therefore, according to the structure of this switching element, a decrease in the gate threshold and an increase in the leakage current can be suppressed. Also, in this switching element, the stress film does not contact the side surface of the gate electrode. Therefore, a small-sized switching element can be realized.

[0012] The present specification also discloses a second manufacturing method for manufacturing a switching element from a semiconductor substrate (12X) composed of a gallium nitride-based semiconductor. The semiconductor substrate has an n-type source region, a p-type body region, and an n-type drain region. The source region is provided in a range including the upper surface of the semiconductor substrate. The body region is provided in a range including the upper surface and is in contact with the source region. The drain region is provided in a range including the upper surface, is in contact with the body region, and is separated from the source region by the body region. The manufacturing method includes a step of forming a gate insulating film covering the upper surface within the range of the body region, a step of forming a gate electrode above the upper surface within the range of the body region and above the gate insulating film, and a step of forming a stress film having compressive stress and not in contact with the side surface of the gate electrode above the upper surface within the range of the body region and above the gate electrode.

[0013] According to this manufacturing method, a decrease in the gate threshold and an increase in the leakage current can be suppressed.

Brief Description of the Drawings

[0014]

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Mode for Carrying Out the Invention

[0015] In the above-described first switching element, the body region may have a first body region (22a) and a second body region (22b) separated from the first body region. The source region may have a first source region (20a) in contact with the first body region and a second source region (20b) in contact with the second body region. The drain region may have a window portion (24b) provided in a range including the upper surface located between the first body region and the second body region. The gate insulating film may cover the upper surface within a range (22as, 24bs, 22bs) straddling the first body region, the window portion, and the second body region. The stress film may have a first stress film (44a) disposed above the upper surface within the range of the first body region and a second stress film (44b) disposed above the upper surface within the range of the second body region and separated from the first stress film. At least a part of the interval (44c) between the first stress film and the second stress film may be disposed above the window portion.

[0016] According to this configuration, it becomes difficult for tensile stress to act on the window portion from the stress film. As a result, the resistance of the window portion can be lowered, and the on-resistance of the switching element can be reduced.

[0017] The above-described first manufacturing method may further include a step of dividing an element region (12U) in which the source region, the body region, and the drain region are formed in the semiconductor substrate from a region (12L) below the element region in the semiconductor substrate.

[0018] When the semiconductor substrate is divided in this way, compressive stress is likely to be applied to the region where the channel is formed. However, the tensile stress acting from the stress film can reduce the compressive stress applied to the region where the channel is formed.

[0019] In the second switching element described above, the body region may have a first body region (22a) and a second body region (22b) separated from the first body region. The source region may have a first source region (20a) in contact with the first body region and a second source region (20b) in contact with the second body region. The drain region may have a window portion (24b) provided in a range including the upper surface located between the first body region and the second body region. The gate insulating film may cover the upper surface within a range (22as, 24bs, 22bs) spanning the first body region, the window portion, and the second body region. The stress film may have a first stress film (444a) disposed above the upper surface within the range of the first body region and a second stress film (444b) disposed above the upper surface within the range of the second body region and separated from the first stress film. At least a part of the interval (444c) between the first stress film and the second stress film may be disposed above the window portion.

[0020] According to this configuration, it becomes difficult for tensile stress to act on the window portion from the stress film. As a result, the resistance of the window portion can be lowered, and the on-resistance of the switching element can be reduced.

[0021] The second manufacturing method described above may further include a step of dividing an element region (12U) in which the source region, the body region, and the drain region are formed in the semiconductor substrate from a region (12L) below the element region in the semiconductor substrate.

[0022] When the semiconductor substrate is divided in this way, compressive stress is likely to be applied to the region where the channel is formed. However, the tensile stress acting from the stress film can reduce the compressive stress applied to the region where the channel is formed.

Example

[0023] The switching element 10 of Example 1 shown in FIG. 1 has a semiconductor substrate 12, a plurality of gate structure portions 40, a source electrode 50, and a drain electrode 52. The semiconductor substrate 12 is made of a gallium nitride-based semiconductor. Note that the gallium nitride-based semiconductor is a semiconductor mainly composed of gallium nitride. The gallium nitride semiconductor includes, for example, GaN, AlGaN, InGaN, AlInGaN, etc. The plurality of gate structure portions 40 are provided on the upper surface 12a of the semiconductor substrate 12. The plurality of gate structure portions 40 are provided at intervals in the x direction on the upper surface of the semiconductor substrate 12. Each gate structure portion 40 extends long in the y direction (that is, the direction orthogonal to the x direction) on the upper surface of the semiconductor substrate 12. The interval between each gate structure portion 40 functions as a contact hole 49. The source electrode 50 is made of metal. The source electrode 50 covers each gate structure portion 40. The source electrode 50 extends into each contact hole 49. The source electrode 50 is in contact with the upper surface 12a of the semiconductor substrate 12 within each contact hole 49. The drain electrode 52 is provided on the lower surface 12b of the semiconductor substrate 12. The drain electrode 52 is in contact with substantially the entire lower surface 12b of the semiconductor substrate 12.

[0024] The semiconductor substrate 12 has a plurality of source regions 20, a plurality of body regions 22, and a drain region 24.

[0025] Each source region 20 is an n-type region. Each source region 20 is provided in a range including the upper surface 12a of the semiconductor substrate 12. Each source region 20 is arranged at intervals in the x direction. Each source region 20 extends long in the y direction. Each source region 20 is provided at the lower part and its periphery of the corresponding contact hole 49. Each source region 20 is in contact with the source electrode 50 in the corresponding contact hole 49.

[0026] Each body region 22 is a p-type region. Each body region 22 is provided around the corresponding source region 20. Each body region 22 extends long in the y direction along the corresponding source region 20. The body regions 22 are arranged at intervals in the x direction. Each body region 22 covers the lower surface and the side surface of the corresponding source region 20. Each body region 22 is exposed on the upper surface 12a of the semiconductor substrate 12 on the side of the corresponding source region 20. That is, each body region 22 is provided in a range including the upper surface 12a of the semiconductor substrate 12.

[0027] The drain region 24 is an n-type region. The drain region 24 has a main portion 24a and a plurality of window portions 24b. The main portion 24a is disposed below each drain region 24. The main portion 24a is in contact with the lower surface of each drain region 24. Each window portion 24b is a portion disposed within the interval between the body regions 22 (that is, the interval in the x direction). Each window portion 24b may be called a JFET portion. Each window portion 24b protrudes upward from the main portion 24a. Each window portion 24b is in contact with the side surfaces of the two body regions 22 located on both sides thereof. Each window portion 24b is exposed on the upper surface 12a of the semiconductor substrate 12 between the two body regions 22. That is, the window portion 24b is provided in a range including the upper surface 12a located between the two body regions 22. Each body region 22 is separated from each other by the drain region 24. Also, each source region 20 is separated from the drain region 24 by the corresponding body region 22.

[0028] As shown in FIG. 1, each gate structure portion 40 is provided so as to straddle the surfaces of two source regions. FIG. 2 shows an enlarged view of one gate structure portion 40. As shown in FIG. 2, the gate structure portion 40 is disposed between two contact holes 49a and 49b. Hereinafter, the source region 20 and the body region 22 below the contact hole 49a are referred to as a first source region 20a and a first body region 22a. Also, hereinafter, the source region 20 and the body region 22 below the contact hole 49b are referred to as a second source region 20b and a second body region 22b. Further, hereinafter, among the upper surface 12a, the range included in the first source region 20a is referred to as range 20as, the range included in the first body region 22a is referred to as range 22as, the range included in the window portion 24b is referred to as range 24bs, the range included in the second body region 22b is referred to as range 22bs, and the range included in the second source region 20b is referred to as range 20bs.

[0029] As shown in FIG. 1, each gate structure portion 40 has a gate insulating film 42, a stress film 44, a gate electrode 46, and an interlayer insulating film 48.

[0030] As shown in FIG. 1, each gate insulating film 42 is arranged at intervals in the x direction on the upper surface 12a of the semiconductor substrate 12. Each gate insulating film 42 extends long in the y direction on the upper surface 12a of the semiconductor substrate 12. Each gate insulating film 42 is made of an insulator such as silicon oxide. As shown in FIG. 2, the gate insulating film 42 extends from the surface of the first source region 20a to the surface of the second source region 20b among the upper surface 12a. In other words, the gate insulating film 42 covers the upper surface 12a in a range straddling the range 20as, the range 22as, the range 24bs, the range 22bs, and the range 20bs.

[0031] As shown in FIG. 1, each stress film 44 is provided on the corresponding gate insulating film 42. Each stress film 44 is composed of an insulator such as silicon nitride. Each stress film 44 covers substantially the entire upper surface of the corresponding gate insulating film 42. Therefore, as shown in FIG. 2, the stress film 44 covers the upper surface of the gate insulating film 42 above the ranges 20as, 22as, 24bs, 22bs, and 20bs. The stress film 44 has a compressive stress. For this reason, a tensile stress acts on the surrounding insulating layer, conductor layer, and semiconductor layer from the stress film 44.

[0032] As shown in FIG. 1, each gate electrode 46 is provided on the corresponding stress film 44. Each gate electrode 46 is composed of a conductor such as polysilicon. Each gate electrode 46 covers the portion of the upper surface of the corresponding stress film 44 excluding the edge. As shown in FIG. 2, the gate electrode 46 covers the upper surface of the stress film 44 above the ranges 20as, 22as, 24bs, 22bs, and 20bs.

[0033] As shown in FIG. 1, each interlayer insulating film 48 is provided on the corresponding gate electrode 46. Each interlayer insulating film 48 covers the upper surface and the side surface of the corresponding gate electrode 46. Each interlayer insulating film 48 is composed of an insulator such as silicon oxide. Contact holes 49 are formed by the intervals between the interlayer insulating films 48. The upper surface of each interlayer insulating film 48 is covered by the source electrode 50. Also, the side surface of each interlayer insulating film 48 is covered by the source electrode 50 in the contact hole 49.

[0034] Next, the operation of the switching element 10 will be described. The switching element 10 is a so-called MOSFET (metal-oxide-semiconductor field effect transistor). A potential higher than that of the source electrode 50 is applied to the drain electrode 52. When a potential higher than the gate threshold is applied to the gate electrode 46, as shown in FIG. 3, electrons are attracted to the range near the gate insulating film 42 in the body region 22, thereby forming a channel 23. Then, as shown by the arrow 100 in FIG. 3, electrons flow from the source electrode 50 into the window portion 24b through the source region 20 and the channel 23. The electrons that have flowed into the window portion 24b flow downward in the drain region 24 to the drain electrode 52. When electrons flow in this way, the switching element 10 is turned on. Note that when the switching element 10 is on, electrons are attracted to the range near the gate insulating film 42 in the window portion 24b. As a result, a high electron concentration layer 25 with a high electron concentration is formed in the range near the gate insulating film 42 in the window portion 24b. The electrical resistance of the high electron concentration layer 25 is lower than the electrical resistance of the drain region 24 outside the high electron concentration layer 25. In this way, when the high electron concentration layer 25 is formed in the window portion 24b when the switching element 10 is on, the resistance of the current path (i.e., the path through which electrons flow) in the window portion 24b decreases. Therefore, the on-resistance of the switching element 10 becomes lower. When the potential of the gate electrode is lowered to a potential equal to or lower than the gate threshold, the channel 23 disappears and the flow of electrons stops. That is, the switching element 10 is turned off.

[0035] Next, a method for manufacturing the switching element 10 will be described. The switching element 10 is manufactured from the semiconductor substrate 12X before processing shown in FIG. 4. The semiconductor substrate 12X before processing is entirely composed of an n-type region having substantially the same n-type impurity concentration as the drain region 24. Also, the thickness of the semiconductor substrate 12X before processing is thicker than the thickness of the semiconductor substrate 12 after processing shown in FIG. 1.

[0036] First, as shown in FIG. 5, by performing ion implantation, epitaxial growth, etc. on the semiconductor substrate 12X, a source region 20 and a body region 22 are formed in the semiconductor substrate 12X. Next, as shown in FIG. 6, a gate insulating film 42 is formed on the upper surface 12a of the semiconductor substrate 12X. Further, as shown in FIG. 7, a stress film 44 is formed on the gate insulating film 42. Here, the stress generated inside the silicon nitride (i.e., the stress film 44) varies depending on the film formation conditions of the silicon nitride. FIG. 8 shows the relationship between the atmospheric pressure when growing silicon nitride by vapor phase growth and the internal stress generated in the formed silicon nitride film. As shown in FIG. 8, when the atmospheric pressure during film formation is high, tensile stress is generated in the silicon nitride film, and when the atmospheric pressure during film formation is low, compressive stress is generated in the silicon nitride film. In the formation process of the stress film 44, by adjusting the atmospheric pressure during film formation, a stress film 44 having compressive stress as the internal stress is formed. When the formation of the stress film 44 is completed, since the stress film 44 has compressive stress, the stress film 44 tends to expand. Therefore, tensile stress acts on the gate insulating film 42 below the stress film 44 and the portion near the upper surface 12a of the semiconductor substrate 12X.

[0037] Next, as shown in FIG. 9, by partially etching the gate insulating film 42 and the stress film 44, contact holes 49 are formed on each source region 20. Here, as shown in FIG. 2, the gate insulating film 42 and the stress film 44 are left on the upper part of the range spanning the range 20as, the range 22as, the range 24bs, the range 22bs, and the range 20bs. Therefore, even after the formation of the contact holes 49, tensile stress acts on the semiconductor layer near the upper surface 12a within the range 20as, the range 22as, the range 24bs, the range 22bs, and the range 20bs from the stress film 44. Note that the gate insulating film 42 and the stress film 44 can be etched using a common mask.

[0038] Once the contact hole 49 is formed, as shown in FIG. 10, a gate electrode 46 is formed on the stress film 44. Here, as shown in FIG. 2, the gate electrode 46 is patterned such that the gate electrode 46 remains in the upper portion of the range spanning the ranges 20as, 22as, 24bs, 22bs, and 20bs. Next, as shown in FIG. 11, an interlayer insulating film 48 is formed to cover the gate electrode 46, and a contact hole is formed again in the interlayer insulating film 48. In other embodiments, after forming the gate insulating film 42 and the stress film 44, patterning the gate electrode 46, and further forming the interlayer insulating film 48, the gate insulating film 42, the stress film 44, and the interlayer insulating film 48 may be etched together to form a contact hole. Thereafter, a source electrode 50 is formed to cover the interlayer insulating film 48. The source electrode 50 is connected to the source region 20 within the contact hole 49.

[0039] Next, as shown in FIG. 12, the semiconductor substrate 12X is irradiated with a laser 90 so that a focus is formed within the drain region 24 below each body region 22. When the semiconductor substrate 12X is irradiated with the laser 90 in this way, crystal defects are formed at the position of the focus of the laser 90. Here, by moving the focus of the laser 90 parallel to the upper surface 12a of the semiconductor substrate 12X, a crystal defect region 92 extending along the upper surface 12a is formed within the drain region 24. In the crystal defect region 92, the strength of the semiconductor substrate 12X decreases.

[0040] Next, as shown in FIG. 13, the semiconductor substrate 12X is divided into an upper portion 12U and a lower portion 12L along the crystal defect region 92. The upper portion 12U is an element region having an element structure including the source region 20, the body region 22, and the drain region 24. The upper portion 12U becomes the semiconductor substrate 12 shown in FIG. 1. By dividing the semiconductor substrate 12X in this way, a semiconductor substrate 12 with a reduced thickness can be obtained. The lower portion 12L can then be reused in the manufacturing process of the switching element. Thereafter, a drain electrode 52 is formed on the lower surface 12b of the semiconductor substrate 12 (i.e., the upper portion 12U), completing the switching element 10 shown in FIG. 1.

[0041] As described above, in the manufacturing method of Example 1, the semiconductor substrate 12 is obtained by dividing the semiconductor substrate 12X as shown in FIG. 13. When the semiconductor substrate 12X is divided, minute irregularities are formed on the lower surface 12b of the semiconductor substrate 12, which is the interface at the time of division. When such minute irregularities are formed on the lower surface 12b, the semiconductor substrate 12 warps so that the upper surface 12a becomes concave due to the Twyman effect. As a result, compressive stress is applied to the semiconductor layer near the upper surface 12a. That is, compressive stress is applied to the portion near the upper surface 12a of the source region 20, the portion near the upper surface 12a of the body region 22, and the portion near the upper surface 12a of the window portion 24b. In a gallium nitride-based semiconductor, when compressive stress is applied to the semiconductor layer, the characteristics of the semiconductor layer shift to the n-type side. For example, when compressive stress is applied to a p-type semiconductor layer, the effective p-type carrier concentration of the p-type semiconductor layer decreases. Also, when compressive stress is applied to an n-type semiconductor layer, the effective n-type carrier concentration of the n-type semiconductor layer increases. Therefore, when compressive stress is applied to the semiconductor layer near the upper surface 12a, the effective n-type carrier concentration increases in the portion near the upper surface 12a of the n-type source region 20, the effective p-type carrier concentration decreases in the portion near the upper surface 12a of the p-type body region 22, and the effective n-type carrier concentration increases in the portion near the upper surface 12a of the n-type window portion 24b. When the effective p-type carrier concentration decreases in the portion near the upper surface 12a of the p-type body region 22 (i.e., the portion where the channel 23 is formed), problems such as a decrease in the gate threshold of the switching element 10 and an increase in the drain-source leakage current occur. However, in the manufacturing method of Example 1, a stress film 44 is provided above the range of the body region 22 in the upper surface 12a (i.e., the ranges 22as and 22bs in FIG. 2). As described above, tensile stress acts from the stress film 44 on the semiconductor layer below it. Therefore, the compressive stress acting on the ranges 22as and 22bs (i.e., the compressive stress generated by the warping of the semiconductor substrate 12) is relaxed by the tensile stress acting on the ranges 22as and 22bs from the stress film 44. That is, the compressive stress acting on the portion where the channel 23 is formed in the body region 22 is relaxed. Furthermore, by providing the stress film 44, the portion where the channel 23 is formed can have tensile stress, and the characteristics of the channel 23 can also be controlled.Further, the stress film 44 composed of silicon nitride has higher mechanical strength than silicon oxide. Since the stress film 44 with high mechanical strength is disposed between the gate electrode 46 and the gate insulating film 42, deformation of the semiconductor substrate 12 is suppressed. Also by this, the compressive stress acting on the portion where the channel 23 in the body region 22 is formed is relaxed. Therefore, according to this manufacturing method, a switching element 10 with a high gate threshold value and low drain-source leakage current can be manufactured.

Embodiment

[0042] Next, the switching element of Example 2 and its manufacturing method will be described. The switching element of Example 2 shown in FIG. 14 has a first stress film 44a and a second stress film 44b as the stress film 44. The first stress film 44a is disposed above the range 22as. The second stress film 44b is disposed above the range 22bs. The first stress film 44a is separated from the second stress film 44b. The interval portion 44c between the first stress film 44a and the second stress film 44b is disposed above the window portion 24b (that is, above the range 24bs). Other configurations of the switching element of Example 2 are the same as those of the switching element 10 of Example 1.

[0043] The manufacturing method of the switching element of Example 2 is the same as that of the switching element 10 of Example 1, except that the stress film 44 is separated and formed into a first stress film 44a and a second stress film 44b. In the switching element of Example 2, since the stress films 44a and 44b are provided above the ranges 22as and 22bs, the compressive stress applied to the portion near the upper surface 12a of the body regions 22a and 22b (i.e., the portion where the channel 23 is formed) can be relaxed in the same manner as in Example 1. Therefore, a switching element with a high gate threshold and low drain-source leakage current can be realized. Also, in the switching element of Example 2, a spacer portion 44c is provided above the window portion 24b. Therefore, the tensile stress applied from the stress film 44 to the window portion 24b is small. Therefore, the compressive stress caused by the warping of the semiconductor substrate 12 is likely to be applied to the portion near the upper surface 12a of the window portion 24b. When compressive stress is applied to the portion near the upper surface 12a of the window portion 24b, the effective n-type impurity concentration of the portion increases. Therefore, when the switching element 10 is turned on, the n-type impurity concentration of the high electron concentration layer 25 shown in FIG. 3 is likely to increase, and the electrical resistance of the high electron concentration layer 25 is likely to decrease. Therefore, the on-resistance when the switching element is turned on becomes lower. According to Example 2, a switching element with a lower on-resistance can be obtained.

[0044] Also, according to the configuration of Example 2, since the width of the stress film 44 becomes narrower than that of Example 1, the stress film 44 becomes more difficult to deform. Therefore, the semiconductor substrate 12 becomes more difficult to deform below the stress film 44. For this reason, according to Example 2, the compressive stress acting on the portion where the channel 23 is formed can be more effectively relaxed.

[0045] Note that in Example 2, the width of the spacer portion 44c substantially matched the width of the range 24bs. However, as shown in FIG. 15, the width of the spacer portion 44c may be narrower than the width of the range 24bs, or as shown in FIG. 16, the width of the spacer portion 44c may be wider than the width of the range 24bs.

[0046] In the above-described Examples 1 and 2, the stress film 44 was in contact with the gate insulating film 42. However, another film (for example, an insulating film) may be interposed between the stress film 44 and the gate insulating film 42. Also, in the above-described Examples 1 and 2, the stress film 44 was in contact with the gate electrode 46. However, another film (for example, an insulating film or a conductive film) may be interposed between the stress film 44 and the gate electrode 46.

Example

[0047] The switching element 300 of Example 3 shown in FIG. 17 has a semiconductor substrate 12, a plurality of gate structure portions 400, a source electrode 50, and a drain electrode 52. The structure of the gate structure portion 400 of the switching element 300 of Example 3 is different from the structure of the gate structure portion 40 of the switching element 10 of Example 1. Except for the gate structure portion, the switching element 300 of Example 3 has the same structure as the switching element 10 of Example 1.

[0048] As shown in FIG. 17, the plurality of gate structure portions 400 are provided on the upper surface 12a of the semiconductor substrate 12. FIG. 18 shows an enlarged view of one gate structure portion 400. As shown in FIGS. 17 and 18, the gate structure portion 400 has a gate insulating film 402, a gate electrode 406, a stress film 444, and an interlayer insulating film 408. As shown in FIG. 17, the plurality of gate structure portions 400 are provided at intervals in the x direction on the upper surface of the semiconductor substrate 12. Each gate structure portion 400 extends long in the y direction on the upper surface of the semiconductor substrate 12. The interval between each gate structure portion 400 functions as a contact hole 49.

[0049] As shown in FIG. 17, each gate insulating film 402 is arranged on the upper surface 12a of the semiconductor substrate 12 with a spacing in the x direction. Each gate insulating film 402 extends long in the y direction on the upper surface 12a of the semiconductor substrate 12. Each gate insulating film 402 is composed of an insulator such as silicon oxide. As shown in FIG. 18, the gate insulating film 402 extends from the surface of the first source region 20a to the surface of the second source region 20b on the upper surface 12a. In other words, the gate insulating film 402 covers the upper surface 12a in a range straddling the ranges 20as, 22as, 24bs, 22bs, and 20bs.

[0050] As shown in FIG. 17, each gate electrode 406 is provided on the corresponding gate insulating film 402. Each gate electrode 406 is composed of a conductor such as polysilicon. Each gate electrode 406 covers a portion of the upper surface of the corresponding gate insulating film 402 excluding the edge portion. As shown in FIG. 18, the gate electrode 406 covers the upper surface of the gate insulating film 402 above the ranges 20as, 22as, 24bs, 22bs, and 20bs.

[0051] As shown in FIG. 17, each stress film 444 is provided on the corresponding gate electrode 406. Each stress film 444 is composed of an insulator such as silicon nitride. Each stress film 444 covers substantially the entire upper surface of the corresponding gate electrode 406. Therefore, as shown in FIG. 18, the stress film 444 covers the upper surface of the gate electrode 406 above the ranges 20as, 22as, 24bs, 22bs, and 20bs. The stress film 444 is not in contact with the side surface of the gate electrode 406. The stress film 444 has a compressive stress. For this reason, a tensile stress acts on the surrounding insulating layer, conductor layer, and semiconductor layer from the stress film 444.

[0052] As shown in FIG. 17, each interlayer insulating film 408 is provided on a corresponding stress film 444. Each interlayer insulating film 408 covers the upper surface of the corresponding stress film 444. Also, each interlayer insulating film 408 covers the side surfaces of the corresponding stress film 444 and the gate electrode 406. Each interlayer insulating film 408 is composed of an insulator such as silicon oxide.

[0053] Next, the operation of the switching element 300 will be described. A potential higher than that of the source electrode 50 is applied to the drain electrode 52. When a potential higher than the gate threshold is applied to the gate electrode 406, as shown in FIG. 19, a channel 423 is formed in a range near the gate insulating film 402 in the body region 22. Also, a high electron concentration layer 425 is formed in a range near the gate insulating film 402 in the window portion 24b. Then, as indicated by the arrow 500 in FIG. 19, electrons flow from the source electrode 50 through the source region 20, the channel 423, and the drain region 24 to the drain electrode 52. When electrons flow in this way, the switching element 10 turns on. When the potential of the gate electrode is lowered to a potential below the gate threshold, the channel 423 disappears and the flow of electrons stops. That is, the switching element 10 turns off.

[0054] Next, a method for manufacturing the switching element 300 of Example 3 will be described. In the manufacturing method of Example 3, processing is performed in the same manner as in the manufacturing method of Example 1 up to the state shown in FIG. 6. Next, as shown in FIG. 20, a gate electrode 406 is formed on the gate insulating film 402, a stress film 444 is formed on the gate electrode 406, and the stress film 444, the gate electrode 406, and the gate insulating film 402 are patterned. As a result, as shown in FIG. 18, the gate insulating film 402, the gate electrode 406, and the stress film 444 are formed on the upper part of the range spanning the ranges 20as, 22as, 24bs, 22bs, and 20bs. In the step of forming the stress film 444, a stress film 444 having compressive stress as internal stress is formed by adjusting the atmospheric pressure during film formation. When the formation of the stress film 444 is completed, since the stress film 444 has compressive stress, the stress film 444 tends to expand. Therefore, tensile stress acts on the gate electrode 406 below the stress film 444, the gate insulating film 402, and the portion near the upper surface 12a of the semiconductor substrate 12X. Also, in patterning the stress film 444, the stress film 444 is patterned so as not to contact the side surface of the gate electrode 406. In patterning the stress film 444 and the gate electrode 406, the stress film 444 and the gate electrode 406 can be etched using a common mask. Next, an interlayer insulating film 408 is formed so as to cover the stress film 444 and the gate electrode 406. Next, a source electrode 50 is formed so as to cover the interlayer insulating film 408.

[0055] Next, in the same manner as FIGS. 12 and 13 (that is, the substrate dividing step of Example 1), the semiconductor substrate 12 is divided into an upper part 12U and a lower part 12L. The upper part 12U becomes the semiconductor substrate 12 shown in FIG. 17. Thereafter, by forming a drain electrode 52 on the lower surface 12b of the semiconductor substrate 12 (that is, the upper part 12U), the switching element 300 shown in FIG. 17 is completed.

[0056] As described above, in the manufacturing method of Example 3, the semiconductor substrate 12 is obtained by dividing the semiconductor substrate 12X. When dividing the semiconductor substrate 12X, minute irregularities are formed on the lower surface 12b of the semiconductor substrate 12, which is the interface at the time of division. Therefore, due to the Twyman effect, the semiconductor substrate 12 warps so that the upper surface 12a becomes concave. As a result, compressive stress is applied to the semiconductor layer near the upper surface 12a. In the manufacturing method of Example 3, a stress film 444 is provided above the range of the body region 22 in the upper surface 12a (that is, the ranges 22as and 22bs in FIG. 18). As described above, tensile stress acts from the stress film 444 on the semiconductor layer below it. Therefore, the compressive stress acting on the ranges 22as and 22bs (that is, the compressive stress caused by the warping of the semiconductor substrate 12) is relaxed by the tensile stress acting on the ranges 22as and 22bs from the stress film 444. That is, the compressive stress acting on the portion where the channel 423 in the body region 22 is formed is relaxed. Further, the stress film 444 made of silicon nitride has higher mechanical strength than silicon oxide. Since the stress film 444 with high mechanical strength is disposed above the gate electrode 406, deformation of the semiconductor substrate 12 is suppressed. Also by this, the compressive stress acting on the portion where the channel 423 in the body region 22 is formed is relaxed. Therefore, according to this manufacturing method, a switching element 10 with a high gate threshold and low drain-source leakage current can be manufactured.

[0057] Also, according to Example 3, since the stress film 444 does not cover the side surface of the gate electrode 406, even if the stress film 444 is provided, the size of the switching element 300 in the x direction does not increase. Thus, according to this configuration, an increase in the size of the switching element 300 due to the provision of the stress film 444 can be suppressed.

Example

[0058] Next, the switching element of Example 4 and its manufacturing method will be described. The switching element of Example 4 shown in FIG. 21 has a stress film 444 having a first stress film 444a and a second stress film 444b. The first stress film 444a is disposed above the range 22as. The second stress film 444b is disposed above the range 22bs. The first stress film 444a is separated from the second stress film 444b. The gap portion 444c between the first stress film 444a and the second stress film 444b is disposed above the window portion 24b (i.e., above the range 24bs). Other configurations of the switching element of Example 4 are the same as those of the switching element 10 of Example 3.

[0059] The manufacturing method of the switching element of Example 4 is the same as the manufacturing method of the switching element 300 of Example 3, except that the stress film 444 is separated and formed into the first stress film 444a and the second stress film 444b. In the switching element of Example 4, since the stress films 444a and 444b are provided above the ranges 22as and 22bs, the compressive stress applied to the portions near the upper surface 12a of the body regions 22a and 22b (i.e., the portions where the channel 423 is formed) can be relaxed in the same manner as in Example 3. Therefore, a switching element with a high gate threshold and low drain-source leakage current can be realized. Further, in the switching element of Example 4, the gap portion 444c is provided above the window portion 24b. Therefore, the tensile stress applied from the stress film 444 to the window portion 24b is small. Therefore, the compressive stress caused by the warping of the semiconductor substrate 12 is likely to be applied to the portion near the upper surface 12a of the window portion 24b. Therefore, when the switching element 10 is turned on, the n-type impurity concentration of the high electron concentration layer 425 shown in FIG. 19 tends to be high, and the electrical resistance of the high electron concentration layer 425 tends to be low. Therefore, the on-resistance when the switching element is turned on becomes lower. According to Example 4, a switching element with a lower on-resistance can be obtained.

[0060] Also, according to the configuration of Example 4, since the width of the stress film 444 becomes narrower than that of Example 3, the stress film 444 becomes more difficult to deform. Therefore, the semiconductor substrate 12 becomes more difficult to deform below the stress film 444. For this reason, according to Example 4, the compressive stress acting on the portion where the channel 423 is formed can be more effectively relaxed.

[0061] In addition, in Example 4, the width of the spacing portion 444c substantially coincided with the width of the range 24bs. However, as shown in FIG. 22, the width of the spacing portion 444c may be narrower than the width of the range 24bs, or as shown in FIG. 23, the width of the spacing portion 444c may be wider than the width of the range 24bs.

[0062] Also, in the above-described Examples 3 and 4, the stress film 444 was in contact with the gate electrode 406. However, another film (for example, an insulating film or a conductive film) may be interposed between the stress film 444 and the gate electrode 406.

[0063] In addition, in the above-described Examples 1 to 4, when the semiconductor substrate 12X was divided into the upper portion 12U and the lower portion 12L, compressive stress was generated in the semiconductor layer where the channel was formed. However, compressive stress may be generated in the semiconductor layer where the channel is formed for other reasons. For example, by forming an electrode layer, an insulating layer, etc. on the upper surface 12a of the semiconductor substrate 12, compressive stress may be generated in the semiconductor layer where the channel is formed. Therefore, the technology disclosed in this specification (that is, the technology for relaxing the compressive stress in the semiconductor layer where the channel is formed by the stress film) may be used not only when compressive stress is generated by dividing the semiconductor substrate but also when compressive stress is generated for other reasons.

[0064] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes to the specific examples exemplified above. The technical elements described in this specification or the drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Also, the technology exemplified in this specification or the drawings achieves multiple objectives simultaneously, and achieving one of those objectives itself has technical utility.

Description of Reference Numerals

[0065] 10: Switching element, 12: Semiconductor substrate, 20: Source region, 2: Body region, 24: Drain region, 42: Gate insulating film, 44: Stress film, 46: Gate electrode

Claims

1. A switching element, comprising: a semiconductor substrate (12) made of a gallium nitride-based semiconductor; a gate insulating film (42); a gate electrode (46); a stress film (44) made of an insulator and having compressive stress; wherein the semiconductor substrate has an n-type source region (20) provided in a range including the upper surface (12a) of the semiconductor substrate; a p-type body region (22) provided in a range including the upper surface and in contact with the source region; an n-type drain region (24) provided in a range including the upper surface and in contact with the body region and separated from the source region by the body region; wherein the gate insulating film covers the upper surface within the range (22as, 22bs) of the body region; the stress film is disposed above the upper surface within the range of the body region and above the gate insulating film; the gate electrode is disposed above the upper surface within the range of the body region and above the stress film; a switching element.

2. The body region has a first body region (22a) and a second body region (22b) separated from the first body region, the source region has a first source region (20a) in contact with the first body region and a second source region (20b) in contact with the second body region, the drain region has a window portion (24b) provided in a range including the upper surface located between the first body region and the second body region, the gate insulating film covers the upper surface within a range (22as, 24bs, 22bs) spanning the first body region, the window portion, and the second body region, the stress film has a first stress film (44a) disposed above the upper surface within the range of the first body region and a second stress film (44b) disposed above the upper surface within the range of the second body region and separated from the first stress film, at least a part of the interval (44c) between the first stress film and the second stress film is disposed above the window portion; The switching element according to Claim 1.

3. A manufacturing method for manufacturing a switching element from a semiconductor substrate (12X) made of a gallium nitride-based semiconductor, comprising: wherein the semiconductor substrate has an n-type source region provided in a range including the upper surface of the semiconductor substrate; It is provided in a range including the upper surface, and includes a p-type body region in contact with the source region, an n-type drain region provided in a range including the upper surface, in contact with the body region, and separated from the source region by the body region, and has the manufacturing method comprising a step of forming a gate insulating film covering the upper surface within the range of the body region, a step of forming a stress film composed of an insulator and having compressive stress on the upper part of the upper surface within the range of the body region and above the gate insulating film, a step of forming a gate electrode on the upper part of the upper surface within the range of the body region and above the stress film, a manufacturing method. **Claim 4** The manufacturing method according to claim 3, further comprising a step of dividing an element region (12U) in which the source region, the body region, and the drain region are formed in the semiconductor substrate from a region (12L) below the element region in the semiconductor substrate. **Claim 5** A switching element, comprising a semiconductor substrate (12) composed of a gallium nitride-based semiconductor, a gate insulating film (402), a gate electrode (406), and a stress film (444) having compressive stress, and has the semiconductor substrate comprising an n-type source region (20) provided in a range including the upper surface of the semiconductor substrate, a p-type body region (22) provided in a range including the upper surface, in contact with the source region, and an n-type drain region (24) provided in a range including the upper surface, in contact with the body region, and separated from the source region by the body region, and has the body region having a first body region (22a) and a second body region (22b) separated from the first body region, the source region having a first source region (20a) in contact with the first body region and a second source region (20b) in contact with the second body region, the drain region having a window portion (24b) provided in a range including the upper surface located between the first body region and the second body region, the gate insulating film covering the upper surface within a range (22as, 24bs, 22bs) straddling the first body region, the window portion, and the second body region, and the gate electrode being disposed on the upper part of the upper surface within the range of the body region and above the gate insulating film. The stress film is disposed above the upper surface within the range of the body region and above the gate electrode. The stress film does not contact the side surface of the gate electrode. The stress film includes a first stress film (444a) disposed above the upper surface within the range of the first body region and a second stress film (444b) disposed above the upper surface within the range of the second body region and separated from the first stress film. At least a part of the gap (444c) between the first stress film and the second stress film is disposed above the window portion. A switching element.

6. A manufacturing method for manufacturing a switching element from a semiconductor substrate (12X) made of a gallium nitride-based semiconductor, wherein the semiconductor substrate has an n-type source region provided in a range including the upper surface of the semiconductor substrate, a p-type body region provided in a range including the upper surface and in contact with the source region, and an n-type drain region provided in a range including the upper surface and in contact with the body region and separated from the source region by the body region. The body region has a first body region (22a) and a second body region (22b) separated from the first body region. The source region has a first source region (20a) in contact with the first body region and a second source region (20b) in contact with the second body region. The drain region has a window portion (24b) provided in a range including the upper surface located between the first body region and the second body region. The manufacturing method includes a step of forming a gate insulating film covering the upper surface within a range spanning the first body region, the window portion, and the second body region (22as, 24bs, 22bs), a step of forming a gate electrode above the upper surface within the range of the body region and above the gate insulating film, and a step of forming a stress film having compressive stress and not in contact with the side surface of the gate electrode above the upper surface within the range of the body region and above the gate electrode. In the step of forming the stress film, the stress film is formed to have a first stress film (444a) disposed above the upper surface within the range of the first body region and a second stress film (444b) disposed above the upper surface within the range of the second body region and separated from the first stress film. ​ ​ In the step of forming the stress film, the stress film is formed such that at least a part of the distance (444c) between the first stress film and the second stress film is disposed above the window portion. Manufacturing method. **Claim 7** The manufacturing method according to claim 6, further comprising a step of dividing an element region (12U) in which the source region, the body region, and the drain region of the semiconductor substrate are formed from a region (12L) below the element region in the semiconductor substrate.

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