Semiconductor device

Abstract

To provide a semiconductor device capable of improving avalanche resistance.SOLUTION: A semiconductor device includes: a substrate having conductivity and a second thickness; a first chip which includes a first surface facing the substrate and a second surface positioned opposite to the first surface, and in which a first electrode electrically connected with the substrate is arranged on the first surface, and a second electrode is arranged on the second surface; a second chip which includes a third surface facing the second surface and a fourth surface positioned opposite to the third surface, and in which a third electrode is arranged on the third surface, and a fourth electrode is arranged on the fourth surface; a first connector arranged between the second electrode and the third electrode, and electrically connected with the second electrode and the third electrode; and a second connector which is electrically connected with the substrate and the fourth electrode, and includes a first part positioned above the second chip, and in which a difference between a first thickness of the first part and a second thickness is not larger than 20% of a larger one among the first thickness and the second thickness.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] Embodiments relate to semiconductor devices.

Background Art

[0002] In some cases, chips of power semiconductors such as MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) are connected in parallel so as to be able to output a large current while suppressing on-resistance.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] An object of embodiments is to provide a semiconductor device capable of improving avalanche tolerance.

Means for Solving the Problems

[0005] The semiconductor device according to the embodiment includes a substrate having conductivity and a second thickness, a first surface facing the substrate, and a second surface located on the opposite side of the first surface. A first electrode electrically connected to the substrate is disposed on the first surface, and a first chip having a second electrode disposed on the second surface. A third surface facing the second surface and a fourth surface located on the opposite side of the third surface are included. A second chip having a third electrode disposed on the third surface and a fourth electrode disposed on the fourth surface, a first connector disposed between the second electrode and the third electrode and electrically connected to the second electrode and the third electrode, and a second connector electrically connected to the substrate and the fourth electrode and including a first portion located above the second chip, wherein a difference between a first thickness of the first portion and the second thickness is 20% or less of the larger one of the first thickness and the second thickness.

Brief Description of Drawings

[0006]

Figure 1

Figure 2

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Figure 5

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Figure 7

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Figure 10

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Figure 13

Embodiments for Carrying Out the Invention

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual and are appropriately simplified. The relationship between the thickness and width of each part, the ratio of the sizes between parts, etc. are not necessarily the same as those in reality. Also, even when representing the same part, there are cases where their dimensions and ratios are represented differently in the drawings. In the present specification and each figure, the same reference numerals are given to elements that are the same as those already described, and detailed descriptions are appropriately omitted.

[0008] Also, hereinafter, in order to make the explanation easier to understand, an XYZ orthogonal coordinate system is used. Also, among the Z directions, the direction of the arrow is defined as the "upward direction", and the opposite direction is defined as the "downward direction", but these directions are relative and have nothing to do with the direction of gravity. Also, among the directions in which the X-axis extends, the direction of the arrow is also referred to as the "+X direction", and the opposite direction is also referred to as the "-X direction". Also, among the directions in which the Y-axis extends, the direction of the arrow is also referred to as the "+Y direction", and the opposite direction is also referred to as the "-Y direction".

[0009] <First Embodiment> First, the first embodiment will be described. FIG. 1 is a top view showing a semiconductor device according to this embodiment. FIG. 2 is a top view showing a substrate, a first lead, a second lead, and a first chip of the semiconductor device according to this embodiment. FIG. 3 is a top view showing a substrate, a first lead, a second lead, a first chip, a first connector, and a third connector of the semiconductor device according to the present embodiment. FIG. 4 is a cross-sectional view taken along the line A-A' of FIG. 1. FIG. 5 is a cross-sectional view taken along the line B-B' of FIG. 1.

[0010] The semiconductor device 100 according to the present embodiment will be outlined with reference to FIGS. 1 and 4. The semiconductor device 100 includes a substrate 110, a first lead 120, a second lead 130, a first chip 140, a second chip 150, a first connector 160, a second connector 170, a third connector 180, and a resin member 190. In FIG. 1, the resin member 190 is shown by a two-dot chain line in order to clearly show the internal structure of the semiconductor device 100. Hereinafter, each part of the semiconductor device 100 will be described in detail.

[0011] The substrate 110 is made of, for example, a metal material. Examples of the metal material used for the substrate 110 include metals with high heat dissipation such as copper. The shape of the substrate 110 is, for example, a substantially flat plate shape. Specifically, as shown in FIG. 4, the lower surface 110a and the upper surface 110b of the substrate 110 are substantially flat and are generally parallel to the X-Y plane. However, the shape of the substrate is not limited to the above.

[0012] The first lead 120 is made of, for example, a metal material. Examples of the metal material used for the first lead 120 include the same materials as those used for the substrate 110. As shown in FIG. 1, the first lead 120 is located on the +X side of the substrate 110 and is separated from the substrate 110. The shape of the first lead 120 is, for example, a substantially flat plate shape. However, the position and shape of the first lead are not limited to the above.

[0013] The second lead 130 is made of, for example, a metal material. Examples of the metal material used for the second lead 130 include the same materials as those used for the substrate 110. The second lead 130 is located on the -X side of the substrate 110 and is separated from the substrate 110 and the first lead 120. The shape of the second lead 130 is, for example, a substantially flat plate shape. However, the position and shape of the second lead are not limited to the above.

[0014] The first chip 140 is disposed on the substrate 110 as shown in FIG. 2. The first chip 140 is, for example, a MOSFET having a field plate (FP) electrode. However, the first chip may be a MOSFET without an FP electrode, or may be another type of semiconductor element. The shape of the first chip 140 is, for example, substantially flat. Specifically, the shape of the first chip 140 in a top view is substantially rectangular. As shown in FIG. 4, the surface of the first chip 140 includes a lower surface 140a facing the substrate 110 and an upper surface 140b located on the opposite side of the lower surface 140a.

[0015] As shown in FIG. 5, the first chip 140 has a semiconductor portion 145. The semiconductor portion 145 is made of a semiconductor material such as silicon, and impurities are locally introduced therein so that the conductivity type is n-type or p-type. A drain electrode 141 is disposed on the lower surface 140a of the first chip 140. The drain electrode 141 is electrically connected to the substrate 110 by a conductive bonding layer 141c such as solder. Here, "disposed on the surface where the electrode is located" means that at least a part of the surface of the electrode is exposed on that surface. In the present embodiment, the bonding layer 141c is in contact with both the substrate 110 and the drain electrode 141. A source electrode 142 and a gate electrode 143 are disposed on the upper surface 140b of the first chip 140.

[0016] When viewed from above, that is, in the +Z direction, the shape of the source electrode 142 is as shown in FIG. 2, such that one corner of the square is cut out and the other corners are rounded. The gate electrode 143 is separated from the source electrode 142 and is disposed in a region where the corner of the source electrode 142 is cut out. The shape of the gate electrode 143 in a top view is a substantially square with rounded corners. The gate electrode 143 is separated from the source electrode 142. However, the positions and shapes of the source electrode and the gate electrode are not limited to the above.

[0017] The second chip 150 is, for example, the same semiconductor element as the first chip 140. Specifically, the second chip 150 is a MOSFET having FP electrodes. Also, in the present embodiment, the chip area and shape of the second chip 150 are substantially the same as the chip area and shape of the first chip 140. Note that the "chip area" refers to the area in the X-Y plane.

[0018] As shown in FIG. 4, the second chip 150 is disposed above the first chip 140. The surface of the second chip 150 includes a lower surface 150a facing the upper surface 140b of the first chip 140 and an upper surface 150b located on the opposite side of the lower surface 150a.

[0019] As shown in FIG. 5, the second chip 150 has a semiconductor portion 155. The semiconductor portion 155 is made of a semiconductor material such as silicon, and impurities are locally introduced therein so that the conductivity type is n-type or p-type. A source electrode 151 and a gate electrode 152 are disposed on the lower surface 150a of the second chip 150. A drain electrode 153 is disposed on the upper surface 150b of the second chip 150.

[0020] The source electrode 151 of the second chip 150 faces the source electrode 142 of the first chip 140. The shape of the source electrode 151 of the second chip 150 is substantially the same as the shape of the source electrode 142 of the first chip 140. The area of the source electrode 151 of the second chip 150 is substantially the same as the area of the source electrode 142 of the first chip 140.

[0021] The gate electrode 152 of the second chip 150 faces the gate electrode 143 of the first chip 140. The shape of the gate electrode 152 of the second chip 150 is substantially the same as the shape of the gate electrode 143 of the first chip 140. The area of the gate electrode 152 of the second chip 150 is substantially the same as the area of the gate electrode 143 of the first chip 140.

[0022] Therefore, the first chip 140 and the second chip 150 are arranged substantially symmetrically with respect to a plane P that passes through the center of the gap between the first chip 140 and the second chip 150 and is substantially parallel to the X-Y plane. However, the positions and shapes of the source electrode and the gate electrode are not limited to the above.

[0023] The area of the first chip 140 and the area of the second chip 150 as viewed from above are each preferably 10 mm 2 or more and 25 mm 2 or less. However, the area of each chip is not limited to the above.

[0024] The first connector 160 is electrically connected to the source electrode 142 of the first chip 140, the source electrode 151 of the second chip 150, and the first lead 120. The first connector 160 is made of, for example, a metal material or the like. As the metal material used for the first connector 160, the same material as that used for the substrate 110 can be used. The first connector 160 is formed, for example, by bending a single copper plate.

[0025] The first connector 160 has a first portion 161 located above the first chip 140, a second portion 162 extending from the first portion 161 toward the first lead 120, and a third portion 163 connected to the lower end of the second portion 162 and extending along the surface of the first lead 120.

[0026] The shape of the first portion 161 is, for example, a substantially flat plate shape substantially parallel to the X-Y plane. The first portion 161 is disposed between the two source electrodes 142 and 151 and extends in the +X direction from above the first chip 140 and the second chip 150 as viewed from above. The first portion 161 is connected to the source electrode 142 of the first chip 140 by a conductive bonding layer 142c such as solder. The first portion 161 is also connected to the source electrode 151 of the second chip 150 by a conductive bonding layer 151c such as solder.

[0027] In this embodiment, the second part 162 is continuous with the end of the first part 161 in the +X direction and extends downward. The third part 163 extends in the +X direction from the lower end of the second part 162. The third part 163 is connected to the first lead 120 by a conductive bonding layer 120c such as solder. However, the shape of the first connector 160 is not limited to the above.

[0028] The third connector 180 is electrically connected to the gate electrode 143 of the first chip 140, the gate electrode 152 of the second chip 150, and the second lead 130. The same material as that used for the first connector 160 can be used for the third connector 180. The third connector 180 is formed, for example, by bending a single copper plate.

[0029] The third connector 180 has a first part 181 located above the first chip 140, a second part 182 extending from the first part 181 toward the second lead 130, and a third part 183 continuous with the lower end of the second part 182 and extending along the surface of the second lead 130.

[0030] The shape of the first part 181 is, for example, a substantially flat plate shape substantially parallel to the X-Y plane. The first part 181 is disposed between the two gate electrodes 143 and 152 and protrudes in the -X direction from the first chip 140 and the second chip 150 when viewed from above. The first part 181 is connected to the gate electrode 143 of the first chip 140 by a conductive bonding layer 143c such as solder. The first part 181 is connected to the gate electrode 152 of the second chip 150 by a conductive bonding layer 152c such as solder.

[0031] In this embodiment, the second part 182 is continuous with the end of the first part 181 in the -X direction and extends downward. The third part 183 extends in the -X direction from the lower end of the second part 182. The third part 183 is connected to the second lead 130 by a conductive bonding layer 130c such as solder. However, the shape of the third connector 180 is not limited to the above.

[0032] As shown in FIG. 5, the second connector 170 is electrically connected to the drain electrode 153 of the second chip 150 and the substrate 110. The second connector 170 is made of, for example, the same material as the substrate 110. The second connector 170 is formed, for example, by bending a single copper plate.

[0033] The second connector 170 has a first portion 171 located above the second chip 150, a second portion 172 extending from the first portion 171 to the substrate 110, and a third portion 173 connected to the lower end of the second portion 172 and extending along the surface of the substrate 110.

[0034] The shape of the first portion 171 is, for example, a substantially flat plate shape substantially parallel to the X-Y plane. The first portion 171 covers the drain electrode 153 of the second chip 150 when viewed from above, and extends in the +Y direction beyond the first chip 140 and the second chip 150 when viewed from above. The first portion 171 is connected to the drain electrode 153 of the second chip 150 by a conductive bonding layer 153c such as solder.

[0035] In this embodiment, the second portion 172 is connected to the end of the first portion 171 in the +Y direction and extends downward. The third portion 173 extends in the +Y direction from the lower end of the second portion 172. The third portion 173 is connected to the substrate 110 by a conductive bonding layer 110c such as solder. It is preferable that the thickness of the second portion 172 is equal to or smaller than the thickness of the first portion 171. By the thickness of the second portion 172 being smaller than the thickness of the first portion 171, it becomes easy to form the second connector 170 by bending. However, the shape of the second connector 170 is not limited to the above.

[0036] In this embodiment, the first thickness D1 of the first portion 171 is smaller than the second thickness D2 of the portion of the substrate 110 that overlaps the drain electrode 141 when viewed from above. The difference between the first thickness D1 and the second thickness D2 is preferably 20% or less of the second thickness D2. However, the first thickness may be greater than the second thickness. In this case, the difference between the first thickness and the second thickness is preferably 20% or less of the first thickness. Also, the first thickness and the second thickness may be the same. That is, the difference between the first thickness and the second thickness is preferably 20% or less of the larger of the first thickness and the second thickness. That is, the thicknesses D1 and D2 preferably satisfy the following equation. (D2 - D1) / D2 × 100 ≤ 20 (D1 ≤ D2) (D1 - D2) / D1 × 100 ≤ 20 (D1 ≥ D2)

[0037] The resin member 190 seals the first chip 140, the second chip 150, the first connector 160, the second connector 170, and the third connector 180. As shown in FIGS. 1, 4, and 5, the resin member 190 exposes the end portion of the substrate 110 in the +Y direction and the lower surface 110a of the substrate 110. The portion of the substrate 110 exposed from the resin member 190 functions as a connection terminal for connecting the two drain electrodes 141 and 153 to the outside. The resin member 190 exposes the end portion of the first lead 120 in the +X direction and the lower surface of the first lead 120. The portion of the first lead 120 exposed from the resin member 190 functions as a connection terminal for connecting the two source electrodes 142 and 151 to the outside. The resin member 190 exposes the end portion of the second lead 130 in the -X direction and the lower surface of the second lead 130. The portion of the second lead 130 exposed from the resin member 190 functions as a connection terminal for connecting the two gate electrodes 143 and 152 to the outside. The resin member 190 is made of a resin material such as a thermosetting resin.

[0038] The breakdown voltages of the first chip 140 and the second chip 150 are preferably greater than 0V and 100V or less, for example. However, the breakdown voltages of the first chip 140 and the second chip 150 are not limited to the above.

[0039] Next, the effects of this embodiment will be described. FIG. 6 is a circuit diagram of the semiconductor device according to this embodiment. In FIG. 6, in the semiconductor device 100, connection terminals to the outside of the two drain electrodes 141 and 153 are denoted by reference numeral 110d, connection terminals to the outside of the two source electrodes 142 and 151 are denoted by reference numeral 120d, and connection terminals to the outside of the two gate electrodes 143 and 152 are denoted by reference numeral 130d.

[0040] As shown in FIGS. 4 and 6, the gate electrode 143 of the first chip 140 and the gate electrode 152 of the second chip 150 are connected to the outside via the third connector 180 and the second lead 130. Therefore, most of the current path from the external connection terminal 130d to the gate electrode 143 and the current path from the external connection terminal 130d to the gate electrode 152 are common. For this reason, a difference in electrical resistance is unlikely to occur between the current path from the connection terminal 130d to the gate electrode 143 and the current path from the connection terminal 130d to the gate electrode 152.

[0041] Similarly, the source electrode 142 of the first chip 140 and the source electrode 151 of the second chip 150 are connected to the outside via the first connector 160 and the first lead 120. Therefore, most of the current path from the source electrode 142 to the external connection terminal 120d and the current path from the source electrode 151 to the external connection terminal 120d are common. For this reason, a difference in electrical resistance is unlikely to occur between the current path from the connection terminal 120d to the source electrode 142 and the current path from the connection terminal 120d to the source electrode 151.

[0042] On the one hand, as shown in FIGS. 5 and 6, the drain electrode 141 of the first chip 140 is externally connected via the substrate 110, and the drain electrode 153 of the second chip 150 is externally connected by the substrate 110 and the second connector 170. Therefore, the current paths from the external connection terminal 110d to the drain electrode 141 and from the external connection terminal 110d to the drain electrode 153 are mostly different. Hereinafter, the electrical resistance of the common portion of these two current paths in the substrate 110 is defined as electrical resistance R1, the electrical resistance of only the current path reaching the drain electrode 141 of the first chip 140 in these two current paths in the substrate 110 is defined as electrical resistance R2, and the electrical resistance of the second connector 170 is defined as electrical resistance R3.

[0043] The smaller the first thickness D1 of the second connector 170 is than the second thickness D2 of the substrate 110, the larger the electrical resistance R3 is than the electrical resistance R2. The larger the electrical resistance R3 is than the electrical resistance R2, the easier it is for current to flow to the drain electrode 141 of the first chip 140 than to the drain electrode 153 of the second chip 150. In such a case, when the source-drain current of the semiconductor device 100 is increased, the first chip 140 through which more current flows is more likely to undergo avalanche breakdown. Conversely, the smaller the second thickness D2 of the substrate 110 is than the first thickness D1 of the second connector 170, the larger the electrical resistance R2 is than the electrical resistance R3. The larger the electrical resistance R2 is than the electrical resistance R3, the easier it is for current to flow to the drain electrode 153 of the second chip 150 than to the drain electrode 141 of the first chip 140. In such a case, when the source-drain current of the semiconductor device 100 is increased, the second chip 150 through which more current flows is more likely to undergo avalanche breakdown.

[0044] In the present embodiment, the difference between the first thickness D1 and the second thickness D2 is 20% or less of the larger thickness of the first thickness D1 and the second thickness D2. Therefore, the difference between the electrical resistance R2 and the electrical resistance R3 can be reduced. As a result, it is possible to suppress current from flowing preferentially to the first chip 140 or the second chip 150 and reaching avalanche breakdown. As described above, the avalanche tolerance of the entire semiconductor device 100 can be improved.

[0045] Also, in this embodiment, the second thickness D2 is smaller than the first thickness D1. Therefore, the amount of thermal expansion of the second connector 170 can be reduced. As a result, when the second connector 170 thermally expands, it is possible to suppress deformation, breakage, etc. of the resin member 190 that covers the second connector 170.

[0046] <First Example> Next, a first example of the first embodiment will be described. FIG. 7 is an evaluation circuit of a semiconductor device according to a reference example and an example. FIG. 8 is a graph showing the relationship between the breakdown voltage and the current ratio Tr1 / Tr2.

[0047] Semiconductor devices according to Reference Examples 1 to 3 and semiconductor devices according to Examples 1 to 3 were fabricated. The semiconductor devices according to Reference Examples 1 to 3 and the semiconductor devices according to Examples 1 to 3 each include a substrate 110, a first lead 120, a second lead 130, a first chip 140, a second chip 150, a first connector 160, a second connector 170, a third connector 180, and a resin member 190, and the configurations other than the first thickness D1 of the second connector 170 are common. In the semiconductor devices according to Reference Examples 1 to 3, the first thickness D1 of the second connector 170 was set to 150 μm, and in the semiconductor devices according to Examples 1 to 3, the first thickness D1 of the second connector 170 was set to 250 μm. In the semiconductor devices according to Reference Examples 1 to 3 and the semiconductor devices according to Examples 1 to 3, the second thickness D2 of the substrate 110 was set to 300 μm in all cases. Therefore, in the semiconductor devices according to Reference Examples 1 to 3, the difference between the first thickness D1 and the second thickness D2 is 150 μm, which is 50% of the second thickness D2. In the semiconductor devices according to Examples 1 to 3, the difference between the first thickness D1 and the second thickness D2 is 50 μm, which is about 17% of the second thickness D2 and 20% or less.

[0048] Also, the breakdown voltages of the semiconductor devices according to Reference Example 1 and Example 1 were set to 40 V, the breakdown voltages of the semiconductor devices according to Reference Example 2 and Example 2 were set to 100 V, and the breakdown voltages of the semiconductor devices according to Reference Example 3 and Example 3 were set to 150 V.

[0049] Then, the semiconductor devices according to Reference Examples 1 to 3 and the semiconductor devices according to Examples 1 to 3 were respectively incorporated into the evaluation circuit shown in FIG. 7, and the current Tr1 flowing through the first chip 140 and the current Tr2 flowing through the second chip 150 were measured. Specifically, the connection terminal 110d was electrically connected to the inductor 910. The inductor 910 was further electrically connected to the power supply 920. The connection terminal 120d was electrically connected to the ground 930. The connection terminal 130d was electrically connected to the signal source 940.

[0050] For each of the semiconductor devices according to Reference Examples 1 to 3 and the semiconductor devices according to Examples 1 to 3, the ratio Tr1 / Tr2 of the current Tr1 to the current Tr2 was calculated. The relationship between the obtained current ratio Tr1 / Tr2 and the breakdown voltage is shown in FIG. 8. In FIG. 8, the horizontal axis represents the breakdown voltage, and the vertical axis represents the current ratio Tr1 / Tr2. The closer the current ratio Tr1 / Tr2 is to 1, the more evenly the current flows through the first chip 140 and the second chip 150.

[0051] As shown in FIG. 8, even at the same breakdown voltage, the semiconductor devices according to Examples 1 to 3 have a current ratio Tr1 / Tr2 closer to 1 than the semiconductor devices according to Reference Examples 1 to 3. Therefore, when increasing the source-drain current of the semiconductor device, it is possible to suppress one of the chips from being destroyed first, and the avalanche tolerance of the entire semiconductor device is improved. Therefore, the difference between the first thickness D1 and the second thickness D2 is preferably 20% or less of the second thickness D2.

[0052] Also, in the range where the withstand voltage is 100V or less, by making the difference between the first thickness D1 and the second thickness D2 20% or less of the second thickness D2, the effect of making the ratio Tr1 / Tr2 approach 1 is higher than in the range where the withstand voltage is greater than 100V. This is presumably because the higher the withstand voltage, the higher the proportion of the internal resistance of each chip 140, 150 in the total resistance of the semiconductor device, and the lower the proportion of the electrical resistances R2, R3. Therefore, it is preferable that the withstand voltage of the semiconductor device is 100V or less.

[0053] <Second Embodiment> Next, a second embodiment of the first embodiment will be described. FIG. 9 is a graph showing the effect of stacking chips, with the chip area of one chip on the horizontal axis and the reduction rate of the on-resistance by stacking and connecting two chips in parallel on the vertical axis. The vertical axis of FIG. 9 shows the reduction rate of the overall on-resistance when two identical chips are stacked and connected in parallel with respect to the on-resistance of one chip. If calculated simply based on only the internal resistance of the chip, the reduction rate of the on-resistance should be -50%.

[0054] As shown in FIG. 9, the smaller the chip area, the more remarkable the reduction rate of the on-resistance. This is presumably because the smaller the chip area, the larger the resistance of the transistor portion, and the proportion of the resistance of the transistor portion in the total resistance increases. Therefore, the reduction of the resistance of the transistor portion by stacking increases the total resistance reduction rate. Therefore, the chip area of the first chip 140 and the chip area of the second chip 150 as viewed from above are preferably 10mm 2 or more and 25mm 2 or less, respectively.

[0055] <Second Embodiment> Next, the second embodiment will be described. FIG. 10 is a cross-sectional view showing the semiconductor device according to this embodiment. In the semiconductor device 200 according to this embodiment, the orientation of the first chip 240 and the orientation of the second chip 250 are different from those of the semiconductor device 100 according to the first embodiment. In the following description, mainly only the differences from the first embodiment will be described. Except for the matters described below, the configuration can be the same as that of the first embodiment. The same applies to other embodiments described later.

[0056] On the lower surface 240a of the first chip 240, a source electrode 241 and a gate electrode 242 are arranged. The source electrode 241 faces the conductive first substrate 210 and is electrically connected to the first substrate 210 via a bonding layer 241c. The gate electrode 242 faces the conductive second substrate 220 and is electrically connected to the second substrate 220 via a bonding layer 242c.

[0057] On the upper surface 240b of the first chip 240, a drain electrode 243 is arranged. The drain electrode 243 faces the first connector 260. The drain electrode 243 is electrically connected to the first connector 260 via a bonding layer 243c. The first connector 260 is connected to a drain lead (not shown) in the same manner as the first connector 160 in the first embodiment.

[0058] On the lower surface 250a of the second chip 250, a drain electrode 251 is arranged. The drain electrode 251 faces the first connector 260. The drain electrode 251 is electrically connected to the first connector 260 via a bonding layer 251c.

[0059] On the upper surface 250b of the second chip 250, a source electrode 252 and a gate electrode 253 are arranged. The source electrode 252 faces the second connector 270. The source electrode 252 is electrically connected to the second connector 270 via a bonding layer 252c. The gate electrode 253 faces the third connector 280. The gate electrode 253 is electrically connected to the third connector 280 via a bonding layer 253c.

[0060] The second connector 270 has a first portion 271 positioned above the second chip 250, a second portion 272 extending from the first portion 271 toward the first substrate 210, and a third portion 273 connected to the lower end of the second portion 272 and extending along the surface of the first substrate 210. The difference between the first thickness D21 of the first portion 271 and the second thickness D22 of the portion of the first substrate 210 that overlaps the source electrode 241 when viewed from above is 20% or less of the larger one of the first thickness D21 and the second thickness D22 (in FIG. 10, the second thickness D22).

[0061] Similarly, the third connector 280 has a first portion 281 positioned above the second chip 250, a second portion 282 extending from the first portion 281 toward the second substrate 220, and a third portion 283 connected to the lower end of the second portion 282 and extending along the surface of the second substrate 220.

[0062] Also in such a semiconductor device 200, by setting the difference between the first thickness D21 and the second thickness D22 to 20% or less of the larger one of the first thickness D21 and the second thickness D22, the difference in electrical resistance between the current path from the first substrate 210 to the source electrode 241 of the first chip 240 and the current path from the first substrate 210 to the source electrode 252 of the second chip 250 via the second connector 270 can be reduced, and current concentration on one chip can be suppressed. As a result, the avalanche tolerance of the semiconductor device 200 can be improved.

[0063] <The Third Embodiment> Next, the third embodiment will be described. FIG. 11 is a cross-sectional view showing a semiconductor device according to this embodiment. As shown in FIG. 11, the semiconductor device 300 according to this embodiment is different from the semiconductor device 100 according to the first embodiment in that it further includes a plurality of metal layers 341e, 342e, 343e.

[0064] In this embodiment, the second thickness D2 is greater than the first thickness D1. Also, the difference between the first thickness D1 and the second thickness D2 is 20% or less of the second thickness D2. Therefore, current flows more easily through the first chip 140 than through the second chip 150. However, the difference between the first thickness D1 and the second thickness D2 may be greater than 20% of the second thickness D2. That is, the difference between the first thickness D1 and the second thickness D2 may be greater than 20% of the larger one of the first thickness D1 and the second thickness D2.

[0065] The metal layer 341e is located between the drain electrode 141 and the bonding layer 141c. The metal layer 341e is in contact with the upper surface of the bonding layer 141c and the lower surface of the drain electrode 141, thereby being electrically connected to the bonding layer 141c and the drain electrode 141. The metal layer 342e is located between the source electrode 142 and the bonding layer 142c. The metal layer 342e is in contact with the upper surface of the source electrode 142 and the lower surface of the bonding layer 142c, thereby being electrically connected to the source electrode 142 and the bonding layer 142c. The metal layer 343e is located between the gate electrode 143 and the bonding layer 143c. The metal layer 343e is in contact with the upper surface of the gate electrode 143 and the lower surface of the bonding layer 143c, thereby being electrically connected to the gate electrode 143 and the bonding layer 143c. The metal layers 341e, 342e, and 343e each extend along the X-Y plane.

[0066] The thermal conductivity of each of the metal layers 341e, 342e, and 343e is higher than the thermal conductivity of the bonding layers 141c, 142c, and 143c. Each metal layer 341e contains, for example, one or more of gold, silver, and copper. The thicknesses of the metal layers 341e, 342e, and 343e are not particularly limited, but are, for example, 10 μm or more and 20 μm or less. On the other hand, the bonding layers 141c, 142c, and 143c are made of, for example, solder. Generally, solder has a low thermal conductivity.

[0067] In the semiconductor device 300 according to this embodiment, since the second thickness D2 is greater than the first thickness D1, current more easily flows through the first chip 140 than through the second chip 150. Therefore, metal layers 341e, 342e, and 343e are respectively disposed on the electrodes 141, 142, and 143 of the first chip 140. Thereby, heat generated in a portion where current particularly concentrates within the first chip 140 is diffused along the X-Y plane, so that the temperature within the first chip 140 can be made uniform. Thereby, occurrence of thermal breakdown in a portion where current concentrates in the first chip 140 can be suppressed, and avalanche breakdown of the first chip 140 can be suppressed. As a result, the avalanche tolerance of the semiconductor device 300 can be improved.

[0068] Further, in this embodiment, each metal layer is disposed closer to the first chip 140 than each bonding layer. Thereby, heat directly transfers from the first chip 140 to each metal layer without passing through the bonding layer having a low thermal conductivity. As a result, heat can be effectively diffused by the metal layer, and the avalanche tolerance of the semiconductor device 300 is surely improved.

[0069] <Test Example> Next, a test example of the third embodiment will be described. FIG. 12 is a histogram with the current flowing through the chip when the chip undergoes avalanche breakdown on the horizontal axis and the appearance frequency of the chip at which each current is measured on the vertical axis. Ten chips having the same configuration as the first chip 140 and the second chip 150 and having a 10-μm-thick metal layer made of copper disposed on each of the drain electrode, the source electrode, and the gate electrode were prepared. Also, ten chips having the same configuration as the first chip 140 and the second chip 150 and having no metal layer disposed on the drain electrode, the source electrode, and the gate electrode were prepared. Then, the current Tr at which each chip undergoes avalanche breakdown was measured. The results are Figure 12 shown in.

[0070] As shown in Fig. 12, it was found that in a chip with a metal layer disposed on the electrodes, the current Tr at the time of chip breakdown tends to be high. That is, it was found that by disposing a metal layer on the electrodes of the chip, the avalanche tolerance of the chip can be improved. When taking the average value of the current Tr for each chip, the avalanche tolerance was improved by about 10% when a metal layer was provided as compared with the case where no metal layer was provided.

[0071] However, it is not necessary to dispose a metal layer on all the electrodes of the first chip. Also, the second thickness may be larger than the first thickness. In this case, current flows more easily through the second chip than the first chip. Therefore, in such a case, if a metal layer is disposed on the electrodes of the second chip, the heat generated in the second chip can be efficiently made uniform. That is, when the first thickness is smaller than the second thickness, it may be disposed on any one of the electrodes of the first chip, and when the first thickness is larger than the second thickness, a metal layer may be disposed on any one of the electrodes of the second chip. Also, such a metal layer may be disposed in the semiconductor device according to the second embodiment.

[0072] <Fourth Embodiment> Next, the fourth embodiment will be described. Fig. 13 is a cross-sectional view showing the semiconductor device according to the present embodiment. Fig. 13 corresponds to Fig. 5 in the first embodiment.

[0073] The semiconductor device 400 according to the present embodiment is different from the semiconductor device 100 according to the first embodiment in that the chip area of the chip through which current flows more easily is smaller than the chip area of the chip through which current flows less easily.

[0074] As shown in FIG. 13, in the semiconductor device 400, the second thickness D2 of the substrate 110 is larger than the first thickness D1 of the first portion 171 of the second connector 170. Therefore, if the first chip 340 and the second chip 350 are chips of the same standard, current tends to concentrate on the first chip 340. Thus, in the present embodiment, the chip area of the first chip 340 is made smaller than the chip area of the second chip 350. Thereby, the internal resistance of the first chip 340 becomes higher than the internal resistance of the second chip 350, and concentration of current on the first chip 340 can be suppressed. Thereby, the avalanche withstand voltage of the entire semiconductor device 400 is improved.

[0075] In each of the above-described embodiments, an example in which the substrate and the second connector are formed of the same material is shown, but the present invention is not limited to this. For example, when the substrate is thicker than the second connector, the electrical resistivity of the material forming the substrate may be made higher than the electrical resistivity of the material forming the second connector. For example, the substrate may be formed of aluminum (electrical resistivity: 28.2 nΩ·m at 20° C.), and the second connector may be formed of copper (electrical resistivity: 16.8 nΩ·m at 20° C.).

[0076] As described above, the embodiments of the present invention have been described. However, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the scope of the invention described in the claims and equivalents thereof. Further, the above-described embodiments may be implemented in combination with each other.

Description of Reference Numerals

[0077] 100, 200, 300, 400: Semiconductor device 110: Substrate 110a: Lower surface 110b: Upper surface 110c, 120c, 130c, 141c, 142c, 143c, 151c, 152c, 153c: Bonding layer 110d, 120d, 130d: Connection terminal 120: First lead 130: Second lead 140, 240, 340: First chip 140a, 240a: Bottom surface 140b, 240b: Top surface 141, 243: Drain electrode 142, 241: Source electrode 143, 242: Gate electrode 145, 155: Semiconductor part 150, 250, 350: Second chip 150a, 250a: Bottom surface 150b, 250b: Top surface 151, 252: Source electrode 152, 253: Gate electrode 153, 251: Drain electrode 160, 260: First connector 161: First part 162: Second part 163: Third part 170, 270: Second connector 171, 271: First part 172, 272: Second part 173, 273: Third part 180, 280: Third connector 181, 281: First part 182, 282: Second part 183, 283: Third part 190: Resin member 210: First substrate 220: Second substrate 341e, 342e, 343e: Metal layer 910: Inductor 920: Power supply 930: Ground 940: Signal source D1, D21: First thickness D2, D22: Second thickness P: Plane R1, R2, R3: Electric resistance Tr, Tr1, Tr2: Current

Claims

1. A substrate having conductivity and a second thickness, A first chip including a first surface facing the substrate and a second surface located on the opposite side of the first surface, wherein a first electrode electrically connected to the substrate is disposed on the first surface and a second electrode is disposed on the second surface, A second chip including a third surface facing the second surface and a fourth surface located on the opposite side of the third surface, wherein a third electrode is disposed on the third surface and a fourth electrode is disposed on the fourth surface, A first connector disposed between the second electrode and the third electrode and electrically connected to the second electrode and the third electrode, A second connector electrically connected to the substrate and the fourth electrode and including a first portion located above the second chip, wherein a difference between a first thickness of the first portion and the second thickness is 20% or less of the first thickness, and the second thickness is smaller than the first thickness, Comprising, A semiconductor device in which a distance between a connection point of the second connector with the substrate and a connection point of the second connector with the fourth electrode is longer than a distance between a connection point of the second connector with the substrate and a connection point of the second connector with the first electrode on the substrate.

2. A first bonding layer having conductivity and located between the first electrode and the substrate, A second bonding layer having conductivity and located between the second electrode and the first connector, A third bonding layer having conductivity and located between the third electrode and the first connector, A fourth bonding layer having conductivity and located between the fourth electrode and the second connector, Having a thermal conductivity higher than the thermal conductivities of the first bonding layer, the second bonding layer, the third bonding layer, and the fourth bonding layer, and when the first thickness is smaller than the second thickness, disposed between the first bonding layer and the first electrode or between the second bonding layer and the second electrode, and when the first thickness is larger than the second thickness, disposed between the third bonding layer and the third electrode or between the fourth bonding layer and the fourth electrode, a metal layer, The semiconductor device according to claim 1, further comprising.

3. A substrate having conductivity, A first chip including a first surface facing the substrate and a second surface located on the opposite side of the first surface, wherein a first electrode electrically connected to the substrate is disposed on the first surface and a second electrode is disposed on the second surface, A second chip including a third surface facing the second surface and a fourth surface located on the opposite side of the third surface, wherein a third electrode is disposed on the third surface and a fourth electrode is disposed on the fourth surface, A first connector disposed between the second electrode and the third electrode and electrically connected to the second electrode and the third electrode; A second connector electrically connected to the substrate and the fourth electrode and including a first portion located above the second chip; A first bonding layer located between the first electrode and the substrate and having conductivity; A second bonding layer located between the second electrode and the first connector and having conductivity; A third bonding layer located between the third electrode and the first connector and having conductivity; A fourth bonding layer located between the fourth electrode and the second connector and having conductivity; A metal layer having a higher thermal conductivity than the thermal conductivities of the first bonding layer, the second bonding layer, the third bonding layer, and the fourth bonding layer, and disposed between at least one of the first bonding layer and the first electrode, the second bonding layer and the second electrode, the third bonding layer and the third electrode, and the fourth bonding layer and the fourth electrode; Comprising; The semiconductor device, wherein when the first thickness of the first portion is smaller than the second thickness of the portion of the substrate that overlaps the first electrode when viewed from above, the metal layer is disposed between the first bonding layer and the first electrode or between the second bonding layer and the second electrode, and when the first thickness is larger than the second thickness, the metal layer is disposed between the third bonding layer and the third electrode or between the fourth bonding layer and the fourth electrode.

4. The first thickness is smaller than the second thickness; The semiconductor device according to claim 3, wherein the metal layer is disposed between both the first bonding layer and the first electrode and between the second bonding layer and the second electrode.

5. A conductive substrate; A first chip including a first surface facing the substrate and a second surface located on the opposite side of the first surface, wherein a first electrode electrically connected to the substrate is disposed on the first surface and a second electrode is disposed on the second surface; A second chip including a third surface facing the second surface and a fourth surface located on the opposite side of the third surface, wherein a third electrode is disposed on the third surface and a fourth electrode is disposed on the fourth surface, and the area when viewed from above is larger than the area of the first chip; A first connector disposed between the second electrode and the third electrode and electrically connected to the second electrode and the third electrode; A second connector that is electrically connected to the substrate and the fourth electrode, includes a first portion located above the second chip, and has a first thickness of the first portion smaller than a second thickness of a portion of the first electrode overlapping when viewed from above in the substrate. A semiconductor device comprising the same. **Claim 6** The second connector further includes a second portion extending from the substrate toward the first portion. The semiconductor device according to any one of claims 1 to 5, wherein a thickness of the second portion is smaller than a thickness of the first portion. **Claim 7** When viewed from above, the area of the first chip and the area of the second chip are each 10 mm ２ or more and 25 mm ２ or less. The semiconductor device according to any one of claims 1 to 6.

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