Method for manufacturing a ferroelectric device

Abstract

To provide a ferroelectric layer having improved ferroelectricity and a device with the ferroelectric layer which has improved performance reliability.SOLUTION: A method includes depositing a doped hafnium dioxide layer on one layer 802 of a semiconductor device, and a ferroelectric layer 804 which is the doped hafnium dioxide layer has a first oxygen vacancy concentration. The method further includes performing an ultra-high vacuum anneal process on the doped hafnium dioxide layer to increase the first oxygen vacancy concentration to a second oxygen vacancy concentration, and performing an oxygen anneal process on the doped hafnium dioxide layer to decrease the second oxygen vacancy concentration.SELECTED DRAWING: Figure 8A

Description

Background Art

[0001] Many modern electronic devices include electronic memory configured to store data. The electronic memory is either volatile memory or non-volatile memory. Volatile memory stores data while power is supplied, and non-volatile memory can store data even when power is removed. Ferroelectric memory devices are one of the expected candidates for next-generation non-volatile memory. For example, ferroelectric memory devices include capacitor-type ferroelectric random access memory (FeRAM) and ferroelectric field effect transistors (FeFET). FeRAM and FeFET devices offer many advantages such as fast write times, high durability, low power consumption, and resistance to radiation damage.

Summary of the Invention

Problems to be Solved by the Invention

[0002] The ferroelectricity of the ferroelectric layer depends on its crystal state. The higher the proportion of the orthorhombic phase in the ferroelectric layer, the better the ferroelectric properties. Also, the dopant concentration and oxygen vacancies affect the ferroelectricity of the ferroelectric layer. However, it is difficult to form a ferroelectric layer with a high proportion of the orthorhombic phase or to form a ferroelectric layer with an excellent balance between dopants and oxygen vacancies.

Means for Solving the Problems

[0003] The present disclosure provides a method. The method includes depositing a doped hafnium dioxide layer on a certain layer, the doped hafnium dioxide layer having a first oxygen vacancy concentration. The method further includes performing an ultra-high vacuum annealing process on the doped hafnium dioxide layer to increase the first oxygen vacancy concentration to a second oxygen vacancy concentration, and performing an oxygen annealing process on the doped hafnium dioxide layer to decrease the second oxygen vacancy concentration.

[0004] The present disclosure provides a method. The method includes depositing a hafnium dioxide layer doped on a layer, where the doped hafnium dioxide layer is partially crystallized in a first crystal phase. The method further includes performing an ion implantation process on the doped hafnium dioxide layer to amorphize the doped hafnium dioxide layer, and performing an annealing process on the doped hafnium dioxide layer to crystallize the doped hafnium dioxide layer in a second crystal phase.

[0005] The present disclosure provides a semiconductor device structure. The structure includes a transistor provided on a substrate, an interconnect structure provided above the transistor, and a ferroelectric capacitor (FeCAP) provided in the interconnect structure. The FeCAP includes a first metal layer, and the first metal layer is a single-crystalline metal layer. The FeCAP further includes a ferroelectric layer provided on the first metal layer, and the ferroelectric layer includes a rhombohedral phase exceeding 90%. The FeCAP further includes a second metal layer provided on the ferroelectric layer.

Advantages of the Invention

[0006] The present disclosure provides a ferroelectric layer having improved ferroelectricity, and a device including the ferroelectric layer has improved performance reliability. In some embodiments, the ferroelectric layer is provided on a single-crystalline metal layer, and the ferroelectric layer includes a rhombohedral phase exceeding 90%. In some embodiments, a UHV annealing process or an ion implantation process is performed after deposition of the ferroelectric layer to increase the proportion of the rhombohedral phase and / or increase the in-layer space for atom movement.

Brief Description of the Drawings

[0007] Aspects of the present disclosure are best understood by reading the following detailed description in conjunction with the accompanying drawings. Note that various features are not drawn to scale in accordance with standard industry practice. In fact, the dimensions of various features shown in the accompanying drawings may be arbitrarily enlarged or reduced for clarity of explanation.

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Best Mode for Carrying Out the Invention

[0008] The following embodiments provide many different embodiments or examples for implementing different features of the present disclosure. For the sake of simplifying the present disclosure, specific examples of elements and arrangements are described below. Of course, these are illustrative and not intended to be limiting. For example, in the following description, the configuration of the first feature above the second feature or on the second feature may include embodiments in which the first and second features are formed in direct contact, and also embodiments in which additional features are formed between the first and second features so that the first and second features do not directly contact. In addition, the present disclosure may repeat reference signs and / or letters in various embodiments. This repetition is for the purpose of simplification and clarity and does not itself define the relationship between the various embodiments and / or configurations being referred to.

[0009] Furthermore, spatial relative terms such as "below", "beneath", "lower", "above", "upper", "on", "top", "upper part", etc. may be used to facilitate the description of the relationship of one element or feature shown in the figure to another element or feature. The spatial relative terms are intended to encompass different directions of the device during use or operation in addition to the illustrated direction. The device may be otherwise oriented (rotated 90 degrees or in other directions), and the spatial relative descriptors used herein may be interpreted in the same way accordingly.

[0010] Still further, when a number, or a range of numbers, is described using terms such as "about", "approximately", etc., the term is intended to include numbers within a reasonable range that includes the stated value, such as plus or minus 10% of the stated number, or other values understood by those skilled in the art. For example, the term "about 5 nm" encompasses dimensions in the range of 4.5 nm to 5.5 nm.

[0011] Some variations of the exemplary methods and structures are described. Those skilled in the art will readily understand that other modifications can be made within the scope of other embodiments. Although the method embodiments may be described in a particular order, various other method embodiments can be executed in any logical order and may include fewer or more steps than those described herein. In some of the figures, some of the reference numerals for the components or features shown therein may be omitted to avoid obscuring other components or features, which is for the ease of depicting the figures.

[0012] FIG. 1A is a circuit diagram of a FeRAM cell according to some embodiments. As shown in FIG. 1A, the FeRAM cell 100 includes a transistor 104 and a capacitor 101. The FeRAM cell 100 may be other types of FeRAM cells, such as a 2-transistor 2-capacitor (2T2C) FeRAM cell. FIG. 1B is a side cross-sectional view of the FeRAM cell 100 of FIG. 1A according to some embodiments. As shown in FIG. 1B, the FeRAM cell 100 includes a transistor 104 provided on a substrate 102. The transistor 104 includes a drain region 104a and a source region 104b provided on the substrate 102. The substrate 102 may be a semiconductor substrate such as a silicon wafer. For example, the substrate 102 can include silicon, compound semiconductors such as gallium arsenide (GaAs), indium phosphide (InP), silicon germanium (SiGe), silicon carbide (SiC), other suitable semiconductor materials, and / or combinations thereof. The substrate 102 may be doped with a dopant such as an n-type dopant or a p-type dopant. The drain region 104a and the source region 104b may be doped with a dopant such as an n-type dopant or a p-type dopant.

[0013] The gate electrode 104c is provided above the substrate 102 between the drain region 104a and the source region 104b. The gate electrode 104c may include one or more layers. For example, the gate electrode 104c may include one or more work function layers and a bulk layer. In some embodiments, the work function layer includes one or more layers of a conductive material such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC, or a multilayer of two or more of these materials. The bulk layer may include a conductive material such as a metal. In some embodiments, the bulk layer includes W, Cu, Ti, Al, or Co. The gate electrode 104c may include additional layers such as an adhesive layer, a barrier layer, a capping layer, or any suitable layer. The work function layer and the additional layers may be optional. A gate dielectric layer 104d is provided between the gate electrode 104c and the substrate 102. The gate dielectric layer 104d includes a dielectric material. In some embodiments, the gate dielectric layer 104d may include a high-k dielectric layer, and in these embodiments, the gate dielectric layer 104d may have a dielectric constant value higher than about 7.0 and may include a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof.

[0014] The transistor 104 may be a suitable transistor such as a planar transistor, a FinFET, or a nanostructure transistor such as a gate-all-around (GAA) FET, a nanosheet FET, or a nanowire FET.

[0015] As shown in FIG. 1B, in some embodiments, the gate electrode 104c may be electrically connected to a word line (WL), the source region 104b may be electrically connected to a bit line (BL), the drain region 104a may be electrically connected to a capacitor 101, and the capacitor 101 may be electrically connected to a drive line (DL). The drain region 104a may be electrically connected to the capacitor 101 via one or more conductive wirings 110 and one or more conductive vias 108. The capacitor 101, the one or more conductive wirings 110, and the one or more conductive vias 108 may be incorporated into a dielectric layer structure 106. The dielectric structure 106 and the functions formed therein may be an interconnect structure, and the dielectric structure 106 may include a plurality of inter-metal dielectric (IMD) layers.

[0016] The capacitor 101 may be a ferroelectric capacitor (FeCAP). In some embodiments, the capacitor 101 includes a first electrode 112, a second electrode 116, and a ferroelectric layer 114 provided between the first electrode 112 and the second electrode 116. In some embodiments, the ferroelectric layer 114 may be a high-k dielectric layer having a dielectric constant higher than about 3.9. For example, the ferroelectric layer 114 may include a high-k dielectric such as a hafnium-based oxide material such as hafnium dioxide (HfO2). Other suitable ferroelectric materials can also be used. In some embodiments, the ferroelectric layer 114 may be, for example, a hafnium-based layer doped with a suitable element such as zirconium, aluminum, lanthanum, titanium, tantalum, silicon, yttrium, scandium, gadolinium, other suitable elements, or combinations thereof.

[0017] In some embodiments, the ferroelectric layer 114 is a doped hafnium dioxide layer having an orthorhombic phase. Other crystal phases, such as the monoclinic or tetragonal phase of the doped hafnium dioxide layer, may not exhibit ferroelectric properties. The doped hafnium dioxide layer having an orthorhombic phase contains oxygen atoms that can move to two different positions under an applied electric field, and the doped hafnium dioxide layer having an orthorhombic phase has two orthorhombic shapes. The two orthorhombic shapes have a mutually convertible barrier that can be switched by applying an electric field. In some embodiments, the addition of dopant atoms to the lattice of the hafnium oxide layer can change the local stress, provide sufficient space for the movement of oxygen atoms, and result in ferroelectric behavior. Larger dopants shift the plane of the monoclinic structure, and the atoms tend to be arranged according to the orthorhombic structure. In some embodiments, the doped hafnium dioxide layer contains a zirconium dopant having a dopant concentration between about 40 mol% and about 60 mol%. For example, the ferroelectric layer 114 may be Hf 0.6 Zr 0.4 O2~Hf 0.4 Zr 0.6 O2. In some embodiments, the zirconium dopant concentration may be outside the range of about 40 mol% to about 60 mol%. For other dopants (D) such as aluminum, lanthanum, titanium, tantalum, silicon, yttrium, scandium, or gadolinium, the dopant concentration may be in the range of about 0.1 mol% to about 15 mol%. For example, the ferroelectric layer 114 may be D 0.01 Hf 0.99 O2~D 0.15 Hf 0.85 O2. Since zirconium and hafnium have similar electronic structures, zirconium as a dopant can have a relatively high dopant concentration, and the oxides of zirconium and hafnium can be substantially the same. In some embodiments, crystallization in the orthorhombic phase produces a mixture of two states. The orthorhombic phase is then polarized to one of the two states by applying a voltage.

[0018] In some embodiments, when deposited, the doped hafnium dioxide layer is in an amorphous or partially crystalline state, and an annealing process is performed to increase the proportion of the orthorhombic phase. The doped hafnium dioxide layer is polyphase, which means it crystallizes into all possible phases (monoclinic, orthorhombic, cubic, tetragonal). The higher the proportion of the orthorhombic phase in the ferroelectric layer 114, the better the ferroelectric properties. The ferroelectric properties of the doped hafnium dioxide layer also depend on the dopant concentration (lattice strain facilitates the movement of elements when an electric field is applied), the oxygen vacancy concentration (oxygen vacancies can help form a space for elements to move within the lattice when an electric field is applied), and the delicate balance between the dopant and oxygen concentration.

[0019] Various embodiments of the present disclosure provide a method for forming a doped hafnium dioxide layer having a high proportion of the orthorhombic phase, such as higher than about 98% or about 100%, higher than about 90%. The method is described in detail in FIGS. 4 - 8C.

[0020] The first electrode 112 includes a conductive material such as W, TaN, TiN, Ti, Ru, Pt, Ir, or other suitable conductive materials. The second electrode 116 includes a conductive material. In some embodiments, the second electrode 116 includes the same material as the first electrode 112.

[0021] FIG. 2A is a circuit diagram of a FeFET cell 200 according to some embodiments. FIG. 2B is a side cross-sectional view of the FeFET cell 200 of FIG. 2A according to some embodiments. As shown in FIGS. 2A and 2B, the FeFET cell 200 includes a FeFET 204 provided on a substrate 202. The substrate 202 may include the same material as the substrate 102. The FeFET 204 includes a source region 204a and a drain region 204b. The source region 204a and the drain region 204b may each include the same material as the source region 104b and the drain region 104a, respectively. A gate electrode 204c is provided above the substrate 202, and the gate electrode 204c may include the same material as the gate electrode 104c. A ferroelectric layer 204d is provided between the gate electrode 204c and the substrate 202. In some embodiments, an interface layer (not shown) may be provided between the ferroelectric layer 204d and the substrate 202. The ferroelectric layer 204d may include the same material as the ferroelectric layer 114. A dielectric structure 206 is provided above the FeFET 204, and a WL and a BL are provided in the dielectric structure 206. In some embodiments, the WL is electrically connected to the gate electrode 204c, and the BL is electrically connected to the source region 204a.

[0022] In some embodiments, the ferroelectric layer 204d is a doped hafnium dioxide layer. Similar to the ferroelectric layer 114 shown in FIG. 1B, the methods described in FIGS. 4-8C increase the proportion of the rhombohedral phase of the ferroelectric layer 204d, which means improving the ferroelectric properties of the ferroelectric layer 204d.

[0023] FIG. 3 is a side cross-sectional view of a ferroelectric layer 302 formed on a polycrystalline metal layer 304 according to some embodiments. As shown in FIG. 3, the polycrystalline metal layer 304 includes two or more crystal phases 304a, 304b, 304c, and the ferroelectric layer 302 formed on the polycrystalline metal layer 304 is also polycrystalline. The ferroelectric layer 302 may include two or more crystal phases 302a, 302b, 302c, 302d, 302e. An annealing process is performed on the ferroelectric layer 302 to increase the proportion of the orthorhombic phase. The ferroelectric layer 302 formed on a polycrystalline metal layer such as the polycrystalline metal layer 304 may have an orthorhombic phase of less than 90%, for example, less than 50% such as about 20% after the annealing process.

[0024] FIG. 4 is a side cross-sectional view of a ferroelectric layer 402 formed on a single-crystalline metal layer 404 according to some embodiments. As shown in FIG. 4, the single-crystalline metal layer 404 includes a single crystal phase, and the ferroelectric layer 402 formed on the single-crystalline metal layer 404 also includes a single crystal phase. In some embodiments, the ferroelectric layer 402 is a doped hafnium dioxide layer, and the lattice constants (or lattice parameters) a and b of the single-crystalline metal layer 404 are substantially the same as the lattice constants a and b of the doped hafnium dioxide layer in the orthorhombic phase. The single-crystalline metal layer 404 may function as a seed layer for the ferroelectric layer 402 to crystallize thereon. When the lattice constants a and b of the single-crystalline metal layer 404 are the same as the lattice constants a and b of the orthorhombic-phase doped hafnium dioxide layer, the ferroelectric layer 402 formed on the single-crystalline metal layer 404 attempts to match the orthorhombic phase. The lattice constant c of the single-crystalline metal layer 404 has little effect on the crystallization of the ferroelectric layer 402 because the lattice constant c relates to dimensions other than the plane serving as a seed. The interface characteristics of the single-crystalline metal layer 404 are more important than the thickness of the single-crystalline metal layer 404.

[0025] In some embodiments, the single-crystalline metal layer 404 has a symmetric crystal structure, and the angle between lattice constants a and b is about 90°. For example, the crystal structure of the single-crystalline metal layer 404 may be cubic, tetragonal, orthorhombic, or other suitable crystal structures. In some embodiments, the crystal structure of the single-crystalline metal layer 404 may be a suitable cubic crystal structure such as simple cubic, body-centered, face-centered, or other suitable structures. The ferroelectric layer 402 deposited on the single-crystalline metal layer 404 attempts to match the cubic-like hafnium dioxide lattice cells of the single-crystalline metal layer 404. A perfect match is not necessary as long as the lattice cells are closer to orthorhombic hafnium dioxide than monoclinic hafnium dioxide. Some degree of mismatch (e.g., up to about 10% such as about 5% to about 10%) between the lattice constants a and b of the single-crystalline metal layer 404 and the lattice constants a and b of the ferroelectric layer 402 is tolerated. For example, when the lattice constants a and b of the single-crystalline metal layer 404 are relatively small, the lattice constant c of the ferroelectric layer 402 tends to be relatively large. When the lattice constants a and b of the single-crystalline metal layer 404 are relatively large, the lattice constant c of the ferroelectric layer 402 tends to be relatively small. The cells of the ferroelectric layer 402 tend to maintain their volume. In both cases, the ferroelectric layer 402 tends to crystallize with lattice constants a and b that match the lattice constants a and b of the single-crystalline metal layer 404. A mismatch greater than about 10% beyond a particular physical thickness (e.g., about 10 nm) of the ferroelectric layer 402 may cause the lattice to relax and the layer to become thin such as less than about 10 nm.

[0026] In some embodiments, the single-crystalline metal layer 404 is a NiAl layer. The NiAl layer has a cubic crystal structure and may be formed by a suitable method such as physical vapor deposition (PVD). The nickel concentration of the NiAl layer may be in the range of about 40 atomic % to about 60 atomic %, such as about 40 atomic % to about 45 atomic %. The nickel content may affect the size and crystallinity of the NiAl crystals. The lower the nickel amount, such as about 40 atomic % to about 45 atomic %, the more favorable the orthorhombic structure alignment. For example, in X-ray crystallographic analysis (XRD), peaks appear around 31 - 32°, which is close to the orthorhombic peak of hafnium dioxide. The peaks are stronger at lower nickel concentrations, such as less than 45 atomic %. NiAl is a cubic crystal with lattice constants a and b equal, such as between about 0.286 nm and about 0.289 nm.

[0027] In some embodiments, the lattice constants a and b of the ferroelectric layer 402 may be multiples of the lattice constants of the single-crystalline metal layer 404, respectively. FIG. 5 shows the crystal structures of the single-crystalline metal layer and the ferroelectric layer of FIG. 4 according to some embodiments. As shown in FIG. 5, the single-crystalline metal layer 404 may be a NiAl layer having a crystal structure 502, and the ferroelectric layer 402 may be a doped hafnium dioxide layer having a crystal structure 504. The lattice constant a of the ferroelectric layer 402 may be a multiple of the lattice constant a' of the single-crystalline metal layer 404. For example, both lattice constants a' and b' of the NiAl layer are about 0.286 nm, and the lattice constants a and b of the ferroelectric layer 402 may be about 0.572 nm, which is about 2 times the lattice constants a' and b'. With lattice constants a and b of about 0.572 nm, the crystal structure of the ferroelectric layer 402 is substantially orthorhombic.

[0028] Referring back to FIG. 4, the ferroelectric layer 402 may be formed by a suitable method such as atomic layer deposition (ALD), physical vapor deposition (PVD), or chemical vapor deposition (CVD). In some embodiments, the ferroelectric layer 402 is formed on the single crystal metal layer 404 by ALD. In some embodiments, the ferroelectric layer 402 has a thickness in the range of about 3 nm to about 20 nm, such as about 5 nm to about 20 nm. In some embodiments, the ferroelectric layer 402 has a thickness greater than about 20 nm or is formed by being processed at a processing temperature of less than about 350 °C, such as about 250 °C to about 300 °C, and an additional annealing process may be performed to increase the proportion of the rhombohedral phase. For example, the annealing process may include heating the ferroelectric layer 402 to a temperature in the range of about 200 °C to about 600 °C for a time of 1 second to 300 seconds in a suitable environment such as oxygen gas, nitrogen gas, or hydrogen gas. In some embodiments, the process of forming the ferroelectric layer 402 may be performed at a rising temperature from about 200 °C to about 600 °C.

[0029] The ferroelectric layer 402 shown in FIG. 4 may have an increased rhombohedral phase, such as a rhombohedral phase exceeding 90%, for example exceeding 98%. In addition, of the 90% rhombohedral phase, 80% of the rhombohedral phase of the ferroelectric layer 402 may be horizontally aligned, which contributes to ferroelectricity. Furthermore, the ferroelectric layer 402 includes crystal domains in the range of about 5 nm to about 20 nm, such as about 10 nm to about 20 nm.

[0030] FIGS. 6A and 6B are side cross-sectional views of a capacitor 600 according to some embodiments. In some embodiments, as shown in FIG. 6A, the capacitor 600 includes the single crystal metal layer 404 as the first electrode and the metal layer 602 as the second electrode, and the ferroelectric layer 402 is provided between the single crystal metal layer 404 and the metal layer 602. In some embodiments, the metal layer 602 may be a single crystal metal layer. The metal of the metal layer 602 may or may not be the same as the metal of the single crystal metal layer 404.

[0031] In some embodiments, as shown in FIG. 6B, capacitor 600 includes single-crystalline metal layer 404 as the first electrode and metal layer 604 as the second electrode, and ferroelectric layer 402 is provided between single-crystalline metal layer 404 and metal layer 604. In some embodiments, metal layer 604 may be a polycrystalline metal layer. The metal of metal layer 604 may or may not be the same as the metal of single-crystalline metal layer 404. Metal layer 602 or metal layer 604 does not affect the crystal structure of ferroelectric layer 402. In some embodiments, an optional annealing process is performed after the formation of metal layer 602 or metal layer 604. Capacitor 600 shown in FIGS. 6A and 6B may be used as capacitor 101 shown in FIGS. 1A and 1B.

[0032] FIGS. 7A-7C depict various stages of forming ferroelectric layer 704 according to some embodiments. As shown in FIG. 7A, ferroelectric layer 704 is deposited on layer 702. Layer 702 may be a metal layer such as first electrode 112 shown in FIG. 1B, or a semiconductor layer such as substrate 202 shown in FIG. 2B. In some embodiments, layer 702 may be single-crystalline metal layer 404 shown in FIG. 4. In some embodiments, layer 702 may be a dielectric layer such as an interface layer. Ferroelectric layer 704 may be a doped hafnium dioxide layer and may be formed by a suitable method such as CVD, ALD, or PVD. Ferroelectric layer 704 includes oxygen vacancies 706. The oxygen vacancies 706 of ferroelectric layer 704 when deposited may range from about 2% to about 5%.

[0033] Next, as shown in FIG. 7B, an ultra-high vacuum (UHV) annealing process is performed to crystallize ferroelectric layer 704 and increase the concentration of oxygen vacancies 706. In some embodiments, the UHV annealing process has a processing temperature in the range of about 20° C. to about 450° C., le -8 torr~le -3 torr such as le -3It is executed at a processing pressure of less than Torr. The UHV annealing process reduces the pressure outside the ferroelectric layer 704, and the oxygen atoms in the ferroelectric layer 704 are detached from the ferroelectric layer 704. The resulting concentration of oxygen vacancies 706 increases from about 5% to about 10%. The removal of oxygen atoms or the formation of additional oxygen vacancies forms a space for the atoms to move within the ferroelectric layer 704, and an increased rhombohedral phase can be obtained under the above-described UHV annealing process conditions as compared with the conventional annealing process. In some embodiments, although the proportion of the rhombohedral phase does not increase, the ferroelectricity is expected to be relatively high because the remaining oxygen atoms in the ferroelectric layer 704 have more room to move as a result of the UHV annealing process.

[0034] After the UHV annealing process, the ferroelectric layer 704 crystallizes with the rhombohedral phase as the main crystal phase. Then, as shown in FIG. 7C, an optional annealing process is performed on the ferroelectric layer 704 to reduce the oxygen vacancies 706 in order to improve the reliability. The annealing process may be performed in an oxygen gas atmosphere at a processing temperature in the range of about 20°C to about 450°C, a processing pressure in the range of about 1 atm to about 20 atm, and a time in the range of about 1 minute to about 5 hours. After crystallization by the UHV annealing process, the crystal phase of the ferroelectric layer 704 is substantially stable, and no phase change should be seen following the optional annealing process. After the optional annealing process, the concentration of the oxygen vacancies 706 is reduced to a level prior to the UHV annealing process, such as about 2% to about 5%. With the reduced concentration of the oxygen vacancies 706, the device reliability is improved.

[0035] The ferroelectric layer 704 formed by the UHV annealing process has improved ferroelectricity as a result of an increased proportion of the rhombohedral phase and / or more space for atoms to move within the ferroelectric layer 704. An optional annealing process further improves device reliability. In some embodiments, the ferroelectric layer 704 may be utilized as the ferroelectric layer 114 within the capacitor 101, and the UHV process and the optional annealing process may be performed prior to the formation of the second electrode 116. In some embodiments, the layer 702 is the first electrode 112 and the ferroelectric layer 704 is the ferroelectric layer 114. In some embodiments, the ferroelectric layer 704 may be utilized as the ferroelectric layer 204d in the FeFET 204, and the UHV process and the optional annealing process may be performed prior to the formation of the gate electrode 204c. In some embodiments, the layer 702 is the substrate 202 (or an interface layer formed on the substrate 202) and the ferroelectric layer 704 is the ferroelectric layer 204d.

[0036] Figures 8A - 8C depict various stages of forming a ferroelectric layer 804 according to some embodiments. As shown in Figure 8A, the ferroelectric layer 804 is deposited on the layer 802. The layer 802 may comprise the same material as the layer 702. The ferroelectric layer 804 may be a doped hafnium dioxide layer and may be formed by a suitable method such as CVD, ALD, or PVD. The ferroelectric layer 804 includes oxygen vacancies 806. The oxygen vacancies 806 in the ferroelectric layer 804 when deposited may range from about 2% to about 5%.

[0037] Next, as shown in FIG. 8B, an ion implantation process 810 is performed on the ferroelectric layer 804 to remove crystallinity from the ferroelectric layer 804 when deposited and to provide an amorphous phase in the ferroelectric layer 804. As described above, in some embodiments, the doped hafnium dioxide layer when deposited may be partially crystallized. The crystal phase of the doped hafnium dioxide layer when deposited is substantially monoclinic, which does not exhibit ferroelectricity. The ion implantation process 810 introduces a dopant 808, which may be different from the dopant of the doped hafnium dioxide layer, into the doped hafnium dioxide layer when deposited to replace elements of the doped hafnium dioxide layer. As a result, the crystallinity of the doped hafnium dioxide layer when deposited is removed. In other words, the crystal structure of the doped hafnium dioxide layer when deposited is disrupted by the dopant 808 from the ion implantation process 810, and the resulting doped hafnium dioxide layer becomes an amorphous layer.

[0038] The ion implantation process 810 may be performed at an ion energy in the range of about 1 keV to about 10 keV. If the ion energy is less than about 1 keV, the monoclinic structure in the doped hafnium dioxide layer when deposited is not disrupted. On the other hand, if the ion energy is greater than about 10 keV, the manufacturing cost increases without significant advantage. The dose amount of the ion implantation process is about 1e 13 / cm 2 ~ about 1e 15 cm 2It may be within the range. The ion implantation process 810 may lead to shallow doping such as about 10 nm or less. In some embodiments, the dopant 808 may be a p-type or n-type dopant such as phosphorus (P), arsenic (As), or boron (B). In some embodiments, the dopant 808 may be gallium (Ga), antimony (Sb), germanium (Ge), silicon (Si), or other suitable dopants. The doped hafnium dioxide layer when deposited already contains a dopant different from the dopant 808 such as zirconium, aluminum, lanthanum, titanium, tantalum, silicon, yttrium, scandium, gadolinium. In some embodiments, the ferroelectric layer 804 contains two different dopants. For example, the first dopant is formed in-situ during the deposition of the doped hafnium dioxide layer, and the second dopant is introduced into the doped hafnium dioxide layer by an ion implantation process performed after the deposition of the doped hafnium dioxide layer.

[0039] Next, as shown in FIG. 8C, an annealing process is performed on the ferroelectric layer 804 to form an orthorhombic phase. The annealing process may be performed at a processing temperature in the range of about 20°C to about 550°C for a time in the range of about 1 second to about 1 hour. The annealing process changes the amorphous phase to a crystalline phase, specifically an orthorhombic phase. Without an ion implantation process to amorphize the monoclinic phase, the ferroelectric layer 804 may contain both the monoclinic phase and the orthorhombic phase after the annealing process. Therefore, by removing the monoclinic phase before performing the annealing process, the resulting ferroelectric layer 804 becomes crystalline and substantially contains the orthorhombic phase.

[0040] In some embodiments, the ferroelectric layer 804 may be utilized as the ferroelectric layer 114 in the capacitor 101, the ion implantation process 810 may be performed before the formation of the second electrode 116, and the annealing process may be performed before or after the formation of the second electrode 116. In some embodiments, the layer 802 is the first electrode 112 and the ferroelectric layer 804 is the ferroelectric layer 114. In some embodiments, the ferroelectric layer 804 may be utilized as the ferroelectric layer 204d in the FeFET 204, the ion implantation process 810 may be performed before the formation of the gate electrode 204c, and the annealing process may be performed before or after the formation of the gate electrode 204c. In some embodiments, the layer 802 is the substrate 202 (or an interface layer formed on the substrate 202) and the ferroelectric layer 804 is the ferroelectric layer 204d.

[0041] Figures 9A - 9G are side cross-sectional views of various manufacturing stages of a semiconductor device substrate 900 according to some embodiments. As shown in Figure 9A, the semiconductor device structure 900 includes a substrate 902 and one or more transistors 904 provided on the substrate 902. The substrate 902 may be the substrate 102, and the transistor 904 may be the same transistor 104 shown in Figure 1B. Each transistor 904 includes a source / drain region 906 and a gate electrode 908 that may be the same as the drain region 104a, the source region 104b, and the gate electrode 104c, respectively. A conductive contact 910 is electrically connected to the source / drain region 906. The conductive contact 910 may be provided in an interlayer dielectric (ILD) layer 912. An interconnect structure 914 is provided above the transistor 904. The interconnect structure 914 may be the dielectric structure 106 shown in Figure 1B. A conductive wiring 916 and a conductive via 918 are formed in the interconnect structure 914. The conductive wiring 916 and the conductive via 918 may be the conductive wiring 110 and the conductive via 108 shown in Figure 1B, respectively.

[0042] Next, as shown in FIG. 9B, a conductive layer 920 is formed on a conductive via 918 electrically connected to one of the source / drain regions 906 of each transistor 904. The conductive layer 920 may include the same material as the first electrode 112 shown in FIG. 1B. In some embodiments, the conductive layer 920 is a single-crystalline metal layer such as the single-crystalline metal layer 404 shown in FIG. 4. Next, as shown in FIG. 9C, a ferroelectric layer 922 is formed on the conductive layer 920. The ferroelectric layer 922 may be the ferroelectric layer 402 shown in FIG. 4. In some embodiments, the ferroelectric layer 922 is the ferroelectric layer 704 shown in FIGS. 7A - 7C, or the ferroelectric layer 804 shown in FIGS. 8A - 8C. Next, as shown in FIG. 9D, a conductive layer 924 is formed on the ferroelectric layer 922. The conductive layer 924 may include the same material as the second electrode 116 shown in FIG. 1B, the metal layer 602 shown in FIG. 6A, or the metal layer 604 shown in FIG. 6B.

[0043] Next, as shown in FIG. 9E, in order to form the capacitor 926, the conductive layers 920, 924 and the ferroelectric layer 922 are patterned. The capacitor 926 may be a FeCAP having improved ferroelectricity as a result of having the ferroelectric layer 922 that can be formed by the process described in FIGS. 4 - 8C. Next, as shown in FIG. 9F, a dielectric layer 928 is formed to incorporate the capacitor 926. The dielectric layer 928 may be an IMD layer and may be part of the interconnect structure 914. The capacitor 926 may be formed in the interconnect structure 914 in a back-end-of-line (BEOL) process. In some embodiments, the capacitor 926 may be formed in a front-end-of-line (FEOL) or middle-of-line (MOL) process. Next, as shown in FIG. 9G, additional processes are performed to complete the interconnect structure 914. At the top of the interconnect structure 914, a plurality of redistribution layers (RDLs) 930 are formed, and contact pads 932 are formed on the RDLs. The semiconductor device structure 900 includes a plurality of FeRAM cells (one transistor 904 and one capacitor 926).

[0044] FIG. 10 is the semiconductor device structure 900 of FIG. 9G according to an alternative embodiment. As shown in FIG. 10, FeRAM cells 950 are formed in the interconnect structure 914. Each FeRAM cell 950 includes a transistor 952 electrically connected to a capacitor 926. Each transistor 952 may be a thin film transistor (TFT) formed in a BEOL process. Each transistor 952 includes a source / drain region 954, a metal oxide layer 956, a gate dielectric layer 958, and a gate electrode 960. The source / drain region 954 may include a conductive material such as a metal or a metal nitride. In some embodiments, the source / drain region 954 includes TiN, TaN, W, or WN. The metal oxide layer 956 serves as the channel region of the TFT. In some embodiments, the metal oxide layer 956 includes a metal oxide semiconductor material such as indium gallium zinc oxide (IGZO), doped zinc oxide, doped indium oxide, doped cadmium, or other suitable metal oxide semiconductor materials. The gate dielectric layer 958 may include the same material as the gate dielectric layer 104d shown in FIG. 1B, and the gate electrode 960 may include the same material as the gate electrode 104c shown in FIG. 1B. The transistor 952 is electrically connected to the capacitor by conductive wiring 916 and a conductive via 918.

[0045] Figs. 11A - 11F are side cross-sectional views of various manufacturing stages of transistor 100 according to some embodiments. As shown in Fig. 11A, an optional interface layer 1104 is formed on substrate 1102, a ferroelectric layer 1106 is formed on interface layer 1104, and a dummy gate 1108 is formed on ferroelectric layer 1106. Substrate 1102 may include the same material as substrate 202 in Fig. 2B, and ferroelectric layer 1106 may include the same material as ferroelectric layer 704 in Figs. 7A - 7C or ferroelectric layer 804 in Figs. 8A - 8C. Dummy gate 1108 may include polycrystalline silicon. Next, as shown in Fig. 11B, ferroelectric layer 1106 and dummy gate 1108 are patterned (interface layer 1104 is omitted). Gate spacers 1110 are formed on the sides of dummy gate 1108 and ferroelectric layer 1106. Next, as shown in Fig. 11C, source / drain regions 1112 are formed on both sides of dummy gate 1108. Source / drain regions 1112 may include the same material as source region 204a and drain region 204b in Fig. 2B. Next, as shown in Fig. 11D, an ILD layer 1114 is formed above source / drain regions 1112. In some embodiments, a contact etch stop layer (CESL) (not shown) is formed on source / drain regions 1112, and ILD layer 1114 is formed on the CESL. Then dummy gate 1108 is removed, and a gate electrode 1116 is formed on ferroelectric layer 1106. Gate electrode 1116 may include the same material as gate electrode 204c in Fig. 2B.

[0046] Next, as shown in FIG. 11E, a conductive contact 1118 is formed in the ILD layer 1114. The conductive contact 1118 is electrically connected to the source / drain region 1112. In some embodiments, a silicide layer (not shown) is formed between the conductive contact 1118 and the source / drain region 1112. In some embodiments, as shown in FIG. 11F, the ferroelectric layer 1106 is removed during the removal of the dummy gate 1108, and another ferroelectric layer 1120 is formed before the formation of the gate electrode 1116. The ferroelectric layer 1120 may include the same material as the ferroelectric layer 704 of FIGS. 7A-7C or the ferroelectric layer 804 of FIGS. 8A-8C. In the embodiment shown in FIG. 11F, the ferroelectric layer 1106 may be a sacrificial layer and may be a high-k dielectric layer that does not exhibit ferroelectricity.

[0047] The transistor 100 is an FeFET including the ferroelectric layer 1106 or the ferroelectric layer 1120. The ferroelectric layer 1106 or the ferroelectric layer 1120 is formed by the process described in FIGS. 7A-7C or FIGS. 8A-8C. The ferroelectricity of the ferroelectric layer 1106 or the ferroelectric layer 1120 is improved, leading to improved device performance and reliability.

[0048] FIG. 12 shows a semiconductor device structure 900 of FIG. 9G according to an alternative embodiment. As shown in FIG. 12, instead of the capacitor 926 in the interconnect structure 914, an FeFET cell 970 is formed in the interconnect structure 914. The FeFET cell 972 includes a source / drain region 974, a ferroelectric layer 976, a metal oxide layer 978, and a gate electrode 980. The source / drain region 974 may include the same material as the source / drain region 954 of FIG. 10. The ferroelectric layer 976 may include the same material as the ferroelectric layer 704 of FIGS. 7A-7C or the ferroelectric layer 804 of FIGS. 8A-8C. The metal oxide layer 978 may include the same material as the metal oxide layer 956 of FIG. 10, and the gate electrode 980 may include the same material as the gate electrode 960. The FeFET 972 may be a TFT.

[0049] FIG. 13 is the semiconductor device structure 900 of FIG. 12 according to an alternative embodiment. As shown in FIG. 13, the FeFET 972 may be substantially identical to the transistor 952 shown in FIG. 10. However, instead of the gate dielectric layer 958, the FeFET 972 includes a ferroelectric layer 982 provided between the metal oxide layer 956 and the gate electrode 960. The ferroelectric layer 982 may include the same material as the ferroelectric layer 402 in FIG. 4, the ferroelectric layer 704 in FIGS. 7A - 7C, or the ferroelectric layer 804 in FIGS. 8A - 8C. In some embodiments, the gate electrode 960 may include the same material as the single - crystal metal layer 404 in FIG. 4. Similar to the transistor 1100, the FeFET 972 includes a ferroelectric layer 976 or a ferroelectric layer 982. The ferroelectric layer 976 or the ferroelectric layer 982 is formed by the process described in FIG. 4, FIGS. 7A - 7C, or FIGS. 8A - 8C. The ferroelectricity of the ferroelectric layer 976 or the ferroelectric layer 982 is improved, leading to improved device performance and reliability.

[0050] The ferroelectric layer formed by the process described in FIG. 4, FIGS. 7A - 7C, or FIGS. 8A - 8C has improved ferroelectricity. The ferroelectric layer may be utilized in FeRAM, FeFET, or other suitable devices.

[0051] The present disclosure provides a ferroelectric layer having improved ferroelectricity. In some embodiments, the ferroelectric layer is formed on a single - crystal metal layer and the ferroelectric layer includes an orthorhombic phase exceeding 90%. In some embodiments, a UHV annealing process or an ion implantation process is performed after depositing the ferroelectric layer to increase the proportion of the orthorhombic phase and / or to increase the in - layer space for atomic movement. Some embodiments achieve advantages. For example, the improved ferroelectricity in the ferroelectric layer leads to improved device performance and reliability.

[0052] One embodiment is a method. The method includes depositing a hafnium dioxide layer doped on a layer, the doped hafnium dioxide layer having a first oxygen vacancy concentration. The method further includes performing an ultra-high vacuum annealing process on the doped hafnium dioxide layer to increase the first oxygen vacancy concentration to a second oxygen vacancy concentration, and performing an oxygen annealing process on the doped hafnium dioxide layer to decrease the second oxygen vacancy concentration.

[0053] Another embodiment is a method. The method includes depositing a hafnium dioxide layer doped on a layer, the doped hafnium dioxide layer being partially crystallized in a first crystal phase. The method further includes performing an ion implantation process on the doped hafnium dioxide layer to amorphize the doped hafnium dioxide layer, and performing an annealing process on the doped hafnium dioxide layer to crystallize the doped hafnium dioxide layer in a second crystal phase.

[0054] A further embodiment is a semiconductor device structure. The structure includes a transistor provided on a substrate, an interconnect structure provided above the transistor, and a ferroelectric capacitor (FeCAP) provided in the interconnect structure. The FeCAP includes a first metal layer, the first metal layer being a single crystal metal layer. The FeCAP further includes a ferroelectric layer provided on the first metal layer, the ferroelectric layer including a rhombohedral phase exceeding 90%. The FeCAP further includes a second metal layer provided on the ferroelectric layer.

[0055] The above has outlined the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that the present disclosure can be easily used as a basis for designing or modifying other processes and structures to perform the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of the present disclosure and that various modifications, replacements, and changes can be made without departing from the spirit and scope of the present disclosure.

Industrial Applicability

[0056] The ferroelectric device and its forming method of the present disclosure can be applied in memory devices and their manufacturing methods.

Explanation of Signs

[0057] 100, 200, 950, 970: FeRAM cell 101, 926: Capacitor 102, 202, 902, 1102: Substrate 104, 904, 952, 1100: Transistor 104a, 204b: Drain region 104b, 204a: Source region 104c, 204c, 908, 960, 980, 1116: Gate electrode 106, 206: Dielectric structure 108: Conductive via 110: Conductive wiring 112: First electrode 114, 204d, 302, 402, 804, 922, 976, 982, 1106, 1120: Ferroelectric layer 116: Second electrode 204, 972: FeFET 304: Polycrystalline metal layer 302a, 302b, 302c, 302d, 304a, 304b, 304c: Crystal phase 404: Single-crystalline metal layer 502, 504: Crystal structure 600: Capacitor 602, 604: Metal layer 702, 802: Layer 706, 806: Oxygen vacancy 808: Dopant 900: Semiconductor device structure 906, 954, 974, 1112: Source / drain region 910, 1118: Conductive contact 914: Interconnection structure 916: Conductive wiring 918: Conductive via 920, 924: Conductive layer 928: Dielectric layer 930: Redistribution layer (RDL) 932: Contact pad 956, 978: Metal oxide layer 958: Gate dielectric layer 1104: Interface layer 1108: dummy gate 1110: Gate spacer 1114: ILD layer BL: Bit line DL: Drive line WL: Word line a, b, c, a’, b’: Lattice constant

Claims

1. Depositing a hafnium dioxide layer doped on a layer, wherein the doped hafnium dioxide layer has a first oxygen vacancy concentration, performing an ultra-high vacuum annealing process on the doped hafnium dioxide layer to increase the first oxygen vacancy concentration to a second oxygen vacancy concentration, and performing an oxygen annealing process to reduce the second oxygen vacancy concentration. A method comprising the steps of.

2. The method according to claim 1, wherein the first oxygen vacancy concentration ranges from about 2% to about 5%.

3. The method according to claim 2, wherein the second oxygen vacancy concentration ranges from about 5% to about 10%.

4. Depositing a hafnium dioxide layer doped with a first dopant and a second dopant on a layer, including introducing a first dopant into the hafnium dioxide layer and depositing the hafnium dioxide layer doped with the first dopant, wherein the hafnium dioxide layer doped with the first dopant is partially crystallized in a first crystal phase, and the first dopant includes zirconium, aluminum, lanthanum, titanium, tantalum, silicon, yttrium, scandium, or gadolinium, performing an ion implantation process on the hafnium dioxide layer doped with the first dopant by introducing a second dopant into the hafnium dioxide layer doped with the first dopant to amorphize the hafnium dioxide layer doped with the first dopant, and the second dopant is different from the first dopant and the second dopant includes phosphorus, arsenic, boron, gallium, antimony, germanium, or silicon, and performing an annealing process on the hafnium dioxide layer doped with the first dopant and the second dopant to crystallize the hafnium dioxide layer doped with the first dopant and the second dopant in a second crystal phase A method comprising the steps of.

5. The method according to claim 4, wherein the first crystal phase is a monoclinic phase and the second crystal phase is an orthorhombic phase.

6. The method according to claim 4, wherein the layer is an interface layer provided on a substrate.

7. Forming a dummy gate on the hafnium dioxide layer doped with the first dopant and the second dopant, Forming a gate spacer on a side portion of the hafnium dioxide layer doped with the dummy gate, the first dopant, and the second dopant; Forming source / drain regions on the substrate; Removing the dummy gate; and Forming a gate electrode on the hafnium dioxide layer doped with the first dopant and the second dopant. The method according to claim 6, further comprising.

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