Nanoscale-aligned three-dimensional stacked integrated circuit

Abstract

To provide a method for fabricating a nanoscale-aligned three-dimensional (3D) stacked integrated circuit.SOLUTION: Pick-and-place strategies are used to stack source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers 201 are stacked in a sequential or parallel fashion. The stacking method may be a face-to-face, face-to-back, back-to-face, or back-to-back fashion. The source wafers stacked in the face-to-back, back-to-face or back-to-back fashion are connected using through-silicon vias (TSVs). Alternatively, source wafers stacked in the face-to-face fashion are connected using inter-layer vias (ILVs).SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] (Cross - Reference to Related Applications) This application claims priority to U.S. Provisional Patent Application No. 62 / 609,891, entitled “Nanoscale - Aligned 3D Stacked Integrated Circuit,” filed on Dec. 22, 2017, which is hereby incorporated by reference in its entirety.

[0002] (Technical Field) The present invention generally relates to semiconductor manufacturing, and more particularly, to nanoscale - aligned three - dimensional (3D) stacked integrated circuits.

Background Art

[0003] Moore's Law is the observation that the number of transistors in a high - density integrated circuit doubles approximately every two years. The two - dimensional (2D) scaling of electronic circuits characterized by Moore's Law has reached its limit in recent times as the feature dimensions approach the atomic scale. For example, the thickness of the high - K capping layer for the 10 nm technology node is close to 0.5 nm, which is smaller than the width of two silicon atoms. The metrology accuracy requirements for multi - patterning technology (MPT) are close to 0.2 nm, which is smaller than the width of one silicon atom.

Summary of the Invention

Problems to be Solved by the Invention

[0004] In light of these and other limitations, 2D scaling and general top - down manufacturing have significant challenges in continuing beyond the 7 nm node.

Means for Solving the Problems

[0005] In one embodiment of the present invention, a method of manufacturing a three-dimensional (3D) system-on-chip (SoC) assembles a layer (k) two-dimensional (2D) die array on a layer (k-1) 2D die array of a layer (k-1) wafer, where 2D dies are disposed on the layer (k-1) wafer and k is a positive integer greater than 1. The 2D die array includes a single 2D die, a single island of 2D dies forming a continuous group of 2D dies, or multiple islands of 2D dies. The method further includes deploying a fluid that enables lubricated relative movement between the layer (k) 2D die array and the layer (k-1) 2D die array, where the fluid enables precise overlay of the layer (k) and layer (k-1) 2D die arrays.

[0006] In another embodiment of the present invention, a method of manufacturing a three-dimensional (3D) system-on-chip (SoC) assembles a layer (k) two-dimensional (2D) die array on a layer (k-1) 2D die array of a layer (k-1) wafer, where 2D dies are disposed on the layer (k-1) wafer and k is a positive integer greater than 1. The 2D die array includes a single 2D die, a single island of 2D dies forming a continuous group of 2D dies, or multiple islands of 2D dies. The method further includes providing a encapsulation layer for protecting respective 2D dies of the layer (k) wafer and the layer (k-1) wafer from an etchant used during a pick-and-place process.

[0007] In another embodiment of the present invention, a method of manufacturing a three-dimensional (3D) system-on-chip (SoC) assembles a layer (k) two-dimensional (2D) die array on a layer (k-1) 2D die array of a layer (k-1) wafer, where 2D dies are disposed on the layer (k-1) wafer and k is a positive integer greater than 1. Further, the 2D die array includes a single 2D die, a single island of 2D dies forming a continuous group of 2D dies, or multiple islands of 2D dies. Further, the 2D die has a thickness of less than 10 micrometers.

[0008] In a further embodiment of the present invention, an electronic design automation (EDA) methodology for designing a three-dimensional (3D) application-specific integrated circuit (ASIC) system-on-chip (SoC) logic circuit includes a combination of software integrated with a two-dimensional (2D) EDA solution, where the software includes a netlist splitting algorithm for splitting a 3D design netlist into 2D modules. The 2D EDA solution is used to perform one or more of synthesis, 3D placement recognition synthesis, placement, clock tree synthesis (CTS), routing, design verification, and sign-off analysis.

[0009] The foregoing has outlined rather generally the features and technical advantages of one or more embodiments of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which may form the subject of the claims of the invention.

[0010] A better understanding of the present invention can be obtained when the following detailed description is considered in conjunction with the following drawings.

Brief Description of the Drawings

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DETAILED DESCRIPTION OF THE INVENTION

[0012] As described in the Background section, two-dimensional (2D) scaling and general top-down fabrication have significant challenges in continuing beyond the 7nm node.

[0013] Embodiments of the present invention address such challenges by scaling in a third (3 rd ) dimension, as described below.

[0014] In one embodiment, the present invention uses a source wafer having a device layer manufactured using a standard 2D semiconductor manufacturing process (described later in connection with FIG. 1), and uses a pick-and-place strategy to stack them (the source wafers) sequentially or in parallel. Such a pick-and-place strategy has been discussed in Sreenivasan et al. (WO2018 / 119451A1) (hereinafter referred to as "Sreenivasan et al."), the entire content of which is incorporated herein by reference. In one embodiment, the stacking is performed in a face-to-face (F2F), face-to-back (F2B), back-to-face (B2F), or back-to-back (B2B) manner. B2F, F2B, and B2B can be connected using, for example, through-silicon vias (TSVs). F2F can be connected using interlayer vias (ILVs).

[0015] Here, a discussion of standard semiconductor processes is considered appropriate.

[0016] As used herein, a "layer-0 source wafer" refers to a fully dense wafer consisting of transistors and interconnects manufactured using a standard 2D manufacturing process. This layer also includes associated alignment marks and forms the starting layer for the final wafer-scale three-dimensional (3D) integrated circuit (IC) stack.

[0017] As used herein, a "layer-k source wafer" refers to a fully arranged wafer consisting of transistors and interconnects manufactured using a standard 2D manufacturing process on a wafer including at least one sacrificial layer such as oxide buried under silicon. This layer also includes associated alignment marks, is assembled on layer "k-1", and is part of the 3D-IC stack. The assembly of this layer may be in one step (where all 2D dies are picked up at once), or may be multiple steps where a single 2D die array or multiple 2D die arrays are picked up from the layer "k" wafer and accurately placed on the layer "k-1" wafer.

[0018] In one embodiment, the assembly is performed to achieve an overlay of sub-50 nm, sub-30 nm, sub-20 nm, sub-10 nm, or sub-5 nm between each 2D die of the layer (k) wafer and the corresponding 2D die of the layer (k-1) wafer.

[0019] Referring to FIG. 1, FIG. 1 shows an exemplary layer-k source wafer 100 that depicts various 2D die arrangements according to one embodiment of the present invention.

[0020] Referring to FIG. 1, the layer-k source wafer 100 includes a 2D die array 101 that is a single 2D die, a 2D die array 102 that is a continuous island of 2D dies, and a 2D die array 103 that is a group of islands.

[0021] As used herein, a "2D die" refers to a single layer of a three-dimensional (3D) system-on-chip (SoC), where the 3D-SoC includes at least two 2D dies that are precisely stacked in a three-dimensional arrangement. These 2D dies are manufactured using standard 2D semiconductor manufacturing processes. In one embodiment, the thickness of the 2D die may be less than 10 micrometers. Wafers thinned using standard wafer thinning processes such as back grinding are expected to remain at a thickness of 15 μm or more due to defects caused by the grinding process. However, 2D dies manufactured using non-grinding processes can be manufactured at a thickness significantly smaller than the current thickness limits.

[0022] As used herein, "2D die array" refers to a single 2D die (see 2D die array 101) or a group of 2D dies, which are collectively moved from their source wafer (e.g., layer - k) and collectively and precisely assembled onto the previous wafer (layer - k - 1) (where k>1). This 2D die array can include a single island of 2D dies (see 2D die array 102) that form an adjacent group. Alternatively, the 2D die array can include multiple islands of 2D dies, where each island of 2D dies forms a continuous group but the islands are not continuous (see 2D die array 103).

[0023] As used herein, "overlay" refers to a vector quantity defined at all points on a wafer. This is the difference between the vector position of a point on the substrate geometry and the vector position of the corresponding point within the overlay pattern. A generally accepted quantifier for the overlay is the (average + 3 sigma) value of the magnitude of the overlay vector.

[0024] As used herein, "alignment" refers to a set of rigid body errors (translation and rotation) between two overlay bodies.

[0025] Referring to FIG. 2, FIG. 2 shows the stacking of a layer - k 2D die array (k>1) onto a 2D die array of layer - 1 according to an embodiment of the present invention.

[0026] As shown in FIG. 2, in one embodiment, layer-1 of the source wafer 201 corresponds to a silicon-on-insulator wafer 202 having three elements 203. In one embodiment, the wafer 202 includes a layered silicon 204 - insulator (sacrificial layer) 205 - silicon 206 substrate. In one embodiment, the element 203, in its most general form, is a "feedstock" consisting of transistor, interconnect, and dielectric layers. Further, in one embodiment, the element 203 can include the silicon layer 204 of the SOI wafer 202 as used herein. It may or may not have any functionality by itself, but can be used to fabricate a working ASIC when assembled together with other elements 203 and optionally additional interconnect and dielectric layers. Further, the high-resolution device layer at the front end with high mask costs will be present inside the element 203. This is to reduce the cost of expensive masks (for the high-resolution device layer) across the manufacture of various ASIC devices.

[0027] In one embodiment, the width of the element 203 corresponds to a 2D die width of several tens of millimeters. In one embodiment, the street width or "scribe width" may range from several hundred nanometers to several tens of micrometers. In one embodiment, such a width corresponds to the boundary 207 of the element 203.

[0028] Each layer of the source wafer shown in FIG. 2, for example, layer-2 ··· layer-n (n is a positive integer), is set in the same manner as layer-1 201. As a result, each of these layers (simply referred to as "layer-k", where k is a positive integer) may generally be referred to as element 201 herein.

[0029] As shown in FIG. 2, the layers of the source wafer are stacked in a weaving pattern (flip, face-up, flip, face-up ···) to form a 3D-IC stack 208, which will be described in more detail below.

[0030] Furthermore, FIG. 2 shows that B2F, F2B, and B2B can be connected using, for example, through-silicon vias (TSVs), and F2F can be connected using interlayer vias (ILVs). Such features will be described in more detail, including the layer-k wafer.

[0031] In one embodiment, the fluid is deployed to enable lubricated relative movement between a layer (k) two-dimensional (2D) array (e.g., 2D array 102) and a layer (k-1) 2D array (e.g., 2D array 102), and the fluid enables precise overlay of the layer (k) and layer (k-1) 2D arrays. In one embodiment, the fluid is a gas, a liquid, or a combination thereof. In one embodiment, such a combination includes heterogeneous gas and liquid portions, or uniformly mixed gas and liquid portions.

[0032] In one embodiment, the first layer 2D array can be on any substrate, but subsequent 2D arrays (which can be pick-and-placed) require an underlying sacrificial layer as shown in FIGS. 3A-3B. As a result, in one embodiment, the layer-k 2D die may require an underlying oxide layer for optimal device functionality (e.g., fully depleted (FD)-SOI and partially depleted (PD)-SOI). This will require another sacrificial layer at a deeper level for pick-and-place. In one embodiment, these are commercially available through Lapis Semiconductor (registered trademark).

[0033] In one embodiment, the 2D die width can range from several tens of micrometers to several tens of millimeters.

[0034] Next, referring to FIGS. 3A-3B, FIGS. 3A-3B show a cross-section of a layer-k SOI wafer having two embedded layers (e.g., an insulator layer and a sacrificial layer that can be composed of silicon oxide) according to an embodiment of the present invention.

[0035] As shown in FIG. 3B, the cross-section of the layer-k SOI wafer 201 shows that the element 203 can be composed of a transistor 301, an interconnect 302, and a dielectric 303. In one embodiment, the element 203 further includes a silicon layer 304. Further, as described above, the layer-k 2D die may require an underlying oxide layer 305 for optimal device performance.

[0036] In one embodiment, as shown in FIG. 3A, the thickness of the 2D die can range from several tens of nanometers to several tens of micrometers.

[0037] Furthermore, in one embodiment, FIG. 3A shows the boundary 207 of the element 203.

[0038] Alternatively, in one embodiment, the layer-k 2D die may not require an underlying oxide, as shown in FIGS. 4A-4B. FIGS. 4A-4B show another cross-section of a layer-k SOI wafer according to an embodiment of the present invention.

[0039] In such an embodiment, the sacrificial layer may need to reside at a deeper level than that found in standard PD-SOI wafers for mechanical stability. These are commercially available through multiple suppliers, for example, ShinEtsu (registered trademark).

[0040] Furthermore, in one embodiment, the sacrificial oxide (for pick-and-place) is at the same depth as that used in standard PD-SOI wafers, as shown in FIGS. 5A-5B. These are commercially available through multiple sources, for example, Soitec (registered trademark).

[0041] FIGS. 5A-5B show a further cross-section of a layer-k SOI wafer according to an embodiment of the present invention.

[0042] As shown in FIGS. 5A-5B, in one embodiment, the thickness of the 2D die is about 100 nanometers or less.

[0043] Discussions on the process and mechanical design concepts of 3D integrated circuits (ICs) are now considered appropriate.

[0044] In one embodiment, the generally applicable assembly sequence is substantially the same as that described by Sreenivasan et al. (WO2018 / 119451A1) (hereinafter referred to as "Sreenivasan et al."), which is hereby incorporated by reference in its entirety. For example, the steps are as follows. That is, 1. etching and encapsulation; 2. bulk etch process (to facilitate subsequent pick and place); 3. 2D die array pickup; 4. alignment of the 2D die array to the product substrate; 5. temporary attachment and bonding; 6. repeat 3-5 until the product wafer is fully assembled.

[0045] In one embodiment, the assembly sequence of the 3D-IC may require some modifications to steps 2, 4, and 5, as discussed below.

[0046] The bulk etching process to facilitate subsequent pick-and-place requires some modification to account for the type of stacking being done (F2F vs F2B vs B2F vs B2B). For B2F and B2B types of stacking, the bulk etch process described by Sreenivasan et al. will be sufficient as there is no need to flip the layer-k wafer. However, for F2F and F2B types of stacking approaches, in addition to bulk etching, a wafer flipping step needs to occur. Further, in F2F type stacking, a peeling step is required to selectively remove the encapsulation layer for face-to-face connection. This can be done in various ways depending on the specific nature of the encapsulation layer used. For example, if the encapsulation layer is composed of Al2O3, timed buffered oxide etching can be used. Alternatively, if the encapsulation layer is composed of chemically vapor deposited (CVD) amorphous carbon, oxygen plasma can be used for stripping. Or, if the encapsulation layer is composed of multiple layers on top of CVD amorphous carbon, e.g., Al2O3, an oxygen plasma step and a buffered oxide etching can be performed sequentially. In one embodiment, the encapsulation layer protects the 2D dies in both the layer-(k) wafer and the layer-(k - 1) wafer from the etchant used during the pick-and-place process. In one embodiment, the encapsulation layer is compatible with existing semiconductor manufacturing technologies such as complementary metal oxide semiconductor (CMOS) and III-V semiconductors (e.g., gallium nitride, gallium arsenide). Two different techniques for flipping and bulk material removal are described below in relation to FIGS. 6, 7A - 7D, 8, and 9A - 9D.

[0047] FIG. 6 is a flowchart of a method for a backgrinding-based approach for inversion and bulk material removal according to an embodiment of the present invention. FIGS. 7A - 7D show cross-sectional views for inversion and bulk material removal using the steps described in FIG. 6 according to an embodiment of the present invention.

[0048] Next, referring to FIG. 6 together with FIGS. 7A to 7D, in step 601, as shown in FIG. 7A, an encapsulation layer (not shown) is peeled off. Further, as illustrated in FIG. 7A, an access hole 701 can be used to speed up the etching process. In one embodiment, the access hole 701 is used for an etchant such as hydrofluoric acid to release a 2D die from the wafer. In one embodiment, the access hole 701 is utilized to generate a conductor enabling a through-silicon via (TSV).

[0049] In step 602, as shown in FIG. 7B, the layer-k wafer 201 is turned over and attached to a glass carrier wafer 702 via a laser debonding adhesive 703 (commercially available).

[0050] In step 603, as shown in FIG. 7C, back grinding of the layer-k wafer 201 is performed.

[0051] In step 604, the sacrificial layer 205 is etched using an acid such as hydrofluoric acid (HF).

[0052] FIG. 8 is a flowchart of a method for a peel-based approach for inversion and bulk material removal according to an embodiment of the present invention. FIGS. 9A to 9E show cross-sectional views for inversion and bulk material removal using the steps described in FIG. 8 according to an embodiment of the present invention.

[0053] Next, referring to FIG. 8 together with FIGS. 9A to 9D, in step 801, a timed HF etching is performed on the sacrificial layer 205 in such a way as to form pyramid pillars (tethers) 901 as shown in FIGS. 9A and 9B. These pyramid-shaped tethers 901 can facilitate the pick-and-place step, as will be described later. Further, as shown in FIG. 9A, an access hole 701 may be used to speed up the etching process.

[0054] In step 802, as shown in FIG. 9C, a encapsulation layer (not shown) is peeled off.

[0055] In step 803, as shown in FIG. 9D, the layer-k wafer 201 is flipped.

[0056] In step 804, the flipped layer-k wafer 201 is attached to the glass carrier wafer 902 via a laser debonding adhesive 903 (commercially available), and as shown in FIG. 9E, the silicon and the sacrificial layers 206 and 205 are peeled off.

[0057] Also, as will be described later, the principle of the present invention provides by aligning the strain control of the picked 2D die array with the product substrate.

[0058] In one embodiment, precise alignment can be achieved based on whether one or more 2D dies are assembled simultaneously, which is different from the method discussed by Sreenivasan et al.

[0059] In the case of multiple 2D dies, the moiré metrology needs to refer to the superstrate rather than the individual 2D dies being picked and placed. This requires alignment marks patterned on the bottom surface of the superstrate. These marks can be patterned on the absolute corners of the superstrate or distributed area-wise. Corresponding marks will be required on the product wafer. A certain amount of strain control of the 2D die can be implemented using thermal actuation. In addition, thermal actuation can be implemented not only for the added degrees of freedom of actuation but also within the wafer chuck. When the superstrate material is not transparent to the wavelength of the light used for measurement (either generally visible or IR), an observation window can be made within the superstrate. Alternatively, the superstrate can be constructed from a transparent material such as commercially available SiC and / or sapphire (Al2O3). The discussion of precise alignment involving multiple 2D dies will be discussed below in relation to FIGS. 10 and 11A - 11B.

[0060] Figure 10 is a flowchart of a method 1000 for overlay and distortion control of a plurality of packed 2D dies according to an embodiment of the present invention. FIGS. 11A - 11B show cross-sectional views for providing overlay and distortion control of a plurality of packed 2D dies using the steps described in FIG. 10 according to an embodiment of the present invention.

[0061] Referring to FIG. 10, in relation to FIGS. 11A - 11B, in step 1001, as the picked 2D die 1101 (picked 2D dies such as 2D die arrays 101, 102, 103) approaches the product wafer 1102, as shown in FIG. 11A, coarse alignment is first performed. FIG. 11A shows a superstrate 1103 having alignment marks 1104 and observation windows 1105.

[0062] In step 1002, fine alignment is performed to align the alignment marks 1104 and observation windows 1105 of the superstrate 1103 with the alignment marks 1106 within the substrate. In one embodiment, thermal actuation via the thermal actuator 1107 can be used to perform a certain amount of distortion control of the 2D die. Additionally, the thermal actuation can be implemented not only for the added degrees of freedom of actuation but also within the wafer chuck 1108.

[0063] For a single 2D die, in addition to the method described above, moiré measurement can be performed using IR - sensitive marks 1201 embedded in the layer - k and layer (k - 1) 2D die 1101 and an IR - transmissive superstrate, as shown in FIGS. 12A - 12B. FIGS. 12A - 12B are diagrams showing overlay and distortion control of a single picked 2D die according to an embodiment of the present invention.

[0064] Next, referring to FIG. 13, FIG. 13 shows that according to one embodiment of the present invention, a silicon through-via (TSV) is made through an access hole that already exists in a pick-and-place 2D die. As shown in FIG. 13, layer -k, layer (k + 1), and layer (k + 2) are arranged such that layer (k + 1) is inverted and layer (k + 2) is face-up. As further shown in FIG. 13, the silicon through-via is manufactured through the field access hole 701.

[0065] The required TSV density can be as high as 10,000 / mm in applications such as static random access memory (SRAM) stacking. At this level of TSV density, the diameter of the TSV can be about 20 nm to 80 nm. Some or all of these TSVs can potentially be routed through the access holes 701 that already exist within the 2D die.

[0066] Now referring to FIGS. 14A - 14C, FIGS. 14A - 14C show an exemplary process for temporary attachment and bonding according to an embodiment of the present invention.

[0067] In one embodiment, bonding can be performed after temporary attachment. In one embodiment, a dynamic air cushion based on a "slow landing" approach can be used. Such systems have conventionally been used in high-precision air bearing stages, hard disk drive systems, and have been studied for drop skating on solid surfaces. In this approach, a thin layer of UV curable adhesive can first be dispensed at the edge of the layer-0 2D die. The adhesive can be composed of a combination of volatile and non-volatile components, and in limited cases, the adhesive is composed of only non-volatile components. A liquid containing the UV curable adhesive and / or volatile components provides damping, thereby substantially minimizing the vibration displacement between the layer-0 and layer-1 2D dies. As a superstrate, when the layer-1 2D die is placed near the layer-0 die, the flow of air through the pressure hole 1401 can be initiated. This creates a bearing consisting of air or nitrogen (to obtain an inert environment) around the 2D die. The combination knob of the superstrate z force and the bearing flow rate can be used to control "soft landing". At the same time, as the superstrate 1103 is pushed down, coarse alignment correction can be performed. At the same time, a second air cushion 1402 is created between the stacked 2D dies. This second air cushion 1402 can provide additional lubrication between the 2D dies during fine alignment correction.

[0068] Furthermore, the outward flow of air from this air cushion ensures that the volatile components within the adhesive (on the edges) do not contaminate the metal-metal contacts 1403 within the bulk of the 2D die. Additionally, the flow rate of the second air cushion 1402 can be controlled by varying the topography of the 2D die using a superspeed 1103 with a z-direction piezoelectric actuator. Such a system has been previously demonstrated. When the 2D die makes contact, a blanket UV exposure 1404 can be performed to cure the adhesive placed on the edges. To further secure the 2D die, surface activation of the metal contacts 1403 can be carried out. Such processes have been previously shown for metal-to-metal bonding involving metals such as copper, tungsten, and aluminum. Surface activation of copper can be achieved using argon ion treatment of the copper surface. In one embodiment, it is assumed that all of the air used in the air bearings described above is semiconductor-grade clean dry air. Alternatively, if nitrogen is used for the bearings, it is also assumed to be of semiconductor grade, clean, and dry. In one embodiment, the surface-activated copper is maintained in an inert environment after the activation process until the bonding step (including transfer from tool-to-tool and processing in all tools). In one embodiment, vacuum holes 1405 may be used to enable a vacuum-based pick-up mechanism.

[0069] Discussions regarding the design electronic design automation (EDA) / computer-aided design (CAD) flow necessary to implement 3D-integrated circuit system-on-chip (SoC) are currently considered appropriate. Typically, a 2D ASIC SoC is composed of billions of transistors optimally placed to meet performance / speed, area, and power specifications. There are commercially available EDA CAD tools that simplify the design process to efficiently design a 2D ASIC SoC, i.e., to meet design specifications with a lower time-to-market turnaround time (TAT). However, such EDA tools for 3D-IC ASIC design do not exist.

[0070] Typical ASIC SoCs are broadly classified into the following segments: namely, logic (CPU, GPU, modem, etc.), memory / cache (static random access memory (SRAM), embedded dynamic random access memory (eDRAM), etc.), third-party IP blocks, analog IP, IO, etc. 3D SoC design aims to implement an SoC with the same functionality while improving performance in terms of reducing footprint, reducing memory access time and latency, higher bandwidth, higher capacity from the perspective of Mbits / mm 2

[0071] ​In this specification, a typical 3D SoC, also referred to as "Nano Precision Aligned 3D Integrated Circuit (N3SI)", includes n base transistor layers, where N > 1. In one embodiment, an application-specific integrated circuit (ASIC) system on a chip with logic and memory circuits is designed and manufactured in three dimensions using a sub-50nm overlay pick-and-place method, enabling precise overlay of logic and memory circuits. Each base layer can have m metal layers, where m ≧ 1 and can vary for each base layer. The base layers within the 3D stack can be arranged relative to each other in any of the following configurations, i.e., face-to-face, face-to-back, back-to-back, etc. Connections between different base layers can be made using interlayer vias (ILVs) when the base layers are in a face-to-face configuration, or nano-scale through-silicon vias (nano-TSVs) when in a face-to-back or back-to-back configuration. The 3D SoC can be designed using any combination of the following design approaches, i.e., 2D logic implementation with 3D memory implementation, 3D logic implementation with 2D memory implementation, 3D logic implementation with 3D memory implementation, etc. 3D logic implementation can be performed at the block / partition level or at the flat level. In 3D block-level logic implementation, partitions are synthesized and routed using 2D tools, but different partitions are placed on different base layers. In this approach, only the top-level SoC design needs to be changed, but the block-level design of the 3D SoC remains the same as that of a 2D SoC. Therefore, this approach is easier to implement. In flat-level 3D logic implementation, partitions are also implemented in 3D, i.e., cells within a partition are placed on multiple base layers. 3D logic implementation and 3D memory design implementation will be described below respectively. The area overhead due to TSVs and HF holes can also be optimized by a space optimization algorithm.

[0072] Next, an electronic design automation (EDA) design method for 3D-IC logic implementation will be described. The conventional 2D ASIC EDA flow for logic implementation is shown in FIG. 15 according to an embodiment of the present invention. Synthesis is performed in the front-end design stage, and the back-end design stage performs placement, pre-CTS optimization, clock tree synthesis (CTS), routing and post-routing optimization, sign-off analysis, and design verification.

[0073] The EDA method of the present invention for 3D-IC SoC is also similar to the 2D ASIC flow. This method attempts to reuse most of the existing commercially available 2D EDA tools along with some in-house developed solutions. Such a flow is hereinafter referred to as the "N3SI EDA flow". In the following subsections, the design steps of the N3SI EDA flow will be described.

[0074] Synthesis of 3D-IC SoC The synthesis of 3D-IC SoC utilizes commercially available 2D synthesis tools. In the first pass, the design is synthesized in exactly the same way as it is done for a 2D SoC. Once placement is performed, 3D placement-aware synthesis is performed. In this synthesis pass, the tool synthesizes the cells more optimally because it has 3D placement information to obtain accurate interconnect load and delay. This process flow is also similar to 2D placement-aware synthesis, but the placement information in this case is three-dimensional.

[0075] Placement of 3D-IC SoC In this section, the 3D placement of logic / standard cells will be described. In the method of the present invention, the design netlist is first divided into a plurality of modules such that each module netlist consists of logic cells etc. placed on different layers of the 3D-IC SoC stack. Next, using commercially available 2D EDA tools, the 2D placement of each module within the assigned layer of the 3D stack is performed. Netlist partitioning can be performed using in-house solutions that utilize standard partitioning algorithms such as FM Min-Cut, Min-Flow. The modules generated by the partitioning are composed of input / output ports that can be placed not only at the module periphery but also anywhere within the module. As a result, the software developed in-house uses standard partitioning algorithms to generate the positions of these ports. The plurality of modules transfer signals through these ports. These ports can be connected via interlayer vias (ILVs) or nano-scale through-silicon vias (nano-TSVs). The positions of these ports may be restricted based on the thermal and mechanical stability of the ILVs and TSVs. Once the port positions are determined, the timing budget and the port positions are fed to the 2D placement tool to ensure that the placement of each module is performed independently while simultaneously measuring the overall timing and performance metrics. To guarantee a legal cell placement, placement or routing blocks are formed in the module regions through which the TSVs or HF holes pass. That is, the software developed in-house uses standard partitioning algorithms to generate placement or routing obstacles, such as to avoid DRC problems at the ILV / TSV locations (design rule check).

[0076] CTS for 3D-IC SoC Clock tree synthesis (CTS) for 3D SoCs can be performed using existing 2D EDA placement and routing (P&R) tools. When the design is partitioned and placed in multiple modules, a clock tree can be constructed and optimized separately for each module. However, the challenge of a 3D clock tree is to ensure that there are no violations such as setup, hold, etc., while considering process variations across multiple wafers on which the 3D clock tree can be constructed. There can be multiple ways to solve or prevent this problem. One possible solution is to constrain the placement of launch and capture flops on the same layer, i.e., the launch and capture flops for the data path need to be placed on the same layer. This can be achieved by an in-house netlist partitioning tool. Another solution is to include a high margin to ensure that there are no violations in the worst-case process variation scenario.

[0077] Route of 3D-IC SoC The routing method for 3D-IC SoCs includes 2D routing within each module and routing across multiple modules using ILVs and nano-TSVs. The resistance and capacitance values can be accurately determined, as will be discussed next. The 3D-IC routing method remains the same as 2D routing. The routing of each module can be performed separately using 2D P&R tools. Routing blockages are formed in the areas where ILVs and TSV interconnections are placed to ensure that there are no design rule check (DRC) violations.

[0078] Parasitic extraction of 3D-IC SoC The design methodology for parasitic extraction of 3D SoCs is different from that of 2D ASICs. The resistance and capacitance values can vary significantly depending on the TSVs and ILVs. Commercially available EDA tools cannot perform 3D extraction. However, embodiments of the present invention utilize a 3D extraction flow that uses an existing 2D extractor. In this flow, first, the layout information of each module or layer is streamed out. Next, the layout / route data of all modules is streamed to a layout editor tool such as Virtuoso®. During the streaming-in, the layout of a specific module can be inverted as needed to make it look the same as a 3D SoC stack. Then, an extractor is executed on this layout. The resulting resistance and capacitance values take into account the 3D layout considering the TSVs and ILVs and are expected to be accurate.

[0079] Next, the 3D design implementation of a static random access memory (SRAM) will be described. A typical SRAM includes a bit cell array having word lines and bit lines, sense amplifiers, column and row decoders, a timer circuit, I / O, and other peripheral circuits. There are multiple SRAM configurations such as a butterfly configuration and a single-sided configuration for arranging SRAM design elements. These configurations differ in terms of implementation complexity, access time, latency, etc. FIG. 16 shows a 2D single-sided SRAM configuration according to an embodiment of the present invention. The SRAM configuration includes basic memory design elements such as a bit array of SRAM cells 1601, bit lines 1602, word lines 1603, I / O cells 1604, a timer circuit 1605, sense amplifiers 1606, and a decoder 1607.

[0080] Similar to the 2D SRAM configuration, the 3D SRAM can be designed in multiple configurations according to design needs. 3D eSRAM is also similar to the 3D SRAM methodology and can design a similar eDRAM configuration. One of the possible 3D single-sided SRAM configurations shown in FIG. 17 is a 3D stacked die of a stand-alone SRAM array. FIG. 17 shows a 3D stand-alone SRAM die stack according to an embodiment of the present invention.

[0081] In this 3D SRAM configuration, each layer implements a self-sustainable 2D single-sided SRAM. Data input, power, and control signals are supplied to each 2D SRAM stacked in a 3D configuration, and output data signals are obtained from each layer. By combining the data outputs from all layers, a complete 3D SRAM output is obtained. For example, as shown in FIG. 17, a 32-bit D in data bus signal is divided into four 8-bit data bus signals and supplied to each of the four layers. The data output D out from each layer is composed of 8 bits, and by combining the data outputs D out from the four layers, a 32-bit output signal is obtained.

[0082] One of the other possible 3D single-sided SRAM configurations is the 3D only-bit-cell stacked SRAM shown in FIG. 18 according to an embodiment of the present invention.

[0083] In this type of 3D SRAM configuration, the base layer, i.e., layer-1, includes a bit cell array 1801 having bit lines 1802 and word lines 1803, and control and peripheral circuit elements such as an IO cell 1804, a timer circuit 1805, a sense amplifier 1806, and a decoder 1807. The stacked 3D layers include only a bit cell array, bit lines, and word lines. In one embodiment, the control circuit in the base layer for 3D SRAM is expected to have more column decoders compared to a 2D configuration. Similar to the single-sided SRAM design, other 2D SRAM configurations such as a butterfly can also be realized in 3D.

[0084] In a 3D only-bit-cell style stacked SRAM, there are multiple ways to design according to the design specifications. In one configuration, each layer includes a bit-cell array of the same size as a 2D SRAM. In a 3D SARM, the lengths of bit lines and word lines, bandwidth, footprint, etc. remain the same as those of a 2D SARM, but the memory capacity, i.e., the array bit-cell density, becomes n times. Here, n is the number of layers. A slight modification to this design configuration would be to add more sense amplifiers to increase the memory bandwidth. FIG. 19 shows a vertical bit-line cross-section of a 3D only-bit-cell stacked SRAM according to an embodiment of the present invention.

[0085] As shown in FIG. 19, in this example, a column decoder is not used to select the bit-line layer. However, it is expected that the memory access time will be reduced by a shorter bit-line length that ultimately reduces the time constant RC. Here, R is the resistance and C is the capacitance. A decoder can be added to this design configuration to select the bit lines for a specific layer.

[0086] Another possible 3D only-bit-cell stacked SRAM design configuration reduces the footprint / area while keeping the memory capacity, i.e., the array bit-cell density, the same. In this configuration, the first base layer includes the same control circuit as that used in a 2D SRAM configuration. The footprint of the bit array is typically 70% of the SARM area in a 2D configuration and can be reduced in a 3D configuration. The bit-cell array area can be divided by n, where n (n>1) is the number of bit-cell array layers. In this configuration, the lengths of the bit lines and word lines become smaller, and a column decoder is added. However, in this type of memory configuration, it is predicted that the memory access time will be shortened.

[0087] By using the principles of the present invention, it is now possible to manufacture three-dimensional (3D) stacked integrated circuits. In one embodiment, a pick-and-place strategy is used to stack source wafers having device layers fabricated using standard two-dimensional (2D) semiconductor manufacturing techniques. The source wafers can be stacked sequentially or in parallel. The stacking can be in a face-to-face, face-to-back, back-to-face or back-to-back manner. Source wafers stacked in a face-to-back, back-to-face or back-to-back manner may be connected using through-silicon vias (TSVs). Alternatively, source wafers stacked in a face-to-face manner may be connected using interlayer vias (ILVs).

[0088] The description of various embodiments of the present invention has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein were chosen in order to best explain the principles of the embodiments, the practical application to technologies found in the marketplace, or the technical improvement, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

Claim 1 A method of manufacturing a three-dimensional (3D) system-on-chip (SoC), comprising: assembling a layer (k) two-dimensional (2D) die array on a layer (k-1) 2D die array of a layer (k-1) wafer, wherein 2D dies are disposed on the layer (k-1) wafer, k is a positive integer greater than 1, and the 2D die array includes a single 2D die, a single island of 2D dies forming a continuous group of 2D dies, or a plurality of islands of 2D dies; disposing a fluid that enables lubricated relative movement between the layer (k) 2D die array and the layer (k-1) 2D die array, wherein the fluid enables precise overlay of the layer (k) and layer (k-1) 2D die arrays; the overlay including a difference between a vector position of a point on the layer (k) 2D die array and a vector position of a corresponding point on the layer (k-1) 2D die array; the fluid including one of a gas, a liquid, and combinations thereof, the combination including heterogeneous gas and liquid portions, or a portion of a gas and a liquid homogeneously mixed; the layer (k) 2D die array being held using one or more superstrates during assembly, one of the one or more superstrates having alignment marks patterned on a bottom surface of the one superstrate; A method characterized by the above. Claim 2 The method according to claim 1, wherein assembling the layer (k) 2D die array on the layer (k-1) 2D die array of the layer (k-1) wafer is performed to achieve one of a sub-100 nm overlay, a sub-50 nm overlay, a sub-30 nm overlay, a sub-20 nm overlay, a sub-10 nm overlay, and a sub-5 nm overlay between each 2D die of the layer (k) wafer and a corresponding 2D die of the layer (k-1) wafer. Claim 3 The method according to claim 1, wherein the 2D die includes access holes for an etchant to release the 2D die from the layer (k-1) wafer. Claim 4 The method according to claim 3, further comprising utilizing the access holes to generate conductors enabling through-silicon vias within the 3D SoC. Claim 5 The method according to claim 1, wherein the SoC includes an application specific integrated circuit (ASIC) system, and the ASIC system includes the logic circuit and the memory circuit designed and manufactured in three dimensions (3D) using a pick-and-place method that enables precise overlay of the logic circuit and the memory circuit.

6. The method according to claim 5, wherein the ASIC system further includes n base layers, where n is greater than 1, and one or more of the n base layers are arranged in one or more of face-to-face, face-to-back, and back-to-back.

7. The method according to claim 5, wherein the ASIC system is designed using any one of a two-dimensional (2D) logic implementation with a three-dimensional (3D) memory implementation, a 3D logic implementation with a 2D memory implementation, and a 3D logic implementation with a 3D memory implementation.

8. The method according to claim 5, wherein the ASIC system is used in one or more of a 3D static random access memory (SRAM) configuration, namely, a 3D stand-alone stacked SRAM and a 3D bit-cell-only stacked SRAM.

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