Silicon carbide semiconductor device and method for manufacturing the same

Abstract

To improve performance of a silicon carbide semiconductor device comprising a vertical SiC power MISFET including a trench formed on a top face of an SiC epitaxial wafer.SOLUTION: A silicon carbide semiconductor device comprises: a trench 9 formed on a top face of a semiconductor layer and including a first side face and a second side face which are opposed to each other in a first direction along the top face of the semiconductor layer; a gate electrode 2 formed inside the trench 9 via an insulation film 7; a body layer 5 in contact with the first side face; a current diffusion region 17 in contact with the first side face and the second side face; and a guard region 8 covering a corner of a bottom face of the trench 9 at the side of the first side face and separated from a corner of the bottom face of the trench 9 at the side of the second side face. In a first direction, a film thickness of the insulation film 7 covering the second side face is larger than a film thickness of the insulation film 7 covering the first side face. The current diffusion region 17 is separated from a side face in a second direction, which crosses the first direction in a planar view, and the guard region 8 covers all four corners of the bottom face of the trench 9.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a silicon carbide semiconductor device which is a power semiconductor device, particularly one having a trench structure, and a method for manufacturing the same.

Background Art

[0002] In addition to high breakdown voltage, low on-resistance and low switching loss are required for semiconductor power devices. However, the current mainstream silicon (Si) power devices are approaching their theoretical performance limits. Since silicon carbide (SiC) has approximately one order of magnitude higher breakdown electric field strength than Si, the drift layer that maintains the breakdown voltage can be made approximately 1 / 10 thinner and the impurity concentration can be made approximately 100 times higher, so that the element resistance can be theoretically reduced by three orders of magnitude or more. Also, since the bandgap is approximately three times larger than that of Si, high-temperature operation is possible. SiC semiconductor devices are expected to have performance superior to Si semiconductor devices, and the development of SiC power devices is underway.

[0003] Patent Document 1 (Japanese Patent Application Laid-Open No. 2015-72999) describes a semiconductor device having an n-type substrate made of silicon carbide, an n-type drift layer on the substrate, and a plurality of stripe-shaped trenches formed on the drift layer. Here, it is described that each trench has a gate electrode formed via an insulating film and an n-type current dispersion layer formed on the drift layer and having a higher impurity concentration than the drift layer. The gate electrode constitutes a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and the bottom of the trench is covered with a p-type bottom layer.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] A structure having a trench enables an increase in the channel area and is expected to reduce the on-resistance. However, generally, there is a trade-off relationship between the on-resistance and the breakdown voltage. Also, since a large electric field is applied to the insulating film in the trench, it is important to relax the electric field of the insulating film. As a technique for relaxing the electric field in the insulating film, for example, as described in Patent Document 1 and Patent Document 2, it is effective to cover the bottom of the trench with a p-type layer.

[0006] However, when a p-type layer covering the entire bottom of the trench is formed, it is necessary to ensure a large distance between adjacent trenches, resulting in a large cell pitch. Also, in Patent Document 1, due to the potential of the p-type layer at the bottom of the trench being floating, in order to prevent the gate insulating film from being destroyed by a surge, an additional p-type layer is formed between the trenches. This p-type layer increases the cell pitch and further forms a depletion layer from the p-type layer, increasing the on-resistance.

[0007] Patent Document 2 describes a structure in which the channel is in the vertical direction based on the structure of Patent Document 1 and the bottom of the trench is covered by a p-type bottom layer. However, in the structure of Patent Document 2, when the cell pitch is reduced aiming for a low on-resistance, the trench interval affects the width of the JFET region, resulting in a problem of increased JFET resistance.

[0008] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0009] Among the embodiments disclosed in the present application, the outline of representative ones will be briefly described as follows.

[0010] A silicon carbide semiconductor device according to an embodiment includes a trench formed on an upper surface of a semiconductor layer and having a first side surface and a second side surface facing each other in a first direction along the upper surface of the semiconductor layer, a gate electrode formed inside the trench via an insulating film, a body layer in contact with the first side surface, current diffusion regions in contact with each of the first side surface and the second side surface, and a guard region covering a corner portion on the first side surface side of a bottom surface of the trench and spaced apart from a corner portion on the second side surface side of the bottom surface of the trench. In the first direction, a thickness of the insulating film covering the first side surface is greater than a thickness of the insulating film covering the second side surface. Here, the current diffusion regions are spaced apart from side surfaces in a second direction intersecting in a plan view in the first direction, and the guard region covers all four corner portions of the bottom surface of the trench.

[0011] A method for manufacturing a silicon carbide semiconductor device according to an embodiment includes a step of forming a source region, a body layer, current diffusion regions, and a drift layer in this order from an upper surface side of a semiconductor substrate containing silicon carbide, and forming a guard region in the drift layer, and a step of forming a trench and a gate electrode inside the trench on the upper surface of the semiconductor substrate. The trench has a first side surface and a second side surface facing each other in a first direction along the upper surface of the semiconductor substrate. The current diffusion regions are spaced apart from side surfaces in a second direction intersecting in a plan view in the first direction, and the guard region covers all four corner portions of the bottom surface of the trench. Here, in the step of forming the gate electrode, a gate electrode made of a conductive film on the first side surface side is formed by removing a portion of the conductive film embedded in the trench via an insulating film and facing the second side surface.

Advantages of the Invention

[0012] Among the inventions disclosed in the present application, the effects obtained by representative ones will be briefly described as follows.

[0013] According to the present invention, the performance of the silicon carbide semiconductor device can be improved.

Brief Description of the Drawings

[0014]

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BEST MODE FOR CARRYING OUT THE INVENTION

[0015] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, members having the same function are denoted by the same reference numerals, and repeated explanations thereof are omitted. Further, in the following embodiments, unless particularly necessary, explanations of the same or similar parts are not repeated in principle. Also, in the drawings for explaining the embodiments, in order to make the configuration easier to understand, hatching may be added even in a plan view or a perspective view. Furthermore, in the drawings for explaining the embodiments, in order to make the configuration easier to understand, hatching may be omitted in a cross-sectional view.

[0016] Also, " - " and " + " are symbols indicating the relative impurity concentration of an n-type or p-type conductivity type. For example, "n -- ", "n -", "n", "n + ", "n ++ The concentration of n-type impurities increases in this order. In the following embodiments, n-type corresponds to the first conductivity type and p-type corresponds to the second conductivity type, but the reverse is also possible.

[0017] <Details of areas for improvement> Hereinafter, the room for improvement will be described in detail with reference to FIG. 27. As shown in FIG. 27, in the comparative example, n + On a silicon carbide (SiC) substrate on which a drain region 12 of a n - A drain region 12, a drift layer 4, an n-type current diffusion region 17, a p-type body layer 5, and a source region 6 are formed in this order. ++ A plurality of trenches 9 are formed in a row on the upper surface of a semiconductor substrate consisting of a source region 6 of a silicon carbide type. The bottom of each trench 9 reaches halfway to the depth of the current diffusion region 17, and a guard region 8a is formed in the semiconductor substrate so as to cover the bottom. A gate electrode 2 is formed in the trench 9 via an insulating film 7f, which is a gate insulating film, and the upper surface of the gate electrode 2 is covered with an insulating film 16. A source electrode 1 covering the gate electrode 2 and the insulating film 16 is formed on the semiconductor substrate. The guard regions 8a at the bottoms of adjacent trenches 9 are spaced apart from each other, and a JFET region 13 is formed in the region between the trenches 9. A drain electrode 3 is formed in contact with the lower surface of the drain region 12, that is, the lower surface of the semiconductor substrate. The gate electrode 2, the source region 6, and the drain region 12 constitute a SiC power MISFET (Metal Insulator Semiconductor Field Effect Transistor).

[0018] A structure having a trench as in the comparative example increases the channel area, and a decrease in on-resistance is expected. However, generally, there is a trade-off relationship between on-resistance and breakdown voltage. In particular, when having a JFET region, if the width of the JFET region is narrowed, the breakdown voltage increases while the resistance (JFET resistance) also increases. Therefore, the design of the JFET region is very important. Furthermore, SiC has a wider bandgap and higher breakdown strength than Si, but the electric field applied to the insulating film also increases accordingly. Thus, it is important to relax the electric field in the insulating film. When the electric field in the insulating film is strong, leakage current occurs in the gate insulating film, leading to device operation failures such as a decrease in the gate insulating film lifetime and breakdown of the gate insulating film.

[0019] In the above comparative example, by covering the bottom of the trench 9 with the p-type guard region 8a, the electric field applied to the insulating film 7f is relaxed. However, from the viewpoint of preventing an increase in on-resistance, there must be a predetermined distance between adjacent guard regions 8a. For this reason, when forming a guard region 8a that covers the entire bottom of the trench 9, it is necessary to ensure a large interval between adjacent trenches 9. That is, if adjacent guard regions 8a are brought closer, the width of the JFET region becomes narrower and the resistance (JFET resistance) becomes higher. Therefore, in order to prevent such an increase in resistance, it is necessary to ensure a large cell pitch.

[0020] Also, in the comparative example, due to the potential of the p-type layer at the bottom of the trench 9 being floating, there is a risk that the gate insulating film may be broken by a surge. To prevent this, it is conceivable to form an additional p-type layer between the trenches 9. However, this p-type layer increases the cell pitch, and furthermore, since a depletion layer is formed from the p-type layer, the on-resistance increases.

[0021] As described above, in the SiC power MISFET equipped with a trench, there is room for improvement in achieving both a reduction in on-resistance and ensuring breakdown voltage.

[0022] In addition, in the trench 9 having a rectangular planar shape and extending in a predetermined direction in a plan view, there are a side surface that is a long side and a side surface that is a short side. When the side surface that is the short side of the trench 9 is used as a channel in a plan view, variations occur in the characteristics of the SiC power MISFET. Thus, there is room for improvement in that the location where the channel of the trench 9 is formed should be unified to the side surface that is the long side of the trench 9.

[0023] Further, in a SiC power MISFET provided with a trench gate electrode, an electric field is particularly likely to concentrate on the corner portion of the bottom surface of the trench 9, which is the three-dimensional corner where the side surface on the short side of the trench 9, the side surface on the long side, and the bottom surface meet. Therefore, there is room for improvement in relaxing the electric field at the corner of the trench 9 in order to prevent defects such as dielectric breakdown.

[0024] Therefore, in the embodiment of the present application, a device is provided to solve the above-mentioned room for improvement. Below, the technical idea in the embodiment with this device will be described.

[0025] (Embodiment 1) Hereinafter, a trench-type MOSFET, which is a SiC power MISFET having a side surface in a trench (groove, recess) as a channel region, will be taken as an example, and a silicon carbide semiconductor device will be described with reference to the drawings.

[0026] (Structure of the silicon carbide semiconductor device) The structure of the silicon carbide semiconductor device according to the first embodiment will be described with reference to FIGS. 1 to 6. In FIG. 1, for clarity of the drawing, part of the illustration of the insulating film 7 (gate insulating film and interlayer insulating film) is omitted. FIGS. 1 and 6 simply show a part of the structure of the SiC power MISFET, and FIG. 4 shows a more specific structure of the SiC power MISFET. For this reason, the structures such as the gate electrode 2 are partially different between FIG. 4 and FIGS. 1 and 6. FIG. 4 is a cross-sectional view taken along line A-A of FIG. 3, and FIG. 5 is a cross-sectional view taken along line B-B of FIG. 3.

[0027] As shown in FIGS. 1 and 4, the silicon carbide semiconductor device of the present embodiment has an n-type silicon carbide (SiC) epitaxial substrate (hereinafter referred to as the SiC epitaxial substrate or the semiconductor substrate). The SiC epitaxial substrate (semiconductor substrate) is an n + -type silicon carbide substrate and an n - -type epitaxial layer (semiconductor layer) formed by epitaxial growth on the silicon carbide substrate, and is a laminated substrate composed of these. The epitaxial layer is a semiconductor layer containing SiC. In each figure of the present application, a drift layer 4, which is an n - -type semiconductor region mainly constituting the epitaxial layer, is shown. Below the drift layer 4, a drain region 12 composed of a silicon carbide substrate of an n + -type semiconductor region is shown. That is, in FIGS. 1 and 4 and other cross-sectional views, the portion shown as the drain region 12 is the silicon carbide substrate.

[0028] In FIG. 2, only the source electrode 1 extending in the Y direction, the trenches 9 extending in the X direction and arranged in a plurality in the Y direction, the current diffusion region 17 formed in contact with the side surfaces of each trench in the Y direction, and the gate electrode 2 are shown. Further, in FIG. 3, in addition to those configurations in FIG. 2, a hatched guard region 8 is shown. The guard region 8 and the current diffusion region 17 are formed at an intermediate depth of the semiconductor substrate. In FIGS. 2 and 3, the guard region 8 and the current diffusion region 17 are shown passing through the gate electrode 2, the source electrode 1, etc. The perspective view shown in FIG. 1 shows the structure of the region indicated by the broken line in FIG. 2.

[0029] As shown in Fig. 2, the cell array constituting the silicon carbide semiconductor device of this embodiment has a configuration in which a plurality of unit cells having a predetermined planar layout are arranged in the X direction. However, the unit cells may be arranged in a matrix in the X direction and the Y direction, rather than being arranged only in the X direction. For example, one unit cell is formed in a half region on one source electrode 1 side of the region between the centers of two adjacent source electrodes 1 in the X direction. In other words, a plurality of unit cells are arranged while being inverted in a line symmetrical manner in the X direction in a plan view.

[0030] The X direction and the Y direction shown in FIG. 2 are directions along the upper surface (main surface) of the semiconductor substrate. That is, the X direction and the Y direction are directions along the upper surface of the semiconductor layer and the upper surface of the silicon carbide substrate. The X direction and the Y direction are orthogonal to each other in a plan view. The Y direction corresponds to the first direction, and the X direction corresponds to the second direction.

[0031] One unit cell is made up of n ++ The semiconductor substrate has a source region 6 (see FIG. 2) which is a type semiconductor region, and a trench 9 formed in the upper surface of the semiconductor substrate in contact with the source region 6 in a plan view. The source region 6 formed in the upper surface of the semiconductor substrate is not shown in FIG. 2. The source region 6 is formed in a region other than the region in which the trench 9 is formed in a plan view.

[0032] The trenches 9 are formed in a matrix in the Y and X directions. Specifically, in one unit cell, a plurality of trenches 9 are arranged in the Y direction in a region adjacent to the source electrode 1 in the X direction. The shape of the trench 9 in a plan view is, for example, rectangular, and the upper ends of all side surfaces (four sides) of the trench 9 in a plan view are in contact with the source region 6. Note that the shapes of the gate insulating film and the gate electrode 2 formed in the trench 9 are not shown in FIG. 2 and FIG. 3. In the present application, the gate electrode 2 in the trench 9 may be referred to as a trench gate electrode.

[0033] Trench 9 extends in the X direction here, whereby the channel width of the SiC power MISFET can be easily increased. Such an increase in the channel width is difficult to achieve in a trench-type MOSFET in which the trench gate electrode extends in the Y direction in the same manner as the source electrode 1. In contrast, in the present embodiment, since the trench gate electrodes are arranged to be spaced apart from each other in the Y direction, trench 9 can be extended in the X direction, and the channel width can be easily increased. As a result, the on-resistance of the SiC power MISFET can be reduced.

[0034] Here, a plurality of trenches 9 are arranged in parallel within the trench formation region. Thereby, the channel width can be increased and the loss can be reduced. The trench formation region referred to here is a region in which a plurality of trenches 9 are formed side by side in the Y direction.

[0035] As shown in FIG. 2, the current diffusion region 17 is in contact with the side surface of trench 9 between adjacent trenches 9 in the Y direction and extends along the longitudinal direction (long side direction, X direction) of trench 9. That is, the current diffusion region 17 is in contact with each of the two side surfaces that are the long sides of trench 9 in plan view. In contrast, the current diffusion region 17 is not in contact with the side surface that is the short side of trench 9 in plan view. In other words, the current diffusion region 17 is spaced apart from the side surface that is the short side. That is, the current diffusion region 17 is spaced apart from the end portion of trench 9 in the X direction. Here, the current diffusion region 17 is not in contact with both end portions in the X direction of the side surface that is the long side of trench 9.

[0036] As shown in FIG. 3, in a plan view, among the long sides of the trench 9 that are parallel to each other, in the vicinity of one of the long sides, the trench 9 and the gate electrode 2 overlap. Thus, a trench gate electrode is formed in the region near the long side where the trench 9 and the gate electrode 2 overlap. The guard region 8 overlaps with the region where the trench 9 and the gate electrode 2 overlap, that is, in the plan view, in the vicinity of one of the long sides of the trench 9 that are parallel to each other. That is, the guard region 8 is formed so as to overlap with the trench gate electrode in the plan view. Further, the guard region 8 is not formed on the other long side and its vicinity of the trench 9 that are parallel to each other in the plan view. In other words, the guard region 8 is separated from at least a part of the other long side of the trench 9 that are parallel to each other in the plan view. This is because, as will be described later with reference to FIG. 6, a current flows at a high density in the vicinity of the side surface 9b (see FIG. 6) of the trench 9.

[0037] Also, the region where the source electrode 1 is formed (source contact region) and the trench formation region are arranged parallel to each other. Further, the JFET region 13 (see FIG. 4), which will be described later, is arranged in a direction (X direction) orthogonal to the extending direction (Y direction) of the source electrode 1. Thereby, since each of the source contact region, the trench formation region, and the JFET region 13 can be independently designed, the design flexibility can be improved. In particular, since the JFET region 13 is independent of the source electrode 1 and can be independently designed with respect to the source electrode 1, the pitch of the JFET region 13 can be narrowed and the number of the JFET regions 13 can be increased.

[0038] Here, FIG. 2 shows the direction α along the normal at the interface between the side surface, which is the long side of the trench 9, and the current diffusion region 17, and the direction β in which the source contact region extends. The range of the angle γ formed by the direction α and the direction β is preferably, for example, -30° < γ < 30°. That is, since SiC is hexagonal, the plane orientation changes at 60°, and the characteristics change significantly. Therefore, when |γ| = 30°, since the components of the two plane orientations are mixed into the channel, in order to align the plane orientation of the main channel, it is preferable that the change amount of the normal vector is within 30°. The planar shape of the trench 9 is not actually rectangular, and it is considered that the corners are rounded and it is close to an elliptical shape. Even in such a case, if the range of the angle γ is within -30° < γ < 30°, changes in the characteristics of the SiC power MISFET can be prevented.

[0039] As shown in FIGS. 4 and 5, a drain region 12 is formed in the semiconductor substrate. In the semiconductor substrate, a drift layer 4 is formed in contact with the drain region 12 on the drain region 12. The n-type impurity concentration of the drain region 12 is higher than the n-type impurity concentration of the drift layer 4. In the epitaxial layer, a drift layer 4, a current diffusion region 17, a body layer 5, a source region 6, a guard region 8, a drain region 12, and a JFET region 13 are formed. The source region 6 corresponds to the first semiconductor region, the body layer 5 corresponds to the second semiconductor region, the drift layer 4 corresponds to the third semiconductor region, the drain region 12 corresponds to the fourth semiconductor region. The guard region 8 corresponds to the fifth semiconductor region, the current diffusion region 17 corresponds to the sixth semiconductor region, and the JFET region 13 corresponds to the seventh semiconductor region.

[0040] On the lower surface of the drain region 12, that is, on the lower surface of the semiconductor substrate, a drain electrode 3 is formed in contact therewith. That is, the lower surface of the semiconductor substrate is covered by the drain electrode 3, and the drain electrode 3 is electrically connected to the drain region 12. The drain electrode 3 is made of, for example, a laminated conductor film containing gold (Au). On the upper surface of the semiconductor substrate (the upper surface of the epitaxial layer), a source region 6 is formed over a predetermined depth from the upper surface of the semiconductor substrate. Further, between the source region 6 and the drift layer 4, a body layer 5 which is a p-type semiconductor region is formed in contact with the lower surface of the source region 6. Further, between the body layer 5 and the drift layer 4, a current diffusion region 17 which is an n-type semiconductor region is formed in contact with the lower surface of the body layer 5. The source region 6 has an n-type impurity concentration higher than that of the current diffusion region 17 and is electrically connected to the source electrode 1. The lower surface of the body layer 5 is in contact with the drift layer 4. The current diffusion region 17 has an n-type impurity concentration higher than that of the drift region 4 and lower than that of the source region 6.

[0041] The trench 9 is formed from the upper surface of the semiconductor substrate to an intermediate depth within the drift layer 4, extends in the X direction, and is arranged in a plurality in the Y direction. On each of both side surfaces of the trench 9 in the Y direction, the current diffusion region 17, the body layer 5, and the source region 6 are in contact in this order from the bottom.

[0042] In the trench 9, a gate electrode 2 is embedded via an insulating film 7. However, the film thickness of the insulating film 7 in the trench 9 is not the same on one side surface side and the other side surface side of the trench 9 in the short side direction (Y direction) in plan view. As shown in FIG. 4, the trench 9 has side surfaces 9a and 9b facing each other in the Y direction. The side surface 9a corresponds to the first side surface, and the side surface 9b corresponds to the second side surface. It is considered that the side surface of the trench 9 has a taper, and in that case, the widths of the trench 9 in the X direction and the Y direction are larger on the upper side than on the lower side. For this reason, a line perpendicular to the side surface 9a does not intersect perpendicularly with the side surface 9b, but even in such a case, in the present application, the side surfaces 9a and 9b are described as facing each other.

[0043] Here, a plurality of trenches 9 are arranged side by side without inverting their planar layout in the Y direction. Therefore, among adjacent trenches 9, the side surface 9a of one trench 9 is adjacent to the side surface 9b of the other trench 9. That is, between the side surface 9a of one trench 9 and the side surface 9b of the other adjacent trench 9, no other trench 9, insulating film 7, or gate electrode 2 is interposed. Therefore, in the Y direction, the side surfaces 9a and 9b are alternately arranged.

[0044] The insulating film 7 includes insulating films 7c, 7d, 7e, 10, and 11. The boundary portion between the upper end of the side surface 9a side of the trench 9 and the upper surface of the semiconductor substrate is smoothly connected and is more rounded than the boundary portion between the upper end of the side surface 9b and the upper surface of the semiconductor substrate. The insulating film 10 is adjacent to the side surface 9b in plan view, while being separated from the side surface 9a. The side surface 9a and the upper surface of the semiconductor substrate between the side surface 9a and the insulating film 10 are continuously covered by the insulating film 7d, which is a gate insulating film. An insulating film 11 is formed on the insulating film 10 via the insulating film 7c. The side surface 9a of the trench 9 is covered by the insulating film 7d having a relatively small film thickness, while the side surface 9b is covered by the insulating film 7c having a larger film thickness than the insulating film 7d.

[0045] In the trench 9, the gate electrode 2 is embedded between the insulating films 7c and 7d. Also, a part of the gate electrode 2 is embedded directly above the trench 9 and directly above the semiconductor substrate between the side surface 9a and the insulating film 10, and another part of the gate electrode 2 is formed to cover the upper surface of the insulating film 11. The gate electrode 2 is covered by the insulating film 7e, which is an interlayer film.

[0046] In the trench 9, a thick insulating film 7c is formed between the gate electrode 2 and the side surface 9b, while only a thin insulating film 7d is formed between the gate electrode 2 and the side surface 9a, and the insulating film 7c is not formed. For this reason, as shown in FIG. 6, the film thickness b in the Y direction of the insulating film 7 covering the side surface 9b is larger than the film thickness a in the Y direction of the insulating film 7 covering the side surface 9a, and the gate electrode 2 is formed closer to the side surface 9a side in the trench 9.

[0047] As shown in FIGS. 1 and 5, the source electrode 1 is disposed on the semiconductor substrate without passing through the insulating film 7 and extends in the Y direction between adjacent insulating films 7. The source electrode 1 is connected to the source region 6. That is, the source electrode 1 is electrically connected to the source region 6. The source electrode 1 may be electrically connected to the source region 6 via a silicide layer (not shown).

[0048] As shown in FIGS. 1, 4, and 5, the guard region 8, the current diffusion region 17, and the JFET region 13 extend in the X direction and are arranged in a plurality in the Y direction. That is, each of the guard region 8, the current diffusion region 17, and the JFET region 13 is arranged in a stripe shape in plan view. Therefore, each of the trench 9 whose side surface 9a is in contact with the body layer 5 and the body layer 5 in contact with the trench 9 is formed in a plurality in the Y direction.

[0049] Here, as shown in FIGS. 1 and 3 to 5, in the drift layer 4, a guard region 8 which is a p-type semiconductor region is formed separately from each of the body layer 5 and the drain region 12. The p-type impurity concentration of the guard region 8 is higher than the p-type impurity concentration of the body layer 5. The guard regions 8 are formed one by one in contact with each of the plurality of trenches 9. The guard region 8 in contact with one trench 9 extends in the X direction. The guard region 8 is in contact with the bottom surface and the side surface 9a of the trench 9, and is not in contact with the side surface 9b. Further, the guard region 8 is separated from the bottom surface in the vicinity of the side surface 9b of the bottom surface of the trench 9. That is, the guard region 8 is formed so as to cover the corner portion on the side surface 9a side of the trench 9, and the corner portion on the side surface 9b side is exposed. In other words, the guard region 8 is in contact with a first surface extending over the side surface 9a of the trench 9 and a part of the bottom surface of the trench 9, and is separated from a second surface extending over the side surface 9b of the trench and the other part of the bottom surface of the trench 9.

[0050] Note that the corner portion of the trench 9 referred to here means the vicinity of the boundary including the boundary between the bottom surface and the side surface of the trench 9. Even when the bottom surface and the side surface of the trench 9 are smoothly connected by a curved surface, in the present application, this curved surface portion is called a corner portion. The guard region 8 covering the corner portion of one trench 9 is separated from the other trenches 9. The bottom surface of the trench 9 is located above the bottom surface of the guard region 8 and below the uppermost surface of the guard region 8. Further, in the X direction, the side surface 9a of the trench 9 is located between the side surfaces on both sides of the guard region 8.

[0051] In the drift layer 4, a JFET (Junction Field Effect Transistor) region 13 which is an n-type or n - -type semiconductor region is formed side by side with the guard region 8 in the Y direction. Specifically, below the body layer 5, the JFET region 13 is adjacent to the guard region 8. The JFET region 13 extends in the X direction side by side with the guard region 8 directly below the source electrode 1. The JFET region 13 is a region located between the guard regions 8 adjacent to each other in the Y direction.

[0052] The n-type impurity concentration in the JFET region 13 is equal to or higher than the n-type impurity concentration in the drift layer 4. Further, the n-type impurity concentration in the JFET region 13 is lower than the n-type impurity concentration in the source region 6. The JFET region 13 is a region where depletion layers extend from respective opposing side surfaces of adjacent guard regions 8 when the SiC power MISFET is in the off state, and the current path is closed by contact of these depletion layers with each other.

[0053] FIG. 5 shows a cross section along the X direction, including the source electrode 1, the current diffusion region 17, and the guard region 8. However, among the structures shown in FIG. 5, the structure above the semiconductor substrate, that is, above the source region 6, is a structure deeper in the Y direction than the cross section of the semiconductor substrate, and is a structure in a cross section including the trench 9 shown by a broken line in FIG. 5. That is, in FIG. 5, the trench 9 located deeper than the current diffusion region 17 and not originally shown is indicated by a broken line for its contour, and the gate electrode 2 located directly above the trench is shown. Although not shown in FIG. 5, a thin insulating film 7 is formed between the semiconductor layer including the source region 6 and the gate electrode 2, and the gate electrode 2 and the source region 6 are insulated from each other.

[0054] As shown in FIG. 5, a part of the current diffusion region 17 is formed above the upper end of the guard region 8, and a part of the guard region 8 is formed below the lower end of the current diffusion region 17. The guard region 8 and the current diffusion region 17 overlap the trench 9 in the Y direction. Although not shown, a line-symmetric structure about the right end portion of FIG. 5 is formed on the right side of FIG. 5. Therefore, in the region adjacent to the side surface 9a which is the long side of the trench 9, in the X direction, the p-type semiconductor region (body layer 5 or guard region 8), the current diffusion region 17, and the p-type semiconductor region (body layer 5 or guard region 8) are arranged in this order. In other words, in the region in contact with the trench 9 in the Y direction, in the X direction, the body layer 5 (or guard region 8), the current diffusion region 17, and the body layer 5 (or guard region 8) are arranged in this order. That is, the distance f between the side surface which is the short side of the trench 9 and the current diffusion region 17 in the X direction, that is, the width of the body layer 5, is represented by 0 < f (see FIGS. 2 and 5). This means that the trench 9 is formed so as to straddle the p-type semiconductor region, the current diffusion region 17, and the p-type semiconductor region.

[0055] In this way, by terminating the current diffusion region 17 in contact with the side surface (the side surface in the short side direction of the trench 9) which is the long side of the trench 9 so as not to reach the end of the trench 9 in the X direction, the end of the trench 9 in the X direction, particularly the side surface which is the short side, is separated from the current diffusion region 17. Thereby, only the side surface which is the long side of the trench 9 is used as the channel of the SiC power MISFET, and the flow of current to the side surface which is the short side can be suppressed.

[0056] Also, in the X direction, the distance g between the side surface, which is the short side of the trench 9, and the guard region 8 is represented by 0 < g (see FIGS. 3 and 5). Also, the height of the bottom surface of the trench 9 is higher than the bottom surface of the guard region 8 and lower than the upper surface of the guard region 8. Here, the relationship between the distance g and the distance h, which is the thickness of the insulating film 7(7d) covering the side surface, which is the short side of the trench 9, is represented by g ≧ h. In other words, the distance h is the distance between the side surface of the trench 9 and the gate electrode 2 in the X direction. That is, in the X direction, the shortest distance g from the side surface of the trench 9 to the end portion of the guard region 8 in contact with the trench 9 is greater than or equal to the distance h between the side surface and the gate electrode 2. This means that the corner portion at the lower end of the gate electrode 2 in the trench 9 is covered by the guard region 8.

[0057] As shown in FIG. 6, the film thickness c of the insulating film 7(7a) directly under the gate electrode 2, which is the shortest distance between the bottom surface of the trench 9 and the gate electrode 2, is greater than the film thickness a in the Y direction of the insulating film 7 covering the side surface 9a. Thereby, the electric field applied to the insulating film 7 from the bottom of the trench 9 can be relaxed. The film thickness c is the thickness of the insulating film covering the bottom surface of the trench 9 in the insulating film 7 in the direction perpendicular to the upper surface of the semiconductor substrate. The film thickness c is, for example, 50 to 500 nm.

[0058] Also, in the Y direction, the distance d, which is the shortest distance from the side surface 9b of the trench 9 to the guard region 8 in contact with the trench 9, is greater than the film thickness b. Therefore, the electric field of the insulating film 7 in the vicinity of the corner portion on the side surface 9b side of the trench 9 can be relaxed. The distance d is the distance from the boundary between the side surface 9b and the bottom surface of the trench 9 to the boundary between the bottom surface of the trench 9 and the guard region 8. The distance d is, for example, 100 to 500 nm.

[0059] Also, in the thickness direction of the semiconductor substrate (the direction perpendicular to the upper surface of the semiconductor substrate), the distance e from the upper surface (the uppermost surface) of the guard region 8 to the bottom surface of the trench 9 is larger than the film thickness c. However, the guard region 8 only needs to cover the corner portion on the side surface 9a side of the trench 9. That is, the distance e may be equal to or less than the film thickness c. e>0 means that the guard region 8 covers the corner portion on the side surface 9a side of the trench 9. Thereby, it becomes possible to reduce the electric lines of force from the bottom of the trench 9. If the distance e is larger than the film thickness c, since the corner portion on the side surface 9a side of the gate electrode 2 is covered by the guard region 8, a more remarkable effect of alleviating the electric field concentration at the corner of the gate electrode 2 can be expected. The distance e is, for example, 100 to 1000 nm.

[0060] <Operation of Silicon Carbide Semiconductor Device> Next, with reference to FIG. 6, the operation of the SiC power MISFET of the present embodiment will be described. The SiC power MISFET has at least a drain region 12, a source region 6, a body layer 5, and a gate electrode 2. When the SiC power MISFET is in the on state, as shown in FIG. 6, a channel is formed in the body layer 5 adjacent to the side surface 9a of the trench 9. On the other hand, it is difficult to form a channel in the body layer 5 adjacent to the side surface 9b of the trench 9. This is because the insulating film 7 covering the side surface 9b of the trench 9 is larger than the insulating film 7 covering the side surface 9a. Also, due to the insulating film 7 covering the side surface 9b of the trench 9 being larger than the insulating film 7 covering the side surface 9a, an accumulation layer in which carriers (here, electrons) are accumulated is formed in the drift layer 4 adjacent to the side surface 9b.

[0061] As a result, when the SiC power MISFET is in the on state, the current flowing from the drain region 12 side is likely to flow into the accumulation layer near the side surface 9b of one trench 9 in the drift layer 4 between adjacent trenches 9. In the on state, the current flows through the channel formed in the body layer 5 adjacent to the side surface 9a of the other trench 9. Therefore, as shown by the thick line in FIG. 6, the current flows through the accumulation layer near the side surface 9b of the trench 9 in the drift layer 4 and through the channel formed near the side surface 9a of the other trench 9 in the body layer 5. The density of the current flowing through the channel in the body layer 5 between adjacent trenches 9 is higher than the density of the current flowing in the drift layer 4 between adjacent trenches 9. Therefore, it can be said that the main current path of the SiC power MISFET exists on the side surface 9a side rather than on the side surface 9b side of the trench 9.

[0062] Also, when the SiC power MISFET is in the off state, no channel is formed, so no current flows. However, in order to suppress the minute current between the source and drain during the off state and improve the breakdown voltage, a guard region 8 and a JFET region 13 are provided under the trench 9. That is, by providing the guard region 8, when the SiC power MISFET is in the off state, the depletion layer extending from adjacent guard regions 8 closes in the JFET region 13 between those guard regions 8, so the current path between the source and drain is cut off. That is, the guard region 8 has a role of connecting the depletion layers generated around it between adjacent guard regions 8, thereby realizing suppression of the minute current and improvement of the breakdown voltage. Therefore, even if the impurity concentration of the drift layer 4 is increased for the purpose of reducing the resistance of the element, the breakdown voltage during the off state can be ensured. In addition, the guard region 8 has a role of preventing the electric field from concentrating near the corner of the trench 9 and preventing dielectric breakdown between the epitaxial layer and the gate electrode 2.

[0063] <Method of manufacturing a silicon carbide semiconductor device> Next, a method for manufacturing a silicon carbide semiconductor device according to the present embodiment will be described with reference to FIGS. 7 to 14. The polarities described below may be reversed between p-type and n-type.

[0064] First, as shown in FIG. 7, a silicon carbide substrate (wafer), that is, a SiC bulk substrate, is prepared. The surface orientation of the upper surface of the silicon carbide substrate is an Si plane, a C plane, or another surface orientation, and the off-angle of the upper surface is 4 degrees. The silicon carbide substrate may be a substrate manufactured using the sublimation method, a substrate using the solution method, a substrate using the gas growth method, or a substrate already having an epitaxial layer deposited thereon. Chemical mechanical polishing (CMP) may be performed before the epitaxial growth process described later. The n-type impurity concentration of the silicon carbide substrate is, for example, 1×10 18 cm -3 ~1×10 21 cm -3 , and here, for example, 1×10 18 cm -3 is used. The crystal type of the silicon carbide substrate may be 4H-SiC, 6H, or 3C. Here, it is preferable to use a wafer with an off-angle on the upper surface, but a just substrate may also be used.

[0065] Next, an epitaxial layer is formed on the silicon carbide substrate by an epitaxial growth process. That is, SiH4 and C3H8 are heated at a temperature of 1500 ° C. or higher using H2 as a carrier gas for epitaxial growth. Thereby, an epitaxial layer is formed on the silicon carbide substrate. The impurity concentration and film thickness of the epitaxial layer at this time vary depending on the device to be manufactured. The impurity concentration is, for example, 1×10 14 cm -3 ~1×10 18 cm -3 or so, and the film thickness is, for example, several μm to several tens of μm. Also, before forming the epitaxial layer, a high-concentration buffer layer may be formed in the silicon carbide substrate. The impurity concentration of the buffer layer is about 1×10 18 cm -3 . This epitaxial layer is also called a drift layer 4.

[0066] Next, the process of forming the ion implantation regions will be described. The p-type implanted ions are Al (aluminum) or B (boron). The n-type implanted ions are N (nitrogen) or P (phosphorus).

[0067] From the upper surface of the drift layer 4 to a predetermined depth within the drift layer 4, a p-type body layer, an n-type current diffusion region 17, a p-type guard region 8, a JFET region 13, and an n ++ type source region 6 are each formed by ion implantation. The body layer 5 may be formed by an epitaxial growth method. The source region 6 is in contact with the upper surface (the upper surface of the semiconductor substrate) of the wafer which is a SiC epitaxial substrate.

[0068] The body layer 5 is in contact with the source region 6 and is formed deeper than the source region 6. The current diffusion region 17 is in contact with the body layer 5 and is formed deeper than the body layer 5. A plurality of guard regions 8 are formed side by side in the drift layer 4 deeper than the body layer 5. The current diffusion region 17 and the JFET region 13 are regions connecting the body layer 5 and the drift layer 4. The JFET region 13 is a region sandwiched between adjacent guard regions 8. Instead of performing ion implantation to form the JFET region 13, the region between adjacent guard regions 8 may be regarded as the JFET region 13, but for the purpose of reducing resistance, ion implantation may be performed to form the JFET region 13. Note that in this embodiment, the minimum configuration for the SiC power MISFET to operate has been described, but for example, a structure with additional functions such as a termination region may be fabricated.

[0069] Subsequently, a carbon film which is a cap material for impurity activation annealing is deposited around the semiconductor substrate composed of the silicon carbide substrate and the epitaxial layer. Thereafter, the impurity activation annealing is performed at a temperature of, for example, 1600 to 1800°C. Thereafter, the carbon layer of the cap material is removed by oxygen plasma ashing. This annealing has the effect of preventing roughening of the surface of the semiconductor substrate. After this, in order to obtain a cleaner surface, a thermal oxide film covering the surface of the semiconductor substrate may be formed and then the thermal oxide film may be removed using a diluted hydrofluoric acid solution.

[0070] Next, as shown in FIG. 8, a trench 9 is formed. Here, on the upper surface of the semiconductor substrate, a trench 9 that penetrates the source region 6 and the body layer 5 and has a bottom that fits within the drift layer is formed by etching using the insulating film 10 as a hard mask. The trench 9 has one side surface 9a and the other side surface 9b in the Y direction. Also, the bottom surface on the side surface 9a side of the trench 9 reaches the mid-depth of one guard region 8. On the other hand, the bottom surface on the side surface 9b side of the trench 9 is separated from the guard region 8. After this, a process for cleaning the etched surface may be performed. The process is, for example, forming a thermal oxide film covering the surface of the semiconductor substrate including the surface of the trench 9, and then removing the thermal oxide film using a diluted hydrofluoric acid solution.

[0071] Next, as shown in FIG. 9, for example, using the CVD (Chemical Vapor Deposition) method, the trench 9 is filled, and an insulating film 7c that covers the side surfaces and the upper surface of the insulating film 10 is formed. The insulating film 7c is made of, for example, a silicon oxide film. Here, a deposited oxide film is formed to such an extent that the trench 9 is completely filled. The film thickness of the insulating film 7c is, for example, 100 to 1000 nm.

[0072] Subsequently, an insulating film 11 is formed on the insulating film 7c, for example, using the CVD method. In plan view, the insulating film 11 covers the insulating film 7c on the side surface 9b side within the trench 9 and exposes the insulating film 7c on the side surface 9a side within the trench 9.

[0073] Next, as shown in FIG. 10, anisotropic etching (for example, dry etching) is performed using the insulating film 11 as a mask. As a result, a part of the insulating film 7c is removed, and the side surface 9a and the upper surface of the semiconductor substrate adjacent to the side surface 9a and exposed from the insulating films 10 and 11 are exposed. At this time, by controlling the etching amount, the insulating film 7c covering the bottom surface of the trench 9 is left. Thereby, the film thickness of the gate insulating film at the bottom of the trench 9 can be increased, and electric field relaxation at the bottom of the trench 9 can be realized. Note that the bottom surface of the trench 9 may be exposed by this etching process.

[0074] Next, as shown in FIG. 11, an insulating film 7d is formed, for example, by a CVD method. Here, since the insulating film 7d is formed by a deposition method, actually, the insulating film 7d may cover the insulating films 10, 11, etc. However, in FIG. 11, the insulating film 7d is shown only in the vicinity of the side surface 9a of the trench 9. The insulating film 7d continuously covers the side surface 9a of the trench 9 and the upper surface of the semiconductor substrate adjacent to the side surface 9a and exposed from the insulating films 10, 11. The film thickness of the insulating film 7d is, for example, 10 to 100 nm. The insulating films 7c, 7d, 10, and 11 constitute the insulating film 7. The insulating film 7 covering the bottom surface of the trench 9 has either one or both of the insulating films 7c and 7d.

[0075] Next, as shown in FIG. 12, a first gate electrode formation step is performed. That is, a gate electrode 2 is formed to fill the trench 9. Here, for example, by a CVD method, a conductive film which is an n-type polycrystalline silicon film is formed on the semiconductor substrate with a thickness of, for example, 100 to 300 nm. Then, the conductive film is patterned using photolithography technology and an etching method to form a gate electrode 2 made of the conductive film. What is formed in the first gate electrode formation step is the gate electrode 2 of the portion extending in the X direction in the trench formation region (see FIG. 2).

[0076] Next, as shown in FIG. 13, a second gate electrode formation step is performed. That is, for example, by a CVD method, a conductive film 2a which is an n-type polycrystalline silicon film is formed on the semiconductor substrate. Then, the conductive film 2a is patterned using photolithography technology and an etching method to form a gate electrode 2 made of the conductive film 2a. That is, the conductive film 2a formed in the second gate electrode formation step is integrated with the conductive film formed in the first gate electrode formation step to constitute the gate electrode 2. What is formed in the second gate electrode formation step is the gate electrode 2 of the portion extending in the Y direction in the trench formation region and straddling a plurality of trenches (see FIG. 2). In FIG. 13, the conductive film 2a located deeper than the cross sections shown in FIGS. 7 to 12 is shown.

[0077] Next, as shown in FIG. 14, an insulating film 7e covering the gate electrode 2 and the insulating film 7 is formed on the semiconductor substrate using, for example, the CVD method.

[0078] Subsequently, a connection hole for making contact with the source region 6 is opened in the insulating film 7. That is, by etching the insulating film 7 using the resist pattern formed on the insulating film 7 as a mask, a connection hole (opening) exposing the upper surface of the semiconductor substrate is formed. Next, a metal film for silicide is deposited on the semiconductor substrate, and silicidation is performed by annealing at, for example, 700°C to 1000°C, thereby forming a silicide layer (not shown) in contact with the upper surface of the semiconductor substrate across the upper surface of the source region 6 at the bottom of the connection hole. Thereafter, although not shown, a connection hole for making contact with the gate electrode 2 is opened in the insulating film 7. That is, by etching the insulating film 7 using the resist pattern formed on the insulating film 7 as a mask, a connection hole (opening) exposing the upper surface of the gate electrode 2 is formed.

[0079] Subsequently, a source electrode 1 is formed in the connection hole above the source region 6 of the insulating film 7. Thereafter, the lower surface of the drain region 12 on the lower surface side of the semiconductor substrate is also silicided to form a drain contact, and then a drain electrode 3 is formed. For the metal film for silicide, the source electrode 1, and the drain electrode 3, materials such as Ni (nickel) or Al (aluminum) are used, for example. Thereafter, the entire surface of the semiconductor substrate is covered with a surface protection film made of an insulator for device protection. Thereafter, through the process of wiring to each electrode, the silicon carbide semiconductor device of the present embodiment is completed.

[0080] <Effect of the silicon carbide semiconductor device> In the present embodiment, for the purpose of reducing the on-resistance and relaxing the electric field in the gate insulating film, a gate insulating film having a structure that is asymmetric left and right in cross-section is formed. Here, as shown in FIG. 6, the film thickness b of the insulating film 7 is larger than the film thickness a, and a p-type guard region 8 is formed under the insulating film 7 at the trench corner below the channel formation surface that is the main current conduction path of the trench-type SiC power MISFET.

[0081] In the on-state of the SiC power MISFET, an accumulation layer is formed in the n-type region (here, the drift layer 4) in contact with the side surface 9b, and the current passes through the accumulation layer near the side surface 9b and enters the inversion layer formed in the body layer 5 in contact with the side surface 9a, and flows from the source region 6 to the source electrode 1. Thereby, it is possible to reduce the on-resistance.

[0082] Also, in the off-state, the trench corner in contact with the side surface 9a is protected by the guard region 8, no electric field concentration occurs, and the electric field is relaxed due to the thick insulating film 7 at the trench corner in contact with the side surface 9b. Therefore, the reliability is improved.

[0083] Also, here, the guard region 8 at the bottom of the trench 9 is formed in a small region on one side (the side surface 9a side) of the trench 9, and the guard region 8 is not formed on the other side (the side surface 9b side) of the trench 9. Therefore, compared with the comparative example in which the entire bottom surface of the trench 9 is covered with the guard region 8a (see FIG. 27), the interval between adjacent trenches 9 can be narrowed. Therefore, the cell pitch can be reduced and the on-resistance can be reduced. Therefore, it is possible to achieve both reduction of the on-resistance and ensuring of the breakdown voltage.

[0084] Also, here, a plurality of guard regions 8 are arranged in a stripe shape, and it is easy to supply a potential to each of them. Therefore, since the potential of the guard region 8 does not float, it is not necessary to further form a p-type layer between the trenches 9 for the purpose of preventing the breakdown of the gate insulating film due to a surge. Therefore, an increase in the cell pitch can be prevented.

[0085] Also, on the short-side surface (the surface that is the long side) of the trench 9, in the X direction, the body layer 5 (or the guard region 8) which is a p-type semiconductor region, the current diffusion region 17, and the body layer 5 (or the guard region 8) which is a p-type semiconductor region are formed in sequence. In this way, by terminating the current diffusion region 17 in contact with the long-side surface of the trench 9 so as not to reach the end of the trench 9 in the X direction, the current diffusion region 17 is separated from the X-direction end of the trench 9. Thereby, only the long-side surface of the trench 9 is used as the channel of the SiC power MISFET, and the flow of current through the short-side surface can be suppressed. Therefore, in the SiC power MISFET of the present embodiment, the short-side surface of the trench is not used as the channel, and mainly only the long-side surface can be used as the channel.

[0086] Thereby, in each of the plurality of trenches 9 formed in the semiconductor substrate, the channel formation location can be unified in the plane orientation along the long side, so that variations in the characteristics of the SiC power MISFET can be prevented.

[0087] Also, the relationship between the distance g shown in FIG. 5 and the distance h which is the thickness of the insulating film 7 covering the short-side surface of the trench 9 is represented by g≧h. That is, all the corner portions at the lower end of the gate electrode 2 in the trench 9 are covered by the guard region 8. Also, all the corner portions at the four corners of the bottom surface of the trench 9 are covered by the guard region 8. The corner portions of the trench 9 mentioned here are three-dimensional corner portions that are the boundaries between the short-side surface, the long-side surface, and the bottom surface of the trench 9. Thereby, the corner portions of the trench gate electrode can be protected by the high-concentration guard region 8, and the electric field concentration at the corner portions can be alleviated.

[0088] As described above, in the present embodiment, the above-mentioned room for improvement can be solved, and the performance of the silicon carbide semiconductor device can be improved.

[0089] (Embodiment 2) This embodiment is different from Embodiment 1 in the pattern of the gate electrode that connects between the trench gate electrodes arranged in the Y direction and the manufacturing method of the silicon carbide semiconductor device.

[0090] <Structure of Silicon Carbide Semiconductor Device> FIG. 15 shows a perspective view of the SiC power MISFET of this embodiment. FIGS. 16 and 17 show a plan view of the silicon carbide semiconductor device of this embodiment. Similar to FIGS. 2 and 3, the guard region 8 is not shown in FIG. 16, and the guard region 8 is shown with hatching in FIG. 17. Here, as shown in FIG. 1, the gate electrode 2 extending in the Y direction does not extend across the central portion of the trench 9 in the X direction, but extends in the Y direction directly above each of the both ends of the trench 9 in the X direction. That is, a plurality of gate electrodes formed in a stripe shape side by side in the Y direction in the trench formation region are formed in the vicinity of the source electrode 1 and are connected in parallel by the gate electrode 2 extending in the Y direction. In the region where the gate electrode 2 extending in the Y direction overlaps the trench 9 in plan view, all of them overlap the guard region 8. That is, the gate electrode 2 extending in the Y direction is spaced apart from the region where the trench 9 and the guard region 8 do not overlap in plan view.

[0091] Here, FIG. 16 shows the direction α along the normal line at the interface between the side surface, which is the long side of the trench 9, and the current diffusion region 17, and the direction β in which the source contact region extends. As described in Embodiment 1, if the range of the angle γ formed by the direction α and the direction β is within -30° < γ < 30°, changes in the characteristics of the SiC power MISFET can be prevented.

[0092] FIG. 18 is a cross-sectional view taken along the line C-C of FIG. 17, and FIG. 19 is a cross-sectional view taken along the line D-D of FIG. 17. As shown in FIG. 18, the structure in the semiconductor substrate is substantially the same as that in Embodiment 1, but the structure of the insulating film and the gate electrode on the semiconductor substrate is different from that in Embodiment 1.

[0093] Here, the insulating film 7 includes insulating films 7a, 7b, and 10. The insulating film 7a is a thin film that continuously covers all side surfaces, the bottom surface of the trench 9, and the upper surface of the semiconductor substrate. The gate electrode 2 is formed from within the trench 9 across the semiconductor substrate on the side 9a side (on the source region 6). On the semiconductor substrate (on the source region 6), the gate electrode 2 is formed through a laminated film composed of the insulating films 10 and 7a formed in sequence on the semiconductor substrate. The insulating film 7a covering the side surface 9b and the gate electrode 2 within the trench 9 are spaced apart from each other, and a part of the insulating film 7b is embedded therebetween. Outside the trench 9, that is, the insulating film 7b on the semiconductor substrate is an interlayer insulating film that covers the insulating films 7a, 10, and the gate electrode 2. That is, the gate electrode 2, the insulating films 7a and 7b are all formed from within the trench 9 across the semiconductor substrate.

[0094] Within the trench 9, insulating films 7a and 7b are formed between the gate electrode 2 and the side surface 9b, while only the insulating film 7a is formed between the gate electrode 2 and the side surface 9a, and 7b is not formed. For this reason, as shown in FIG. 6, the film thickness b in the Y direction of the insulating film 7 covering the side surface 9b is larger than the film thickness a in the Y direction of the insulating film 7 covering the side surface 9a, and the gate electrode 2 is formed closer to the side 9a within the trench 9.

[0095] As shown in FIG. 19, here, similar to the first embodiment, in the region in contact with the trench 9 in the Y direction, in the X direction, the body layer 5 (or the guard region 8) which is a p-type semiconductor region, the current diffusion region 17, and the body layer 5 (or the guard region 8) which is a p-type semiconductor region are formed in sequence side by side. That is, in the X direction, the distance f between the side surface which is the short side of the trench 9 and the current diffusion region 17, that is, the width of the body layer 5, is represented by 0 < f (see FIGS. 16 and 19). Thereby, the formation of a channel on the short side of the trench 9 is prevented, and the surface orientation of the channel is aligned with the side surface which is the long side of the trench 9.

[0096] Also, in the X direction, the distance g between the side surface, which is the short side of the trench 9, and the guard region 8 is represented by 0 < g (see FIGS. 17 and 19). Also, the height of the bottom surface of the trench 9 is higher than the bottom surface of the guard region 8 and lower than the upper surface of the guard region 8. Here, the relationship between the distance g and the distance h, which is the thickness of the insulating film 7(7b) covering the side surface that is the short side of the trench 9, is represented by g ≧ h. This means that the corner at the lower end of the gate electrode 2 in the trench 9 is covered by the guard region 8. Thereby, the electric field at the corner of the trench 9 can be relaxed.

[0097] <Method for manufacturing silicon carbide semiconductor device> Next, the method for manufacturing the silicon carbide semiconductor device of the present embodiment will be described with reference to FIGS. 20 to 24.

[0098] First, the same processes as those described with reference to FIGS. 7 and 8 are performed.

[0099] Next, as shown in FIG. 20, an insulating film 7a that constitutes a gate insulating film is formed on the semiconductor substrate. The thickness of the insulating film 7a is, for example, about 10 to 100 nm. The insulating film 7a is composed of, for example, a deposited oxide insulating film. The film thickness of the insulating film 7a formed by the deposition method is larger for the portion covering the bottom surface of the trench 9 than for the portions covering the side surfaces 9a and 9b, respectively.

[0100] Next, as shown in FIG. 21, conductive films 2b and 2c, which are n-type polycrystalline silicon films with a thickness of about 100 to 300 nm, are formed on the semiconductor substrate. Here, the conductive film 2b is deposited by, for example, the CVD method. As a result, the conductive film 2b is embedded in the trench 9 via the insulating film 7a. Subsequently, using photolithography technology and the dry etching method, the conductive film 2b is patterned, thereby exposing a part of the upper surface of the insulating film 7a outside the trench 9. In FIG. 21, in addition to the cross-section of the conductive film 2b, the conductive film 2c, which is made of the same film as the conductive film 2c and is a pattern located deeper than the cross-section shown in FIG. 20, is shown. The conductive film 2c is a pattern extending in the short-side direction of the trench 9 directly above the longitudinal end of the trench 9. In this way, the point that the conductive film (gate electrode) extending in the short-side direction (Y direction) of the trench 9 can be formed in one step (film formation step and processing step) is different from the first embodiment (see FIGS. 12 and 13).

[0101] Next, as shown in FIG. 22, a resist pattern 20 made of a photoresist film is formed on the semiconductor substrate. The resist pattern 20 exposes the conductive film 2b on the side 9b side in the trench 9 and covers the conductive film 2b on the side 9a side in the trench 9 and the conductive film 2c (see FIG. 21) in a plan view.

[0102] Next, as shown in FIG. 23, dry etching (anisotropic etching) is performed using the resist pattern 20 as a mask, and then the resist pattern 20 is removed. Here, the portion of the conductive film 2b facing the side 9b is removed. In this way, the conductive film 2b on the side 9b side in the trench 9 is removed, and the gate electrode 2 made of the conductive film 2b on the side 9a side in the trench 9 is formed. Also, the conductive film 2c (not shown) also constitutes the gate electrode 2.

[0103] Next, as shown in FIG. 24, an insulating film 7b, which is an interlayer film, is formed so as to cover the gate electrode 2. The insulating film 7b is made of, for example, a silicon oxide film and is formed by, for example, CVD method. As a result, the insulating film 7b is embedded in the region where the conductive film 2b in the trench 9 has been removed by the etching process described with reference to FIG. 23. The insulating films 10, 7a, and 7b constitute the insulating film 7.

[0104] Thereafter, the source electrode 1 and the drain electrode 3 are formed in the same manner as the process described with reference to FIG. 14. Thus, the silicon carbide semiconductor device of the present embodiment is completed.

[0105] <Effect of the silicon carbide semiconductor device> Even when the trench is filled with an insulating film after forming a gate electrode with asymmetric left and right in the trench as in the present embodiment, the same effects as those of the first embodiment can be obtained.

[0106] That is, in the present embodiment, for the purpose of reducing the on-resistance and relaxing the electric field in the gate insulating film, a gate insulating film having an asymmetric left and right structure in cross section is formed. Here, as shown in FIG. 6, the film thickness b of the insulating film 7 is larger than the film thickness a, and a p-type guard region 8 is formed under the insulating film 7 at the trench corner below the channel formation surface that is the main current conduction path of the trench-type SiC power MISFET.

[0107] In the on-state of the SiC power MISFET, an accumulation layer is formed in the n-type region (here, the drift layer 4) in contact with the side surface 9b, and the current passes through the accumulation layer near the side surface 9b and enters the inversion layer formed in the body layer 5 in contact with the side surface 9a, and flows from the source region 6 to the source electrode 1. Thereby, it is possible to reduce the on-resistance.

[0108] Also, in the off-state, the trench corner in contact with the side surface 9a is protected by the guard region 8, no electric field concentration occurs, and the trench corner in contact with the side surface 9b has a thick insulating film 7, so the electric field is relaxed. Therefore, the reliability is improved.

[0109] Also, here, the guard region 8 at the bottom of the trench 9 is formed in a small region on one side (side 9a side) of the trench 9, and the guard region 8 is not formed on the other side (side 9b side) of the trench 9. Therefore, compared with the comparative example in which the entire bottom surface of the trench 9 is covered with the guard region 8a (see FIG. 27), the interval between adjacent trenches 9 can be narrowed. Therefore, the cell pitch can be reduced, and the on-resistance can be reduced. Therefore, it is possible to achieve both reduction of the on-resistance and securing of the breakdown voltage.

[0110] Also, here, a plurality of guard regions 8 are arranged in a stripe shape, and it is easy to supply a potential to each of them. Therefore, since the potential of the guard region 8 does not float, it is not necessary to further form a p-type layer between the trenches 9 for the purpose of preventing the gate insulating film from being broken by a surge. Therefore, an increase in the cell pitch can be prevented.

[0111] Also, by terminating the current diffusion region 17 in contact with the side surface which is the long side of the trench 9 so as not to reach the end of the trench 9 in the X direction, the current diffusion region 17 is separated from the end of the trench 9 in the X direction. Thereby, only the side surface which is the long side of the trench 9 is used as the channel of the SiC power MISFET, and the flow of current through the side surface which is the short side can be suppressed. Therefore, in the SiC power MISFET of the present embodiment, the side surface which is the short side of the trench is not used as the channel, and mainly only the side surface which is the long side can be used as the channel.

[0112] Thereby, since the channel formation location can be unified in the plane orientation along the long side in each of the plurality of trenches 9 formed in the semiconductor substrate, variation in the characteristics of the SiC power MISFET can be prevented.

[0113] Also, the relationship between the distance g shown in FIG. 19 and the thickness h of the insulating film 7 covering the side surface which is the short side of the trench 9 is represented by g≧h. That is, all the corner portions at the lower end of the gate electrode 2 in the trench 9 are covered by the guard region 8. Thereby, since the corner portion of the trench gate electrode can be protected by the high-concentration guard region 8, the electric field concentration at the corner portion can be alleviated.

[0114] As described above, in this embodiment, the performance of the silicon carbide semiconductor device can be improved.

[0115] Also, in this embodiment, as described with reference to FIG. 21, a conductive film (gate electrode) extending in the short side direction (Y direction) of the trench 9 can be formed in a single process (film formation process and processing process). That is, in the method of manufacturing a semiconductor device according to this embodiment, as shown in FIG. 2, when attempting to form a pattern of the gate electrode 2 extending in the Y direction directly above the central portion of the trench 9 in the X direction, in the etching process described with reference to FIG. 23, a part of the pattern of the gate electrode 2 extending in the Y direction remains in the trench 9 at the central portion. Since the pattern is formed in the vicinity of the side surface 9b in the trench 9, there will be a gate electrode 2 in the trench 9 that is not covered by the guard region 8. As a result, the electric field is likely to concentrate, and to prevent a decrease in the reliability of the gate insulating film while forming the pattern straddling the central portion of the trench 9, it is necessary to form the gate electrode 2 in two separate formation steps as in the first embodiment.

[0116] In contrast, in this embodiment, the gate electrode 2 that straddles the central portion of the trench 9 in the X direction is not formed. That is, the gate electrode 2 extending in the Y direction and connected to a plurality of trench gate electrodes is formed directly above the end portion of the trench 9 in the X direction. That is, the gate electrode 2 extending in the Y direction is formed at a position overlapping the guard region 8 in plan view. In other words, in plan view, the region where the gate electrode 2 extending in the Y direction and the trench 9 overlap all overlaps with the guard region 8. Therefore, even if the gate electrode 2 is formed on the side surface 9b side in the trench 9, the electric field concentration at the corner portion of the trench 9 can be prevented.

[0117] Therefore, it is not necessary to form the gate electrodes 2 in the plurality of trenches 9 and the gate electrode 2 that connects these gate electrodes 2 in parallel on the semiconductor substrate in separate processes. For this reason, the manufacturing method of the silicon carbide semiconductor device can be simplified, and the manufacturing cost can be reduced.

[0118] (Embodiment 3) On the upper surface of the semiconductor substrate, a potential fixing region may be formed, for example, to supply potentials to the body layer 5 and the guard region 8.

[0119] FIG. 25 shows a plan view of the silicon carbide semiconductor device of the present embodiment, and FIG. 26 shows a cross-sectional view of the silicon carbide semiconductor device of the present embodiment. In FIG. 25, for easy understanding of the figure, the potential fixing region 18 is hatched. The potential fixing region 18 corresponds to the eighth semiconductor region.

[0120] As shown in FIGS. 25 and 26, the source electrode 1 is electrically connected to the potential fixing region 18 which is a p ++ -type semiconductor region formed on the upper surface of the semiconductor substrate. In the Y direction, the source electrode 1 and the potential fixing region 18 are in contact with each other, and the potential fixing region 18 and the trench 9 are in contact with each other on the side surface 9b.

[0121] The lower surface of the potential fixing region 18 is in contact with the body layer 5. The potential fixing region 18 has a p-type impurity concentration higher than that of either the body layer 5 or the guard region 8. Since the body layer 5 is electrically connected to the source electrode 1 via the potential fixing region 18, a source voltage can be applied from the source electrode 1 to the body layer 5. Also, in a region not shown, since the guard region 8 is electrically connected to the source electrode 1 via the potential fixing region 18, a source voltage can be applied from the source electrode 1 to the guard region 8.

[0122] As described above, the invention made by the present inventors has been specifically described based on the embodiments. However, it goes without saying that the present invention is not limited to the above embodiments and can be variously modified without departing from the gist thereof.

[0123] For example, the materials, conductivity types, and manufacturing conditions of each part are not limited to the descriptions of the above-described embodiments, and it goes without saying that many modifications are possible for each. Here, for the sake of explanation, the conductivity types of the semiconductor substrate and the semiconductor film have been described while being fixed, but they are not limited to the conductivity types described in the above-described embodiments. That is, in the above-described Embodiments 1 to 3, the n-type SiC power MISFET has been described, but even in a p-type SiC power MISFET in which the conductivity type of each semiconductor region is inverted, the effects of the above-described Embodiments 1 to 3 can be obtained.

[0124] In addition, Embodiment 3 can be combined with either Embodiment 1 or Embodiment 2.

Explanation of Reference Numerals

[0125] 2 Gate electrode 3 Drain electrode 4 Drift layer 5 Body layer 6 Source region 8 Guard region 7, 7a to 7e Insulating film 9 Trench 9a, 9b Side surface 12 Drain region 13 JFET region 17 Current diffusion region 18 Potential fixing region

Claims

1. A silicon carbide substrate of a first conductivity type; A semiconductor layer formed on the silicon carbide substrate and containing silicon carbide; A first semiconductor region of the first conductivity type formed at an upper part within the semiconductor layer; A second semiconductor region of a second conductivity type different from the first conductivity type, formed from the lower end of the first semiconductor region to a middle depth within the semiconductor layer; A third semiconductor region of the first conductivity type formed within the semiconductor layer below the second semiconductor region; A trench formed from the upper surface of the semiconductor layer to a middle depth of the third semiconductor region, and having a first side surface and a second side surface facing each other in a first direction along the upper surface of the semiconductor layer; A gate electrode formed inside the trench via an insulating film; A fourth semiconductor region of the first conductivity type formed within the silicon carbide substrate; A fifth semiconductor region of the second conductivity type formed within the third semiconductor region below the second semiconductor region; A sixth semiconductor region of the first conductivity type formed between the second semiconductor region and the third semiconductor region within the semiconductor layer; comprising; The first semiconductor region, the gate electrode, the second semiconductor region, and the fourth semiconductor region constitute a field effect transistor; The first side surface is in contact with the second semiconductor region, and in the first direction, the trench and the fifth semiconductor region in contact with the trench are each formed in a plurality and arranged side by side; In the first direction, the first side surface and the second side surface are alternately arranged; The insulating film has a first insulating film covering the first side surface, a second insulating film covering the second side surface, and a third insulating film covering the bottom surface of the trench; In the first direction, the film thickness of the second insulating film is larger than the film thickness of the first insulating film; The fifth semiconductor region is in contact with a first surface extending over the first side surface of the trench and a part of the bottom surface, and is separated from a second surface extending over the second side surface of the trench and another part of the bottom surface; The impurity concentration of the sixth semiconductor region is higher than the impurity concentration of the third semiconductor region and lower than the impurity concentration of the first semiconductor region; The sixth semiconductor region is in contact with the first side surface and the second side surface of the trench, and is separated from a third side surface of the trench in a second direction intersecting the first direction in a plan view; A silicon carbide semiconductor device, wherein the fifth semiconductor region covers all four corner portions of the bottom surface of the trench.

2. In the silicon carbide semiconductor device according to claim 1, a source electrode formed on the semiconductor layer and connected to the first semiconductor region, a seventh semiconductor region of the first conductivity type formed between the fifth semiconductor regions adjacent to each other in the first direction, further comprising: each of the fifth semiconductor region and the seventh semiconductor region extends in the second direction, the source electrode extends in the first direction and is arranged in a plurality and juxtaposed in the second direction, a silicon carbide semiconductor device.

3. In the silicon carbide semiconductor device according to claim 1, the gate electrode has a first portion extending in the second direction on the semiconductor layer and a second portion formed inside each of the plurality of trenches, the plurality of second portions of the gate electrode are connected in parallel by the first portion of the gate electrode, a silicon carbide semiconductor device.

4. In the silicon carbide semiconductor device according to claim 3, the first portion of the gate electrode is connected to each of the plurality of second portions of the gate electrode directly above the end of the trench in the second direction, a silicon carbide semiconductor device.

5. In the silicon carbide semiconductor device according to claim 1, in the second direction, the shortest distance from the third side surface to the end portion of the fifth semiconductor region in contact with the trench is greater than or equal to the distance between the third side surface and the gate electrode, a silicon carbide semiconductor device.

6. In the silicon carbide semiconductor device according to claim 1, further comprising an eighth semiconductor region of the second conductivity type formed in contact with the second side surface at the upper part in the semiconductor layer, the eighth semiconductor region is electrically connected to the second semiconductor region, a silicon carbide semiconductor device.

7. (a) A step of preparing a semiconductor substrate including a silicon carbide substrate of the first conductivity type and a semiconductor layer of the first conductivity type formed on the silicon carbide substrate, containing silicon carbide and having a third semiconductor region of the first conductivity type inside. (b) forming a first semiconductor region of the first conductivity type on the upper surface of the semiconductor layer, forming a second semiconductor region of a second conductivity type different from the first conductivity type from the lower end of the first semiconductor region to a middle depth of the semiconductor layer within the semiconductor layer, forming a sixth semiconductor region of the first conductivity type from the lower end of the second semiconductor region to a middle depth of the semiconductor layer within the semiconductor layer, and forming a plurality of fifth semiconductor regions of the second conductivity type in the third semiconductor region below the second semiconductor region; (c) forming a plurality of trenches having first and second side surfaces facing each other in a first direction along the upper surface of the semiconductor layer from the upper surface of the semiconductor layer to a middle depth of the third semiconductor region; (d) forming a first insulating film covering the side surfaces and the bottom surface of the trench; (e) forming a conductive film on the inside of the trench and on the upper surface of the semiconductor layer via the first insulating film; (f) forming a gate electrode made of the conductive film by removing a portion of the conductive film facing the second side surface; (g) embedding a second insulating film in the region in the trench from which the conductive film was removed in step (f); comprising; the silicon carbide substrate includes a fourth semiconductor region of the first conductivity type inside; the first semiconductor region, the gate electrode, the second semiconductor region, and the fourth semiconductor region constitute a field effect transistor; the first side surface is in contact with the second semiconductor region, and the trenches and the fifth semiconductor regions in contact with the trenches are each formed in a plurality and arranged side by side in the first direction; in the first direction, the first side surface and the second side surface are alternately arranged; the fifth semiconductor region is in contact with a first surface extending from the first side surface of the trench to a part of the bottom surface, and is separated from a second surface extending from the second side surface of the trench to the other part of the bottom surface; the impurity concentration of the sixth semiconductor region is higher than the impurity concentration of the third semiconductor region and lower than the impurity concentration of the first semiconductor region; the sixth semiconductor region is in contact with the first and second side surfaces of the trench and is separated from a third side surface of the trench in a second direction intersecting the first direction in a plan view; the gate electrode has a first portion extending in the second direction on the semiconductor layer and a second portion formed inside each of the plurality of trenches; The plurality of the second portions of the gate electrode are connected in parallel by the first portion of the gate electrode, The first portion of the gate electrode is connected to each of the plurality of the second portions of the gate electrode directly above the end of the trench in the second direction, a method of manufacturing a silicon carbide semiconductor device.

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