Method for manufacturing a semiconductor device

Abstract

Provided is a high-yield method for semiconductor device fabrication. When forming a film of a gate insulator or an insulator in contact with an oxide semiconductor such as an interlayer film in a semiconductor device having the oxide semiconductor on a substrate, the insulator film can be formed without diffusion of hydrogen into the oxide semiconductor by setting constants derived from film forming conditions in predetermined ranges. Specifically, the set values of the film forming power, effective electrode area, film forming pressure, and flow rate of film forming gas including hydrogen in the film forming conditions can be selected as appropriate.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Another aspect of the present invention relates to a semiconductor wafer, a module, and an electronic device.

[0002] In this specification and the like, the semiconductor device generally refers to all devices that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and memory devices are one aspect of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, and electronic devices may be said to have semiconductor devices in some cases.

[0003] Note that one aspect of the present invention is not limited to the above technical field. One aspect of the invention disclosed in this specification and the like relates to an article, a method, or a manufacturing method. Another aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter.

Background Art

[0004] Techniques for constructing transistors using semiconductor thin films formed on a substrate having an insulating surface have attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, but oxide semiconductors are attracting attention as other materials.

[0005] In oxide semiconductors, CAAC (c-axis aligned crystalline) structures and nc (nanocrystalline) structures that are neither single crystals nor amorphous have been found (see Non-Patent Document 1 and Non-Patent Document 2).

[0006] In Non-Patent Document 1 and Non-Patent Document 2, techniques for fabricating transistors using oxide semiconductors having a CAAC structure are disclosed.

Prior Art Documents

Non-Patent Documents

[0007]

Non-Patent Document 1

Non-Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0008] One aspect of the present invention is to provide a semiconductor device with good reliability as one of the problems. Another aspect of the present invention is to provide a semiconductor device having good electrical characteristics as one of the problems. Another aspect of the present invention is to provide a semiconductor device with a large on-current as one of the problems. Another aspect of the present invention is to provide a semiconductor device capable of miniaturization or high integration as one of the problems. Another aspect of the present invention is to provide a semiconductor device with low power consumption as one of the problems.

[0009] Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not necessarily have to solve all of these problems. Note that other problems will become apparent from the descriptions in the specification, drawings, claims, etc., and it is possible to extract these other problems from the descriptions in the specification, drawings, claims, etc.

Means for Solving the Problems

[0010] One aspect of the present invention is a method for manufacturing a semiconductor device in which an oxide semiconductor is formed on a substrate, and an insulator is formed on the oxide semiconductor by a chemical vapor deposition method under conditions satisfying the following formula (1). In the formula, PW [W] is the film-forming power, S [cm 2 is the area of the execution electrode, P [Pa] is the film-forming pressure, and f [sccm] is the flow rate of the film-forming gas of the silane (SiH4) system, respectively.

[0011]

Formula

[0012] One aspect of the present invention is a method for manufacturing a semiconductor device in which an oxide semiconductor is formed on a substrate, and an insulator is formed on the oxide semiconductor by a chemical vapor deposition method under conditions satisfying the following formula (2). In the formula, PW [W] is the film-forming power, S [cm 2 is the area of the execution electrode, P [Pa] is the film-forming pressure, and f [sccm] is the flow rate of the film-forming gas of the silane (SiH4) system, respectively.

[0013]

Formula

[0014] In the above, after forming the oxide semiconductor, a conductor is formed in contact with the oxide semiconductor, and a part of the conductor is removed to expose the oxide semiconductor, and an insulator is formed in the exposed region of the oxide semiconductor. This is a method for manufacturing a semiconductor device.

[0015] In the above, a method for manufacturing a semiconductor device in which a metal oxide film is formed in contact with a conductor.

[0016] In the above, the metal oxide film is a method for manufacturing a semiconductor device that suppresses the diffusion of hydrogen and impurities.

[0017] In the above, the oxide semiconductor is a method for manufacturing a semiconductor device that is an In-Ga-Zn oxide.

Advantages of the Invention

[0018] According to one aspect of the present invention, a semiconductor device with high yield can be manufactured. According to one aspect of the present invention, a semiconductor device can be manufactured at low cost.

[0019] According to one aspect of the present invention, a semiconductor device with good reliability can be provided. Also, according to one aspect of the present invention, a semiconductor device having good electrical characteristics can be provided. Also, according to one aspect of the present invention, a semiconductor device with a large on-current can be provided. Also, according to one aspect of the present invention, a semiconductor device capable of miniaturization or high integration can be provided. Also, according to one aspect of the present invention, a semiconductor device with low power consumption can be provided.

[0020] Note that the description of these effects does not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have all of these effects. Note that other effects will be obvious from the description in the specification, drawings, claims, etc., and it is possible to extract these other effects from the description in the specification, drawings, claims, etc.

Brief Description of the Drawings

[0021] FIG. 1A is a top view of a semiconductor device according to one aspect of the present invention. FIGS. 1B to 1D are cross-sectional views of a semiconductor device according to one aspect of the present invention. FIG. 2A is a top view of a semiconductor device according to one aspect of the present invention. FIGS. 2B to 2D are cross-sectional views of a semiconductor device according to one aspect of the present invention. FIG. 3A is a top view of a semiconductor device according to one aspect of the present invention. FIGS. 3B to 3D are cross-sectional views of a semiconductor device according to one aspect of the present invention. FIG. 4A is a top view of a semiconductor device according to one aspect of the present invention. FIGS. 4B to 4D are cross-sectional views of a semiconductor device according to one aspect of the present invention. FIG. 5A is a top view of a semiconductor device according to one aspect of the present invention. FIGS. 5B to 5D are cross-sectional views of a semiconductor device according to one aspect of the present invention. FIG. 6A is a top view of a semiconductor device according to one embodiment of the present invention. FIGS. 6B to 6D are cross-sectional views of a semiconductor device according to one embodiment of the present invention. FIG. 7A is a top view of a semiconductor device according to one embodiment of the present invention. FIGS. 7B to 7D are cross-sectional views of a semiconductor device according to one embodiment of the present invention. FIG. 8A is a top view of a semiconductor device according to one embodiment of the present invention. FIGS. 8B to 8D are cross-sectional views of a semiconductor device according to one embodiment of the present invention. FIG. 9A is a top view of a semiconductor device according to one embodiment of the present invention. FIGS. 9B to 9D are cross-sectional views of a semiconductor device according to one embodiment of the present invention. FIG. 10A is a top view of a semiconductor device according to one embodiment of the present invention. FIGS. 10B and 10C are cross-sectional views of a semiconductor device according to one embodiment of the present invention. FIG. 11A is a top view of a semiconductor device according to one embodiment of the present invention. FIGS. 11B to 11D are cross-sectional views of a semiconductor device according to one embodiment of the present invention. FIG. 12 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 13 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 14 is a cross-sectional view showing the configuration of a memory device according to one embodiment of the present invention. FIG. 15A is a block diagram showing a configuration example of a memory device according to one embodiment of the present invention, and FIG. 15B is a perspective view. FIGS. 16A to 16H are circuit diagrams showing configuration examples of a memory device according to one embodiment of the present invention. FIG. 17A is a block diagram of a semiconductor device according to one embodiment of the present invention, and FIG. 17B is a schematic diagram. FIGS. 18A to 18E are schematic diagrams of a memory device according to one embodiment of the present invention. FIGS. 19A to 19H are diagrams showing an electronic device according to one embodiment of the present invention. FIG. 20A is a schematic diagram of a sample according to this embodiment, and FIG. 20B is a diagram for explaining the addition concentration of deuterium. FIG. 21A is a schematic diagram of a sample according to this embodiment, and FIG. 21B is a diagram for explaining the state of the upper surface. FIGS. 22A and 22B are diagrams for explaining the state of the upper surface of a sample according to this embodiment. FIG. 23 is a diagram for explaining the film floating ratio of the sample according to this embodiment. FIGS. 24A and 24B are diagrams for explaining the cross section of the sample according to this embodiment.

Mode for Carrying Out the Invention

[0022] Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different modes, and it is easily understood by those skilled in the art that the forms and details can be variously changed without departing from the spirit and its scope. Therefore, the present invention is not construed as being limited to the description content of the following embodiments.

[0023] Also, in the drawings, the size, layer thickness, or region may be exaggerated for clarity. Thus, it is not necessarily limited to that scale. Note that the drawings schematically show ideal examples and are not limited to the shapes or values shown in the drawings. For example, in an actual manufacturing process, layers, resist masks, etc. may unintentionally become thinner due to processes such as etching, but may not be reflected in the drawings for ease of understanding. Also, in the drawings, the same reference numerals are commonly used for the same part or parts having the same function among different drawings, and repeated explanations thereof may be omitted. Also, when referring to the same function, the hatch pattern may be the same and may not be particularly labeled.

[0024] Also, particularly in top views (also referred to as "plan views") and perspective views, etc., for ease of understanding the invention, the description of some components may be omitted. Also, the description of some hidden lines, etc. may be omitted.

[0025] In addition, in this specification and the like, ordinal numbers such as first, second, etc. are used for convenience and do not indicate the process order or the stacking order. Therefore, for example, "the first" can be appropriately replaced with "the second" or "the third" etc. and described. Also, the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify an aspect of the present invention.

[0026] In addition, in this specification and the like, terms indicating arrangements such as "above" and "below" are used for convenience in explaining the positional relationship between components with reference to the drawings. Also, the positional relationship between components appropriately changes according to the direction of depicting each component. Therefore, it is not limited to the terms described in the specification and can be appropriately rephrased according to the situation.

[0027] For example, in this specification and the like, when it is explicitly described that X and Y are connected, it is assumed that the cases where X and Y are electrically connected, where X and Y are functionally connected, and where X and Y are directly connected are disclosed in this specification and the like. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or the text, and those other than the connection relationship shown in the figure or the text are also assumed to be disclosed in the figure or the text. Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0028] In addition, in this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. And it has a region (hereinafter also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to the region where current mainly flows.

[0029] Also, the functions of the source and drain may be interchanged when transistors with different polarities are employed or when the direction of current changes during circuit operation. Therefore, in this specification and the like, the terms "source" and "drain" may be used interchangeably.

[0030] Note that the channel length is, for example, in the top view of the transistor, the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the region where the semiconductor (or the part where current flows in the semiconductor when the transistor is in the on state) and the gate electrode overlap each other, or in the channel formation region. Note that in one transistor, the channel length does not necessarily take the same value in all regions. That is, the channel length of one transistor may not be determined by a single value. Therefore, in this specification, the channel length is taken as any one value, the maximum value, the minimum value, or the average value in the channel formation region.

[0031] The channel width is, for example, in the top view of the transistor, the length of the channel formation region in the direction perpendicular to the channel length direction in the region where the semiconductor (or the part where current flows in the semiconductor when the transistor is in the on state) and the gate electrode overlap each other, or in the channel formation region. Note that in one transistor, the channel width does not necessarily take the same value in all regions. That is, the channel width of one transistor may not be determined by a single value. Therefore, in this specification, the channel width is taken as any one value, the maximum value, the minimum value, or the average value in the channel formation region.

[0032] In this specification and the like, depending on the structure of the transistor, the channel width in the region where the channel is actually formed (hereinafter also referred to as the "effective channel width") may differ from the channel width shown in the top view of the transistor (hereinafter also referred to as the "apparent channel width"). For example, when the gate electrode covers the side surface of the semiconductor, the effective channel width may become larger than the apparent channel width, and the influence may become non-negligible. For example, in a fine transistor in which the gate electrode covers the side surface of the semiconductor, the ratio of the channel formation region formed on the side surface of the semiconductor may increase. In that case, the effective channel width is larger than the apparent channel width.

[0033] In such a case, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, when the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width.

[0034] In this specification, when simply described as the channel width, it may refer to the apparent channel width. Or, in this specification, when simply described as the channel width, it may refer to the effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, etc. can be determined by analyzing a cross-sectional TEM image or the like.

[0035] Note that impurities in a semiconductor refer to, for example, components other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be said to be an impurity. When impurities are contained, for example, the density of defect levels in the semiconductor may increase, or the crystallinity may decrease. When the semiconductor is an oxide semiconductor, examples of impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, transition metals other than the main components of the oxide semiconductor, and for example, hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. Note that water may also function as an impurity. Further, for example, oxygen deficiency may be formed in the oxide semiconductor due to the mixing of impurities.

[0036] Note that in this specification and the like, silicon oxynitride means a substance having a higher oxygen content than nitrogen in its composition. Further, silicon nitride oxide means a substance having a higher nitrogen content than oxygen in its composition.

[0037] Also, in this specification and the like, the term "insulator" can be rephrased as an insulating film or insulating layer. Further, the term "conductor" can be rephrased as a conductive film or conductive layer. Also, the term "semiconductor" can be rephrased as a semiconductor film or semiconductor layer.

[0038] Also, in this specification and the like, "parallel" means a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Further, "substantially parallel" means a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Also, "perpendicular" means a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. Further, "substantially perpendicular" means a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0039] In this specification and the like, a metal oxide is an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS), etc. For example, when a metal oxide is used for the semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when described as an OS transistor, it can be paraphrased as a transistor having a metal oxide or an oxide semiconductor.

[0040] Also, in this specification and the like, normally-off means that when no potential is applied to the gate or when a ground potential is applied to the gate, the drain current per 1 μm channel width flowing through the transistor is 1×10 -20 A or less at room temperature, 1×10 -18 A or less at 85 °C, or 1×10 -16 A or less at 125 °C.

[0041] (Embodiment 1) In this embodiment, an example of a semiconductor device having a transistor 200 according to one aspect of the present invention will be described. The transistor 200 according to one aspect of the present invention is a transistor having an oxide semiconductor in a channel formation region.

[0042] Here, a detailed description of an example of a semiconductor device having a transistor according to one aspect of the present invention will be given below with reference to the drawings.

[0043] <Configuration Example of Semiconductor Device> FIG. 1 is a top view and a cross-sectional view of a semiconductor device having a transistor 200 according to one aspect of the present invention. FIG. 1A is a top view of the semiconductor device. FIGS. 1B and 1C are cross-sectional views of the semiconductor device. Here, FIG. 1B is a cross-sectional view of a portion indicated by a dashed-dotted line A1 - A2 in FIG. 1A. FIG. 1C is a cross-sectional view of a portion indicated by a dashed-dotted line A3 - A4 in FIG. 1A. FIG. 1D is a cross-sectional view of a portion indicated by a dashed-dotted line A5 - A6 in FIG. 1A. Note that in the top view of FIG. 1A, some elements are omitted for clarity of the drawing.

[0044] A semiconductor device according to one aspect of the present invention includes a transistor 200, and insulators 214, 216, 280, 282, and 284 that function as interlayer films. Note that the insulator 280 is provided in contact with at least the oxide 230.

[0045] [Transistor 200] As shown in FIG. 1, the transistor 200 includes a conductor 205 disposed on a substrate (not shown), the conductor 205 being disposed so as to be embedded in the insulator 216, an insulator 222 disposed on the insulator 216 and on the conductor 205, an insulator 224 disposed on the insulator 222, oxides 230 (oxides 230a and 230b) disposed on the insulator 224, an insulator 250 disposed on the oxides 230, conductors 260 (conductors 260a and 260b) disposed on the insulator 250, conductors 240a and 240b in contact with a part of the upper surface of the oxide 230b, an insulator 245a disposed on the conductor 240a, and an insulator 245b disposed on the conductor 240b. Note that the conductors 240a and 240b may be collectively referred to as the conductor 240. Note that the insulators 245a and 245b may be collectively referred to as the insulator 245.

[0046] In addition, for the transistor 200, it is preferable to use a metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as an oxide semiconductor for the oxides 230 (oxides 230a and 230b) including a region where a channel is formed (hereinafter also referred to as a channel formation region).

[0047] As the oxide semiconductor, for example, a metal oxide such as In-M-Zn oxide (element M is selected from one or more of aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc.) may be used. Further, as the oxide semiconductor, In-Ga-Zn oxide, In-Ga oxide, or In-Zn oxide may be used.

[0048] Note that as the oxide semiconductor functioning as the channel formation region, an oxide semiconductor having a band gap of preferably 2 eV or more, more preferably 2.5 eV or more is used. By using an oxide semiconductor having a large band gap in this way, the off-current of the transistor can be reduced.

[0049] Since the transistor 200 using an oxide semiconductor in the channel formation region has an extremely small leakage current in the non-conducting state, a semiconductor device with low power consumption can be provided.

[0050] Further, by using an oxide semiconductor, various elements can be stacked and three-dimensionally integrated. That is, since the oxide semiconductor can be formed into a film by using a sputtering method or the like, not only can a circuit be developed on the plane of the substrate, but also a three-dimensional integrated circuit (3D integrated circuit) with circuits developed in the vertical direction can be formed.

[0051] On the other hand, in a transistor using an oxide semiconductor, its electrical characteristics fluctuate due to impurities and oxygen deficiencies in the oxide semiconductor, and it tends to have a normally-on characteristic (a characteristic in which a channel exists even without applying a voltage to the gate electrode and current flows through the transistor). Examples of the impurities in the oxide semiconductor that affect the electrical characteristics of the transistor include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, etc.

[0052] Here, the influence of each impurity in the oxide semiconductor will be described.

[0053] When impurities are incorporated into an oxide semiconductor, defect levels or oxygen deficiencies may be formed. When impurities are incorporated into the channel formation region of an oxide semiconductor, the electrical characteristics of a transistor using the oxide semiconductor tend to vary, and the reliability may deteriorate. Further, when the channel formation region contains oxygen deficiencies, the transistor tends to have normally-on characteristics.

[0054] In addition, the defect levels may include trap levels. The charges trapped in the trap levels of a metal oxide may take a long time to disappear and may behave like fixed charges. Therefore, the electrical characteristics of a transistor having a metal oxide with a high trap level density in the channel formation region may become unstable.

[0055] In addition, when impurities are present in the channel formation region of an oxide semiconductor, the crystallinity of the channel formation region may be lowered, and the crystallinity of the oxide provided in contact with the channel formation region may also be lowered. When the crystallinity of the channel formation region is low, the stability or reliability of the transistor tends to deteriorate. Further, when the crystallinity of the oxide provided in contact with the channel formation region is low, interface levels are formed, and the stability or reliability of the transistor may deteriorate.

[0056] Therefore, in order to improve the stability or reliability of a transistor, it is effective to reduce the impurity concentration in the channel formation region of the oxide semiconductor and its vicinity.

[0057] Specifically, in the channel formation region of the oxide semiconductor and its vicinity, the concentrations of impurities such as hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon obtained by SIMS (Secondary Ion Mass Spectrometry: SIMS) are set to 1×10 20 atoms / cm 3 or less, preferably 2×10 19 atoms / cm 3 or less.

[0058] Alternatively, in the channel formation region of the oxide semiconductor and its vicinity, the concentration of impurities obtained by elemental analysis using EDX is set to 1.0 atomic% or less. When an oxide containing element M is used as the oxide semiconductor, in the channel formation region of the oxide semiconductor and its vicinity, the concentration ratio of the above impurities to element M is set to less than 0.10, preferably less than 0.05. Here, the concentration of element M used when calculating the above concentration ratio may be the concentration in the same region as the region where the concentration of the above impurities is calculated, or the concentration in the oxide semiconductor.

[0059] In addition, since a metal oxide with a reduced impurity concentration has a low density of defect levels, the trap level density may also be low.

[0060] Therefore, it is preferable to use a high-purity intrinsic oxide semiconductor with reduced impurities and oxygen deficiencies in the channel formation region of the transistor. In this specification and the like, a low impurity concentration and a low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic.

[0061] In addition, even when a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor is formed into a film, impurities may diffuse from a structure in contact with the oxide semiconductor or from outside the structure into the oxide semiconductor.

[0062] In particular, when forming an insulator that functions as a gate insulator in contact with the oxide semiconductor or an insulator that functions as an interlayer film, hydrogen may be added.

[0063] Specifically, as the gate insulator or the interlayer film, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with pores, etc. can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0064] On the one hand, when forming a film of silicon oxide or silicon oxynitride by chemical vapor deposition (CVD), a film-forming gas containing hydrogen such as a silane (SiH4)-based film-forming gas, for example, monosilane (SiH4), tetraethoxysilane ([Si(OC2H5)4]; TEOS), trimethoxysilane ([Si(OCH3)3H]; TMS), etc. may be used.

[0065] In addition, an organic silane gas may also be used. For example, as the organic silane gas, in addition to the aforementioned tetraethoxysilane (TEOS: chemical formula Si(OC2H5)4), silicon-containing compounds such as tetramethylsilane (TMS: chemical formula Si(CH3)4), tetramethylcyclotetrasiloxane (TMCTS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisilazane (HMDS), triethoxysilane (SiH(OC2H5)3), tris(dimethylamino)silane (SiH(N(CH3)2)3), etc. are used.

[0066] When forming an insulator using a film-forming gas containing hydrogen, there is a high probability that the hydrogen contained in the film-forming gas diffuses into the interior of the oxide semiconductor exposed on the surface to be coated.

[0067] Among the impurities, hydrogen also has a small atomic radius, and has the property of easily moving (or having a high tendency to diffuse) in the insulating layer or the conductive layer.

[0068] In addition, when providing a conductor in contact with a metal oxide, when hydrogen reaches the structure (the laminated structure of the metal oxide and the conductor), there is a high probability that film lifting and film peeling (also called peeling) occur between the metal oxide and the conductor.

[0069] That is, when an oxide semiconductor, which is a metal oxide, is in contact with a conductor, or when an insulating metal oxide is provided in contact with a conductor as part of a transistor structure, hydrogen diffused in the oxide semiconductor may reach the interface between the metal oxide and the conductor, and film lifting and film peeling may occur.

[0070] Specifically, in a semiconductor device having the transistor 200 shown in FIG. 1, film lifting or film peeling tends to occur at the surface where the oxide 230b is in contact with the conductor 240, or at the surface where the conductor 240 is in contact with the insulator 245.

[0071] Therefore, in the present embodiment, when a film-forming gas containing hydrogen is used in the chemical vapor deposition method for forming a structure constituting a semiconductor, a film-forming condition is used in which a constant Y satisfying the following formula is 0 < Y ≤ 8.0, preferably 0 < Y ≤ 7.0. Note that the constant Y can be expressed using the film-forming power PW [W], the execution electrode area S [cm 2 , the film-forming pressure P [Pa], and the flow rate f [sccm] of the film-forming gas containing hydrogen.

[0072]

Equation

[0073] By performing film formation using the film-forming condition in which the above constant Y is 0 < Y ≤ 8.0, preferably 0 < Y ≤ 7.0, it is possible to suppress hydrogen in the film-forming atmosphere from diffusing from the surface to be film-formed exposed to the film-forming gas into the object to be film-formed. That is, by setting the film-forming power PW, the pressure P, and the flow rate f to optimal conditions, it is possible to form an insulator without hydrogen contained in the film-forming gas diffusing into the object to be film-formed.

[0074] Further, by disposing an insulator formed under a film formation condition where the above constant Y satisfies 0 < Y ≤ 8.0, preferably 0 < Y ≤ 7.0, in proximity to the metal oxide, it is possible to suppress film lifting and film peeling (also referred to as peeling) that occur between the metal oxide and the conductor. Specifically, in a semiconductor device having the transistor 200 shown in FIG. 1, it is possible to prevent film lifting or film peeling that may occur at the surface where the oxide 230b and the conductor 240 are in contact, or at the surface where the conductor 240 and the insulator 245 are in contact.

[0075] Hereinafter, the detailed structure of the transistor will be described.

[0076] The oxide 230 preferably has a laminated structure of a plurality of oxide layers having different chemical compositions. Specifically, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b.

[0077] In the transistor 200 shown in FIG. 1, the oxide 230 is shown having a structure in which two layers, the oxide 230a and the oxide 230b, are laminated. However, the present invention is not limited to this. For example, a single layer of the oxide 230b or a structure having a laminated structure of three or more layers may be provided. Further, the oxide 230a and the oxide 230b may each have a laminated structure.

[0078] Also, as shown in FIG. 1D, at least the side surfaces of the oxide 230b and the conductor 240 are preferably substantially perpendicular to the surface where the insulator 224 and the oxide 230a are in contact. Specifically, in FIG. 1D, the side surfaces of the oxide 230b and the conductor 240 are preferably set to 60 degrees or more and 95 degrees or less, preferably 88 degrees or more and 92 degrees or less, with respect to the surface where the insulator 224 and the oxide 230a are in contact.

[0079] Also, as shown in FIG. 1C, the upper end portion of the oxide 230 in the channel formation region preferably has a shape with a curvature. That is, in the channel formation region, the upper surface and the side surface of the oxide 230 preferably have a shape that smoothly connects with a curved surface without forming a corner. Since there is no corner in the channel formation region, electric field concentration due to the electric field of either or both of the conductor 260 functioning as the first gate electrode and the conductor 205 functioning as the second gate electrode does not occur, and deterioration of the oxide 230 can be suppressed.

[0080] On the other hand, as shown in FIG. 1D, the upper end portion of the oxide 230 in the region overlapping with the conductor 240 preferably has a shape with a smaller curvature than the upper end portion of the oxide 230 in the channel formation region. The above structure can be formed by processing the oxide 230b and the conductor 240 using the same mask. Therefore, since the conductor 240 overlaps within the projected area of the oxide 230b, a fine transistor can be fabricated.

[0081] The conductor 260 functions as a first gate electrode (also referred to as a top gate).

[0082] Here, the end portion of the conductor 240a and the end portion of the conductor 240b preferably lie on the same plane as the side surface of the opening. Also, as shown in FIG. 1B or FIG. 1C, the upper surface of the conductor 260 substantially coincides with the upper surface of the insulator 250 and the upper surface of the oxide 230c.

[0083] Also, as shown in FIG. 1C, in the region where the conductor 260 and the oxide 230 do not overlap, the shortest distance from the surface where the conductor 260 and the insulator 250 are in contact to the upper surface of the insulator 222 is preferably shorter than the shortest distance from the surface where the oxide 230b and the oxide 230a are in contact to the upper surface of the insulator 222. That is, in the channel width direction of the transistor 200, the side surface of the oxide 230b has a structure that is covered by the conductor 260 at least via the insulator 250.

[0084] By configuring the conductor 260 that functions as a gate electrode to cover the side and upper surfaces of the channel formation region of the oxide 230b via the insulator 250 or the like, the electric field of the conductor 260 acts on the entire channel formation region of the oxide 230b. Therefore, the on-current of the transistor 200 can be increased and the frequency characteristics can be improved.

[0085] Note that the conductor 260 preferably includes a conductor 260a and a conductor 260b disposed on the conductor 260a. For example, the conductor 260a is preferably disposed so as to cover the bottom and side surfaces of the conductor 260b.

[0086] It is preferable to use a conductive material for the conductor 260a that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, it is preferable to use a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).

[0087] In addition, since the conductor 260a has a function of suppressing the diffusion of oxygen, it is possible to suppress the oxidation of the conductor 260b by oxygen contained in the insulator 250 and the resulting decrease in conductivity. As the conductive material having a function of suppressing the diffusion of oxygen, it is preferable to use, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0088] In addition, since the conductor 260 also functions as a wiring, it is preferable to use a conductor having high conductivity. For example, the conductor 260b can be made of a conductive material mainly composed of tungsten, copper, or aluminum. Also, the conductor 260b may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0089] In FIG. 1, the conductor 260 is shown as a two-layer structure of the conductor 260a and the conductor 260b, but it may also have a single-layer structure or a laminated structure of three or more layers.

[0090] The conductor 205 functions as a second gate (also referred to as a bottom gate) electrode.

[0091] Also, when the conductor 205 functions as a gate electrode, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently without linking it to the potential applied to the conductor 260. In particular, by applying a negative potential to the conductor 205, it is possible to increase the Vth of the transistor 200 and reduce the off-current. Therefore, applying a negative potential to the conductor 205 can make the drain current smaller when the potential applied to the conductor 260 is 0V than when no negative potential is applied.

[0092] The conductor 205 is arranged to overlap with the oxide 230 and the conductor 260. Also, the conductor 205 is preferably provided by being embedded in the insulator 216 or the insulator 214.

[0093] In the channel width direction, the conductor 205 is preferably provided to be larger than the channel formation region in the oxide 230. In particular, as shown in FIG. 1C, the conductor 205 preferably extends intersecting the channel width direction of the oxide 230.

[0094] Here, outside the side surface in the channel width direction of the oxide 230, the conductor 205 and the conductor 260 preferably overlap via an insulator. By having such a configuration, the channel formation region of the oxide 230 can be electrically surrounded by the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the conductor 205 functioning as the second gate electrode.

[0095] Also, in FIG. 1, the conductor 205 is shown as a configuration in which a first conductor and a second conductor are laminated, but the present invention is not limited to this. For example, the conductor 205 may be provided in a single layer or a laminated structure of three or more layers. When the structure has a laminated structure, ordinal numbers may be assigned in the formation order for distinction.

[0096] Here, for the first conductor of the conductor 205, it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N2O, NO, NO2), and copper atoms. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0097] By using a conductive material having a function of suppressing the diffusion of oxygen for the first conductor of the conductor 205, it is possible to suppress the oxidation of the second conductor of the conductor 205 and the decrease in conductivity. As the conductive material having a function of suppressing the diffusion of oxygen, for example, it is preferable to use tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. Therefore, as the first conductor of the conductor 205, the above conductive material may be a single layer or a laminate. For example, the first conductor of the conductor 205 may be a laminate of tantalum, tantalum nitride, ruthenium, or ruthenium oxide and titanium or titanium nitride.

[0098] In addition, for the second conductor of the conductor 205, it is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum. Although the second conductor of the conductor 205 is shown as a single layer, it may also have a laminated structure. For example, it may be a laminate of titanium or titanium nitride and the conductive material.

[0099] Also, as shown in FIG. 1C, the conductor 205 is stretched and also functions as a wiring. However, it is not limited to this, and a configuration may be adopted in which a conductor that functions as a wiring is provided under the conductor 205. Also, the conductor 205 does not necessarily need to be provided one by one for each transistor. For example, a configuration may be adopted in which the conductor 205 is shared by a plurality of transistors.

[0100] The conductor 240 (conductor 240a and conductor 240b) functions as a source electrode or a drain electrode.

[0101] Specifically, it is preferable to use TaNxOy as the conductor 240. Note that TaNxOy may contain aluminum. Further, for example, titanium nitride, a nitride containing titanium and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. may be used. These materials are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when absorbing oxygen.

[0102] Further, an insulator 245 that functions as a barrier layer may be provided on the conductor 240.

[0103] As shown in FIG. 1B, the insulator 245 preferably contacts the upper surface of the conductor 240. With this configuration, absorption of excess oxygen by the insulator 280 due to the conductor 240 can be suppressed. Further, by suppressing oxidation of the conductor 240, an increase in contact resistance between the transistor 200 and the wiring can be suppressed. Therefore, good electrical characteristics and reliability can be given to the transistor 200.

[0104] Therefore, the insulator 245 preferably has a function of suppressing oxygen diffusion. For example, the insulator 245 preferably has a function of suppressing oxygen diffusion more than the insulator 280.

[0105] As the insulator 245, for example, an insulator containing one or both oxides of aluminum and hafnium may be formed into a film. Further, as the insulator 245, for example, an insulator containing aluminum nitride may be used.

[0106] The insulator 250 functions as a first gate insulator.

[0107] The insulator 250 is disposed in contact with at least the oxide 230. As the insulator 250, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having pores, etc. can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0108] Also, it is preferable to use, as the insulator 250, an oxide material in which some oxygen desorbs upon heating. The oxide that desorbs oxygen upon heating is an oxide film in which the desorption amount of oxygen molecules is 1.0×10 18 molecules / cm 3 or more, preferably 1.0×10 19 molecules / cm 3 or more, more preferably 2.0×10 19 molecules / cm 3 or more, or 3.0×10 20 molecules / cm 3 or more, as determined by TDS (Thermal Desorption Spectroscopy) analysis. Note that the surface temperature of the film during the above TDS analysis is preferably in the range of 100°C or more and 700°C or less, or 100°C or more and 400°C or less.

[0109] By providing, as the insulator 250, an insulator that releases oxygen upon heating, in contact with the oxide 230, oxygen can be effectively supplied to the channel formation region of the oxide 230b, and oxygen deficiency in the channel formation region of the oxide 230b can be reduced. Therefore, it is possible to provide a transistor that suppresses fluctuations in electrical characteristics, has stable electrical characteristics, and has improved reliability. Also, the impurity concentration of water, hydrogen, etc. in the insulator 250 is preferably reduced.

[0110] Also, a metal oxide may be provided between the insulator 250 and the conductor 260. It is preferable that the metal oxide suppresses the diffusion of oxygen from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. That is, it is possible to suppress a decrease in the amount of oxygen supplied to the oxide 230. In addition, oxidation of the conductor 260 by oxygen in the insulator 250 can be suppressed.

[0111] Note that the metal oxide may function as part of the gate insulator. Therefore, when using silicon oxide, silicon oxynitride, etc. for the insulator 250, it is preferable to use a metal oxide that is a high-k material with a high relative permittivity as the metal oxide. By forming the gate insulator into a laminated structure of the insulator 250 and the metal oxide, a laminated structure that is stable against heat and has a high relative permittivity can be obtained. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. In addition, it is possible to thin the equivalent oxide film thickness (EOT) of the insulator that functions as the gate insulator.

[0112] Specifically, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc. can be used. In particular, it is preferable to use an insulator containing one or both of the oxides of aluminum and hafnium.

[0113] Also, the metal oxide may function as part of the first gate electrode. For example, an oxide semiconductor that can be used as the oxide 230 can be used as the metal oxide. In that case, by forming the conductor 260 by sputtering, the electrical resistance value of the metal oxide can be decreased to make it a conductor.

[0114] By having the above metal oxide, it is possible to improve the on-current of the transistor 200 without weakening the influence of the electric field from the conductor 260. Further, by maintaining the distance between the conductor 260 and the oxide 230 by the physical thickness of the insulator 250 and the above metal oxide, the leakage current between the conductor 260 and the oxide 230 can be suppressed. Further, by providing a laminated structure of the insulator 250 and the above metal oxide, the physical distance between the conductor 260 and the oxide 230 and the electric field strength applied from the conductor 260 to the oxide 230 can be easily adjusted appropriately.

[0115] The insulator 222 and the insulator 224 function as a second gate insulator.

[0116] The insulator 222 preferably has a function of suppressing the diffusion of hydrogen (for example, at least one of a hydrogen atom, a hydrogen molecule, etc.). Further, the insulator 222 preferably has a function of suppressing the diffusion of oxygen (for example, at least one of an oxygen atom, an oxygen molecule, etc.). For example, the insulator 222 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 224.

[0117] As the insulator 222, an insulator containing one or both of oxides of aluminum and hafnium, which are insulating materials, may be used. As the insulator, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses the release of oxygen from the oxide 230 to the substrate side and the diffusion of impurities such as hydrogen from the peripheral portion of the transistor 200 to the oxide 230. Therefore, by providing the insulator 222, it is possible to suppress the diffusion of impurities such as hydrogen to the inside of the transistor 200 and suppress the generation of oxygen vacancies in the oxide 230. Further, it is possible to suppress the reaction of the conductor 205 with the oxygen contained in the insulator 224 and the oxide 230.

[0118] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator. Alternatively, these insulators may be nitrided. Further, the insulator 222 may be used by laminating silicon oxide, silicon oxynitride, or silicon nitride on these insulators.

[0119] Further, the insulator 222 may be used as a single layer or a laminate of insulators containing so-called high-k materials such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), (Ba,Sr)TiO3 (BST), etc. As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for the insulator that functions as a gate insulator, it becomes possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0120] The insulator 224 in contact with the oxide 230 preferably desorbs oxygen by heating, similar to the insulator 250. For example, the insulator 224 may be appropriately silicon oxide, silicon oxynitride, etc. By providing an oxygen-containing insulator in contact with the oxide 230, the oxygen deficiency in the oxide 230 can be reduced, and the reliability of the transistor 200 can be improved.

[0121] Note that the insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In that case, it is not limited to a laminated structure made of the same material, and a laminated structure made of different materials may also be used.

[0122] The insulators 214, 216, 280, 282, and 284 function as interlayer films.

[0123] The insulator 214 preferably functions as an insulating barrier film that suppresses the diffusion of impurities such as water and hydrogen from the substrate side into the transistor 200. Therefore, it is preferable to use an insulating material for the insulator 214 that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N2O, NO, NO2), and copper atoms. Alternatively, it is preferable to use an insulating material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).

[0124] For example, it is preferable to use aluminum oxide, silicon nitride, etc. as the insulator 214. Thereby, it is possible to suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200 side rather than through the insulator 214. Alternatively, it is possible to suppress the diffusion of oxygen contained in the insulator 224, etc., to the substrate side rather than through the insulator 214. Note that the insulator 214 may have a laminated structure of two or more layers. In that case, it is not limited to a laminated structure made of the same material, and a laminated structure made of different materials may also be used. For example, a laminate of aluminum oxide and silicon nitride may be used.

[0125] Also, for example, it is preferable to use silicon nitride formed by a sputtering method as the insulator 214. Thereby, the hydrogen concentration in the insulator 214 can be lowered, and it is possible to more effectively suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200 side rather than through the insulator 214.

[0126] The insulator 216 that functions as an interlayer film preferably has a lower dielectric constant than the insulator 214. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced. For example, as the insulator 216, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with pores, etc. may be appropriately used.

[0127] In addition, the insulator 216 preferably has a region where the hydrogen concentration is low and oxygen is present in excess compared to the stoichiometric composition (hereinafter also referred to as the excess oxygen region) or oxygen that is released by heating (hereinafter also referred to as excess oxygen). For example, as the insulator 216, it is preferable to use silicon oxide formed by a sputtering method. Thereby, the mixing of hydrogen into the oxide 230 can be suppressed, or oxygen can be supplied to the oxide 230 to reduce oxygen deficiencies in the oxide 230. Therefore, it is possible to provide a transistor that suppresses fluctuations in electrical characteristics, has stable electrical characteristics, and has improved reliability.

[0128] Note that the insulator 216 may have a laminated structure. For example, in the insulator 216, a configuration may be adopted in which an insulator similar to the insulator 214 is provided at least in a portion that contacts the side surface of the conductor 205. By adopting such a configuration, oxidation of the conductor 205 by the oxygen contained in the insulator 216 can be suppressed. Alternatively, it is possible to suppress a decrease in the amount of oxygen contained in the insulator 216 due to the conductor 205.

[0129] The insulator 280 is provided on the insulator 224, the oxide 230, and the conductor 240. Also, the upper surface of the insulator 280 may be flattened.

[0130] The insulator 280 that functions as an interlayer film preferably has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced. The insulator 280 is preferably provided using, for example, a material similar to the insulator 216. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having pores are preferable because a region containing oxygen that desorbs by heating can be easily formed.

[0131] It is preferable that the impurity concentrations such as water and hydrogen in the insulator 280 are reduced. Further, the insulator 280 preferably has a low hydrogen concentration and has an excess oxygen region or excess oxygen, and for example, it may be provided using the same material as the insulator 216. Note that the insulator 280 may have a laminated structure of two or more layers.

[0132] Similar to the insulator 214 and the like, the insulator 282 preferably functions as an insulating barrier film that suppresses the diffusion of impurities such as water and hydrogen into the insulator 280 from above. Further, similar to the insulator 214 and the like, the insulator 282 preferably has a low hydrogen concentration and has a function of suppressing the diffusion of hydrogen.

[0133] Also, as shown in FIG. 1B, the insulator 282 preferably contacts the upper surfaces of the conductor 260 and the insulator 250, respectively. Thereby, it is possible to suppress impurities such as hydrogen contained in the insulator 284 and the like from mixing into the insulator 250. Therefore, it is possible to suppress an adverse effect on the electrical characteristics of the transistor and the reliability of the transistor.

[0134] It is preferable to provide an insulator 284 that functions as an interlayer film on the insulator 282. Similar to the insulator 216 and the like, the insulator 284 preferably has a low dielectric constant. Further, similar to the insulator 224 and the like, it is preferable that the impurity concentrations such as water and hydrogen in the film are reduced.

[0135] <Constituent Materials of Semiconductor Device> Hereinafter, the constituent materials that can be used in the semiconductor device will be described.

[0136] <<Substrate>> As the substrate for forming the transistor 200, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as yttria-stabilized zirconia substrate), a resin substrate, and the like. Examples of the semiconductor substrate include a semiconductor substrate made of silicon, germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Further, there is a semiconductor substrate having an insulator region inside the aforementioned semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, and the like. Or, there is a substrate having a metal nitride, a substrate having a metal oxide, and the like. Further, there is a substrate in which a conductor or a semiconductor is provided on an insulator substrate, a substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductor substrate, and the like. Or, those with elements provided on these substrates may also be used. Examples of the elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0137] <<Insulator>> Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, metal nitride oxides, etc. having insulating properties.

[0138] For example, as the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for the insulator that functions as the gate insulator, it is possible to lower the voltage during transistor operation while maintaining the physical film thickness. On the other hand, by using a material with a low relative permittivity for the insulator that functions as the interlayer film, the parasitic capacitance generated between the wirings can be reduced. Therefore, the material may be selected according to the function of the insulator.

[0139] In addition, examples of insulators with a high relative permittivity include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0140] Examples of insulators with a low relative permittivity include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with pores, or resin.

[0141] In addition, a transistor using an oxide semiconductor can have its electrical characteristics stabilized by surrounding it with insulators (such as insulator 214, insulator 222, insulator 245, and insulator 282) that have a function of suppressing the permeation of impurities such as hydrogen and oxygen. As insulators having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used either singly or in a stacked manner. Specifically, as insulators having a function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride can be used.

[0142] In addition, the insulator that functions as a gate insulator is preferably an insulator having a region containing oxygen that desorbs upon heating. For example, by forming a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that desorbs upon heating is in contact with the oxide 230, the oxygen deficiency of the oxide 230 can be compensated.

[0143] <<Conductor>> As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-described metal element as a component, or an alloy combining the above-described metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. Further, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when absorbing oxygen. Also, a semiconductor with high electrical conductivity typified by polycrystalline silicon containing impurity elements such as phosphorus, or a silicide such as nickel silicide may be used.

[0144] Also, a plurality of conductive layers formed of the above materials may be laminated and used. For example, a laminated structure combining a material containing the above-described metal element and a conductive material containing oxygen may be used. Also, a laminated structure combining a material containing the above-described metal element and a conductive material containing nitrogen may be used. Also, a laminated structure combining a material containing the above-described metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be used.

[0145] In the case of using an oxide in the channel formation region of a transistor, it is preferable to use a stacked structure in which a conductor functioning as a gate electrode is a combination of a material containing the above-described metal element and a conductive material containing oxygen. In this case, it is advisable to provide the conductive material containing oxygen on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is likely to be supplied to the channel formation region.

[0146] In particular, as the conductor functioning as the gate electrode, it is preferable to use a metal element contained in a metal oxide in which a channel is formed and a conductive material containing oxygen. Further, a conductive material containing the above-described metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. Further, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide added with silicon may be used. Further, indium gallium zinc oxide containing nitrogen may be used. By using such a material, it may be possible to capture hydrogen contained in the metal oxide in which a channel is formed. Or, it may be possible to capture hydrogen mixed from an external insulator or the like.

[0147] <<Metal Oxide>> As the oxide 230, it is preferable to use a metal oxide that functions as an oxide semiconductor. Hereinafter, metal oxides applicable to the oxide 230 according to the present invention will be described.

[0148] The metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition to these, it is preferable that gallium, yttrium, tin, etc. are contained. Further, one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. may be contained.

[0149] Here, consider the case where the metal oxide is an In-M-Zn oxide having indium, element M, and zinc. Note that element M is aluminum, gallium, yttrium, or tin. Elements applicable to other element Ms include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. However, there may be cases where a plurality of the aforementioned elements are combined as element M.

[0150] In this specification etc., a metal oxide having nitrogen may also be collectively referred to as a metal oxide. Also, a metal oxide having nitrogen may be referred to as a metal oxynitride.

[0151] [Structure of Metal Oxide] The oxide semiconductor (metal oxide) is divided into a single crystal oxide semiconductor and other non-single crystal oxide semiconductors. Examples of the non-single crystal oxide semiconductor include CAAC-OS, polycrystalline oxide semiconductor, nc-OS (nanocrystalline oxide semiconductor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous-like oxide semiconductor), and amorphous oxide semiconductor.

[0152] CAAC-OS has a c-axis orientation, and in the a-b plane direction, a plurality of nanocrystals are connected to form a crystal structure with strain. The strain refers to a location where the orientation of the lattice arrangement changes between a region where the lattice arrangement is aligned and another region where the lattice arrangement is aligned in the region where the plurality of nanocrystals are connected.

[0153] The nanocrystals are based on a hexagon, but are not necessarily regular hexagons and may be non-regular hexagons. Also, in the strain, there may be lattice arrangements such as pentagons and heptagons. In CAAC-OS, it is difficult to confirm a clear grain boundary (also referred to as a grain boundary) even near the strain. That is, it can be seen that the formation of grain boundaries is suppressed by the strain of the lattice arrangement. This is because CAAC-OS can tolerate strain due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction and the interatomic bond distance changes due to the substitution of metal elements.

[0154] Also, CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium and oxygen (hereinafter referred to as the In layer) and a layer containing element M, zinc, and oxygen (hereinafter referred to as the (M,Zn) layer) are laminated. Indium and element M are mutually substitutable. When element M in the (M,Zn) layer is substituted with indium, it can also be represented as an (In,M,Zn) layer. Also, when indium in the In layer is substituted with element M, it can also be represented as an (In,M) layer.

[0155] CAAC-OS is a highly crystalline metal oxide. On the other hand, since it is difficult to confirm a clear grain boundary in CAAC-OS, it can be said that a decrease in electron mobility due to grain boundaries is less likely to occur. Also, since the crystallinity of metal oxides may decrease due to the incorporation of impurities or the generation of defects, CAAC-OS can also be said to be a metal oxide with few impurities and defects (such as oxygen deficiencies). Therefore, the physical properties of the metal oxide having CAAC-OS are stable. For this reason, the metal oxide having CAAC-OS is heat-resistant and highly reliable.

[0156] nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Further, nc-OS has no regularity in the crystal orientation among different nanocrystals. Therefore, no orientation is observed in the whole film. Thus, depending on the analysis method, nc-OS may not be distinguishable from a-like OS or an amorphous oxide semiconductor.

[0157] Note that indium-gallium-zinc oxide (hereinafter, IGZO), which is a kind of metal oxide having indium, gallium, and zinc, may take a stable structure by using the above-described nanocrystals. In particular, since IGZO has a tendency that crystal growth is difficult in the air, it may be structurally more stable to use smaller crystals (for example, the above-described nanocrystals) than larger crystals (here, crystals of several mm or crystals of several cm).

[0158] a-like OS is a metal oxide having a structure between nc-OS and an amorphous oxide semiconductor. a-like OS has a loose or low-density region. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS.

[0159] Oxide semiconductors (metal oxides) have various structures and each has different characteristics. The oxide semiconductor according to one embodiment of the present invention may have two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, a-like OS, nc-OS, and CAAC-OS.

[0160] <Method for manufacturing a semiconductor device> Next, a method for manufacturing a semiconductor device having the transistor 200 according to one embodiment of the present invention shown in FIG. 1 will be described with reference to FIGS. 2 to 8.

[0161] In FIGS. 2 to 8, A in each figure shows a top view. Also, B in each figure is a cross-sectional view corresponding to the portion indicated by the dashed line A1 - A2 shown in A, and is also a cross-sectional view in the channel length direction of the transistor 200. Further, C in each figure is a cross-sectional view corresponding to the portion indicated by the dashed line A3 - A4 in A, and is also a cross-sectional view in the channel width direction of the transistor 200. Also, D in each figure is a cross-sectional view of the portion indicated by the dashed line A5 - A6 in A of each figure, and is also a cross-sectional view in the channel width direction of the transistor 200. Note that in the top view of A in each figure, some elements are omitted for clarity of the figure.

[0162] First, a substrate (not shown) is prepared, and an insulator 214 is formed on the substrate. The formation of the insulator 214 can be performed using a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like.

[0163] Note that the CVD method can be classified into a plasma enhanced CVD (PECVD) method using plasma, a thermal CVD (TCVD) method using heat, a photo CVD method using light, and the like. Further, it can be divided into a metal CVD (MCVD) method and a metal organic CVD (MOCVD) method depending on the raw material gas used.

[0164] The plasma CVD method can obtain high-quality films at relatively low temperatures. Also, the thermal CVD method, which does not use plasma, is a film-forming method capable of reducing plasma damage to the object to be processed. For example, wirings, electrodes, elements (such as transistors and capacitor elements) included in semiconductor devices may be charged up by receiving charges from plasma. At this time, the wirings, electrodes, elements, etc. included in the semiconductor device may be damaged by the accumulated charges. On the other hand, in the case of the thermal CVD method that does not use plasma, such plasma damage does not occur, so the yield of semiconductor devices can be increased. Also, in the thermal CVD method, since plasma damage does not occur during film formation, a film with few defects can be obtained.

[0165] Also, the ALD method utilizes the self-limiting property of atoms and can deposit atoms one by one, so it enables extremely thin film formation, film formation on structures with a high aspect ratio, film formation with few defects such as pinholes, film formation with excellent coverage, film formation at low temperatures, and other effects. Also, the ALD method includes the PEALD (Plasma Enhanced ALD) method that uses plasma. Utilizing plasma may be preferable as it enables film formation at lower temperatures. Note that some of the precursors used in the ALD method contain impurities such as carbon. Therefore, the film formed by the ALD method may contain more impurities such as carbon compared to the film formed by other film-forming methods. Note that the quantification of impurities can be performed using X-ray photoelectron spectroscopy (XPS).

[0166] Unlike film deposition methods in which particles emitted from a target or the like are deposited, the CVD method and the ALD method are film deposition methods in which a film is formed by a reaction on the surface of an object to be processed. Therefore, it is a film deposition method that is less affected by the shape of the object to be processed and has good step coverage. In particular, the ALD method is suitable for covering the surface of an opening with a high aspect ratio because it has excellent step coverage and excellent thickness uniformity. However, since the ALD method has a relatively slow film deposition rate, it may be preferable to use it in combination with other film deposition methods such as the CVD method with a high film deposition rate.

[0167] The composition of the obtained film can be controlled by the flow rate ratio of the source gases in the CVD method and the ALD method. For example, in the CVD method and the ALD method, a film with an arbitrary composition can be formed by the flow rate ratio of the source gases. Further, for example, in the CVD method and the ALD method, a film with a continuously changing composition can be formed by changing the flow rate ratio of the source gases while forming the film. When forming a film while changing the flow rate ratio of the source gases, the time required for film formation can be shortened because it does not require the time required for transfer and pressure adjustment compared to the case of forming a film using a plurality of film deposition chambers. Therefore, the productivity of the semiconductor device may be increased.

[0168] In the present embodiment, aluminum oxide is formed as the insulator 214 by a sputtering method. Further, the insulator 214 may have a multilayer structure.

[0169] Next, an insulator 216 is formed on the insulator 214. The formation of the insulator 216 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In the present embodiment, silicon oxynitride is formed as the insulating film that becomes the insulator 216 by a CVD method.

[0170] Next, an opening reaching the insulator 214 is formed in the insulator 216. The opening includes, for example, grooves, slits, etc. In some cases, the region where the opening is formed may be referred to as an opening portion. The formation of the opening may use wet etching, but dry etching is more preferable for microfabrication. Also, it is preferable to select the insulator 214 as an insulator that functions as an etching stopper film when etching the insulator 216 to form a groove. For example, when silicon oxynitride is used for the insulator 216 forming the groove, silicon nitride, aluminum oxide, or hafnium oxide may be used for the insulator 214.

[0171] As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high-frequency voltage to one of the parallel plate electrodes. Or it may be configured to apply a plurality of different high-frequency voltages to one of the parallel plate electrodes. Or it may be configured to apply high-frequency voltages of the same frequency to each of the parallel plate electrodes. Or it may be configured to apply high-frequency voltages of different frequencies to each of the parallel plate electrodes. Or a dry etching apparatus having a high-density plasma source can be used. The dry etching apparatus having a high-density plasma source can use, for example, an inductively coupled plasma (ICP) etching apparatus, etc.

[0172] After the formation of the opening, a conductive film serving as the first conductor of the conductor 205 is formed. It is desirable that the conductive film includes a conductor having a function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, etc. can be used. Or it can be a laminated film of a conductor having a function of suppressing oxygen permeation and tantalum, tungsten, titanium, molybdenum, aluminum, copper, molybdenum-tungsten alloy. The formation of the conductive film can be performed using a sputtering method, CVD method, MBE method, PLD method, ALD method, etc.

[0173] In this embodiment, as the conductive film serving as the first conductor of the conductor 205, a tantalum nitride film or a film formed by laminating titanium nitride on tantalum nitride is formed by sputtering. By using such a metal nitride as the first conductor of the conductor 205, even if a metal such as copper that is likely to diffuse is used as the second conductor of the conductor 205 described later, it is possible to prevent the metal from diffusing out from the first conductor of the conductor 205.

[0174] Next, a conductive film serving as the second conductor of the conductor 205 is formed on the conductive film serving as the first conductor of the conductor 205. The formation of the conductive film can be performed using a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, tungsten is formed as the conductive film.

[0175] Next, by performing CMP (Chemical Mechanical Polishing) treatment, a part of the conductive film serving as the first conductor of the conductor 205 and the conductive film serving as the second conductor of the conductor 205 is removed to expose the insulator 216. As a result, the conductive film serving as the first conductor of the conductor 205 and the conductive film serving as the second conductor of the conductor 205 remain only in the opening. Thereby, a conductor 205 including the first conductor of the conductor 205 and the second conductor of the conductor 205 having a flat upper surface can be formed (see FIG. 2).

[0176] Note that after forming the conductor 205, a part of the second conductor of the conductor 205 may be removed to form a groove in the second conductor of the conductor 205, a conductive film may be formed on the conductor 205 and the insulator 216 so as to fill the groove, and a process of performing CMP treatment may be performed. By the CMP treatment, a part of the conductive film is removed to expose the insulator 216. Note that a part of the second conductor of the conductor 205 may be removed using a dry etching method or the like.

[0177] By the above process, a conductor 205 including the conductive film with a flat upper surface can be formed. By improving the flatness of the upper surfaces of the insulator 216 and the conductor 205, the crystallinity of the oxide 230 can be improved. Note that the same material as the first conductor of the conductor 205 or the second conductor of the conductor 205 may be used for the conductive film.

[0178] Hereinafter, a method for forming the conductor 205 different from the above will be described.

[0179] A conductive film to be the conductor 205 is formed on the insulator 214. The formation of the conductive film to be the conductor 205 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Also, the conductive film to be the conductor 205 can be a multilayer film. For example, tungsten is formed as the conductive film to be the conductor 205.

[0180] Next, the conductive film to be the conductor 205 is processed using a lithography method to form the conductor 205.

[0181] In the lithography method, first, a resist is exposed through a mask. Next, the exposed area is removed or left using a developer to form a resist mask. Next, by performing an etching process through the resist mask, conductors, semiconductors, insulators, etc. can be processed into a desired shape. For example, a resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Also, a liquid immersion technique in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure may be used. Also, instead of the light described above, an electron beam or an ion beam may be used. Note that when an electron beam or an ion beam is used, a mask is not required. The resist mask can be removed by performing a dry etching process such as ashing, a wet etching process, a wet etching process after a dry etching process, or a dry etching process after a wet etching process.

[0182] Alternatively, a hard mask made of an insulator or a conductor may be used instead of the resist mask. When using a hard mask, an insulating film or a conductive film serving as the hard mask material is formed on the conductive film that will become the conductor 205, a resist mask is formed thereon, and a hard mask having a desired shape can be formed by etching the hard mask material. The etching of the conductive film that will become the conductor 205 may be performed after removing the resist mask, or may be performed while leaving the resist mask. In the latter case, the resist mask may disappear during etching. The hard mask may be removed by etching after the etching of the conductive film that will become the conductor 205. On the other hand, if the material of the hard mask has no influence on the subsequent process or can be used in the subsequent process, it is not always necessary to remove the hard mask.

[0183] Next, an insulating film that will become the insulator 216 is formed on the insulator 214 and the conductor 205. The insulating film is formed so as to contact the upper surface and the side surface of the conductor 205. The formation of the insulating film can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0184] Here, the film thickness of the insulating film that will become the insulator 216 is preferably equal to or greater than the film thickness of the conductor 205. For example, if the film thickness of the conductor 205 is 1, the film thickness of the insulating film that will become the insulator 216 is 1 or more and 3 or less.

[0185] Next, by performing CMP processing on the insulating film that will become the insulator 216, a part of the insulating film that will become the insulator 216 is removed, and the surface of the conductor 205 is exposed. Thereby, the conductor 205 and the insulator 216 with a flat upper surface can be formed. The above are different formation methods of the conductor 205.

[0186] Next, an insulator 222 is formed on the insulator 216 and the conductor 205. The formation of the insulator 222 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In the present embodiment, hafnium oxide or aluminum oxide is formed as the insulator 222 by an ALD method.

[0187] Subsequently, heat treatment is preferably performed. The heat treatment may be performed at 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower. Note that the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. Further, the heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to supplement the desorbed oxygen after heat treatment in an atmosphere of nitrogen gas or an inert gas.

[0188] In the present embodiment, as the heat treatment, after forming the insulator 222, a treatment is performed at a temperature of 400°C for 1 hour in a nitrogen atmosphere, and then continuously, a treatment is performed at a temperature of 400°C for 1 hour in an oxygen atmosphere. By this heat treatment, impurities such as water and hydrogen contained in the insulator 222 can be removed. Further, the heat treatment can also be performed at a timing such as after forming the insulator 224.

[0189] Next, an insulator 224 is formed on the insulator 222. The formation of the insulator 224 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In the present embodiment, a silicon oxynitride film is formed as the insulator 224 by a CVD method.

[0190] Here, when forming the insulator 224, a film-forming condition is used in which the constant Y satisfying the above-mentioned formula (1) is 0 < Y ≤ 8.0, preferably 0 < Y ≤ 7.0. By forming a film using a film-forming condition in which the constant Y is 0 < Y ≤ 8.0, preferably 0 < Y ≤ 7.0, a high-quality film with a reduced hydrogen concentration can be formed. Further, by setting the film-forming power PW, pressure P, and flow rate f to optimal conditions, the hydrogen contained in the film-forming gas can be prevented from being driven into the object to be film-formed, and the insulator can be formed.

[0191] In addition, in order to form an excess oxygen region in the insulator 224, plasma treatment containing oxygen may be performed under reduced pressure. For the plasma treatment containing oxygen, it is preferable to use, for example, a device having a power source for generating high-density plasma using microwaves. Alternatively, it may have a power source for applying RF (Radio Frequency) to the substrate side. By using high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently introduced into the insulator 224. Alternatively, after performing plasma treatment containing an inert gas using this device, plasma treatment containing oxygen may be performed to supplement the desorbed oxygen. Note that by appropriately selecting the conditions for the plasma treatment, impurities such as water and hydrogen contained in the insulator 224 can be removed. In that case, heat treatment may not be performed.

[0192] Specifically, as an example of the plasma treatment, there is microwave-excited plasma treatment. By performing the microwave-excited plasma treatment, hydrogen, water, or impurities, which are impurities in the insulator as the object to be treated, can be removed. Further, by performing the microwave-excited plasma treatment, the film quality of the insulator can be modified to suppress the diffusion of hydrogen, water, or impurities. Therefore, it is possible to suppress the diffusion of hydrogen, water, or impurities to the oxide 230 through the insulator 250 and the insulator 224 in a subsequent process such as forming a conductive film to be the conductor 260 or a post-treatment such as heat treatment.

[0193] For example, the binding energy between a hydrogen atom and a silicon atom in solid silicon oxide is 3.3 eV, the binding energy between a carbon atom and a silicon atom is 3.4 eV, and the binding energy between a nitrogen atom and a silicon atom is 3.5 eV. Therefore, to remove a hydrogen atom bonded to a silicon atom, at least a radical or ion having an energy of 3.3 eV or more is caused to collide with the bond between the hydrogen atom and the silicon atom, so that the bond between the hydrogen atom and the silicon atom can be broken.

[0194] Regarding other impurities such as nitrogen and carbon, similarly, at least a radical or ion having an energy equal to or higher than the binding energy is caused to collide with the bond between the impurity atom and the silicon atom, so that the bond between the impurity atom and the silicon atom can be broken.

[0195] Here, as radicals and ions generated by plasma excited by microwaves, the ground state O( 3 P) of an oxygen atom radical, the first excited state O( 1 D) of an oxygen atom radical, and the monovalent cation O2+ of an oxygen molecule, etc. are present. The energy of O( 3 P) is 2.42 eV, and the energy of O( 1 D) is 4.6 eV. Also, since O 2 + has a charge and is accelerated by the potential distribution and bias in the plasma, the energy is not uniquely determined, but at least only the internal energy is higher than that of O( 1 D).

[0196] That is, radicals and ions such as O( 1 D) and O2+ can break the bonds between hydrogen, nitrogen, and carbon atoms in the insulator 250 and silicon atoms, and remove hydrogen, nitrogen, and carbon bonded to the silicon atoms. Also, when performing microwave-excited plasma treatment, impurities such as hydrogen, nitrogen, and carbon can be reduced by the thermal energy applied to the substrate, etc.

[0197] On the other hand, O(3 Since P has low reactivity, it does not react with the insulator 250 and diffuses deep into the film. Or, O( 3 P) reaches the oxide 230 through the insulator 250 and diffuses into the oxide 230. When O( 3 P) approaches the oxygen deficiency containing hydrogen, the hydrogen in the oxygen deficiency is released from the oxygen deficiency, and instead, O( 3 P) enters the oxygen deficiency, and the oxygen deficiency is compensated. Therefore, in the oxide 230, the generation of electrons as carriers can be suppressed.

[0198] Note that the ratio of O( 3 P) to the overall radicals and ion species increases by performing the microwave-excited plasma treatment under high-pressure conditions. In order to compensate for the oxygen deficiency in the oxide 230, it is preferable that the ratio of O( 3 P) is higher. Therefore, the microwave-excited plasma treatment may be performed at a pressure of 133 Pa or more, preferably 200 Pa, more preferably 400 Pa or more. Also, it is preferable to perform the treatment with an oxygen flow ratio (O2 / O2+Ar) of 50% or less, preferably 10% or more and 30% or less.

[0199] Also, for example, after forming an aluminum oxide film on the insulator 224 by sputtering, CMP treatment may be performed until reaching the insulator 224. By performing the CMP treatment, the surface of the insulator 224 can be planarized and smoothed. By disposing the aluminum oxide on the insulator 224 and performing the CMP treatment, it becomes easy to detect the end point of the CMP treatment. Also, although a part of the insulator 224 may be polished by the CMP treatment and the film thickness of the insulator 224 may become thinner, the film thickness may be adjusted during the film formation of the insulator 224. By planarizing and smoothing the surface of the insulator 224, it may be possible to prevent deterioration of the coverage rate of the oxide to be formed later and prevent a decrease in the yield of the semiconductor device. Also, it is preferable to form an aluminum oxide film on the insulator 224 by sputtering because oxygen can be added to the insulator 224.

[0200] Next, an oxide film 230A and an oxide film 230B are sequentially formed on the insulator 224 (see Fig. 2). Note that it is preferable to form the oxide film 230A and the oxide film 230B continuously without exposing them to the atmospheric environment. By forming the films without opening to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the oxide film 230A and the oxide film 230B, and the vicinity of the interface between the oxide film 230A and the oxide film 230B can be kept clean.

[0201] The oxide film 230A and the oxide film 230B can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0202] For example, when forming the oxide film 230A and the oxide film 230B by a sputtering method, oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, the excess oxygen in the formed oxide film can be increased. Also, when forming the above oxide film by a sputtering method, the above In-M-Zn oxide target or the like can be used.

[0203] In particular, when forming the oxide film 230A, a part of the oxygen contained in the sputtering gas may be supplied to the insulator 224. Therefore, the proportion of oxygen contained in the sputtering gas may be 70% or more, preferably 80% or more, and more preferably 100%.

[0204] Also, when forming the oxide film 230B by sputtering, if the ratio of oxygen contained in the sputtering gas is more than 30% and 100% or less, preferably 70% or more and 100% or less, an oxygen-excessive type oxide semiconductor is formed. A transistor using an oxygen-excessive type oxide semiconductor in the channel formation region can obtain relatively high reliability. However, one aspect of the present invention is not limited to this. When forming the oxide film 230B by sputtering, if the ratio of oxygen contained in the sputtering gas is 1% or more and 30% or less, preferably 5% or more and 20% or less, an oxygen-deficient type oxide semiconductor is formed. A transistor using an oxygen-deficient type oxide semiconductor in the channel formation region can obtain relatively high field-effect mobility. Also, by performing film formation while heating the substrate, the crystallinity of the oxide film can be improved.

[0205] In the present embodiment, as the oxide film 230A, film formation is performed by sputtering using an In-Ga-Zn oxide target with an atomic ratio of 1:3:4. Also, as the oxide film 230B, film formation is performed by sputtering using an In-Ga-Zn oxide target with an atomic ratio of In:Ga:Zn = 4:2:4.1. Note that each oxide film may be formed in accordance with the characteristics required for the oxide 230 by appropriately selecting the film formation conditions and the atomic ratio.

[0206] Note that it is preferable to form the insulator 222, the insulator 224, the oxide film 230A, and the oxide film 230B without exposing them to the atmosphere. For example, a multi-chamber type film formation apparatus may be used.

[0207] Next, heat treatment may be performed. The above-described heat treatment conditions can be used for the heat treatment. By the heat treatment, impurities such as water and hydrogen in the oxide film 230A and the oxide film 230B can be removed. In the present embodiment, after performing a treatment at a temperature of 400°C for 1 hour in a nitrogen atmosphere, a treatment at a temperature of 400°C for 1 hour in an oxygen atmosphere is continuously performed.

[0208] Next, a conductive film 240A is formed on the oxide film 230B. The formation of the conductive film 240A can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. (see Fig. 2). Note that before forming the conductive film 240A, a heat treatment may be performed. The heat treatment is performed under reduced pressure, and the conductive film 240A may be continuously formed without being exposed to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide film 230B can be removed, and further, the moisture concentration and hydrogen concentration in the oxide film 230A and the oxide film 230B can be reduced. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower. In this embodiment, the temperature of the heat treatment is set to 200°C.

[0209] Subsequently, an insulating film 245A that functions as a barrier layer is formed.

[0210] For example, aluminum oxide may be formed as the insulating film 245A by the ALD method. By forming using the ALD method, a film with a dense structure, reduced defects such as cracks and pinholes, or a uniform thickness can be formed.

[0211] Next, a film 290A that serves as a hard mask is formed on the insulating film 245A (see Fig. 2). For example, tungsten or tantalum nitride may be formed as the film 290A that serves as a hard mask by a sputtering method.

[0212] Next, a resist mask 292 is formed on the film 290A that serves as a hard mask by photolithography. By selectively removing a part of the film 290A that serves as a hard mask and a part of the insulating film 245A using the resist mask 292, a hard mask 290B and an insulating layer 245B are formed (Fig. 3).

[0213] Next, using the hard mask 290B and the insulating layer 245B, a part of the conductive film 240A is selectively removed to form an island-shaped conductive layer 240B (Fig. 4). Note that at this time, a part or all of the hard mask 290B may be removed.

[0214] Subsequently, using the island-shaped conductive layer 240B, the insulating layer 245B, and the hard mask 290B as masks, a part of the oxide film 230A and a part of the oxide film 230B are selectively removed. Note that in this step, a part of the insulator 224 may also be removed at the same time. Thereafter, by removing the hard mask 290B, a stacked structure of the island-shaped oxide 230a, the island-shaped oxide 230b, the island-shaped conductive layer 240B, and the island-shaped insulating layer 245B can be formed.

[0215] Also, in this step, by processing the conductive film 240A using the hard mask 290B, the occurrence of unnecessary etching (also referred to as CD loss) in the shape of the conductor 240 can be suppressed.

[0216] For example, when using a resist mask, the mask may be side-etched during etching, the end surface of the workpiece may be exposed, and the corners may become rounded. In the conductor 240, if such a defect is large, the volume of the conductor 240 may decrease from the design value, and the on-current may become small.

[0217] Therefore, by using a hard mask and using a material with a large selectivity of the etching rate with respect to the hard mask as the workpiece, the shape of the hard mask can be maintained during etching, and the workpiece can be prevented from having a shape defect. Specifically, when the etching rate of the material used for the hard mask is set to 1, a material with an etching rate of 5 or more, preferably 10 or more, for the workpiece may be used as the mask.

[0218] Next, an insulating film 280A is formed on the stacked structure of the island-shaped oxide 230a, the island-shaped oxide 230b, the island-shaped conductive layer 240B, and the island-shaped insulating layer 245B. The insulating film 280A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0219] In this embodiment, a silicon oxide film is formed as the insulating film 280A by CVD method or sputtering method. Note that, before forming the insulating film 280A, a heat treatment may be performed. The heat treatment is performed under reduced pressure, and the insulating film may be continuously formed without being exposed to the atmosphere. By performing such treatment, moisture and hydrogen adsorbed on the surface of the insulator 224 etc. can be removed, and furthermore, the moisture concentration and hydrogen concentration in the oxide 230a, oxide 230b, and insulator 224 can be reduced. The above-described heat treatment conditions can be used.

[0220] Here, when forming the insulator 280, a film forming condition is used such that the constant Y satisfying the above-mentioned formula 1 is 0 < Y ≤ 8.0, preferably 0 < Y ≤ 7.0. By forming a film using a film forming condition such that the constant Y is 0 < Y ≤ 8.0, preferably 0 < Y ≤ 7.0, a high-quality film with a reduced hydrogen concentration can be formed. Also, by setting the film forming power PW, pressure P, and flow rate f to optimal conditions, the insulator can be formed without the hydrogen contained in the film forming gas being implanted into the interior of the object to be film formed (specifically, the insulator 224, oxide 230, conductive layer 240B, and insulating layer 245B).

[0221] Also, the insulating film 280A may have a multilayer structure. For example, a structure may be adopted in which a silicon oxide film is formed by sputtering method and then a silicon oxide film is formed on the silicon oxide film by CVD method.

[0222] Next, a CMP treatment is performed on the insulating film 280A to form an insulator 280 having a flat upper surface (see FIG. 5). Subsequently, a part of the insulator 280 and a part of the conductive layer 240B are processed to form an opening reaching the oxide 230b (see FIG. 6).

[0223] In the transistor 200 shown in FIG. 1, the conductor 260 is provided by filling an opening formed in the insulator 280 or the like. That is, the conductor 260 is embedded in the opening provided in the insulator 280 via the insulator 250 or the like, so that the conductor 260 can be self-alignedly arranged in the region between the conductor 240a and the conductor 240b without alignment.

[0224] The opening is preferably formed so as to overlap the conductor 205. By forming the opening, the conductor 240a, the conductive layer 240B, the insulator 245a, and the insulating layer 245B are formed. At this time, the film thickness of the region of the oxide 230b overlapping the opening may become thin (see FIG. 6).

[0225] Also, a part of the insulator 280, a part of the insulating layer 245B, and a part of the conductive layer 240B may be processed under different conditions. For example, a part of the insulator 280 may be processed by a dry etching method, a part of the insulating layer 245B may be processed by a wet etching method, and a part of the conductive layer 240B may be processed by a dry etching method.

[0226] Here, it is preferable to remove impurities attached to the surface or diffused inside the oxide 230a, the oxide 230b, etc. Examples of the impurities include components contained in the insulator 280, the insulating layer 245B, and the conductive layer 240B, components contained in members used in the apparatus used to form the above-mentioned opening, and components contained in the gas or liquid used for etching. Examples of the impurities include aluminum, silicon, tantalum, fluorine, chlorine, etc.

[0227] In order to remove the above-mentioned impurities or the like, a cleaning process may be performed. Examples of the cleaning method include wet cleaning using a cleaning liquid or the like, plasma treatment using plasma, and cleaning by heat treatment, and the above-mentioned cleaning may be appropriately combined.

[0228] As wet cleaning, an aqueous solution obtained by diluting aqueous ammonia, oxalic acid, phosphoric acid, hydrofluoric acid, etc. with carbonated water or pure water, pure water, carbonated water, etc. may be used for the cleaning treatment. Further, ultrasonic cleaning using these aqueous solutions, pure water, or carbonated water may be performed. Further, these cleanings may be appropriately combined and performed.

[0229] Next, heat treatment may be performed. The heat treatment is preferably performed in an atmosphere containing oxygen. Further, the heat treatment may be performed under reduced pressure, and the oxide film 230C may be continuously formed without being exposed to the atmosphere (see Fig. 7). By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide 230b, etc. can be removed, and further, the moisture concentration and hydrogen concentration in the oxides 230a and 230b can be reduced. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower. In the present embodiment, the temperature of the heat treatment is 200°C.

[0230] The insulating film 250A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. (see Fig. 7). In the present embodiment, as the insulating film 250A, silicon oxynitride is formed by a CVD method. Note that the film formation temperature when forming the insulating film 250A is preferably 350°C or higher and less than 450°C, particularly around 400°C. By forming the insulating film 250A at 400°C, an insulating film with few impurities can be formed.

[0231] Here, when forming the insulating film 250A, a film formation condition in which a constant Y satisfying the above-mentioned number 1 is 0 < Y ≤ 8.0, preferably 0 < Y ≤ 7.0 is used. By forming the film using a film formation condition in which the constant Y is 0 < Y ≤ 8.0, preferably 0 < Y ≤ 7.0, a high-quality film with a reduced hydrogen concentration can be formed. Further, by setting the film formation power PW, pressure P, and flow rate f to optimal conditions, hydrogen contained in the film formation gas can be prevented from being driven into the objects to be film-formed (specifically, the insulator 224, the oxide 230, the conductor 240, the insulator 245, and the insulator 280), and the insulator can be formed.

[0232] Next, the conductive film 260A and the conductive film 260B are formed in sequence. The formation of the conductive film 260A and the conductive film 260B can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In the present embodiment, the conductive film 260A is formed using the ALD method, and the conductive film 260B is formed using the CVD method (see FIG. 7).

[0233] Next, by performing CMP processing to polish the oxide film 230C, the insulating film 250A, the conductive film 260A, and the conductive film 260B until the insulator 280 is exposed, the insulator 250 and the conductor 260 (the conductor 260a and the conductor 260b) are formed (see FIG. 8). Further, the insulator 250 is disposed so as to cover the inner wall of the opening. Further, the conductor 260 is disposed so as to fill the opening via the insulator 250.

[0234] Next, a heat treatment may be performed. In the present embodiment, a treatment is performed at a temperature of 400° C. for 1 hour in a nitrogen atmosphere. By this heat treatment, the moisture concentration and the hydrogen concentration in the insulator 250 and the insulator 280 can be reduced.

[0235] Next, an insulator 282 is formed on the insulator 250, the conductor 260, and the insulator 280. The formation of the insulator 282 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulator 282, for example, it is preferable to form an aluminum oxide film or a silicon nitride film by a sputtering method. By forming an aluminum oxide film or a silicon nitride film by a sputtering method, the diffusion of hydrogen in the insulator 284 to the oxide 230 can be suppressed. Further, by forming the insulator 282 so as to be in contact with the conductor 260, the oxidation of the conductor 260 can be suppressed, which is preferable.

[0236] In addition, as the insulator 282, by forming an aluminum oxide film by a sputtering method, oxygen can be supplied to the insulator 280. The oxygen supplied to the insulator 280 may be supplied to the channel formation region of the oxide 230b through the insulator 250. Further, when oxygen is supplied to the insulator 280, the oxygen contained in the insulator 280 before the formation of the insulator 282 may be supplied to the channel formation region of the oxide 230b through the insulator 250.

[0237] Further, the insulator 282 may have a multilayer structure. For example, it may have a structure in which an aluminum oxide film is formed by a sputtering method and a silicon nitride film is formed by a sputtering method on the aluminum oxide film.

[0238] Next, heat treatment may be performed. The heat treatment conditions described above can be used. By the heat treatment, the moisture concentration and hydrogen concentration of the insulator 280 can be reduced. In addition, the oxygen contained in the insulator 282 can be injected into the insulator 280.

[0239] Before forming the insulator 282, first, an aluminum oxide film may be formed on the insulator 280 or the like by a sputtering method, then heat treatment may be performed using the above-described heat treatment conditions, and then the aluminum oxide film may be removed by a CMP process. By this process, more excess oxygen regions can be formed in the insulator 280. In this process, a part of the insulator 280, a part of the conductor 260, and a part of the insulator 250 may be removed.

[0240] In addition, an insulator may be provided between the insulator 280 and the insulator 282. As the insulator, for example, silicon oxide formed by a sputtering method may be used. By providing the insulator, an excess oxygen region can be formed in the insulator 280.

[0241] Next, an insulator 284 may be formed on the insulator 282. The formation of the insulator 284 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. (see FIG. 1).

[0242] As described above, a semiconductor device having the transistor 200 shown in FIG. 1 can be manufactured.

[0243] Also, after the formation of the transistor 200, an opening may be formed so as to surround the transistor 200, and an insulator having high barrier properties against hydrogen or water may be formed so as to cover the opening.

[0244] Specifically, as an insulator having barrier properties, metal oxides such as aluminum oxide and nitrides such as silicon nitride may have a function of suppressing the diffusion of hydrogen (hereinafter also referred to as barrier properties against hydrogen). In particular, when compared with silicon oxide, aluminum oxide and silicon nitride have a function of suppressing the diffusion of impurities such as oxygen, water, and hydrogen.

[0245] By wrapping the transistor 200 with the above-described insulator having high barrier properties, it is possible to prevent moisture and hydrogen from entering from the outside. Alternatively, a plurality of transistors 200 may be collectively wrapped with an insulator having high barrier properties against hydrogen or water. When forming an opening so as to surround the transistor 200, for example, forming an opening reaching the insulator 214 or the insulator 222 and forming the above-described insulator having high barrier properties in contact with the insulator 214 or the insulator 222 is suitable because it can also serve as part of the manufacturing process of the transistor 200. As the insulator having high barrier properties against hydrogen or water, for example, the same material as the insulator 222 may be used.

[0246] According to one aspect of the present invention, a semiconductor device with good reliability can be provided. Further, according to one aspect of the present invention, a semiconductor device having good electrical characteristics can be provided. Further, according to one aspect of the present invention, a semiconductor device with a large on-current can be provided. Further, according to one aspect of the present invention, a semiconductor device capable of miniaturization or high integration can be provided. Further, one aspect of the present invention aims to provide a semiconductor device with low power consumption.

[0247] <Modification Example 1 of Semiconductor Device> Hereinafter, with reference to FIG. 9, an example of a semiconductor device having a transistor 200 according to one aspect of the present invention will be described.

[0248] Here, FIG. 9A shows a top view. Further, FIG. 9B is a cross-sectional view corresponding to the portion indicated by the dashed line A1 - A2 shown in FIG. 9A. Further, FIG. 9C is a cross-sectional view corresponding to the portion indicated by the dashed line A3 - A4 in FIG. 9A. Further, FIG. 9D is a cross-sectional view corresponding to the portion indicated by the dashed line A5 - A6 in FIG. 9A. In the top view of FIG. 9A, some elements are omitted for clarity of the figure.

[0249] The semiconductor device shown in FIG. 9 is different from the semiconductor device shown in FIG. 1 in that it has an oxide 230c. By arranging the oxide 230c and processing the insulator 280, the insulator 245, and the conductor 240, when an opening is provided, the defects generated on the surface of the oxide 230b or the oxide 230a can be filled. Note that the oxides 230a, 230b, and 230c may be collectively referred to as the oxide 230.

[0250] As the oxide 230c, a metal oxide that can be used for the oxide 230a or the oxide 230b can be used.

[0251] For example, when the oxide 230b is an In - Ga - Zn oxide, as the oxides 230a and 230c, an In - Ga - Zn oxide, a Ga - Zn oxide, gallium oxide, etc. may be used.

[0252] Further, the oxide 230b and the oxide 230c preferably have crystallinity. For example, it is preferable to use CAAC-OS (c-axis aligned crystalline oxide semiconductor) described later. Oxides having crystallinity such as CAAC-OS have few impurities and defects (such as oxygen deficiency) and have a dense structure with high crystallinity. Therefore, it is possible to suppress the extraction of oxygen from the oxide 230b by the source electrode or the drain electrode. Further, even when heat treatment is performed, it is possible to reduce the extraction of oxygen from the oxide 230b, so that the transistor 200 is stable against a high temperature (so-called thermal budget) in the manufacturing process.

[0253] Note that, in the transistor 200 shown in FIG. 9, the oxide 230c is shown as a single layer, but the present invention is not limited thereto. For example, the oxide 230c may have a laminated structure of two or more layers.

[0254] The film formation of the film to be the oxide 230c can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The film to be the oxide 230c may be formed using the same film formation method as that of the oxide film 230A or the oxide film 230B according to the characteristics required for the oxide film 230C. In the present embodiment, as the film to be the oxide 230c, a film is formed by a sputtering method using an In-Ga-Zn oxide target with In:Ga:Zn = 1:3:4 [atomic ratio] or 4:2:4.1 [atomic ratio]. Alternatively, as the film to be the oxide 230c, a film is formed by a sputtering method using an In-Ga-Zn oxide target with 4:2:4.1 [atomic ratio], and then a film is formed thereon using an In-Ga-Zn oxide target with In:Ga:Zn = 1:3:4 [atomic ratio].

[0255] In particular, when forming the film that becomes the oxide 230c, a part of the oxygen contained in the sputtering gas may be supplied to the oxide 230a and the oxide 230b. Therefore, the proportion of oxygen contained in the sputtering gas for the film that becomes the oxide 230c may be 70% or more, preferably 80% or more, and more preferably 100%.

[0256] Next, heat treatment may be performed. The heat treatment is performed under reduced pressure, and the insulating film 250A may be continuously formed without being exposed to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the film that becomes the oxide 230c can be removed, and further, the moisture concentration and hydrogen concentration in the oxide 230a, the oxide 230b, and the oxide film 230C can be reduced. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower.

[0257] <Modification Example 2 of Semiconductor Device> Hereinafter, with reference to FIG. 10, an example of a semiconductor device having a transistor 200 according to one aspect of the present invention will be described.

[0258] Here, FIG. 10A shows a top view. Further, FIG. 10B is a cross-sectional view corresponding to the portion indicated by the dashed-dotted line A1 - A2 shown in FIG. 10A. Further, FIG. 10C is a cross-sectional view corresponding to the portion indicated by the dashed-dotted line A3 - A4 in FIG. 10A. In the top view of FIG. 10A, some elements are omitted for clarity of the drawing.

[0259] The semiconductor device shown in FIG. 10 is different from the semiconductor device shown in FIG. 9 in that the oxide 230b has a laminated structure. Also, the oxide 230c has a laminated structure. Also, it is different in having the insulator 273 and the insulator 274.

[0260] The oxide 230c may have a laminated structure of two or more layers. For example, in FIG. 10, it has a first oxide of the oxide 230c and a second oxide of the oxide 230c disposed on the first oxide of the oxide 230c.

[0261] Specifically, the first oxide of the oxide 230c preferably contains at least one of the metal elements constituting the metal oxide used for the oxide 230b, and more preferably contains all of the metal elements. For example, an In-Ga-Zn oxide may be used as the first oxide of the oxide 230c, and an In-Ga-Zn oxide, a Ga-Zn oxide, or gallium oxide may be used as the second oxide of the oxide 230c. With this structure, the density of defect energy levels at the interface between the oxide 230b and the first oxide of the oxide 230c can be reduced.

[0262] Further, the second oxide of the oxide 230c is preferably a metal oxide that suppresses the diffusion or permeation of oxygen more than the first oxide of the oxide 230c. By providing the second oxide of the oxide 230c between the insulator 250 and the first oxide of the oxide 230c, it is possible to suppress the oxygen contained in the insulator 280 from diffusing into the insulator 250. Therefore, the oxygen is more likely to be supplied to the oxide 230b through the first oxide of the oxide 230c.

[0263] Also, in the metal oxide used for the second oxide of the oxide 230c, by making the atomic ratio of In to the metal element that is the main component smaller than the atomic ratio of In to the metal element that is the main component in the metal oxide used for the first oxide of the oxide 230c, it is possible to suppress the diffusion of In to the insulator 250 side. Since the insulator 250 functions as a gate insulator, if In mixes into the insulator 250 or the like, the characteristics of the transistor deteriorate. Therefore, by forming the oxide 230c into a laminated structure, it becomes possible to provide a highly reliable semiconductor device.

[0264] Also, the oxide 230b may have a laminated structure of two or more layers. For example, in FIG. 10, the oxide 230b has a first oxide of the oxide 230b and a second oxide of the oxide 230b disposed on the first oxide of the oxide 230b.

[0265] Specifically, the second oxide of the oxide 230b may be provided between the first oxide of the oxide 230b and the conductor 240 (conductor 240a and conductor 240b) that functions as a source electrode or a drain electrode. In this structure, it is preferable that the second oxide of the oxide 230b has a function of suppressing oxygen permeation.

[0266] Therefore, by disposing the second oxide of the oxide 230b having a function of suppressing oxygen permeation between the conductor 240 that functions as a source electrode or a drain electrode and the first oxide of the oxide 230b, it is preferable because the electrical resistance between the conductor 240 and the first oxide of the oxide 230b is reduced. By adopting such a configuration, the electrical characteristics of the transistor 200 and the reliability of the transistor 200 can be improved.

[0267] That is, since the conductor 240 and the first oxide of the oxide 230b are not in contact with each other, it is possible to suppress the conductor 240 from absorbing the oxygen of the first oxide of the oxide 230b. By preventing the oxidation of the conductor 240, it is possible to suppress a decrease in the conductivity of the conductor 240.

[0268] As the second oxide of the oxide 230b, a metal oxide containing element M may be used. In particular, as element M, aluminum, gallium, yttrium, or tin may be used. It is preferable that the concentration of element M in the second oxide of the oxide 230b is higher than that in the first oxide of the oxide 230b. Further, gallium oxide may be used as the second oxide of the oxide 230b. Further, a metal oxide such as an In-M-Zn oxide may be used as the second oxide of the oxide 230b.

[0269] Specifically, in the metal oxide used for the second oxide of the oxide 230b, the atomic ratio of the element M to In is preferably greater than the atomic ratio of the element M to In in the metal oxide used for the first oxide of the oxide 230b. Further, the film thickness of the second oxide of the oxide 230b is preferably 0.5 nm or more and 5 nm or less, more preferably 1 nm or more and 3 nm or less. Further, the second oxide of the oxide 230b preferably has crystallinity. When the second oxide of the oxide 230b has crystallinity, the release of oxygen in the first oxide of the oxide 230b can be reduced. For example, when the second oxide of the oxide 230b has a crystal structure such as a hexagonal crystal, the release of oxygen in the first oxide of the oxide 230b may be suppressed.

[0270] Further, when the conductor 240 (conductor 240a and conductor 240b) is in contact with the oxide 230, oxygen in the oxide 230 may diffuse into the conductor 240 and the conductor 240 may be oxidized. When the conductor 240 is oxidized, the probability that the conductivity of the conductor 240 decreases is high. Note that the diffusion of oxygen in the oxide 230 into the conductor 240 can be rephrased as the conductor 240 absorbing oxygen in the oxide 230.

[0271] Further, when oxygen in the oxide 230 (typically the oxide 230b) diffuses into the conductor 240, a different layer may be formed between the conductor 240 and the oxide 230. Since the different layer contains more oxygen than the conductor 240, it is presumed that the different layer has insulating properties. At this time, the three-layer structure of the conductor 240, the different layer, and the oxide 230 can be regarded as a three-layer structure composed of a metal-insulator-semiconductor, and may be called a MIS (Metal-Insulator-Semiconductor) structure, or a diode junction structure mainly composed of a MIS structure.

[0272] Further, a barrier insulator 273 may be provided so as to cover the upper surface of the conductor 240 and the side surfaces of the oxide 230a, the oxide 230b, and the conductor 240. When the insulator 273 is provided, the insulator 245 does not necessarily have to be provided.

[0273] For example, in the region where the conductor 240 of the oxide 230 overlaps, the metal element of the conductor 240 is added, or oxygen is absorbed by the conductor 240, resulting in oxygen deficiency. That is, the vicinity of the surface of the oxide 230 in contact with the conductor 240 may locally have a lower resistance. By reducing the resistance in the region where the oxide 230 and the conductor 240 overlap, the on-current of the transistor 200 can be improved.

[0274] On the other hand, the excess oxygen in the insulator 280 diffuses into the oxide 230 from the side surface of the oxide 230 in the region overlapping with the conductor 240. Therefore, the locally reduced resistance region generated in the oxide 230 in the region overlapping with the conductor 240 may decrease, and the on-current of the transistor 200 may decrease.

[0275] Therefore, by providing the insulator 273, it is possible to suppress the supply of excess oxygen from the insulator 280 to the side surface of the oxide 230 in the region overlapping with the conductor 240. On the other hand, the excess oxygen in the insulator 280 can be supplied to the channel formation region of the oxide 230b through the oxide 230c. Therefore, the oxygen deficiency generated in the channel formation region of the oxide 230 can be efficiently compensated without reducing the resistance region generated near the surface of the oxide 230 in contact with the conductor 240.

[0276] In addition, when the insulator 224 has an excess oxygen region, in the oxide 230, the excess oxygen in the insulator 224 diffuses into the oxide 230b through the oxide 230a. That is, excess oxygen can be supplied from the oxide 230a side. Therefore, while suppressing the decrease in the resistance region generated near the surface of the oxide 230 in contact with the conductor 240, the oxygen deficiency generated in the channel formation region of the oxide 230 can be compensated.

[0277] Note that the insulator 273 may be an aluminum oxide film formed using a sputtering apparatus. As the insulator 273, by forming the aluminum oxide film in an oxygen gas atmosphere, while forming the insulator 273, excess oxygen can be introduced into the insulator 224.

[0278] Also, an insulator 274 may be provided on the insulator 273. Note that the insulator 274 preferably has a function of suppressing the diffusion of oxygen, similarly to the insulator 273.

[0279] Specifically, the insulator 273 formed by the sputtering method has low film-forming properties. Therefore, it is preferable to form the insulator 274 using the ALD method. The ALD method can form a film with excellent step coverage and thickness uniformity, so it is less affected by the shape of the object to be processed and has good step coverage.

[0280] <Application Examples of Semiconductor Devices> Hereinafter, with reference to FIG. 11, an example in which the laminated structure of the interlayer film and the plug of one aspect of the present invention are applied to a semiconductor device having the transistor 200 according to this embodiment will be described.

[0281] Here, FIG. 11A shows a top view. FIG. 11B is a cross-sectional view corresponding to the portion indicated by the dashed line A1 - A2 shown in FIG. 11A. FIG. 11C is a cross-sectional view corresponding to the portion indicated by the dashed line A3 - A4 in FIG. 11A. FIG. 11D is a cross-sectional view corresponding to the portion indicated by the dashed line A5 - A6 in FIG. 11A. In the top view of FIG. 11A, some elements are omitted for clarity of the drawing.

[0282] In the semiconductor device shown in FIG. 11, the insulator 280, the insulator 282, the insulator 283, and the insulator 284 have openings exposing the transistor 200. Further, a conductor 246 (conductor 246a and conductor 246b) that functions as a plug connected to the transistor 200 is provided in the opening. Also, an insulator 247 is provided on the side surface of the opening.

[0283] Note that the conductor 246 has a function as a plug that is electrically connected to the transistor 200 or as a wiring.

[0284] In addition, the semiconductor device shown in FIG. 11 has an insulator 212 and an insulator 283 that function as barrier layers above and below the transistor 200. Also, the insulator 212 and the insulator 283 are in contact with each other in a region that is the side surface of the transistor 200 or an end portion of the substrate. That is, the semiconductor device shown in FIG. 11 has a structure in which the transistor 200 and the insulator 280 having an excess oxygen region are sealed by a barrier layer.

[0285] Also, the region where the insulator 212 and the insulator 283 are in contact may be provided along the scribe line. Further, for example, when a plurality of transistors 200 are arranged in a matrix, the region where the insulator 212 and the insulator 283 are in contact may be provided along the matrix in which the plurality of transistors are arranged.

[0286] Note that when the region where the insulator 212 and the insulator 283 are in contact is provided at the end portion of the substrate, the region may be provided so as to overlap with the scribe line.

[0287] Note that the insulator 283 is provided on the insulator 282. The insulator 284 uses a material having a large etch rate selectivity with respect to the conductor 248 when processing the conductor 248. Therefore, the insulator 284 may be provided on the insulator 283 as necessary.

[0288] Also, it is preferable that the insulator 247 is in contact with the insulator 283. By the insulator 247 and the insulator 283 being in contact with each other, the transistor 200 and the insulator 280 having an excess oxygen region are sealed by a barrier layer.

[0289] Specifically, the insulator 247 is provided in contact with the side walls of the openings of the insulator 283, the insulator 282, and the insulator 280, and the conductor 246 is formed in contact with the side surface thereof. The transistor 200 is located at at least a part of the bottom of the opening, and the conductor 246 is in contact with the transistor 200.

[0290] In addition, in the <Modification Example of Semiconductor Device> and <Application Example of Semiconductor Device>, the same reference numerals are assigned to structures having the same functions as the structures constituting the semiconductor device shown in the <Configuration Example of Semiconductor Device>. Note that, also in this item, as the constituent material of the semiconductor device, the materials described in detail in the <Configuration Example of Semiconductor Device> can be used.

[0291] From the above, a semiconductor device with good reliability can be provided. Also, a semiconductor device having good electrical characteristics can be provided. Also, a semiconductor device capable of miniaturization or high integration can be provided. Also, a semiconductor device with low power consumption can be provided.

[0292] As described above, the configurations, methods, etc. shown in the present embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments and examples.

[0293] (Embodiment 2) In this embodiment, one form of the semiconductor device will be described with reference to FIGS. 12 and 13.

[0294] [Storage Device 1] An example of a semiconductor device (memory device) using a capacitive element, which is one aspect of the present invention, is shown in FIG. 12. In the semiconductor device of one aspect of the present invention, the transistor 200 is provided above the transistor 300, and the capacitive element 100 is provided above the transistor 200. It is preferable that at least a part of the capacitive element 100 or the transistor 300 overlaps with the transistor 200. Thereby, since the occupied area in the top view of the capacitive element 100, the transistor 200, and the transistor 300 can be reduced, the semiconductor device according to the present embodiment can be miniaturized or highly integrated. Note that the semiconductor device according to the present embodiment can be applied to, for example, a logic circuit typified by a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit), or a memory circuit typified by a DRAM (Dynamic Random Access Memory) or an NVM (Non-Volatile Memory).

[0295] Note that, as the transistor 200, the transistor 200 described in the previous embodiment can be used. Therefore, regarding the transistor 200 and the layer including the transistor 200, the description of the previous embodiment can be referred to.

[0296] Transistor 200 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. Since transistor 200 has a small off-current, by using this in a memory device, it is possible to hold the stored content for a long time. That is, since it does not require a refresh operation or the frequency of the refresh operation is extremely low, the power consumption of the memory device can be sufficiently reduced. Further, compared with a transistor using silicon in the semiconductor layer, transistor 200 has good electrical characteristics at high temperatures. For example, transistor 200 exhibits good electrical characteristics even in the temperature range of 125°C to 150°C. Also, in the temperature range of 125°C to 150°C, transistor 200 has an on / off ratio of the transistor of 10 digits or more. In other words, compared with a transistor using silicon in the semiconductor layer, transistor 200 has characteristics such as on-current, which is an example of transistor characteristics, and frequency characteristics that are more excellent as the temperature increases.

[0297] In the semiconductor device shown in FIG. 12, wiring 1001 is electrically connected to the source of transistor 300, wiring 1002 is electrically connected to the drain of transistor 300, and wiring 1007 is electrically connected to the gate of transistor 300. Also, wiring 1003 is electrically connected to one of the source and drain of transistor 200, wiring 1004 is electrically connected to the first gate of transistor 200, and wiring 1006 is electrically connected to the second gate of transistor 200. Then, the other of the source and drain of transistor 200 is electrically connected to one of the electrodes of capacitor element 100, and wiring 1005 is electrically connected to the other of the electrodes of capacitor element 100.

[0298] The semiconductor device shown in Fig. 12 has the characteristic that the charge charged on one of the electrodes of the capacitive element 100 can be held by the switching of the transistor 200, so that writing, holding, and reading of information are possible. Also, the transistor 200 is an element provided with a back gate in addition to the source, gate (top gate), and drain. That is, since it is a four-terminal element, compared with two-terminal elements typified by MRAM (Magnetoresistive Random Access Memory), ReRAM (Resistive Random Access Memory), phase-change memory, etc. that utilize MTJ (Magnetic Tunnel Junction) characteristics, it has the feature that independent control of input and output can be easily performed. Also, in MRAM, ReRAM, and phase-change memory, structural changes may occur at the atomic level when information is rewritten. On the other hand, the semiconductor device shown in Fig. 12 operates by the charge or discharge of electrons using the transistor and the capacitive element when information is rewritten, so it has the features of excellent repeated rewrite resistance and few structural changes.

[0299] Also, the semiconductor device shown in Fig. 12 can form a memory cell array by arranging it in a matrix. In this case, the transistor 300 can be used as a read circuit or a drive circuit connected to the memory cell array. Also, the semiconductor device shown in Fig. 12 forms a memory cell array as described above. When the semiconductor device shown in Fig. 12 is used as a memory element, for example, an operating frequency of 200 MHz or more can be achieved in the range where the drive voltage is 2.5 V and the evaluation environment temperature is from -40°C to 85°C.

[0300] <Transistor 300> The transistor 300 is provided on the substrate 311 and has a conductor 316 that functions as a gate electrode, an insulator 315 that functions as a gate insulator, a semiconductor region 313 that is part of the substrate 311, and low-resistance regions 314a and 314b that function as a source region or a drain region.

[0301] Here, an insulator 315 is disposed on the semiconductor region 313, and a conductor 316 is disposed on the insulator 315. Further, the transistors 300 formed in the same layer are electrically separated by an insulator 312 that functions as an element isolation insulating layer. As the insulator 312, an insulator similar to the insulator 326 described later can be used. The transistor 300 may be either a p-channel type or an n-channel type.

[0302] The substrate 311 preferably includes a semiconductor such as a silicon-based semiconductor in a region where a channel of the semiconductor region 313 is formed, a region in the vicinity thereof, a source region, or a low-resistance region 314a or 314b that serves as a drain region, and preferably includes single-crystalline silicon. Alternatively, it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may also be used. Alternatively, by using GaAs and GaAlAs or the like, the transistor 300 may be a HEMT (High Electron Mobility Transistor).

[0303] The low-resistance regions 314a and 314b include, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron.

[0304] As the conductor 316 that functions as a gate electrode, a conductive material such as a semiconductor material such as silicon, a metal material, an alloy material, or a metal oxide material that contains an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron can be used.

[0305] Note that since the work function is determined by the material of the conductor, the threshold voltage can be adjusted by changing the material of the conductor. Specifically, it is preferable to use materials such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embedability, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and in particular, using tungsten is preferable in terms of heat resistance.

[0306] Here, in the transistor 300 shown in FIG. 12, the semiconductor region 313 (a part of the substrate 311) where the channel is formed has a convex shape. Also, the side surface and the upper surface of the semiconductor region 313 are provided so as to be covered with the conductor 316 via the insulator 315. Since such a transistor 300 utilizes the convex portion of the semiconductor substrate, it is also called a FIN type transistor. Note that an insulator that functions as a mask for forming the convex portion may be in contact with the upper portion of the convex portion. Further, although the case where a part of the semiconductor substrate is processed to form the convex portion is shown here, an SOI substrate may be processed to form a semiconductor film having a convex shape.

[0307] Note that the transistor 300 shown in FIG. 12 is an example and is not limited to its structure, and an appropriate transistor may be used according to the circuit configuration and the driving method.

[0308] Further, as shown in FIG. 12, the semiconductor device is provided with the transistor 300 and the transistor 200 stacked. For example, the transistor 300 can be formed of a silicon-based semiconductor material, and the transistor 200 can be formed of an oxide semiconductor. In this way, the semiconductor device shown in FIG. 12 can be formed by mixing a silicon-based semiconductor material and an oxide semiconductor in different layers. Also, the semiconductor device shown in FIG. 12 can be manufactured by the same process as the manufacturing apparatus used for the silicon-based semiconductor material, and high integration is also possible.

[0309] <Capacitor element> The capacitive element 100 includes an insulator 114 on an insulator 160, an insulator 140 on the insulator 114, a conductor 110 disposed in an opening formed in the insulator 114 and the insulator 140, an insulator 130 on the conductor 110 and the insulator 140, a conductor 120 on the insulator 130, and an insulator 150 on the conductor 120 and the insulator 130. Here, at least a part of the conductor 110, the insulator 130, and the conductor 120 is disposed in the opening formed in the insulator 114 and the insulator 140.

[0310] The conductor 110 functions as a lower electrode of the capacitive element 100, the conductor 120 functions as an upper electrode of the capacitive element 100, and the insulator 130 functions as a dielectric of the capacitive element 100. In the capacitive element 100, at the opening of the insulator 114 and the insulator 140, not only the bottom surface but also the side surfaces are configured such that the upper electrode and the lower electrode face each other with the dielectric interposed therebetween, and the capacitance per unit area can be increased. Therefore, the deeper the depth of the opening, the larger the capacitance of the capacitive element 100 can be. By increasing the capacitance per unit area of the capacitive element 100 in this way, miniaturization or high integration of the semiconductor device can be promoted.

[0311] The insulator 114 and the insulator 150 may be made of an insulator that can be used for the insulator 280. Further, the insulator 140 preferably functions as an etching stopper when forming the opening of the insulator 114, and may be made of an insulator that can be used for the insulator 214.

[0312] The shape of the opening formed in the insulator 114 and the insulator 140 as viewed from above may be a quadrilateral, a polygon other than a quadrilateral, a shape in which the corners are curved in a polygon, or a circular shape including an ellipse. Here, in a top view, it is preferable that the area of the overlap between the opening and the transistor 200 is larger. By adopting such a configuration, the occupied area of the semiconductor device having the capacitive element 100 and the transistor 200 can be reduced.

[0313] The conductor 110 is disposed in contact with the insulator 140 and the opening formed in the insulator 114. Preferably, the upper surface of the conductor 110 substantially coincides with the upper surface of the insulator 140. Further, a conductor 152 provided on the insulator 160 is in contact with the lower surface of the conductor 110. The conductor 110 is preferably formed by using a method such as ALD method or CVD method. For example, a conductor that can be used for the conductor 205 may be used.

[0314] The insulator 130 is disposed so as to cover the conductor 110 and the insulator 140. For example, it is preferable to form the insulator 130 by using a method such as ALD method or CVD method. The insulator 130 may be formed of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, zirconium oxide, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, etc., and can be provided in a laminated or single layer structure. For example, as the insulator 130, an insulating film laminated in the order of zirconium oxide, aluminum oxide, and zirconium oxide can be used.

[0315] Further, for the insulator 130, it is preferable to use a material having a high dielectric breakdown strength such as silicon oxynitride or a high dielectric constant (high-k) material. Alternatively, a laminated structure of a material having a high dielectric breakdown strength and a high dielectric constant (high-k) material may be used.

[0316] Note that examples of the insulator of the high dielectric constant (high-k) material (material having a high relative dielectric constant) include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, nitrides containing silicon and hafnium, etc. By using such a high-k material, even if the insulator 130 is thickened, the capacitance of the capacitor element 100 can be sufficiently ensured. By thickening the insulator 130, the leakage current generated between the conductor 110 and the conductor 120 can be suppressed.

[0317] On the other hand, examples of materials with high dielectric breakdown strength include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with pores, resins, and the like. For example, silicon nitride (SiN x ) formed by ALD method, silicon oxide (SiO x ) formed by PEALD method, and silicon nitride (SiN x ) formed by ALD method can be used as the insulating film laminated in this order. By using such an insulator with high dielectric breakdown strength, the dielectric breakdown strength can be improved, and the electrostatic breakdown of the capacitor element 100 can be suppressed.

[0318] The conductor 120 is disposed so as to fill the openings formed in the insulator 140 and the insulator 114. Also, the conductor 120 is electrically connected to the wiring 1005 via the conductor 112 and the conductor 153. The conductor 120 is preferably formed by using ALD method, CVD method, or the like. For example, a conductor that can be used for the conductor 205 may be used.

[0319] In addition, since the transistor 200 has a configuration using an oxide semiconductor, it has excellent compatibility with the capacitor element 100. Specifically, the transistor 200 using an oxide semiconductor has a small off-current, so that it is possible to retain the stored content for a long time when used in combination with the capacitor element 100.

[0320] <Wiring layer> A wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided between each structure. Also, a plurality of wiring layers can be provided according to the design. Here, conductors that function as plugs or wiring may be given the same reference numeral for a plurality of structures. Also, in this specification and the like, the wiring and the plug electrically connected to the wiring may be an integral body. That is, a part of the conductor may function as wiring, and a part of the conductor may function as a plug.

[0321] For example, on the transistor 300, as an interlayer film, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked and provided. Further, in the insulator 320, the insulator 322, the insulator 324, and the insulator 326, a conductor 328 that is electrically connected to a conductor 153 functioning as a terminal, a conductor 330, and the like are embedded. Note that the conductor 328 and the conductor 330 function as plugs or wirings.

[0322] Further, the insulator functioning as an interlayer film may function as a planarization film that covers the uneven shape below it. For example, the upper surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance flatness.

[0323] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. 12, an insulator 350, an insulator 352, and an insulator 354 are sequentially stacked and provided. Further, in the insulator 350, the insulator 352, and the insulator 354, a conductor 356 is formed. The conductor 356 functions as a plug or a wiring.

[0324] On the insulator 354 and the conductor 356, an insulator 210, an insulator 212, an insulator 214, and an insulator 216 are sequentially stacked and provided. Further, in the insulator 210, the insulator 212, the insulator 214, and the insulator 216, a conductor 218 and a conductor (conductor 205) that constitutes the transistor 200 are embedded. Note that the conductor 218 functions as a plug or a wiring that is electrically connected to the transistor 300.

[0325] In addition, conductors such as the conductor 112 and the conductors (conductor 120, conductor 110) constituting the capacitor element 100 are embedded in the insulator 114, insulator 140, insulator 130, insulator 150, and insulator 154. Note that the conductor 112 functions as a plug or wiring that electrically connects the capacitor element 100, the transistor 200, or the transistor 300 to the conductor 153 that functions as a terminal.

[0326] In addition, the conductor 153 is provided on the insulator 154, and the conductor 153 is covered with the insulator 156. Here, the conductor 153 is in contact with the upper surface of the conductor 112 and functions as a terminal of the capacitor element 100, the transistor 200, or the transistor 300.

[0327] Note that examples of insulators that can be used as interlayer films include insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, metal nitride oxides, and the like. For example, an insulator that functions as an interlayer film can reduce the parasitic capacitance generated between wirings by using a material with a low relative permittivity. Therefore, the material may be selected according to the function of the insulator.

[0328] For example, it is preferable that insulators such as insulator 320, insulator 322, insulator 326, insulator 352, insulator 354, insulator 212, insulator 114, insulator 150, and insulator 156 have a low dielectric constant. For example, the insulator preferably includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with pores, resin, and the like. Or, the insulator preferably has a laminated structure of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen or silicon oxide with pores, and resin. Since silicon oxide and silicon oxynitride are thermally stable, a laminated structure that is thermally stable and has a low dielectric constant can be obtained by combining them with resin. Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic.

[0329] In addition, the resistivity of the insulator provided above or below the conductor 152 or conductor 153 is 1.0×10 12 Ωcm or more and 1.0×10 15 Ωcm or less, preferably 5.0×10 12 Ωcm or more and 1.0×10 14 Ωcm or less, more preferably 1.0×10 13 Ωcm or more and 5.0×10 13 Ωcm or less. By setting the resistivity of the insulator provided above or below the conductor 152 or conductor 153 within the above range, the insulator can disperse the charges accumulated between wirings such as the transistor 200, transistor 300, capacitor element 100, and conductor 152 while maintaining insulation, and can suppress characteristic defects and electrostatic breakdown of the transistor due to the charges and the semiconductor device having the transistor, which is preferable. As such an insulator, silicon nitride or silicon nitride oxide can be used. For example, the resistivity of the insulator 160 or insulator 154 may be set within the above range.

[0330] In addition, a transistor using an oxide semiconductor can have its electrical characteristics stabilized by surrounding it with an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen. Therefore, as the insulator 324, insulator 350, insulator 210, etc., an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen may be used.

[0331] As the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum may be used in a single layer or in a stacked layer. Specifically, as the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide or tantalum oxide, silicon oxynitride or silicon nitride can be used.

[0332] As the conductor that can be used for wiring and plugs, a material containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. can be used. Also, a semiconductor having a high electrical conductivity typified by polycrystalline silicon containing impurity elements such as phosphorus, or a silicide such as nickel silicide may be used.

[0333] For example, as the conductors 328, 330, 356, 218, 112, 152, 153, etc., conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials formed of the above materials can be used singly or in a laminated manner. It is preferable to use high melting point materials such as tungsten and molybdenum that achieve both heat resistance and conductivity, and it is more preferable to use tungsten. Alternatively, it is preferable to form them with low resistance conductive materials such as aluminum and copper. By using a low resistance conductive material, the wiring resistance can be lowered.

[0334] <Wiring or plug of the layer provided with the oxide semiconductor> In addition, when an oxide semiconductor is used for the transistor 200, an insulator having an excess oxygen region may be provided in the vicinity of the oxide semiconductor. In that case, it is preferable to provide a barrier insulator between the insulator having the excess oxygen region and the conductor provided on the insulator having the excess oxygen region.

[0335] For example, in FIG. 12, it is advisable to provide an insulator 247 between the insulator 280 having excess oxygen and the conductor 248. By providing the insulator 247 and the insulator 282 in contact with each other, the conductor 248 and the transistor 200 can be structured to be sealed by the barrier insulator.

[0336] That is, by providing the insulator 247, it is possible to suppress the absorption of the excess oxygen possessed by the insulator 280 by the conductor 248. Further, by having the insulator 247, it is possible to suppress the diffusion of hydrogen, which is an impurity, to the transistor 200 through the conductor 248.

[0337] Here, the conductor 248 functions as a plug or wiring that is electrically connected to the transistor 200 or the transistor 300.

[0338] Specifically, an insulator 247 is provided in contact with the sidewall of the opening of the insulator 284, the insulator 282, and the insulator 280, and a conductor 248 is formed in contact with its side surface. A conductor 240 is located at at least a part of the bottom of the opening, and the conductor 248 is in contact with the conductor 240.

[0339] The conductor 248 is preferably made of a conductive material mainly composed of tungsten, copper, or aluminum. Also, the conductor 248 may have a laminated structure. Note that in the transistor 200, a configuration in which the conductor 248 is provided as a two-layer laminated structure is shown, but the present invention is not limited to this. For example, the conductor 248 may be provided as a single layer or a laminated structure of three or more layers.

[0340] Also, when the conductor 248 has a laminated structure, the conductor that is in contact with the conductor 240 and is in contact with the insulator 280, the insulator 282, and the insulator 284 via the insulator 247 is preferably made of a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. Also, the conductive material having a function of suppressing the permeation of impurities such as water and hydrogen may be used singly or in a laminate. By using the conductive material, it is possible to prevent oxygen added to the insulator 280 from being absorbed by the conductor 248. Also, it is possible to suppress impurities such as water and hydrogen contained in the upper layer than the insulator 284 from diffusing to the oxide 230 through the conductor 248.

[0341] As the insulator 247, for example, an insulator that can be used for the insulator 214 or the like may be used. The insulator 247 can suppress impurities such as water and hydrogen contained in the insulator 280 from diffusing to the oxide 230 through the conductor 248. Also, it is possible to prevent oxygen contained in the insulator 280 from being absorbed by the conductor 248.

[0342] Further, although not shown, a conductor 152 that functions as a wiring may be disposed in contact with the upper surface of the upper surface of the conductor 248. As the conductor that functions as a wiring, it is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum. Further, the conductor may have a laminated structure, for example, a laminate of titanium or titanium nitride and the above conductive material. Note that the conductor may be formed so as to be embedded in an opening provided in an insulator.

[0343] The above is the description of the configuration example. By using this configuration, a semiconductor device using a transistor having an oxide semiconductor can be miniaturized or highly integrated. Further, in a semiconductor device using a transistor having an oxide semiconductor, variations in electrical characteristics can be suppressed and reliability can be improved. Further, a transistor having an oxide semiconductor with a large on-current can be provided. Further, a transistor having an oxide semiconductor with a small off-current can be provided. Further, a semiconductor device with reduced power consumption can be provided.

[0344] [Storage device 2] An example of a semiconductor device (storage device) using the semiconductor device according to one aspect of the present invention is shown in FIG. 13. The semiconductor device shown in FIG. 13 has a transistor 200, a transistor 300, and a capacitor element 100, similar to the semiconductor device shown in FIG. 12. However, the semiconductor device shown in FIG. 13 is different from the semiconductor device shown in FIG. 12 in that the capacitor element 100 is of a planar type and the transistor 200 and the transistor 300 are electrically connected.

[0345] In a semiconductor device according to one aspect of the present invention, the transistor 200 is provided above the transistor 300, and the capacitor element 100 is provided above the transistor 300 and the transistor 200. It is preferable that at least a part of the capacitor element 100 or the transistor 300 overlaps with the transistor 200. Thereby, since the occupied area in the top view of the capacitor element 100, the transistor 200, and the transistor 300 can be reduced, the semiconductor device according to the present embodiment can be miniaturized or highly integrated.

[0346] Note that the above-described transistors 200 and 300 can be used as the transistors 200 and 300. Therefore, regarding the transistors 200 and 300 and the layers including them, the above description can be referred to.

[0347] In the semiconductor device shown in FIG. 13, the wiring 2001 is electrically connected to the source of the transistor 300, and the wiring 2002 is electrically connected to the drain of the transistor 300. Also, the wiring 2003 is electrically connected to one of the source and drain of the transistor 200, the wiring 2004 is electrically connected to the first gate of the transistor 200, and the wiring 2006 is electrically connected to the second gate of the transistor 200. Then, the gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor element 100, and the wiring 2005 is electrically connected to the other of the electrodes of the capacitor element 100. Note that, hereinafter, the node at which the gate of the transistor 300, the other of the source and drain of the transistor 200, and one of the electrodes of the capacitor element 100 are connected may be referred to as the node FG.

[0348] The semiconductor device shown in FIG. 13 has the characteristic that the potential of the gate (node FG) of the transistor 300 can be held by the switching of the transistor 200, so that information can be written, held, and read out.

[0349] In addition, the semiconductor device shown in FIG. 13 can form a memory cell array by being arranged in a matrix.

[0350] Since the layer including the transistor 300 has the same structure as the semiconductor device shown in FIG. 12, the structure below the insulator 354 can refer to the above description.

[0351] On the insulator 354, the insulators 210, 212, 214, and 216 are arranged. Here, as with the insulator 350 and the like, an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen can be used as the insulator 210.

[0352] The conductor 218 is embedded in the insulators 210, 212, 214, and 216. The conductor 218 functions as a plug or wiring that is electrically connected to the capacitor element 100, the transistor 200, or the transistor 300. For example, the conductor 218 is electrically connected to the conductor 316 that functions as the gate electrode of the transistor 300.

[0353] In addition, the conductor 248 functions as a plug or wiring that is electrically connected to the transistor 200 or the transistor 300. For example, the conductor 248 electrically connects the conductor 240b that functions as the other of the source and drain of the transistor 200 and the conductor 110 that functions as one of the electrodes of the capacitor element 100 via the conductor 248.

[0354] In addition, the planar capacitor element 100 is provided above the transistor 200. The capacitor element 100 has a conductor 110 that functions as a first electrode, a conductor 120 that functions as a second electrode, and an insulator 130 that functions as a dielectric. Note that the conductor 110, the conductor 120, and the insulator 130 described in the above storage device 1 can be used.

[0355] Conductor 153 and conductor 110 are provided in contact with the upper surface of conductor 248. Conductor 153 is in contact with the upper surface of conductor 248 and functions as a terminal of transistor 200 or transistor 300.

[0356] Conductor 153 and conductor 110 are covered by insulator 130, and conductor 120 is arranged so as to overlap conductor 110 via insulator 130. Further, insulator 114 is arranged on conductor 120 and insulator 130.

[0357] Also, in FIG. 13, an example in which a planar capacitor element is used as capacitor element 100 has been shown, but the semiconductor device shown in this embodiment is not limited to this. For example, as capacitor element 100, a cylindrical capacitor element 100 as shown in FIG. 12 may be used.

[0358] [Storage device 3] An example of a storage device using the semiconductor device which is one aspect of the present invention is shown in FIG. 14. The storage device shown in FIG. 14 has transistor 400 in addition to the semiconductor device having transistor 200, transistor 300, and capacitor element 100 shown in FIG. 13.

[0359] Transistor 400 can control the second gate voltage of transistor 200. For example, the first gate and the second gate of transistor 400 are diode-connected to the source, and the source of transistor 400 and the second gate of transistor 200 are connected. When the negative potential of the second gate of transistor 200 is held in this configuration, the voltage between the first gate and the source and the voltage between the second gate and the source of transistor 400 become 0V. In transistor 400, since the drain current when the second gate voltage and the first gate voltage are 0V is very small, the negative potential of the second gate of transistor 200 can be maintained for a long time without supplying power to transistor 200 and transistor 400. Thereby, the storage device having transistor 200 and transistor 400 can retain the stored content for a long time.

[0360] Therefore, in FIG. 14, wiring 1001 is electrically connected to the source of transistor 300, and wiring 1002 is electrically connected to the drain of transistor 300. Also, wiring 1003 is electrically connected to one of the source and drain of transistor 200, wiring 1004 is electrically connected to the gate of transistor 200, and wiring 1006 is electrically connected to the back gate of transistor 200. Then, the gate of transistor 300, and the other of the source and drain of transistor 200 are electrically connected to one of the electrodes of capacitor element 100, and wiring 1005 is electrically connected to the other of the electrodes of capacitor element 100. Wiring 1007 is electrically connected to the source of transistor 400, wiring 1008 is electrically connected to the gate of transistor 400, wiring 1009 is electrically connected to the back gate of transistor 400, and wiring 1010 is electrically connected to the drain of transistor 400. Here, wiring 1006, wiring 1007, wiring 1008, and wiring 1009 are electrically connected.

[0361] Also, the memory device shown in FIG. 14 can form a memory cell array by being arranged in a matrix, similar to the memory devices shown in FIGS. 12 and 13. Note that one transistor 400 can control the second gate voltage of a plurality of transistors 200. Therefore, it is preferable to provide transistor 400 in a smaller number than transistor 200.

[0362] <Transistor 400> Transistor 400 is formed in the same layer as transistor 200 and can be fabricated in parallel. Transistor 400 includes a conductor 460 (conductor 460a and conductor 460b) that functions as a first gate electrode, a conductor 405 that functions as a second gate electrode, insulators 222, 224, and 450 that function as a gate insulating layer, an oxide 430c having a region where a channel is formed, conductors 440a, oxides 431a, and oxides 431b that function as one of a source or a drain, conductors 440b, oxides 432a, and oxides 432b that function as the other of the source or the drain, and insulators 445a and 445b that function as a barrier layer.

[0363] In transistor 400, conductor 405 is in the same layer as conductor 205. Oxides 431a and 432a are in the same layer as oxide 230a, and oxides 431b and 432b are in the same layer as oxide 230b. Conductors 440 (conductor 440a and conductor 440b) are in the same layer as conductor 240. Insulators 445 (insulator 445a and insulator 445b) are in the same layer as insulator 245. Oxide 430c is in the same layer as oxide 230c. Insulator 450 is in the same layer as insulator 250. Conductor 460 is in the same layer as conductor 260.

[0364] Note that structures formed in the same layer can be formed simultaneously. For example, oxide 430c can be formed by processing the oxide film that becomes oxide 230c.

[0365] Oxide 430c, which functions as the active layer of transistor 400, has reduced oxygen deficiency and reduced impurities such as hydrogen or water, similar to oxide 230 and the like. As a result, the threshold voltage of transistor 400 can be made greater than 0 V, the off-current can be reduced, and the drain current when the second gate voltage and the first gate voltage are 0 V can be made very small.

[0366] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments and the like.

[0367] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments, examples, and the like.

[0368] (Embodiment 3) In this embodiment, with reference to FIGS. 15 and 16, a transistor using an oxide as a semiconductor (hereinafter sometimes referred to as an OS transistor), which is an aspect of the present invention, and a storage device (hereinafter sometimes referred to as an OS memory device) to which a capacitor element is applied will be described. The OS memory device is a storage device having at least a capacitor element and an OS transistor that controls the charging and discharging of the capacitor element. Since the off-current of the OS transistor is extremely small, the OS memory device has excellent holding characteristics and can function as a non-volatile memory.

[0369] <Configuration example of the storage device> FIG. 15A shows an example of the configuration of the OS memory device. The storage device 1400 includes a peripheral circuit 1411 and a memory cell array 1470. The peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.

[0370] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, and the like. The precharge circuit has a function of precharging the wiring. The sense amplifier has a function of amplifying the data signal read from the memory cell. The above-mentioned wiring is the wiring connected to the memory cells included in the memory cell array 1470, which will be described in detail later. The amplified data signal is output to the outside of the storage device 1400 as a data signal RDATA via the output circuit 1440. The row circuit 1420 includes, for example, a row decoder, a word line driver circuit, and the like, and can select the row to be accessed.

[0371] The memory device 1400 is supplied with a low power supply voltage (VSS) as a power supply voltage from the outside, a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470. Further, control signals (CE, WE, RE), an address signal ADDR, and a data signal WDATA are input to the memory device 1400 from the outside. The address signal ADDR is input to a row decoder and a column decoder, and WDATA is input to a write circuit.

[0372] The control logic circuit 1460 processes input signals (CE, WE, RE) from the outside and generates control signals for the row decoder and the column decoder. CE is a chip enable signal, WE is a write enable signal, and RE is a read enable signal. The signals processed by the control logic circuit 1460 are not limited to these, and other control signals may be input as necessary.

[0373] The memory cell array 1470 has a plurality of memory cells MC arranged in a matrix and a plurality of wirings. Note that the number of wirings connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cell MC, the number of memory cells MC in a column, etc. Also, the number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cell MC, the number of memory cells MC in a row, etc.

[0374] In FIG. 15A, an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane is shown, but the present embodiment is not limited to this. For example, as shown in FIG. 15B, the memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411. For example, a configuration in which a sense amplifier is provided so as to overlap under the memory cell array 1470 may be adopted.

[0375] A configuration example of a memory cell applicable to the above-described memory cell MC will be described with reference to FIG. 16.

[0376] [DOSRAM] Figures 16A to 16C show circuit configuration examples of memory cells of a DRAM. In this specification and the like, a DRAM using a 1OS transistor 1 capacitor type memory cell may be referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 1471 shown in FIG. 16A has a transistor M1 and a capacitor element CA. Note that the transistor M1 has a gate (which may be called a top gate) and a back gate.

[0377] The first terminal of the transistor M1 is connected to the first terminal of the capacitor element CA, the second terminal of the transistor M1 is connected to the wiring BIL, the gate of the transistor M1 is connected to the wiring WOL, and the back gate of the transistor M1 is connected to the wiring BGL. The second terminal of the capacitor element CA is connected to the wiring CAL.

[0378] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor element CA. It is preferable to apply a low-level potential to the wiring CAL during data writing and reading. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M1 can be increased or decreased.

[0379] Here, the memory cell 1471 shown in FIG. 16A corresponds to the storage device shown in FIG. 12. That is, the transistor M1 corresponds to the transistor 200, the capacitor element CA corresponds to the capacitor element 100, the wiring BIL corresponds to the wiring 1003, the wiring WOL corresponds to the wiring 1004, the wiring BGL corresponds to the wiring 1006, and the wiring CAL corresponds to the wiring 1005. Note that the transistor 300 described in FIG. 12 corresponds to the transistor provided in the peripheral circuit 1411 of the storage device 1400 shown in FIG. 15B.

[0380] Also, the memory cell MC is not limited to the memory cell 1471, and the circuit configuration can be changed. For example, the memory cell MC may be configured such that the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1472 shown in FIG. 16B. Further, for example, the memory cell MC may be a memory cell composed of a transistor having a single gate structure, that is, a transistor M1 without a back gate, as in the memory cell 1473 shown in FIG. 16C.

[0381] When the semiconductor device shown in the above embodiment is used for the memory cell 1471 or the like, the transistor 200 can be used as the transistor M1, and the capacitor element 100 can be used as the capacitor element CA. By using the OS transistor as the transistor M1, the leakage current of the transistor M1 can be made very low. That is, since the written data can be held by the transistor M1 for a long time, the frequency of refreshing the memory cell can be reduced. Further, the refresh operation of the memory cell can be made unnecessary. Also, since the leakage current is very low, multi-value data or analog data can be held for the memory cell 1471, the memory cell 1472, and the memory cell 1473.

[0382] Also, in the DOSRAM, when the sense amplifier is provided so as to overlap below the memory cell array 1470 as described above, the bit line can be shortened. Thereby, the bit line capacitance becomes small, and the holding capacitance of the memory cell can be reduced.

[0383] [NOSRAM] Figures 16D to 16G show circuit configuration examples of gain cell type memory cells of a two-transistor one-capacitor element. The memory cell 1474 shown in Figure 16D includes a transistor M2, a transistor M3, and a capacitor element CB. Note that the transistor M2 has a top gate (sometimes simply referred to as a gate) and a back gate. In this specification and the like, a storage device having a gain cell type memory cell using the transistor M2 as an OS transistor may be referred to as a NOSRAM (Nonvolatile Oxide Semiconductor RAM).

[0384] The first terminal of the transistor M2 is connected to the first terminal of the capacitor element CB, the second terminal of the transistor M2 is connected to the wiring WBL, the gate of the transistor M2 is connected to the wiring WOL, and the back gate of the transistor M2 is connected to the wiring BGL. The second terminal of the capacitor element CB is connected to the wiring CAL. The first terminal of the transistor M3 is connected to the wiring RBL, the second terminal of the transistor M3 is connected to the wiring SL, and the gate of the transistor M3 is connected to the first terminal of the capacitor element CB.

[0385] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor element CB. It is preferable to apply a low-level potential to the wiring CAL during data writing, during data holding, and during data reading. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M2 can be increased or decreased.

[0386] Here, the memory cell 1474 shown in FIG. 16D corresponds to the memory device shown in FIG. 13. That is, the transistor M2 corresponds to the transistor 200, the capacitive element CB corresponds to the capacitive element 100, the transistor M3 corresponds to the transistor 300, the wiring WBL corresponds to the wiring 2003, the wiring WOL corresponds to the wiring 2004, the wiring BGL corresponds to the wiring 2006, the wiring CAL corresponds to the wiring 2005, the wiring RBL corresponds to the wiring 2002, and the wiring SL corresponds to the wiring 2001.

[0387] Also, the memory cell MC is not limited to the memory cell 1474, and the circuit configuration can be appropriately changed. For example, the memory cell MC may be configured such that the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1475 shown in FIG. 16E. Further, for example, the memory cell MC may be a memory cell composed of a transistor having a single gate structure, that is, a transistor M2 having no back gate, as in the memory cell 1476 shown in FIG. 16F. Further, for example, the memory cell MC may have a configuration in which the wiring WBL and the wiring RBL are combined into a single wiring BIL, as in the memory cell 1477 shown in FIG. 16G.

[0388] When the semiconductor device shown in the above embodiment is used for the memory cell 1474 or the like, the transistor 200 can be used as the transistor M2, the transistor 300 can be used as the transistor M3, and the capacitive element 100 can be used as the capacitive element CB. By using an OS transistor as the transistor M2, the leakage current of the transistor M2 can be made very low. As a result, the written data can be held by the transistor M2 for a long time, so that the frequency of refreshing the memory cell can be reduced. Further, the refresh operation of the memory cell can be made unnecessary. Also, since the leakage current is very low, multi-valued data or analog data can be held in the memory cell 1474. The same applies to the memory cells 1475 to 1477.

[0389] Note that the transistor M3 may be a transistor having silicon in the channel formation region (hereinafter sometimes referred to as an Si transistor). The conductivity type of the Si transistor may be an n-channel type or a p-channel type. The Si transistor may have a higher field-effect mobility than the OS transistor. Therefore, an Si transistor may be used as the transistor M3 that functions as a read transistor. Also, by using an Si transistor for the transistor M3, the transistor M2 can be provided by stacking it on the transistor M3, so that the occupied area of the memory cell can be reduced and high integration of the storage device can be achieved.

[0390] Also, the transistor M3 may be an OS transistor. When OS transistors are used for the transistor M2 and the transistor M3, the memory cell array 1470 can be configured with a circuit using only n-type transistors.

[0391] Also, FIG. 16H shows an example of a gain cell type memory cell of a three-transistor one-capacitor element. The memory cell 1478 shown in FIG. 16H has transistors M4 to M6 and a capacitor element CC. The capacitor element CC is provided as appropriate. The memory cell 1478 is electrically connected to a wiring BIL, a wiring RWL, a wiring WWL, a wiring BGL, and a wiring GNDL. The wiring GNDL is a wiring that gives a low-level potential. Note that the memory cell 1478 may be electrically connected to a wiring RBL or a wiring WBL instead of the wiring BIL.

[0392] The transistor M4 is an OS transistor having a back gate, and the back gate is electrically connected to the wiring BGL. Note that the back gate and the gate of the transistor M4 may be electrically connected to each other. Alternatively, the transistor M4 may not have a back gate.

[0393] Note that the transistor M5 and the transistor M6 may each be an n-channel type Si transistor or a p-channel type Si transistor. Alternatively, the transistors M4 to M6 may be OS transistors. In this case, the memory cell array 1470 can be configured with only n-type transistors.

[0394] When the semiconductor device shown in the above embodiment is used for the memory cell 1478, the transistor 200 can be used as the transistor M4, the transistor 300 can be used as the transistors M5 and M6, and the capacitor element 100 can be used as the capacitor element CC. By using an OS transistor as the transistor M4, the leakage current of the transistor M4 can be made very low.

[0395] Note that the configurations of the peripheral circuit 1411, the memory cell array 1470, etc. shown in this embodiment are not limited to the above. The arrangements or functions of these circuits, and the wirings, circuit elements, etc. connected to the circuits may be changed, deleted, or added as necessary.

[0396] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments, examples, etc.

[0397] (Embodiment 4) In this embodiment, an example of a chip 1200 on which the semiconductor device of the present invention is mounted is shown using FIG. 17. A plurality of circuits (systems) are mounted on the chip 1200. Thus, the technology of integrating a plurality of circuits (systems) on one chip is sometimes called a System on Chip (SoC).

[0398] As shown in FIG. 17A, the chip 1200 includes a CPU 1211, a GPU 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, etc.

[0399] The chip 1200 is provided with bumps (not shown) and is connected to the first surface of a Printed Circuit Board (PCB) 1201 as shown in FIG. 17B. Further, a plurality of bumps 1202 are provided on the back surface of the first surface of the PCB 1201 and are connected to a motherboard 1203.

[0400] The motherboard 1203 may be provided with storage devices such as a DRAM 1221 and a flash memory 1222. For example, DOSRAM shown in the previous embodiment can be used for the DRAM 1221. Also, for example, NOSRAM shown in the previous embodiment can be used for the flash memory 1222.

[0401] The CPU 1211 preferably has a plurality of CPU cores. Also, the GPU 1212 preferably has a plurality of GPU cores. Further, the CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a common memory for the CPU 1211 and the GPU 1212 may be provided on the chip 1200. NOSRAM and DOSRAM described above can be used for the memory. Also, the GPU 1212 is suitable for parallel calculation of a large number of data and can be used for image processing and multiplication-accumulation operations. By providing an image processing circuit or a multiplication-accumulation circuit using the oxide semiconductor of the present invention in the GPU 1212, it becomes possible to execute image processing and multiplication-accumulation operations with low power consumption.

[0402] Also, since the CPU 1211 and the GPU 1212 are provided on the same chip, the wiring between the CPU 1211 and the GPU 1212 can be shortened, and data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and the GPU 1212, and transfer of the calculation result from the GPU 1212 to the CPU 1211 after calculation in the GPU 1212 can be performed at high speed.

[0403] The analog arithmetic unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. Also, the analog arithmetic unit 1213 may be provided with the above-mentioned sum-of-products arithmetic circuit.

[0404] The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222.

[0405] The interface 1215 has an interface circuit with external connection devices such as a display device, a speaker, a microphone, a camera, and a controller. The controller includes a mouse, a keyboard, a game controller, etc. As such an interface, USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface), etc. can be used.

[0406] The network circuit 1216 has a network circuit such as a LAN (Local Area Network). Also, it may have a circuit for network security.

[0407] The above-mentioned circuit (system) can be formed on the chip 1200 in the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

[0408] The PCB 1201 provided with the chip 1200 having the GPU 1212, the motherboard 1203 provided with the DRAM 1221 and the flash memory 1222 can be called a GPU module 1204.

[0409] Since the GPU module 1204 has the chip 1200 using SoC technology, its size can be reduced. Also, since it is excellent in image processing, it is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop PCs, and portable (portable) game consoles. Further, by the multiplication-accumulation circuit using the GPU 1212, methods such as deep neural network (DNN), convolutional neural network (CNN), recurrent neural network (RNN), autoencoder, deep Boltzmann machine (DBM), and deep belief network (DBN) can be executed. Therefore, the chip 1200 can be used as an AI chip, or the GPU module 1204 can be used as an AI system module.

[0410] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments, examples, etc.

[0411] (Embodiment 5) In this embodiment, an application example of a storage device using the semiconductor device shown in the previous embodiment will be described. The semiconductor device shown in the previous embodiment can be applied to storage devices of various electronic devices (for example, information terminals, computers, smartphones, e-book terminals, digital cameras (including video cameras), recording and playback devices, navigation systems, etc.). Here, the computer includes not only tablet-type computers, notebook-type computers, and desktop-type computers, but also large computers such as server systems. Alternatively, the semiconductor device shown in the previous embodiment is applied to various removable storage devices such as memory cards (for example, SD cards), USB memories, and SSDs (solid state drives). FIG. 18 schematically shows some configuration examples of the removable storage device. For example, the semiconductor device shown in the previous embodiment is processed into a packaged memory chip and used in various storage devices and removable memories.

[0412] Figure 18A is a schematic diagram of a USB memory. The USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a substrate 1104. The substrate 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the substrate 1104. A semiconductor device shown in the previous embodiments can be incorporated into the memory chip 1105 or the like on the substrate 1104.

[0413] Figure 18B is a schematic diagram of the appearance of an SD card, and Figure 18C is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. By providing a memory chip 1114 also on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. Also, a wireless chip having a wireless communication function may be provided on the substrate 1113. Thereby, data of the memory chip 1114 can be read and written by wireless communication between the host device and the SD card 1110. A semiconductor device shown in the previous embodiments can be incorporated into the memory chip 1114 or the like on the substrate 1113.

[0414] Figure 18D is a schematic diagram of the appearance of an SSD, and Figure 18E is a schematic diagram of the internal structure of the SSD. The SSD 1150 has a housing 1151, a connector 1152, and a substrate 1153. The substrate 1153 is housed in the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are attached to the substrate 1153. The memory chip 1155 is a work memory of the controller chip 1156, and for example, a DOSRAM chip may be used. By providing a memory chip 1154 also on the back side of the substrate 1153, the capacity of the SSD 1150 can be increased. A semiconductor device shown in the previous embodiments can be incorporated into the memory chip 1154 or the like on the substrate 1153.

[0415] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments, examples, etc.

[0416] (Embodiment 6) The semiconductor device according to one aspect of the present invention can be used for processors such as CPUs and GPUs, or chips. Fig. 19 shows a specific example of an electronic device including a processor such as a CPU or GPU, or a chip according to one aspect of the present invention.

[0417] <Electronic device / system> The GPU or chip according to one aspect of the present invention can be mounted on various electronic devices. Examples of electronic devices include, for example, television devices, monitors for desktop or notebook information terminals, digital signage (electronic billboards), large game machines such as pachinko machines, etc., electronic devices with relatively large screens, as well as digital cameras, digital video cameras, digital photo frames, e-book readers, mobile phones, portable game machines, portable information terminals, audio playback devices, etc. In addition, by providing the GPU or chip according to one aspect of the present invention in an electronic device, artificial intelligence can be mounted on the electronic device.

[0418] The electronic device according to one aspect of the present invention may have an antenna. By receiving a signal with the antenna, display of video, information, etc. can be performed on the display unit. Also, when the electronic device has an antenna and a secondary battery, the antenna may be used for wireless power transmission.

[0419] The electronic device according to one aspect of the present invention may have a sensor (including a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, inclination, vibration, odor, or infrared rays).

[0420] An electronic device according to an aspect of the present invention can have various functions. For example, it can have functions such as displaying various types of information (still images, moving images, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, or time, a function of executing various software (programs), a wireless communication function, a function of reading programs or data recorded on a recording medium, etc. FIG. 19 shows an example of an electronic device.

[0421] [Information terminal] FIG. 19A shows a mobile phone (smartphone), which is a type of information terminal. The information terminal 5100 has a housing 5101 and a display unit 5102. As an input interface, a touch panel is provided on the display unit 5102, and buttons are provided on the housing 5101.

[0422] By applying a chip according to an aspect of the present invention, the information terminal 5100 can execute applications using artificial intelligence. Examples of applications using artificial intelligence include, for example, an application that recognizes a conversation and displays the conversation content on the display unit 5102, an application that recognizes characters, figures, etc. input by a user on the touch panel provided on the display unit 5102 and displays them on the display unit 5102, an application that performs biometric authentication such as fingerprint or voiceprint, etc.

[0423] FIG. 19B shows a notebook-type information terminal 5200. The notebook-type information terminal 5200 has a main body 5201 of the information terminal, a display unit 5202, and a keyboard 5203.

[0424] Similar to the above-described information terminal 5100, the notebook-type information terminal 5200 can execute applications using artificial intelligence by applying a chip according to an aspect of the present invention. Examples of applications using artificial intelligence include, for example, design support software, text proofreading software, recipe automatic generation software, etc. Also, by using the notebook-type information terminal 5200, new artificial intelligence can be developed.

[0425] Note that in the above description, a smartphone and a notebook information terminal are taken as examples of electronic devices and are illustrated in FIGS. 19A and 19B respectively. However, information terminals other than smartphones and notebook information terminals can be applied. Examples of information terminals other than smartphones and notebook information terminals include, for example, PDAs (Personal Digital Assistants), desktop information terminals, workstations, and the like.

[0426] [Game machine] FIG. 19C shows a portable game machine 5300 which is an example of a game machine. The portable game machine 5300 includes a housing 5301, housings 5302 and 5303, a display unit 5304, a connection unit 5305, operation keys 5306, and the like. The housings 5302 and 5303 can be removed from the housing 5301. By attaching the connection unit 5305 provided on the housing 5301 to another housing (not shown), the video output to the display unit 5304 can be output to another video device (not shown). At this time, the housings 5302 and 5303 can each function as an operation unit. Thereby, a plurality of players can play games simultaneously. Chips such as those shown in the previous embodiments can be incorporated into the chips provided on the substrates of the housing 5301, the housing 5302, and the housing 5303.

[0427] FIG. 19D shows a stationary game machine 5400 which is an example of a game machine. A controller 5402 is connected to the stationary game machine 5400 wirelessly or by wire.

[0428] By applying the GPU or chip of one aspect of the present invention to game machines such as the portable game machine 5300 and the stationary game machine 5400, a game machine with low power consumption can be realized. In addition, due to the low power consumption, heat generation from the circuit can be reduced, so that the influence on the circuit itself, peripheral circuits, and modules due to heat generation can be minimized.

[0429] Furthermore, by applying the GPU or chip of one aspect of the present invention to the portable game machine 5300, a portable game machine 5300 having artificial intelligence can be realized.

[0430] Originally, expressions such as the progress of the game, the speech and actions of the creatures appearing in the game, and the phenomena occurring in the game are determined by the program of the game. However, by applying artificial intelligence to the portable game machine 5300, expressions not limited to the game program become possible. For example, expressions such as the content asked by the player, the progress of the game, the time, and the speech and actions of the characters appearing in the game changing become possible.

[0431] Also, when playing a game that requires multiple players on the portable game machine 5300, since the game player can be anthropomorphically configured by artificial intelligence, the game can be played even by one person by using an artificial intelligence-based game player as the opponent.

[0432] In FIGS. 19C and 19D, a portable game machine and a stationary game machine are illustrated as examples of game machines, but the game machine to which the GPU or chip of one aspect of the present invention is applied is not limited to this. Examples of the game machine to which the GPU or chip of one aspect of the present invention is applied include, for example, arcade game machines installed in entertainment facilities (such as game centers and amusement parks), and pitching machines for batting practice installed in sports facilities.

[0433] [Large computer] The GPU or chip of one aspect of the present invention can be applied to a large computer.

[0434] FIG. 19E is a diagram showing a supercomputer 5500, which is an example of a large computer. FIG. 19F is a diagram showing a rack-mounted computer 5502 included in the supercomputer 5500.

[0435] The supercomputer 5500 includes a rack 5501 and a plurality of rack-mounted computers 5502. The plurality of computers 5502 are stored in the rack 5501. Further, a plurality of circuit boards 5504 are provided in the computers 5502, and the GPUs or chips described in the above embodiments can be mounted on the circuit boards.

[0436] The supercomputer 5500 is a large computer mainly used for scientific and technological calculations. In scientific and technological calculations, since it is necessary to process a huge number of operations at high speed, the power consumption is high and the heat generation of the chips is large. By applying the GPU or chip of one aspect of the present invention to the supercomputer 5500, a supercomputer with low power consumption can be realized. In addition, due to the low power consumption, the heat generation from the circuit can be reduced, so that the influence of the heat generation on the circuit itself, the peripheral circuits, and the modules can be reduced.

[0437] In FIGS. 19E and 19F, a supercomputer is illustrated as an example of a large computer, but the large computer to which the GPU or chip of one aspect of the present invention is applied is not limited to this. Examples of the large computer to which the GPU or chip of one aspect of the present invention is applied include, for example, a computer (server) that provides services, a large general-purpose computer (mainframe), and the like.

[0438] [Mobile object] The GPU or chip of one aspect of the present invention can be applied to a mobile object, an automobile, and the periphery of the driver's seat of the automobile.

[0439] FIG. 19G is a view showing the periphery of the windshield in the interior of an automobile, which is an example of a mobile object. In FIG. 19G, in addition to the display panels 5701, 5702, and 5703 attached to the dashboard, a display panel 5704 attached to the pillar is illustrated.

[0440] The display panels 5701 to 5703 can provide various information by displaying a speedometer, a tachometer, an odometer, a fuel gauge, a gear state, an air conditioner setting, and the like. In addition, the display items and layout displayed on the display panel can be appropriately changed according to the user's preference, and the designability can be enhanced. The display panels 5701 to 5703 can also be used as lighting devices.

[0441] The display panel 5704 can complement the visual field (blind spot) blocked by the pillar by projecting the video from an imaging device (not shown) provided in the vehicle. That is, by displaying the image from the imaging device provided outside the vehicle, the blind spot can be compensated and the safety can be improved. In addition, by projecting the video that complements the invisible part, the safety check can be performed more naturally without discomfort. The display panel 5704 can also be used as a lighting device.

[0442] Since the GPU or chip according to one aspect of the present invention can be applied as a component of artificial intelligence, for example, the chip can be used in an automatic driving system of a vehicle. In addition, the chip can be used in a system for performing road guidance, danger prediction, and the like. The display panels 5701 to 5704 may be configured to display information such as road guidance and danger prediction.

[0443] In the above description, the vehicle is described as an example of the moving body, but the moving body is not limited to the vehicle. For example, examples of the moving body include trains, monorails, ships, aircraft (helicopters, unmanned aerial vehicles (drones), airplanes, rockets), and the like. The chip according to one aspect of the present invention can be applied to these moving bodies to provide a system using artificial intelligence.

[0444] [Electrical Appliance] FIG. 19H shows an electric refrigerator-freezer 5800 which is an example of an electrical appliance. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0445] By applying the chip of one aspect of the present invention to the electric refrigerator 5800, an electric refrigerator 5800 with artificial intelligence can be realized. By utilizing artificial intelligence, the electric refrigerator 5800 can have functions such as automatically generating a menu based on the food stored in the electric refrigerator 5800, the expiration date of the food, etc., and automatically adjusting the temperature according to the food stored in the electric refrigerator 5800.

[0446] Although the electric refrigerator has been described as an example of an electrical appliance, other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, IH cookers, water servers, air conditioners and other heating and cooling appliances, washing machines, dryers, audio-visual equipment, etc.

[0447] The electronic devices described in this embodiment, the functions of the electronic devices, application examples of artificial intelligence, and their effects, etc., can be appropriately combined with the descriptions of other electronic devices.

[0448] This embodiment can be implemented by appropriately combining with the configurations described in other embodiments, examples, etc.

Example

[0449] In this example, a laminated structure including an insulator, which is one aspect of the present invention, was fabricated and analyzed using SIMS. In this example, samples 1A to 1H were fabricated.

[0450] <1. Configuration and Fabrication Method of Each Sample> Hereinafter, samples 1A, 1B, 1C, 1D, 1E, 1F, 1G, and 1H according to one aspect of the present invention will be described. The structures of samples 1A to 1H are shown in FIG. 20A. Samples 1A to 1H include a substrate 900, an insulator 914 on the substrate 900, an insulator 916 on the insulator 914, an insulator 922 on the insulator 916, an oxide semiconductor 930 (oxide semiconductors 930a, 930b, 930c, and 903d) on the insulator 922, and an insulator 950 on the oxide semiconductor 930.

[0451] Next, the manufacturing method of each sample will be described.

[0452] First, a silicon substrate was prepared as the substrate 900. Subsequently, a thermal oxide film with a thickness of 100 nm was formed as the insulator 914 on the substrate 900.

[0453] Next, a hafnium oxide film with a thickness of 20 nm was formed as the insulator 916 on the insulator 914. Subsequently, a silicon oxynitride film with a thickness of 30 nm was formed as the insulator 922 on the insulator 916.

[0454] Next, an oxide semiconductor 930a containing In, Ga, and Zn with a film thickness of 5 nm was formed on the insulator 922 using a sputtering method. The oxide semiconductor 930a was formed using an oxide target containing In, Ga, and Zn (atomic ratio In:Ga:Zn = 1:3:4), with oxygen (O2) at a flow rate of 45 sccm as the film-forming gas, a film-forming pressure of 0.7 Pa, a film-forming power of 500 W, a substrate temperature of 130 °C, and a target-substrate distance of 60 mm. Subsequently, an oxide semiconductor 930b containing In, Ga, and Zn with a film thickness of 15 nm was formed on the oxide semiconductor 930a using a sputtering method. The oxide semiconductor 930b was formed using an oxide target containing In, Ga, and Zn (atomic ratio In:Ga:Zn = 4:2:4.1), with oxygen (O2) at a flow rate of 45 sccm as the film-forming gas, a film-forming pressure of 0.7 Pa, a film-forming power of 500 W, a substrate temperature of 130 °C, and a target-substrate distance of 60 mm.

[0455] Next, a heat treatment was performed at 200 °C for 5 minutes in a reduced-pressure atmosphere.

[0456] Subsequently, an oxide semiconductor 930c containing In, Ga, and Zn with a film thickness of 8 nm was formed on the oxide semiconductor 930b using a sputtering method. The oxide semiconductor 930c was formed using an oxide target containing In, Ga, and Zn (atomic ratio In:Ga:Zn = 4:2:4.1), with oxygen (O2) at a flow rate of 45 sccm as the film-forming gas, a film-forming pressure of 0.7 Pa, a film-forming power of 500 W, a substrate temperature of 130 °C, and a target-substrate distance of 60 mm. Subsequently, an oxide semiconductor 930b containing In, Ga, and Zn with a film thickness of 8 nm was formed on the oxide semiconductor 930a using a sputtering method. The oxide semiconductor 930d was formed using an oxide target containing In, Ga, and Zn (atomic ratio In:Ga:Zn = 1:3:4), with oxygen (O2) at a flow rate of 45 sccm as the film-forming gas, a film-forming pressure of 0.7 Pa, a film-forming power of 500 W, a substrate temperature of 130 °C, and a target-substrate distance of 60 mm.

[0457] Next, a silicon oxide film with a thickness of 10.8 nm was formed as the insulator 950 on the oxide semiconductor 930d by CVD method. Here, the film formation conditions for Samples 1A to 1H are shown in Table 1.

[0458] Also, during the formation of the insulator 950, by adding deuterium (D2) with a flow rate of 200 sccm, the amount of hydrogen diffusing during film formation was examined for the film formation object.

[0459] [Table 1]

[0460] Through the above steps, Samples 1A to 1H of this example were fabricated. Also, the measurement of each sample was performed before and after heat treatment assuming the heat history of the post-process for Samples 1A to 1H.

[0461] Note that the heat treatment was performed at 400 °C for 1 hour in a nitrogen atmosphere.

[0462] <2. Measurement of the amount of deuterium (D2) in the oxide semiconductor 930 of each sample> Next, using the oxide semiconductor 930 of Samples 1A to 1H as the quantification layer, SIMS analysis was performed from the substrate side to detect the deuterium (D2) concentration, and the result of measuring the amount of deuterium in the oxide semiconductor 930 is shown in Fig. 20B. Note that the hydrogen concentration evaluation was performed by Secondary Ion Mass Spectrometry (SIMS), and a CAMECA dynamic SIMS device IMS-7f was used as the analysis device.

[0463] Fig. 20B shows the concentration of deuterium (D2) [atoms / cm 2 calculated by integrating the profile of the deuterium (D2) concentration in the oxide semiconductor 930, which is the quantification layer, for each sample.

[0464] From FIG. 20B, by setting the value of the constant Y to 0 < Y < 18, preferably 0 < Y ≤ 7.0, in the film formation conditions of the insulator 950, it was possible to reduce the amount of hydrogen diffused into the film formation object (in this example, the oxide semiconductor 930) in the process of forming the insulator 950.

[0465] That is, in the film formation power PW [W], the execution electrode area S [cm 2 , the film formation pressure P [Pa], and the flow rate f [sccm] of the film formation gas containing hydrogen, which are variables for determining the value of the constant Y, the following was found.

[0466] It was confirmed that when the flow rate f [sccm] of the film formation gas increased, the amount of hydrogen diffused into the film formation object was reduced. On the other hand, it was confirmed that the film formation power per unit area calculated by dividing the film formation power PW [W] by the execution electrode area S [cm 2 and the film formation pressure P [Pa] increased, the amount of hydrogen diffused into the film formation object increased.

[0467] In particular, it was found that the increase amount of the hydrogen amount diffused into the film formation object when the film formation power was increased was relatively small. On the other hand, when the film formation pressure P [Pa] was increased, the amount of hydrogen diffused into the film formation object increased gently. Also, it was found that the increase in the amount of hydrogen diffused accompanying the increase in the flow rate f [sccm] of the film formation gas had a large slope and a greater influence than the film formation power and the film formation pressure P [Pa].

[0468] From the above, in the film formation conditions of the insulator, by setting the value of the constant Y to 0 < Y < 17, preferably 0 < Y ≤ 7.0, it was possible to provide an insulator that can be formed without diffusing hydrogen to the film formation object.

[0469] As described above, the configuration shown in this example can be used in appropriate combination with other examples or other embodiments.

Example

[0470] In this embodiment, a laminated structure including an insulator, which is one aspect of the present invention, was fabricated and observed using an optical microscope. In this embodiment, Samples 2A to 2I were fabricated.

[0471] <1. Configuration and Fabrication Method of Each Sample> Hereinafter, Samples 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, and 2I according to one aspect of the present invention will be described. The structures of Samples 2A to 2I are shown in FIG. 21A. Samples 2A to 2I include a substrate 800, an insulator 814 on the substrate 800, an insulator 816 on the insulator 814, an insulator 820 on the insulator 816, an insulator 822 on the insulator 820, an insulator 824 on the insulator 822, an oxide semiconductor 830 (oxide semiconductors 830a and 830b) on the insulator 824, a conductor 840 on the oxide semiconductor 830, insulators 845 (insulators 845a and 845b) on the conductor 840, and an insulator 880 on the insulators 845.

[0472] Next, the fabrication method of each sample will be described.

[0473] First, a silicon substrate was prepared as the substrate 800. Subsequently, a thermal oxide film with a thickness of 400 nm was formed as the insulator 814 on the substrate 800.

[0474] Next, an aluminum oxide film with a thickness of 40 nm was formed as the insulator 816 on the insulator 814. Subsequently, a silicon oxynitride film with a thickness of 200 nm was formed as the insulator 820 on the insulator 816.

[0475] Next, a hafnium oxide film with a thickness of 20 nm was formed as the insulator 822 on the insulator 820. Subsequently, a silicon oxynitride film with a thickness of 30 nm was formed as the insulator 824 on the insulator 822.

[0476] Next, an oxide semiconductor 830a containing In, Ga, and Zn with a film thickness of 5 nm was formed on the insulator 824 by sputtering. The oxide semiconductor 830a was formed using an oxide target containing In, Ga, and Zn (atomic ratio In:Ga:Zn = 1:3:4), with oxygen (O2) at a flow rate of 45 sccm as the film-forming gas, a film-forming pressure of 0.7 Pa, a film-forming power of 500 W, a substrate temperature of 130 °C, and a target-substrate distance of 60 mm. Subsequently, an oxide semiconductor 830b containing In, Ga, and Zn with a film thickness of 15 nm was formed on the oxide semiconductor 830a by sputtering. The oxide semiconductor 830b was formed using an oxide target containing In, Ga, and Zn (atomic ratio In:Ga:Zn = 4:2:4.1), with oxygen (O2) at a flow rate of 45 sccm as the film-forming gas, a film-forming pressure of 0.7 Pa, a film-forming power of 500 W, a substrate temperature of 130 °C, and a target-substrate distance of 60 mm.

[0477] Next, a tungsten nitride film with a film thickness of 25 nm was formed as the conductor 840 on the oxide semiconductor 830b by sputtering.

[0478] Next, an aluminum oxide film with a film thickness of 5 nm was formed as the insulator 845a on the conductor 840 by sputtering. Subsequently, a 3-nm aluminum oxide film was formed as the insulator 845b on the insulator 845a by ALD.

[0479] Next, a silicon oxide film with a film thickness of 170 nm was formed as the insulator 880 on the insulator 845b by CVD. Here, the film-forming conditions for Samples 2A to 2I are shown in Table 2.

[0480]

Table 2

[0481] Through the above steps, Samples 2A to 2I of this example were fabricated.

[0482] <2. Observation of Each Sample by Optical Microscope Image> Next, the results of observing Samples 2A to 2I with an optical microscope (bright field, magnification 1000 times) are shown in FIG. 21B and FIG. 22.

[0483] FIG. 21B shows optical microscope photographs of Samples 2A, 2B, 2C, and 2D under the condition that the film-forming pressure during film formation is 200 [Pa]. Further, FIG. 22A shows optical microscope photographs of Sample 2B and Sample 2E under the condition that the film-forming power during film formation is 120 [W]. Further, FIG. 22B shows optical microscope photographs of Sample 2C, Sample 2F, and Sample 2G under the condition that the film-forming power during film formation is 85 [W].

[0484] From FIG. 21B, it was found that the smaller the film-forming power during film formation, the less film lifting. Also, from FIG. 22, it was found that the smaller the film-forming pressure during film formation, the less film lifting.

[0485] Here, FIG. 23 shows the ratio (%) of film lifting to the value of constant Y in Samples 2A to 2I. The ratio of film lifting was calculated by image analysis of the optical microscope image. From FIG. 23, it was confirmed that there is a correlation between the value of constant Y and the ratio at which film lifting occurs.

[0486] That is, by setting the value of constant Y to 0 < Y < 10, the occurrence of film lifting and peeling could be reduced. In particular, by setting the value of constant Y to 0 < Y ≤ 8.0, the occurrence of film lifting and peeling could be prevented.

[0487] Therefore, under the film-forming conditions of the insulator 880, by setting the value of constant Y to 0 < Y ≤ 8.0, the occurrence of film lifting and peeling between the insulator adjacent to the insulator 880 and the conductor could be prevented.

[0488] As described above, the configuration shown in this example can be used in appropriate combination with other examples or other embodiments.

Example

[0489] In this embodiment, as Sample 3A and Sample 3B, a semiconductor device having the transistor 200 shown in FIG. 9, which is one aspect of the present invention, was fabricated, and a reliability test of the transistor 200 was performed. Note that the channel length of the transistor 200 was designed to be 60 nm, and the channel width was designed to be 60 nm.

[0490] <Method for fabricating samples> Hereinafter, the methods for fabricating Sample 3A and Sample 3B will be described.

[0491] Note that as the oxide 230a, the oxide 230b, and the oxide 230c, indium-gallium-zinc oxide was formed by a sputtering method. For the film that becomes the oxide 230a, an indium-gallium-zinc oxide film with a thickness of 5 nm was formed using a target with an atomic ratio of In:Ga:Zn = 1:3:4. For the film that becomes the oxide 230b, an indium-gallium-zinc oxide film with a thickness of 15 nm was formed using a target with an atomic ratio of In:Ga:Zn = 4:2:4.1.

[0492] Also, as the oxide 230c, indium-gallium-zinc oxide was formed by a sputtering method. As the oxide 230c, first, an indium-gallium-zinc oxide film with a thickness of 8 nm was formed using a target with an atomic ratio of In:Ga:Zn = 4:2:4.1, and then an indium-gallium-zinc oxide film with a thickness of 8 nm was formed using a target with an atomic ratio of In:Ga:Zn = 1:3:4.

[0493] Also, as the conductor 240, titanium nitride with a thickness of 25 mn was formed by a sputtering method. Subsequently, as the insulator 245, aluminum oxide was formed. For the film that becomes the insulator 245, first, a 5-nm aluminum oxide film was formed by a sputtering method, and then an aluminum oxide film with a thickness of 3 nm was formed by an ALD method.

[0494] Also, as the insulator 280 that functions as an interlayer film in contact with the transistor 200, a silicon oxynitride (SiON) film with a thickness of 110 nm was formed by a CVD method.

[0495] Here, the film formation conditions of the insulator 280 in each sample are shown below.

[0496] [Table 3]

[0497] From the above, Sample 3A and Sample 3B were fabricated.

[0498] <2. Cross-sectional Observation of Each Sample> Cross-sectional observation was performed on Sample 3A and Sample 3B. The cross-sectional observation was carried out using a scanning transmission electron microscope (STEM). The observation apparatus used was HD-2700 manufactured by Hitachi High-Technologies Corporation. The cross-sectional STEM observation results are shown in FIG. 24.

[0499] FIG. 24A shows the STEM photograph of the cross-section of Sample 3A with the constant Y being 32.5, and FIG. 24B shows the STEM photograph of the cross-section of Sample 3B with the constant Y being 1.9.

[0500] From FIG. 24, it was confirmed that the transistor 200 of the present invention can be provided by using an insulator with the constant Y being 1.9 as the insulator 280 in contact with the transistor 200. On the other hand, it was confirmed that film peeling occurred between the oxide 230 and the conductor 240 by using an insulator with the constant Y being 32.5 as the insulator 280 in contact with the transistor 200.

[0501] As described above, the configuration shown in this embodiment can be used in appropriate combination with other embodiments or other implementation forms. [Explanation of Reference Numerals]

[0502] 200: Transistor, 205: Conductor, 210: Insulator, 212: Insulator, 214: Insulator, 216: Insulator, 218: Conductor, 222: Insulator, 224: Insulator, 230: Oxide, 230a: Oxide, 230A: Oxide film, 230b: Oxide, 230B: Oxide film, 230c: Oxide, 230C: Oxide film, 240: Conductor, 240a: Conductor, 240A: Conductive film, 240b: Conductor, 240B: Conductive layer, 245: Insulator, 245a: Insulator, 245A: Insulating film, 245b: Insulator, 245B: Insulating layer, 246: Conductor, 247: Insulator, 248: Conductor, 250: Insulator, 250A: Insulating film, 260: Conductor, 260a: Conductor, 260A: Conductive film, 260b: Conductor, 260B: Conductive film, 273: Insulator, 274: Insulator, 280: Insulator, 280A: Insulating film, 282: Insulator, 283: Insulator, 284: Insulator, 290: Hard mask, 290A: Film, 290B: Hard mask, 292: Resist mask, 295: Opening, 300: Transistor, 311: Substrate, 312: Insulator, 313: Semiconductor region, 314a: Low-resistance region, 314b: Low-resistance region, 315: Insulator, 316: Conductor, 320: Insulator, 322: Insulator, 324: Insulator, 326: Insulator, 328: Conductor, 330: Conductor, 350: Insulator, 352: Insulator, 354: Insulator, 356: Conductor, 400: Transistor, 405: Conductor, 405a: Conductor, 405b: Conductor, 430c: Oxide, 431a: Oxide, 431b: Oxide, 432a: Oxide, 432b: Oxide, 440: Conductor, 440a: Conductor, 440b: Conductor, 445: Insulator, 445a: Insulator, 445b: Insulator, 450: Insulator, 460: Conductor, 460a: Conductor, 460b: Conductor, 800: Substrate, 814: Insulator, 816: Insulator, 820: Insulator, 822: Insulator, 824: Insulator, 830: Oxide semiconductor, 830a: Oxide semiconductor, 830b: Oxide semiconductor, 840: Conductor, 845: Insulator, 845a: Insulator, 845b: Insulator, 880: Insulator, 900: Substrate, 903d: Oxide semiconductor, 914: Insulator, 916: Insulator, 922: Insulator, 924: Insulator, 930: Oxide semiconductor, 930a: Oxide semiconductor, 930b: Oxide semiconductor, 930c: Oxide semiconductor, 930d: Oxide semiconductor, 950: Insulator, 980: Insulator

Claims

1. Form an oxide semiconductor on a substrate, Form a conductor in contact with the oxide semiconductor, By removing a part of the conductor, a source electrode and a drain electrode are formed and a portion that becomes a channel formation region of the oxide semiconductor is exposed, Form a first gate insulator by chemical vapor deposition under conditions satisfying the following formula (1) on the exposed region of the oxide semiconductor, A method of manufacturing a semiconductor device for forming a first gate electrode in contact with the first gate insulator. [Formula 1] (In the formula, PW[W] is the film formation power, S[cm ２ is the area of the working electrode, P[Pa] is the film formation pressure, and f[sc cm] is the flow rate of the film formation gas of the silane (SiH ４ )-based system, respectively.)

2. Form a second gate electrode on a substrate, Form hafnium oxide or aluminum oxide as a first insulator on the second gate electrode, Form silicon oxynitride as a second insulator by chemical vapor deposition under conditions satisfying the following formula (2) on the first insulator, The first insulator and the second insulator have a function as a second gate insulator, Form an oxide semiconductor on the second insulator, Form a conductor in contact with the oxide semiconductor, Form aluminum oxide in contact with the conductor, Form silicon oxide by chemical vapor deposition under conditions satisfying the following formula (2) in contact with the aluminum oxide, By removing a part of the silicon oxide, the aluminum oxide and the conductor, a source electrode and a drain electrode are formed and a portion that becomes a channel formation region of the oxide semiconductor is exposed, Form a first gate insulator by chemical vapor deposition under conditions satisfying the following formula (2) on the exposed region of the oxide semiconductor, A method of manufacturing a semiconductor device for forming a first gate electrode in contact with the first gate insulator. [Formula 2] (In the formula, PW[W] is the film formation power, S[cm ２ is the execution electrode area, P[Pa] is the film formation pressure, and f[sccm] is the flow rate of the film formation gas of the silane (SiH ４ ).)

3. In claim 1 or 2, A method of manufacturing a semiconductor device, wherein the oxide semiconductor is an In-Ga-Zn oxide.

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