Multilayer Encapsulation and Manufacturing Method for Moisture Robustness and High-Acceleration Life Tests

Abstract

The semiconductor die includes a semiconductor body and a multi-layer environmental barrier on the semiconductor body. The multi-layer environmental barrier includes a plurality of sub-layers stacked on the semiconductor body. Each sub-layer includes a respective stress in one or more directions, and the respective stresses of at least two of the sub-layers are different. The sub-layers may include a first stressor sub-layer including a first stress and a second stressor sub-layer including a second stress that at least partially compensates the first stress in one or more directions. Related apparatus and manufacturing methods are also discussed.

Description

Technical Field

[0001] This application claims the benefit of priority of U.S. Patent Application No. 17 / 591,704, filed on February 3, 2022, which is a continuation-in-part of U.S. Patent Application No. 17 / 335,796, filed on June 1, 2021, the entire disclosure of which is incorporated herein by reference.

[0002] The present invention relates to semiconductor devices, and more particularly, to environmental protection of semiconductor devices and related manufacturing methods.

Background Art

[0003] Materials such as silicon (Si) and gallium arsenide (GaAs) have found wide applications in semiconductor devices for low-power and, in the case of Si, low-frequency applications. However, these materials may not be very suitable for high-power and / or high-frequency applications, for example, due to their relatively small band gaps (1.12 eV for Si and 1.42 for GaAs at room temperature) and relatively small breakdown voltages.

[0004] For high-power, high-temperature, and / or high-frequency applications and devices, wide-bandgap semiconductor materials such as silicon carbide (SiC) (e.g., having a band gap of about 3.2 eV for 4H-SiC at room temperature) and group III nitrides (e.g., having a band gap of about 3.36 eV for gallium nitride (GaN) at room temperature) may be used. As used herein, the term "group III nitride" refers to semiconductor compounds formed between nitrogen (N) and elements of group III in the periodic table, typically aluminum (Al), gallium (Ga), and / or indium (In). This term refers to binary, ternary, and quaternary compounds such as GaN, AlGaN, and AlInGaN. These compounds have an empirical formula in which 1 mole of nitrogen is combined with a total of 1 mole of group III elements. These materials may have higher breakdown field strengths and higher electron saturation velocities compared to GaAs and Si.

[0005] Semiconductor devices made of SiC and / or group III nitrides may include power transistor devices such as field effect transistor (FET) devices including MOSFETs (metal oxide semiconductor field effect transistors), DMOS (double-diffused metal oxide semiconductor) transistors, HEMTs (high electron mobility transistors), MESFETs (metal semiconductor field effect transistors), LDMOS (laterally diffused metal oxide semiconductor) transistors, etc. These devices are generally passivated with an oxide layer such as silicon dioxide (SiO2) to protect the exposed surface of the device and / or for other reasons. However, the interface between the semiconductor body and the oxide layer may be insufficient to obtain a high surface mobility of electrons. For example, the interface between SiC and SiO2 has conventionally shown a high density of interface states, which may reduce the surface electron mobility and introduce carrier traps, which may in turn reduce the desired performance characteristics of the device. Therefore, semiconductor devices including those with an oxide layer may incorporate one or more layers of silicon nitride (e.g., amorphous silicon nitride, SiNx) to improve the resulting electron properties, as described, for example, in Patent Document 1.

[0006] Semiconductor devices may need to operate in high temperature and / or high humidity environments, and chips that are inadequately designed or processed may exhibit failure mechanisms, which may reduce or compromise the expected operating life of the device. For example, if moisture is allowed to reach the semiconductor device, corrosion may occur, which can degrade the performance of the semiconductor device. Moisture protection in semiconductor components is generally implemented using a final passivation film such as SiN having a single layer deposited by CVD.

[0007] As an environmental barrier, SiN may form a better seal on the device compared to SiO2, reducing or preventing contaminants such as water from reaching the epitaxial layer of the device and causing degradation. For example, as described in Patent Document 2, plasma-enhanced chemical vapor deposition (PECVD) may be used to form SiN as an environmental barrier for semiconductor devices. However, the SiN layer formed by PECVD may be prone to defects such as pinholes and columnar structures, and these defects may allow moisture to penetrate the SiN layer and reach the device.

Prior Art Documents

Patent Documents

[0008]

Patent Document 1

Patent Document 2

Summary of the Invention

[0009] According to some embodiments of the present invention, a semiconductor die includes a semiconductor body and a multilayer environmental barrier on the semiconductor body. The multilayer environmental barrier includes first and second sublayers of first and second oxide materials, respectively, and the first oxide material is different from the second oxide material.

[0010] In some embodiments, the first and second sublayers may be atomic layer deposition (ALD) layers.

[0011] In some embodiments, at least one of the first or second oxide materials may have a higher density than silicon nitride.

[0012] In some embodiments, at least one of the first or second oxide materials may be an insulating metal oxide.

[0013] In some embodiments, the first and second sub-layers may be included in a repeating layer structure, and the first and second oxide materials may include an insulating metal oxide and a non-metal oxide, respectively.

[0014] In some embodiments, the insulating metal oxide may be at least one of aluminum oxide, zirconium oxide, or hafnium oxide.

[0015] In some embodiments, the insulating metal oxide may be aluminum oxide, and the non-metal oxide may include silicon oxide.

[0016] In some embodiments, the ratio of the thickness of the first sub-layer to the thickness of the second sub-layer may be about 2:1 or more, about 5:1 or more, or about 8:1 or more.

[0017] In some embodiments, a passivation layer may be provided between the semiconductor body and the multi-layer environmental barrier. For example, the passivation layer may include silicon nitride.

[0018] In some embodiments, the surface of the multi-layer environmental barrier opposite the passivation layer may include a layer of silicon oxide or silicon nitride.

[0019] In some embodiments, the first oxide material may have a diffusion coefficient with respect to water that is different from that of the second oxide material.

[0020] In some embodiments, a gate, source contact, and drain contact may be provided on the semiconductor body, and the passivation layer may extend over the gate, source contact, and drain contact. The first and second sub-layers may conformally extend over the passivation layer with substantially uniform respective thicknesses along the gate, source contact, and drain contact.

[0021] In some embodiments, the first and second sub-layers may be included in a repeating layer structure. The multi-layer environmental barrier may include at least two repeating layer structures, at least ten repeating layer structures, or at least twenty repeating layer structures.

[0022] In some embodiments, the total thickness of the multi-layer environmental barrier may be from about 500 angstroms to about 3000 angstroms.

[0023] In some embodiments, the repeating layer structure may be a two-layer structure in which the first and second sub-layers are laminated, a three-layer structure in which the first sub-layer, the second sub-layer, and the third sub-layer are laminated, and / or a four-layer structure in which the first sub-layer, the second sub-layer, the third sub-layer, and the fourth sub-layer are laminated.

[0024] According to some embodiments of the present invention, a semiconductor die includes a semiconductor body and a multi-layer environmental barrier on the semiconductor body. The multi-layer environmental barrier includes a repeating layer structure having two or more sub-layers of respective insulating materials, and at least one of the respective insulating materials has a density higher than that of silicon nitride.

[0025] In some embodiments, the two or more sub-layers may be atomic layer deposition (ALD) layers.

[0026] In some embodiments, the density of at least one of the respective insulating materials may be higher than that of at least one of the other respective insulating materials.

[0027] In some embodiments, at least one of the respective insulating materials may be a metal oxide, and at least one of the other respective insulating materials may be a non-metal oxide.

[0028] In some embodiments, the metal oxide may be aluminum oxide, zirconium oxide, or hafnium oxide.

[0029] In some embodiments, the non-metal oxide may be silicon oxide.

[0030] In some embodiments, a passivation layer may be provided between the semiconductor body and the multi-layer environmental barrier.

[0031] In some embodiments, the ratio of the thicknesses of the first and second sub-layers of two or more sub-layers may be about 2:1 or more, about 5:1 or more, or about 8:1 or more.

[0032] In some embodiments, a gate, a source contact, and a drain contact may be provided on the semiconductor body, and the passivation layer may extend over the gate, the source contact, and the drain contact. Two or more sub-layers may conformally extend over the passivation layer with substantially uniform respective thicknesses along the gate, the source contact, and the drain contact.

[0033] In some embodiments, at least two of the respective insulating materials may have different diffusion coefficients with respect to water.

[0034] According to some embodiments of the present invention, a semiconductor die includes a semiconductor body and a multi-layer environmental barrier on the semiconductor body. The multi-layer environmental barrier includes a repeating layer structure having a first insulating sub-layer and a second insulating sub-layer. The ratio of the first thickness of the first insulating sub-layer to the second thickness of the second insulating sub-layer is about 2:1 or more.

[0035] In some embodiments, the first and second insulating sub-layers may be the first and second materials, respectively, and the density of the first material may be higher than the density of the second material.

[0036] In some embodiments, the density of at least one of the first material or the second material may be higher than that of silicon nitride.

[0037] In some embodiments, the first and second insulating sub-layers may be atomic layer deposition (ALD) layers.

[0038] In some embodiments, the first material may be a metal and the second material may be a non-metal.

[0039] In some embodiments, the first material may be aluminum oxide, zirconium oxide, hafnium oxide, or silicon nitride.

[0040] In some embodiments, the second material may be silicon oxide.

[0041] In some embodiments, the first material may have a diffusion coefficient with respect to water that is different from that of the second material.

[0042] According to some embodiments of the present invention, a method of manufacturing a semiconductor die includes providing a semiconductor body and forming a multilayer environmental barrier on the semiconductor body. The multilayer environmental barrier includes first and second sublayers of first and second oxide materials, respectively, and the first oxide material is different from the second oxide material.

[0043] In some embodiments, forming the multilayer environmental barrier on the passivation layer may include forming the first and second sublayers by atomic layer deposition (ALD).

[0044] In some embodiments, forming the multilayer environmental barrier may include alternately performing a first ALD process for forming the first sublayer and a second ALD process for forming the second sublayer on the first sublayer so as to define a repeating layer structure.

[0045] In some embodiments, at least one of the first or second oxide materials may have a density higher than that of silicon nitride.

[0046] In some embodiments, at least one of the first or second oxide materials may be an insulating metal oxide.

[0047] In some embodiments, the other of the first and second oxide materials may be a non-metal oxide.

[0048] In some embodiments, the insulating metal oxide may be at least one of aluminum oxide, zirconium oxide, or hafnium oxide.

[0049] In some embodiments, the insulating metal oxide may be aluminum oxide, and the non-metal oxide may be silicon oxide.

[0050] In some embodiments, the passivation layer may be formed on the semiconductor body before forming the multilayer environmental barrier.

[0051] In some embodiments, the gate, source contact, and drain contact may be formed on the semiconductor body. The passivation layer may be formed on the gate, source contact, and drain contact. The first and second sub-layers may conformally extend on the passivation layer with substantially uniform respective thicknesses along the gate, source contact, and drain contact.

[0052] In some embodiments, the surface of the multilayer environmental barrier opposite to the semiconductor body may include a layer of silicon oxide or silicon nitride.

[0053] In some embodiments, the first oxide material may have a diffusion coefficient with respect to water that is different from that of the second oxide material.

[0054] According to some embodiments of the present invention, the semiconductor die includes a semiconductor body and a multilayer environmental barrier including a plurality of sub-layers stacked on the semiconductor body. Each sub-layer includes respective stress in one or more directions, and the respective stresses of at least two of the sub-layers are different.

[0055] In some embodiments, at least two of the sublayers may include a first stressor sublayer including a first stress and a second stressor sublayer including a second stress that at least partially compensates the first stress in one or more directions.

[0056] In some embodiments, the first stress may be tensile and the second stress may be compressive.

[0057] In some embodiments, the first and second stressor sublayers may each include a first and a second oxide material, respectively. The first oxide material may be different from the second oxide material.

[0058] In some embodiments, at least one of the first or second stressor sublayers may include a metal-insulating material.

[0059] In some embodiments, another one of the first or second stressor sublayers may include a metal.

[0060] In some embodiments, the metal-insulating material may include at least one of aluminum oxide, zirconium oxide, or hafnium oxide.

[0061] In some embodiments, another one of the first or second stressor sublayers may include a non-metal insulating material.

[0062] In some embodiments, the metal-insulating material may include aluminum oxide, and the non-metal insulating material may include silicon oxide.

[0063] In some embodiments, the sublayer includes a repeating layer structure including the first and second stressor sublayers.

[0064] In some embodiments, the repeating layer structure may include a two-layer structure in which a first stressor sublayer and a second stressor sublayer are stacked, a three-layer structure in which a first stressor sublayer, a second stressor sublayer, and a third stressor sublayer are stacked, and / or a four-layer structure in which a first stressor sublayer, a second stressor sublayer, a third stressor sublayer, and a fourth stressor sublayer are stacked.

[0065] In some embodiments, the multilayer environmental barrier may include at least two repeating layer structures, at least ten repeating layer structures, or at least twenty repeating layer structures.

[0066] In some embodiments, the first stressor sublayer may be between the second stressor sublayer and the semiconductor body. The first stressor sublayer may include a first material having a higher density than a second material of the second stressor sublayer.

[0067] In some embodiments, the density of at least one of the first material of the first stressor sublayer or the second material of the second stressor sublayer may be higher than that of silicon nitride.

[0068] In some embodiments, the ratio of the thickness of the first stressor sublayer to the thickness of the second stressor sublayer may be about 2:1 or more, about 5:1 or more, or about 8:1 or more.

[0069] In some embodiments, the semiconductor die may further include a gate, a source contact, and a drain contact on the semiconductor body. The first and second stressor sublayers may conformally extend directly over the gate, the source contact, and the drain contact with substantially uniform respective thicknesses.

[0070] In some embodiments, the first and second stressor sublayers may include atomic layer deposition (ALD) layers.

[0071] In some embodiments, the multilayer environmental barrier may include one or more diffusion barrier properties, and the collective stress of the sublayers of the multilayer environmental barrier may be less than that of one or more silicon nitride layers including at least one of the diffusion barrier properties.

[0072] According to some embodiments of the present invention, a semiconductor die includes a semiconductor body and a multilayer environmental barrier including two or more sublayers stacked on the semiconductor body in a repeating layer structure. The multilayer environmental barrier includes two or more diffusion barrier properties. The collective stress of the multilayer environmental barrier is less than that of one or more silicon nitride layers including at least one of the diffusion barrier properties.

[0073] In some embodiments, each sublayer may include respective stress in one or more directions, and the respective stresses of at least two of the sublayers may be different.

[0074] In some embodiments, at least one of the diffusion barrier properties may include moisture protection, and the total thickness of the multilayer environmental barrier may be from about 500 angstroms to about 3500 angstroms.

[0075] In some embodiments, the collective stress of the multilayer environmental barrier may be less than that of one or more silicon nitride layers over the operating temperature range of a packaged device including the semiconductor die.

[0076] According to some embodiments of the present invention, a method of manufacturing a semiconductor die includes providing a semiconductor body and forming a multilayer environmental barrier including a plurality of sublayers stacked on the semiconductor body. Forming the multilayer environmental barrier includes forming a first stressor sublayer including a first stress and forming a second stressor sublayer including a second stress on the first stressor sublayer, the second stress at least partially compensating the first stress in one or more directions.

[0077] In some embodiments, the first stress may be tensile and the second stress may be compressive.

[0078] In some embodiments, forming the multilayer environmental barrier may include forming the first and second stressor sublayers using atomic layer deposition (ALD).

[0079] In some embodiments, forming the multilayer environmental barrier may include alternately performing a first ALD process to form the first stressor sublayer and a second ALD process to form the second stressor sublayer in a repeating layer structure.

[0080] In some embodiments, the first and second stressor sublayers may each include a first and a second oxide material, respectively, where the first oxide material is different from the second oxide material.

[0081] In some embodiments, at least one of the first or second stressor sublayers may include a metal-insulating material. The metal-insulating material may include at least one of aluminum oxide, zirconium oxide, or hafnium oxide.

[0082] In some embodiments, another one of the first or second stressor sublayers may include a metal.

[0083] In some embodiments, another one of the first or second stressor sublayers may include a non-metal insulating material.

[0084] In some embodiments, the metal-insulating material may include aluminum oxide, and the non-metal insulating material may include silicon oxide.

[0085] In some embodiments, the first stressor sublayer may include a first material having a greater density than a second material of the second stressor sublayer.

[0086] In some embodiments, the multilayer environmental barrier may include one or more diffusion barrier properties, and the collective stress of the sublayers of the multilayer environmental barrier may be less than that of one or more silicon nitride layers including at least one of the diffusion barrier properties.

[0087] In some embodiments, the total thickness of the multilayer environmental barrier may be from about 500 angstroms to about 3500 angstroms.

[0088] According to some embodiments of the present invention, a semiconductor die includes a semiconductor body and a multilayer environmental barrier on the semiconductor body. The multilayer environmental barrier includes a first sublayer of a metal insulating material and a second sublayer of a non-metal insulating material laminated to each other.

[0089] In some embodiments, the metal insulating material may be a metal oxide or a metal nitride, and the non-metal insulating material may be a non-metal oxide or a non-metal nitride.

[0090] In some embodiments, the metal insulating material may include at least one of aluminum (Al), zirconium (Zr), or hafnium (Hf), and the non-metal insulating material may include at least one of bismuth (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), or tellurium (Te).

[0091] In some embodiments, the first sublayer may be between the second sublayer and the semiconductor body.

[0092] In some embodiments, the first sublayer may include a first stress, and the second sublayer may include a second stress that at least partially compensates for the first stress in one or more directions.

[0093] In some embodiments, the first and second sublayers may be alternately laminated in a repeating layer structure. For example, the multilayer environmental barrier may include at least two repeating layer structures, at least 10 repeating layer structures, or at least 20 repeating layer structures.

[0094] In some embodiments, the semiconductor die may include a high electron mobility transistor.

[0095] In some embodiments, the semiconductor die may include a metal oxide semiconductor field effect transistor.

[0096] Other devices, apparatuses and / or methods according to some embodiments will become apparent to those skilled in the art upon review of the following drawings and detailed description. All such additional embodiments are intended to be included within this description, within the scope of the invention, and to be protected by the appended claims, in addition to any and all combinations of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0097]

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[0098] Packages for some semiconductor devices may not provide a hermetic seal for environmental protection in some applications. The environment may include an operating environment (i.e., when operating under bias in a user application) or a manufacturing environment (i.e., processing conditions that may include different ionic contaminant profiles such as integration, packaging techniques, etc.). Thus, a encapsulation structure or environmental barrier may be provided over a semiconductor device as protection from humidity and / or other conditions of the environment (also referred to as a die-level environmental barrier). As used herein, "die" or chip may refer to a small block or body of semiconductor material or other substrate on which electronic circuit elements are fabricated. The die may include a number of individual "unit cell" transistor structures that may be electrically connected in parallel or series in some implementations. The semiconductor die described herein may include a semiconductor body as well as metal and / or insulating layers formed thereon.

[0099] One implementation of the die-level environmental barrier may be the top or final passivation film, which is generally a single layer deposited by chemical vapor deposition (CVD). The material selection for the final passivation film may be determined by the desired diffusion barrier characteristics, and its function is to prevent various contaminant species present in a humid environment from reaching the active regions of the semiconductor die. For example, in addition to water vapor, a high-humidity environment may also contain trace elements of various atomic, molecular, and ionic contaminant species. Examples of various ionic species include, but are not limited to, halogens (e.g., Cl-, F-, Br-, etc.), molecular ions (e.g., OH-, NO2-, NO3-, PO4-, SO4-, etc.), cations (e.g., Na+, K+, Au+, Ti+, etc.), and weak organic acids (e.g., carbonates, acetates, etc.). Such ionic species can be a cause of degradation for electrical devices under bias. This is because the electric field may accelerate ion migration or diffusion through the moisture protection layer. For example, a PECVD SiN layer may provide diffusion barrier characteristics with respect to water molecules, but in addition to being susceptible to moisture ingress due to defects (such as pinholes and / or columnar structures), it is also susceptible to oxidation, etching, and / or corrosion in the presence of contaminant halogens (e.g., F- and Cl-). The presence of such contaminants can occur frequently and can be provided from multiple sources.

[0100] Some embodiments of the present invention may arise from the recognition that, considering a wide range of possible contaminant species, the selection of a protective film material can represent a non-ideal trade-off. Accordingly, embodiments of the present invention provide a protective film herein that includes a plurality of laminated sub-layers of various insulating materials (such as dielectric materials) having different properties, also referred to herein as a multi-layer environmental barrier film or stack or structure, or simply a multi-layer environmental barrier. The multi-layer environmental barrier may include respective insulating sub-layers having different diffusion barrier properties to protect the semiconductor die from not only water molecules but also various ionic species that may be present in the environment. That is, laminating sub-layers of various insulating materials having different diffusion coefficients (e.g., with respect to water molecules) can provide a humidity barrier that targets the movement of various ionic trace atoms in addition to water molecules in the environment. It will be understood that the layers or sub-layers described herein may have a uniform or varying thickness and / or may be continuous or discontinuous.

[0101] As discussed herein, the multi-layer environmental barrier is a low-defect, highly conformal material stack. In particular, the multi-layer environmental barrier may include two or more sub-layers of various materials and / or thicknesses (e.g., as an alternating or repeating layer structure in some embodiments) to target different contaminant species and provide a more robust humidity diffusion barrier for semiconductor devices. Some embodiments described herein may provide a multi-layer environmental barrier that includes additional sub-layers of different insulating materials that replace or are combined with (e.g., alternating with) SiN sub-layers, which may reduce defect formation and / or slow down the effect of halogens, thereby improving the diffusion barrier properties of the stack. In some embodiments, at least one of the sub-layers may include a material having a higher density than SiN that can prevent the ingress of moisture and / or other contaminants. More generally, the selection of different properties for the sub-layers described herein and / or additional interfaces defined between the sub-layers can provide an increased barrier against the propagation of defects or contaminants.

[0102] FIG. 1 is a schematic cross-sectional view of a semiconductor device or die 100 including a multilayer environmental barrier according to some embodiments of the present invention. As shown in FIG. 1, a multilayer environmental barrier film or stack 160 is provided over a semiconductor body 190 to protect the semiconductor body 190 from moisture and / or other environmental conditions. The semiconductor body 190 may be provided on a substrate (shown as 122 in subsequent figures) such as a silicon carbide (SiC) substrate. The semiconductor body 190 may be a SiC-based and / or group III nitride-based material in some embodiments. A portion of the semiconductor body 190 may define a channel region of a transistor device. Metal layers and / or other structures of such a transistor device are not shown in FIG. 1.

[0103] In some embodiments, an optional (shown by dashed lines) passivation layer or layer structure 150 may be provided on the surface of the semiconductor body 190, and the multilayer environmental barrier 160 may be provided on the passivation layer on the side opposite the semiconductor body 190. The passivation structure 150 may be configured to reduce the parasitic capacitance of one or more layers of the semiconductor body 190, reduce charge trapping, and / or otherwise enhance the electronic properties. When present, the passivation structure 150 may include, for example, one or more layers of SiN deposited by CVD. More generally, the passivation structure 150 may be a multilayer deposition using a deposition method other than atomic layer deposition (ALD).

[0104] The multilayer environmental barrier 160 includes two or more sub-layers 160a - 160d of respective insulating materials having different properties formed in a laminated structure. In some embodiments, the sub-layers 160a - 160d may be alternately laminated in a periodic or other repeating layer structure. For example, the multilayer stack 160 may include a two-layer stack (two sub-layers 160a, 160b per period, e.g., including AlOx - SiOx), a three-layer stack (three sub-layers 160a, 160b, 160c per period, e.g., including AlOx - SiOx - HfOx), or a four-layer stack (four sub-layers 160a, 160b, 160c, 160d per period, e.g., including AlOx - SiOx - HfOx - ZrOx). More generally, the multilayer environmental barrier 160 described herein is not limited with respect to the number of sub-layers 160a - 160d in each repeating structure or period. Similarly, the multilayer environmental barrier 160 described herein is not limited with respect to the number of repeating structures or periods in the stack. The multilayer stack 160 may include a combination of different repeating layer structures, e.g., in some examples, a repeating structure of a four-layer stack on a two-layer stack having one or more intervening layers. The repeating layer structure may be periodic or non-periodic. In some embodiments, the multilayer environmental barrier 160 may include at least two repeating layer structures or periods, at least ten repeating layer structures or periods, or at least twenty repeating layer structures or periods. Each repeating layer structure may have a thickness greater than about 5 nanometers (nm) (about 50 angstroms (Å)), e.g., about 10 nm (100 Å). Thus, the multilayer environmental barrier 160 may have a total thickness of about 500 Å to about 8000 Å, e.g., greater than about 1000 Å, greater than about 1500 Å, or greater than or equal to about 2000 Å.

[0105] Two or more different characteristics among the sub-layers 160a - 160d in each periodic or repeating layer structure may each provide a respective diffusion barrier characteristic. Each diffusion barrier characteristic may be defined by the material composition and / or thickness of each sub-layer 160a - 160d. For example, an insulating sub-layer of a relatively denser material (e.g., aluminum oxide or other insulating metal oxides or nitrides, having a higher density than silicon nitride) and / or an insulating sub-layer of a relatively greater thickness may provide better protection against the ingress of water / moisture and / or various ionic species that may be present in the environment. Insulating sub-layers of other materials (e.g., semiconductor oxides or nitrides such as silicon oxide) may provide better protection against etchants and / or other subsequent manufacturing conditions. As used herein, a "non-metallic" insulating material or layer refers to an insulating material or layer that does not contain metal but may include metalloids or semi-metals such as (but not limited to) bismuth (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te), etc. Examples of non-metallic insulating materials or layers may include, but are not limited to, metalloid oxides (e.g., BOx, SiOx, GeOx, AsOx, SbOx, TeOx) and metalloid nitrides (e.g., SiN).

[0106] The top sub-layer 160d of the stack 160 (or an additional capping layer 170 on the top sub-layer 160d) may be a non-metallic insulating material or layer (e.g., a semi-metallic insulating material such as silicon oxide or silicon nitride) that protects the underlying layer from subsequent chemical processing conditions (e.g., basic etching chemistry). Additionally, each interface between the multi-layer stack of sub-layers 160a - 160d having different characteristics can provide a barrier that prevents defects and / or contaminants in one sub-layer from propagating to the next sub-layer in the stack 160. Thus, laminating a plurality of sub-layers 160a - 160d of various materials and / or thicknesses, each configured based on its respective contaminants or environmental conditions (e.g., in a repeating layer structure), can provide protection against multiple contaminant species.

[0107] That is, the multilayer environmental barrier 160, which includes a combination of sub-layers 160a to 160d having different diffusion barrier characteristics, can be adjusted to protect against the entry of a wider range of contaminant species than any one of the sub-layers. Such contaminant species may include, but are not limited to, halogens (Cl−, F−, Br−), molecular ions (OH−, NO2−, NO3−, PO4−, SO4−, etc.), cations (Na+, K+, Au+, Ti+, etc.), and weak organic acids (carbonates, acetates, etc.). For example, the sub-layer 160a may include a material composition and / or thickness that provides a low diffusion coefficient with respect to water, the sub-layer 160b may include a material composition and / or thickness that provides a low diffusion coefficient with respect to halogen-based ionic species, the sub-layer 160c may include a material composition and / or thickness that provides a low diffusion coefficient with respect to non-halogen-based ionic species, and the sub-layer 160d may include a material composition and / or thickness that provides protection against basic chemical compounds. In some embodiments, the different sub-layers 160a to 160d may be deposited using the same deposition technique, such as ALD, which may enable the fabrication of the entire multilayer stack structure 160 in the same process chamber or, otherwise, without breaking the vacuum in the process chamber.

[0108] Combinations of different material compositions, thicknesses, and / or other properties of the respective sub-layers 160a - 160d may be varied or otherwise customized for different applications or environments and / or may provide combinations of properties for use in multiple applications or environments. For example, the multi-layer environmental barrier structure 160 as described herein may include sub-layers 160a - 160d having respective compositions that vary according to environmental conditions or contaminants specific to a particular package type, such as the exemplary package types shown in FIGS. 8A - 8C. It will be understood that the package types shown herein are provided by way of example and not limitation. Additional exemplary package types that may be associated with particular contaminants include, but are not limited to, through-hole-based, surface-mount-based, chip carriers, pin grid arrays, flat, small outline integrated circuits (SOIC), chip scale, ball grid arrays, transistor / diode / small pin count ICs, and / or multi-chip packages including ceramic or plastic packages. As another example, the multi-layer environmental barrier structure 160 as described herein may include sub-layers 160a - 160d each configured to provide a diffusion barrier against respective conditions or contaminants in order to provide a multi-layer environmental barrier 160 including a combination of sub-layers 160a - 160d that is universally applicable in a plurality of different environments or applications.

[0109] Figures 2, 3, and 4 are schematic cross-sectional views of transistor devices including a multilayer environmental barrier according to some embodiments of the present invention. As shown in FIGS. 2, 3, and 4, transistor devices 200, 300, and 400 are formed on a substrate 122 such as, for example, a silicon carbide substrate. The devices 200, 300, and 400 shown represent unit cell transistor structures of a semiconductor die, in which hundreds or thousands of unit cell transistor structures are formed on a semiconductor substrate 122 and may be electrically connected (e.g., in parallel). The substrate 122 may be a semi-insulating SiC substrate. However, embodiments of the present invention may utilize any suitable substrate such as sapphire (Al2O3), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), silicon (Si), GaAs, LAO, zinc oxide (ZnO), OAO, indium phosphide (InP), etc. The substrate 122 may be a SiC wafer, and the devices 200, 300, 400 may be formed, at least in part, via wafer-level processing, and then the wafer may be diced or otherwise singulated to provide dies including a plurality of unit cell transistor structures.

[0110] The semiconductor body 190 may be a semiconductor layer structure including one or more layers formed by epitaxial growth. The layers of the semiconductor body 190 may include one or more wide bandgap materials such as, for example, one or more group III nitride-based layers. For example, the semiconductor body 190 may be formed from one or more layers of GaN or AlGaN. However, other group III nitride materials may be used. As another example, both the substrate 122 and the semiconductor body 190 may be formed from SiC.

[0111] The source region 215 and the drain region 205 are formed in the semiconductor body 190, for example, by implanting appropriate ions into the surface of the semiconductor body 190 to achieve a desired doping concentration. The source contact 115 is formed by one or more metal layers on the surface of the semiconductor body 190 over the source region 215. Similarly, the drain contact 105 is formed by one or more metal layers on the surface of the semiconductor body 190 over the drain region 205. The source and drain contacts 115 and 105 may each provide a low-resistance ohmic contact to the source and drain regions 215 and 205. The gate 110 is formed by one or more metal layers on the surface of the semiconductor body 190 between the source region 215 and the drain region 205.

[0112] FIG. 2 shows a metal semiconductor field effect transistor (MESFET) device 200, where in this case the region of semiconductor body 190 between source and drain regions 215 and 205 provides the conductive channel or channel region of MESFET 200. FIG. 3 shows a metal oxide semiconductor field effect transistor (MOSFET) device 300, where in this case the region of semiconductor body 190 between source and drain regions 215 and 205 provides the channel region of MOSFET 300, and gate 110 is separated from the channel region by gate oxide layer 109. FIG. 4 shows a high electron mobility transistor (HEMT) device 400, where in this case semiconductor body 190 includes a low bandgap channel layer 124 on substrate 122 and a high bandgap barrier layer 126 on channel layer 124 opposite substrate 122. A 2DEG conduction channel 40 can be induced in the region of semiconductor body 190 between source and drain regions 215 and 205 along the heterointerface between channel layer 124 and barrier layer 126. In some embodiments, substrate 122 includes SiC, channel layer 124 includes GaN, and barrier layer 126 includes AlGaN. A metal field plate 128 may be provided and, in some embodiments, may be electrically connected to gate 110 (which may reduce the peak electric field, thereby increasing the breakdown voltage and reducing the high field charge trapping effect) or may be electrically connected to source contact 115 (which may reduce the gate-drain capacitance (C gd ), increase the gain, and / or improve the linearity of device 400).

[0113] One or more insulator layers (e.g., one or more passivation layers) 150 are formed on the surface of semiconductor body 190. The passivation layer 150 may passivate the surface state and / or otherwise improve the electrical characteristics along the surface or the interface with the semiconductor body 190. The passivation layer 150 may include SiN and in some embodiments may be deposited by a CVD process (such as PECVD) or other non-ALD process. Although mainly discussed herein with respect to the SiN passivation layer 150, it will be understood that the passivation layer 150 is not limited to SiN.

[0114] Transistor devices 200, 300, and 400 each include a multilayer environmental barrier 160. Selective capping layers such as the non-metal oxide-based or nitride-based capping layer 170 of FIG. 1 are not shown for ease of illustration. The examples of FIGS. 2, 3, and 4 are intended to show that the multilayer environmental barrier 160 is not limited to use with any particular transistor structure, but rather can be utilized as an environmental barrier for any suitable semiconductor device. Thus, further details regarding the operation of devices 200, 300, and 400 are not described in detail herein.

[0115] The multilayer environmental barrier 160 includes a plurality of insulating sub-layers (such as dielectric sub-layers) having different characteristics (such as different material compositions and / or thicknesses). As shown in FIGS. 2, 3, and 4, the multilayer environmental barrier layer 160 conformally covers various elements of transistor devices 200, 300, and 400. In some embodiments, the plurality of sub-layers of the multilayer environmental barrier 160 may be oxide layers of different materials deposited using the same process tool chamber or, alternatively, without breaking the vacuum in the process chamber. For example, each sub-layer of the multilayer environmental barrier 160 may be deposited using ALD, and ALD may enable the volume of structure 160 to include sub-layers having a high degree of conformality and thickness uniformity in the same process chamber.

[0116] As described herein, using multiple sub-layers of different material compositions and / or thicknesses may provide substantially improved environmental barrier properties compared to some conventional environmental barriers, such as those including alternating oxide and nitride sub-layers. Without being bound by any particular theory, it is recognized that such SiN sub-layers may be susceptible to oxidation, etching, and / or corrosion in the presence of contaminant halogens such as F- and Cl-. Additionally, it is recognized that ALD-based layers may provide improved conformality, which may be advantageous and / or important for moisture protection. However, SiN is generally deposited by CVD, which may result in defects (e.g., pin-holes, columnar structures). Also, the deposition of conventional alternating oxide and nitride sub-layers in the same may be problematic due to cross-contamination issues. It is further recognized that thicker and / or denser insulating films or sub-layers (such as insulating metal oxides) may provide improved protection against contaminant ingress. For example, AlO, HfO, and / or ZrO-based layers may have a higher density than SiN-based layers and may provide better moisture protection. Thus, in some embodiments, one or more sub-layers of different insulating materials may be laminated (or replaced) alternately with conventional oxide or nitride sub-layers, thereby providing a multi-layer environmental barrier having different diffusion barrier properties, i.e., improved resistance to oxidation, etching, and / or corrosion with respect to multiple different contaminants or combinations of different contaminants.

[0117] A plurality of material environmental barrier stacks can be customized to address wet environments having different contaminant compositions, for example, to provide a barrier to elements or chemicals other than (or in addition to) water. In some embodiments, at least one of the sub-layers may have a different density and / or thickness than the material of at least one other sub-layer of the multi-layer environmental barrier. For example, each insulating material of at least one of the sub-layers may have a density greater than SiN. Additionally, a non-metallic insulating film or sub-layer may be included in the stack to provide the desired chemical processing protection. Thus, combinations of stacked sub-layers of different material compositions and / or different thicknesses (e.g., in a repeating or periodic layer structure) as described herein can provide better protection against contaminant ingress and / or damage while simultaneously providing protection against subsequent manufacturing processes.

[0118] FIGS. 5A, 5B, 5C, 5D and 5E are enlarged views of transistor devices showing in more detail various combinations of sub-layers in a multi-layer environmental barrier according to some embodiments of the present invention. Two-layer periodic structures 160', 160'', 160''', 160 including first and second sub-layers alternately stacked on a selective passivation layer or layer structure 150 (4) , 160 (5) are shown in FIGS. 5A - 5E with respect to these structures 160', 160'', 160''', 160 (4) , 160 (5) are shown by way of example only, and it will be understood that the multi-layer environmental barriers 160', 160'', 160''', 160 (4) , 160 (5) , 160 (6) (collectively 160) may include three or more sub-layers having different properties (e.g., defining a three-layer structure, a four-layer structure), and / or may be stacked in a non-repeating layer structure or a periodic or non-periodic repeating layer structure.

[0119] In the example of FIG. 5A, the multilayer environmental barrier 160' includes a stack of sub-layers 160a', 160b' of respective insulating materials that are alternately laminated to define a periodic, repeating layer structure where each period includes a first sub-layer 160a' and a second sub-layer 160b'. One of the respective insulating materials of the first and second sub-layers 160a', 160b' may have a relatively higher density than the other. One or more of the sub-layers 160a', 160b' may have a greater density than that of SiN. Another of the sub-layers 160a', 160b' may have a density equal to or less than that of SiN. In FIG. 5A, the first sub-layer 160a' includes a relatively high-density insulating material, and the second insulating sub-layer 160b' includes a relatively low-density material. For example, the first insulating sub-layer 160a' may include a metal insulating material such as aluminum oxide (AlO), hafnium oxide (HfO), or zirconium oxide (ZrO), or other metal-rich insulating materials. That is, examples of metal insulating materials or layers may include, but are not limited to, metal oxides (e.g., AlO, HfO, ZrO) or metal nitrides. The second insulating sub-layer 160b' may include a non-metal insulating material, such as a semiconductor oxide or nitride like silicon oxide (SiO) or silicon nitride (SiN), or other metal-deficient insulating materials. As described above, examples of non-metal insulating materials or layers may include, but are not limited to, metalloid oxides (e.g., BOx, SiOx, GeOx, AsOx, SbOx, TeOx) and metalloid nitrides (e.g., SiN). The materials described herein with respect to compound chemical formulas (e.g., SiO) may include any compound of different stoichiometries or constituent elements, and the amorphous or crystalline state of the material. The typical densities of SiO, SiN, AlO, ZrO, and HfO are 2.65, 3.17, 3.95, 5.68, and 9.68 grams per cubic centimeter (g / cm 3 ) respectively. That is, with respect to material density, HfO > ZrO > AlO > SiN > SiO. Generally, a film with a higher density can provide better prevention of water or other contaminant ingress. For example, HfO and ZrO have higher densities than AlO, SiN, and SiO, and thus can better prevent the ingress of contaminants.

[0120] In the example of FIG. 5B, the multilayer environmental barrier 160'' includes a stack of sub-layers 160a'', 160b'' of respective oxide materials alternately laminated so as to define a periodic repeating layer structure in which each period includes a first oxide sub-layer 160a'' and a second oxide sub-layer 160b''. The respective oxide materials of the first and second oxide sub-layers 160a'', 160b'' may have different material compositions from each other. For example, the first oxide sub-layer 160a'' may include AlO, HfO, or ZrO, while the second oxide sub-layer 160b'' may include SiO. FIG. 5C shows a more specific example of a multilayer environmental barrier 160''' that includes a first sub-layer 160a''' of an insulating metal oxide material or layer (e.g., AlO, HfO, or ZrO) and a second sub-layer 160b''' of an insulating non-metal oxide material or layer (e.g., SiO) alternately laminated in a periodic repeating layer structure. Thus, the multilayer environmental barrier 160''' including alternately laminated first and second sub-layers 160a''' and 160b''' can reduce the susceptibility of the non-metal oxide sub-layer 160b''' to oxidation, etching, and / or corrosion. In the example of FIG. 5D, the multilayer environmental barrier 160 (4) includes a stack of sub-layers 160a of respective nitride materials alternately laminated so as to define a periodic repeating layer structure in which each period includes a first nitride sub-layer 160a (4) and a second nitride sub-layer 160b (4) and the respective nitride materials of the sub-layers 160a (4) , 160b (4) may have different material compositions from each other. FIG. 5E shows another example of a multilayer environmental barrier 160 (4) that includes a first sub-layer 160a (4) of an insulating metal oxide material (e.g., AlO, HfO, or ZrO) and a second sub-layer 160b (5) of a metal material (e.g., Al, Au) alternately laminated in a periodic repeating layer structure, and the metal sub-layer 160b (5) can provide a more effective barrier against moisture ingress. (5) (5)

[0121] As shown in FIGS. 5A to 5E, at least two of the sub-layers of each period of the multi-layer environmental barrier 160 may have different thicknesses from each other. For example, the first sub-layer 160a’ / 160a’’ / 160a’’’ / 160a (4) / 160a (5) / 160a (6) (collectively 160a) and the thickness T2 of the second sub-layer 160b’ / 160b’’ / 160b’’’ / 160b (4) / 160b (5) / 160b (6) (collectively 160b) may be greater than 2:1, may be greater than 5:1, may be greater than 8:1, or may be greater than 10:1 in some embodiments. The ratio of the thicknesses of the sub-layers 160a, 160b may depend on or be based on the respective densities of different insulating materials. For example, in the shown two-layer periodic layer structure, the sub-layer 160a’ of the first higher-density material may be deposited to have a thickness T1 greater than the thickness T2 of the sub-layer 160b’ of the second lower-density material. Similarly, the multi-layer environmental barrier 160 including a three-layer periodic layer structure or a four-layer periodic layer structure may include three sub-layers or four sub-layers respectively, and at least two of the sub-layers in each period may have different thicknesses.

[0122] Although FIGS. 5A to 5E show various sub-layer material combinations, it will be understood that the multi-layer environmental barrier according to embodiments of the present invention is not limited to these specific materials. For example, in some embodiments, the sub-layers 160a, 160b may include organic materials and inorganic materials alternately laminated to define the multi-layer environmental barrier 160. In particular, in FIG. 5B, one of the oxide layers 160a’’, 160b’’ may be replaced by an organic material sub-layer so as to define a multi-layer environmental barrier 160’’ of alternately positioned organic sub-layers / oxide sub-layers. Similarly, in FIG. 5B, one of the nitride layers 160a (4) 、160b (4) may be replaced by an organic material sub-layer so as to define a multi-layer environmental barrier 160 (4) of alternately positioned organic sub-layers / nitride sub-layers.

[0123] More generally, the multilayer environmental barrier 160 shown in FIGS. 5A - 5E may include two or more sub - layers 160a, 160b having different material compositions and the same thickness, the same material composition and different thicknesses, or different material compositions and different thicknesses. The two or more sub - layers 160a, 160b may be laminated in a repeating or non - repeating layer structure. The repeating layer structure may be periodic (having two or more periods) or aperiodic.

[0124] In a particular embodiment of the multilayer environmental barrier 160 shown in FIGS. 5A - 5C, the first sub - layer 160a of each period may be AlO and the second sub - layer 160b of each period may be SiO. The SiO sub - layer may be an amorphous layer (e.g., silica) or crystalline (e.g., SiO2). Similarly, the AlO sub - layer may be an amorphous layer (e.g., alumina) or a crystalline layer (e.g., Al2O3). AlO may be relatively stable and may be relatively easy to manufacture using widely available deposition tools compared to some nitride materials (e.g., SiN). AlO may have a higher density than SiN and thus may provide an improved moisture barrier. The AlO sub - layer may be, for example, several times thicker than the SiO sub - layer. This is because the deposition rate and / or density for AlO can be several times that of SiO. For example, the thickness T2 of the SiO sub - layer may be less than about one - fourth or less than about one - fifth of the thickness T1 of the AlO sub - layer in some embodiments. In a particular embodiment, the respective thicknesses T1 and T2 of the AlO and SiO sub - layers in the multilayer environmental barrier as described herein may be about 2 - 8 nm and 1 nm, respectively, such that the thickness ratio of AlO to SiO may be, for example, about 2:1 or more, about 5:1 or more, or about 8:1 or more.

[0125] Referring further to FIGS. 5A - 5E, a non - metallic insulating layer such as SiO or SiN may be included as the top sub - layer 160b of the multi - layer environmental barrier 160 or on top of the top sub - layer 160b. For example, SiO may protect sub - layers beneath the multi - layer environmental barrier structure 160 in further chemical processing that may rely on basic (non - acidic) chemistry. In some embodiments, the non - metallic insulating layer may be implemented by the top sub - layer 160b of the multi - layer environmental barrier 160. In other embodiments, the non - metallic insulating layer may be implemented by an additional SiO or SiN capping layer 170 formed on top of the top sub - layer 160b of the multi - layer environmental barrier 160. That is, the surface of the multi - layer environmental barrier 160 on the side opposite the passivation layer 150 may be a non - metallic insulating layer or may have a non - metallic insulating layer thereon.

[0126] In some embodiments, two or more sub - layers of the multi - layer environmental barrier 160 may be formed by a conformal deposition process such as ALD. An ALD (sub) layer or ALD material may refer to a layer or material formed by ALD, including but not limited to thermal ALD and plasma - enhanced ALD (PEALD) processes. The use of ALD to form multiple (or all) sub - layers in the multi - layer stack 160 enables sub - layers with a substantially uniform thickness that conformally extends along the underlying surface, that are thinner, and that have better step coverage than can be achieved by CVD. For example, ALD can achieve up to 100% conformality compared to about 80% CVD sidewall coverage of the upper or flat thickness. As described herein, the conformality of a layer along a particular surface may be expressed as a percentage of the thickness of the layer when deposited on a flat surface. The ALD process may also be advantageous in forming the multi - layer stack by enabling the fabrication of multiple thin sub - layers in the same chamber without additional wafer movement (i.e., without breaking vacuum) and without reset between sub - steps (e.g., to avoid cross - contamination).

[0127] FIGS. 6A, 6B, and 6C are STEM images showing cross-sectional views of transistor devices including multilayer environmental barriers formed from ALD oxide sublayers according to some embodiments of the present invention. In particular, FIG. 6A is a cross-sectional view of a HEMT device 600. FIG. 6B is an enlarged view of the passivation layer 150 and the multilayer environmental barrier 160 shown in FIG. 6A. FIG. 6C is an enlarged view of the multilayer environmental barrier 160 shown in FIG. 6B.

[0128] As shown in FIGS. 6A - 6C, the multilayer environmental barrier 160 may be a two-layer stack including alternating sublayers of ALD SiO and ALD AlO. The ALD process may enable the deposition of AlO and SiO sublayers with substantially uniform thickness and high conformality (e.g., greater than 80% and up to about 100% of the flat surface thickness). In particular, FIG. 6B shows that the AlO / SiO environmental barrier 160 substantially conforms to the shape of the underlying passivation layer 150 formed over the gate 110 and the field plate 128. Each of the AlO and SiO sublayers has a substantially uniform thickness and extends conformally along the shape defined by the passivation layer 150 and the underlying gate 110 and field plate 128 structures.

[0129] The AlO sub-layer may have a relatively high density and thus may provide improved moisture robustness and improved protection against oxidation, etching, and / or corrosion by contaminant halogens compared to SiN. The alternately positioned SiO sub-layers may define a plurality of AlO / SiO interfaces with the AlO layers, which can reduce or prevent the propagation of defects and / or contaminants of one sub-layer to the next sub-layer in stack 160. The SiO sub-layers may also provide protection in subsequent processing (e.g., against basic etching chemistry). Additionally or alternatively, the multi-layer environmental barrier 160 may include sub-layers of ALD HfO, ZrO, and / or SiN. In the exemplary device 600 shown in FIGS. 6A - 6C, the top or terminal layer in the multi-layer environmental barrier 160 is a SiO sub-layer. However, in other embodiments, an additional SiO or SiN capping layer 170 may be formed over the top sub-layer of the multi-layer environmental barrier 160.

[0130] FIGS. 7A, 7B, 7C, and 7D are cross-sectional views showing intermediate manufacturing steps in a method of manufacturing a multi-layer environmental barrier in a semiconductor device according to some embodiments of the present invention. As shown in FIG. 7A, the transistor structure includes a gate 110, a source contact 115, and a drain contact 105 over a semiconductor body 190 (including a channel layer 124 and a barrier layer 126 on a substrate 122 in this example, shown with respect to the HEMT device 400 of FIG. 4). A passivation layer or layer structure 150, such as a SiN-based passivation layer, is formed over the gate 110 and over portions of the semiconductor body 190 between the gate and the source and drain contacts 115 and 105.

[0131] A metal field plate 128 is formed on the passivation layer 150. Although shown as including a stepped profile that conformally extends along the passivation layer 150 having a first stepped portion adjacent to or overlapping the gate 110 and a second stepped portion adjacent to the drain contact 105, the field plate 128 may be implemented in various configurations in accordance with embodiments of the present invention. For example, the field plate 128 may have a substantially flat profile that extends along a portion of the passivation layer 150 between the gate 110 and the drain contact 105 or between the gate 110 and the source contact 115, and / or may be laterally spaced apart from the gate 110 such that there is no overlap of the gate 110 in the vertical (Z) direction.

[0132] As shown in FIGS. 7B and 7C, the ALD process is performed to conformally deposit a first insulating sublayer 160a on the surface of the passivation layer 150 and to conformally deposit a second insulating sublayer 160b on the surface of the first insulating sublayer 160a. For example, the first insulating sublayer 160a may include a metal insulating material such as AlO, HfO, ZrO, or other metal oxides or insulating layers having a density greater than SiN. In some embodiments, the second insulating sublayer 160b may include a non-metal insulating material such as SiO, SiN, or other non-metal oxides or insulating layers having a density equal to or less than SiN.

[0133] The ALD process may rely on alternating self-limiting reactions between gaseous reactants and an exposed solid surface to deposit highly conformal insulating sub-layers 160a, 160b having a substantially uniform thickness that may be controllable at the sub-monolayer level. In particular, the semiconductor body 190 including features 105, 110, 115, 128, and 150 formed thereon is exposed to two reactants A (in FIG. 7B) and B (in FIG. 7C) in a continuous non-overlapping manner in the process chamber. In FIG. 7B, reactant A reacts with a finite number of reaction sites on the exposed surfaces of the semiconductor body 190 and the features to define the first sub-layer 160a, and growth stops when a finite number of sites are consumed in a self-limiting fashion. The remaining amount of reactant A is exhausted from the chamber, and without breaking the vacuum in the chamber, reactant B is introduced in FIG. 7C. Reactant B similarly reacts with a finite number of reaction sites on the exposed surface to define the second sub-layer 160b, growth stops when a finite number of sites are consumed, and the remaining amount of reactant B is exhausted from the chamber. By alternating exposure to reactants A and B, a thin film multi-layer environmental barrier 160 including alternatingly positioned sub-layers 160a and 160b is deposited as shown in FIG. 7D.

[0134] The ALD process deposits sub-layers 160a and 160b having a substantially uniform thickness and high conformality over complex underlying shapes or structures. For example, ALD may achieve conformality of up to 100% of the thickness of the flat portions of sub-layers 160a and 160b. The ALD process may also be advantageous in forming the multi-layer stack 160 by enabling the fabrication of multiple thin sub-layers 160a, 160b in the same chamber without additional wafer movement (i.e., without breaking the vacuum) and without reset between sub-steps (e.g., to avoid cross-contamination).

[0135] In some embodiments, at lower temperatures, an ALD process such as that shown in FIGS. 7B and 7C may produce an amorphous film, which may then be crystallized. For example, in some embodiments, a first sublayer 160a may be deposited as amorphous AlO (also referred to as AlOx), which may be crystallized to form Al2O3. A second sublayer 160b may be deposited as amorphous SiO (also referred to as SiOx), which may be crystallized to form SiO2. A non-metal oxide layer such as SiO or SiN may be formed using an ALD or non-ALD process as the topmost sublayer 160b of the multilayer environmental barrier 160 or on top of the topmost sublayer 160b (e.g., as a capping layer 170).

[0136] As described above, a multilayer environmental barrier structure 160 as described herein may include sublayers having respective compositions selected based on application-specific environmental conditions / contaminants. For example, the environmental conditions / contaminants may be specific to a particular semiconductor package type, including ceramic or plastic packages such as open cavities, overmolds, thermally enhanced, through-hole-based, surface mount-based, chip carriers, pin grid arrays, flat, small outline integrated circuits (SOICs), chip scale, ball grid arrays, transistor / diode / small pin count ICs, and / or multi-chip packages. Thus, some embodiments described herein may provide a multilayer environmental barrier structure 160 that includes sublayers of respective materials that are intended to correspond to a particular package technology.

[0137] FIGS. 8A, 8B, and 8C are schematic cross-sectional views showing a plurality of exemplary package types 800A, 800B, 800C, each package technology 800A, 800B, 800C may contain specific ionic or other contaminant contents. FIGS. 8A-8C show the packaging of a transistor device 1000 that may include any of the transistor structures 200, 300, 400 described herein.

[0138] In particular, FIG. 8A is a schematic side view of a package 800A for a group-III nitride-based RF transistor amplifier. As shown in FIG. 8A, the packaged RF transistor amplifier 800A includes an RF transistor amplifier die 1000 packaged in an open-cavity package structure 810A. The package structure 810A includes a metal gate lead 822A, a metal drain lead 824A, a metal submount 830, sidewalls 840, and a lid 842.

[0139] The submount 830 may include materials configured to assist in the thermal management of the package 800A. For example, the submount 830 may include copper and / or molybdenum. In some embodiments, the submount 830 may be composed of multiple layers and / or may include vias / interconnects. In an exemplary embodiment, the submount 830 may be a multi-layer copper / molybdenum / copper metal flange including a core molybdenum layer having copper cladding layers on its respective major surfaces. In some embodiments, the submount 830 may include a metal heat sink that is part of a lead frame or a metal slug. The sidewalls 840 and / or the lid 842 may be formed from an insulating material or may include an insulating material in some embodiments. For example, the sidewalls 840 and / or the lid 842 may be formed from a ceramic material or may include a ceramic material. In some embodiments, the sidewalls 840 and / or the lid 842 may be formed from, for example, Al2O3. The lid 842 may be adhered to the sidewalls 840 using an epoxy glue. The sidewalls 840 may be attached to the submount 830, for example, via brazing. The gate lead 822A and the drain lead 824A may be configured to penetrate the sidewalls 840, but embodiments of the present invention are not limited thereto.

[0140] The RF transistor amplifier die 1000 is mounted on the upper surface of the metal submount 830 in an air-filled cavity 812 defined by a metal submount 830, a ceramic sidewall 840, and a ceramic lid 842. The gate and drain terminals 132, 134 of the RF transistor amplifier die 1000 are on the upper side of the semiconductor structure 190, while the source terminal 136 is on the lower side of the semiconductor structure 190. The source terminal 136 may be mounted on the metal submount 830 using, for example, a conductive die attach material (not shown). The metal submount 830 may provide an electrical connection to the source terminal 136 and may also function as a heat dissipation structure that dissipates heat generated in the RF transistor amplifier die 1000.

[0141] The input matching circuit 850 and / or the output matching circuit 852 may also be mounted within the package 800A. The matching circuits 850, 852 may include impedance matching and / or harmonic termination circuits. The impedance matching circuit may be used to match the impedance of the fundamental components of the RF signals input to or output from the RF transistor amplifier to the impedance at the input or output of the RF transistor amplifier die 1000, respectively. The harmonic termination circuit may be used to ground the harmonics of the fundamental RF signal that may be present at the input or output of the RF transistor amplifier die 1000. Two or more input matching circuits 850 and / or output matching circuits 852 may be provided. As schematically shown in FIG. 8A, the input and output matching circuits 850, 852 may be mounted on the metal submount 830. The gate lead 822A may be connected to the input matching circuit 850 by one or more bond wires 854, and the input matching circuit 850 may be connected to the gate terminal 132 of the RF transistor amplifier die 1000 by one or more additional bond wires 854. Similarly, the drain lead 824A may be connected to the output matching circuit 852 by one or more bond wires 854, and the output matching circuit 852 may be connected to the drain terminal 134 of the RF transistor amplifier die 1000 by one or more additional bond wires 854. The bond wire 854, which is an inductive element, may form part of the input and / or output matching circuit.

[0142] The multilayer environmental barrier 160 as described herein is formed on the upper side of the semiconductor structure 190 and may be patterned to expose the gate and drain terminals 132, 134. The multilayer environmental barrier 160 may include, for example, two or more sub-layers of respective insulating materials in a repeating layer structure, as described above. The composition and / or thickness of the sub-layers, the number of sub-layers, and / or the number of periods may vary based on the ionic content or other contaminants that may be present in a particular package type 800A, 800B, 800C.

[0143] Figure 8B is a schematic side view of a packaged group-III nitride-based RF transistor amplifier 800B that includes a transistor device 1000 packaged in a printed circuit board-based package structure 810B. The packaged RF transistor amplifier 800B is very similar to the packaged RF transistor amplifier 800A of FIG. 8A, except that the gate and drain leads 822A, 824A of the package structure 810A are replaced with printed circuit board-based leads 822B, 824B in the package structure 810B.

[0144] The package structure 810B includes a submount 830, ceramic sidewalls 840, and a ceramic lid 842, which may be substantially identical to the same numbered elements of the package structure 810A discussed above. The package structure 810B further includes a printed circuit board 820. Conductive traces on the printed circuit board 820 form a metal gate lead 822B and a metal drain lead 824B. The printed circuit board 820 may be attached to the submount 830, for example, via a conductive glue. The printed circuit board 820 includes a central opening, and the RF transistor amplifier die 1000 is mounted within this opening in the submount 830. The other components of the RF transistor amplifier 800B may be the same as the same numbered components of the RF transistor amplifier 800A, and thus, further description thereof is omitted.

[0145] FIG. 8C is a schematic side view of another packaged group-III nitride-based RF transistor amplifier 800C. The RF transistor amplifier 800C differs from the RF transistor amplifier 800A in that it includes a different package structure 810C. The package structure 810C includes a metal submount 830 (which may be similar or identical to the submount 830 of the package structure 810A), and metal gate and drain leads 822C, 824C. The RF transistor amplifier 800C also includes a plastic overmold 860 that at least partially surrounds the RF transistor amplifier die 1000, leads 822C, 824C, and metal submount 830. Since the other components of the RF transistor amplifier 800C may be the same as the components of the same number of the RF transistor amplifier 800A, further description thereof is omitted.

[0146] FIG. 9 is a schematic plan view of a transistor device or die 1000 showing the metallization on the surface of the semiconductor structure 190. The multilayer environmental barrier 160 and / or other dielectric layers provided as described herein to separate the various conductive elements of the metallization structure from each other are not shown in FIG. 9 for the sake of simplicity of the drawing.

[0147] As shown in FIG. 9, the transistor device or die 1000 may include a plurality of transistor structures 900 connected in parallel to device terminals or electrodes (e.g., input terminals, output terminals, and ground terminals). For example, each of the gate 110, drain 105, and source 115 contacts may extend in a first direction (e.g., the Y direction), thereby defining gate, drain, and / or source “fingers” that may be connected by one or more respective buses (e.g., gate bus 112 and drain bus 114 on the upper surface of the semiconductor structure 190).

[0148] In FIG. 9, gate fingers 110, drain fingers 105, and source fingers 115 extend parallel to each other, with gate fingers 110 extending from gate bus 112 in a first direction and drain fingers 105 extending from drain bus 114 in a direction opposite to the first direction. Each gate finger 110 may be positioned between drain finger 105 and source finger 115 to define a unit cell 900 such as the unit cell transistor structures 200, 300, 400 described herein. Gate fingers 110, drain fingers 105, and source fingers 115 (and connecting buses) may each define a part of the gate-connected, drain-connected, and source-connected electrodes of the device, as defined by an upper-side or front-side metallization structure. Gate fingers 110 are electrically connected to a common gate bus 112, drain fingers 105 are electrically connected to a common drain bus 114, and source fingers 115 are electrically connected together (e.g., via respective via openings 146 and a back-side metal layer on the back surface of substrate 122), so it can be seen that unit cell transistors 900 are electrically connected together in parallel.

[0149] One of the terminals of the device (e.g., the source terminal connected to source contact 115) may be configured to be coupled to a reference signal such as electrical ground. In some embodiments, a conductive substrate via connection or structure (e.g., a back-side via opening formed through the back surface) may pass through substrate 122 and epitaxial layers 124, 126, thereby ejecting a part of one of contacts 105, 115 and enabling contact with a pad or terminal on the back side of the substrate (e.g., to couple source contact 115 to ground). In other embodiments, a ground connection to one of the terminal devices (e.g., the source terminal) may be provided outside the active region, e.g., in the peripheral region. In some embodiments, a back-metal layer on the back side of substrate 122 may provide a back-side ground plane, e.g., in applications where proximity to ground may be desired.

[0150] Further embodiments of the present invention can arise from the recognition that moisture protection can be improved by increasing the thickness of the environmental barrier film. However, in some single-layer environmental barrier films, the increased thickness also increases the uniaxial static film stress during operation, which can reduce or degrade the device lifetime. For example, as discussed herein, SiN deposited by CVD may be used as an environmental barrier film. CVD-based SiN films can include a predetermined type of stress (e.g., tensile or compressive) that can be adjusted by adjusting the deposition conditions (e.g., temperature), but the magnitude of the stress can increase with the thickness of the SiN layer. The increased stress can, for example, adversely affect device characteristics in the transistor channel region. In particular, in HEMT devices, the stress may affect the carrier density in the 2DEG channel, which can result in a degradation of device performance.

[0151] As used herein, the term "stress" may refer to the force applied between adjacent particles of a material (such as may be induced by intrinsic forces from layers located above or below, for example), while "strain" may refer to a measure of the deformation of a material (such as due to stress from a layer). Embodiments of the present invention may provide a stress-compensated multilayer encapsulation structure or environmental barrier configured to reduce or minimize stress while also providing moisture protection equal to or better than some conventional environmental barrier films in some embodiments. For example, uniaxial stress can be reduced or minimized by providing a multiaxial stress (e.g., uniaxial, biaxial, or triaxial) in a multilayer thin film as described herein. The overall stress may be compensated by fabricating sublayers of the multilayer environmental barrier to provide different types and / or directional stresses in each sublayer, such that each sublayer may compensate for the stress provided by the sublayer above and / or below it in the stack.

[0152] As used herein, a layer or sublayer that "compensates" for the stress of another layer or sublayer may counteract (with respect to the type and / or direction), at least partially compensate for, or react against a particular type and / or direction of stress of the other layer or sublayer. That is, a multilayer environmental barrier film as described herein may include sublayers having respective stresses that vary in type (e.g., tensile or compressive) and / or direction (e.g., X, Y, and / or Z directions). For example, state-of-the-art deposition techniques such as atomic layer deposition (ALD) may be used to form multilayer films having sublayers of various materials, whereby each sublayer has respective stresses that are different from those of the sublayer above or below it. ALD may be used to form sublayers of different materials in various combinations, including two-layer, three-layer, and four-layer stacks. A multilayer environmental barrier as described herein may be configured to provide stress reduction, either alone or in combination with the diffusion barrier properties (e.g., moisture protection) described herein.

[0153] FIG. 10 is an enlarged view of a transistor device that more particularly shows an exemplary combination of stress compensation sublayers in a multilayer environmental barrier formed on a semiconductor body according to some embodiments of the present invention. A two-layer periodic structure 160 including first and second stressor sublayers 160a (6) , 160b (6) alternately laminated on a selective passivation layer or layer structure 150 (6) is shown in FIG. 10 with respect thereto, but this structure 160 (6) is shown by way of example only, and with respect to the multilayer environmental barriers 160', 160'', 160''', 160 (4) , 160 (5) with respect to the multilayer environmental barrier 160 (6)(collectively 160) may include three or more stressor sub-layers having different respective stresses (e.g., defining a three-layer structure, a four-layer structure), and / or may be deposited in a non-repeating layer structure or a periodic or non-periodic repeating layer structure directly on the semiconductor body 190 and the gate 110, drain 105 and source 115 contacts, or on a selective intervening passivation layer 150. It will be understood that this is possible.

[0154] In the example of FIG. 10, the multilayer environmental barrier 160 (6) is a stressor sub-layer 160a of each material alternately stacked to define a periodic repeating layer structure including a first sub-layer 160a having a respective stress with a different type and / or direction for each period (6) and a second sub-layer 160b (6) The stressor sub-layers 160a (6) and 160b (6) of the stack. One of each of the first and second stressor sub-layers 160a (6) and 160b (6) of each material may be configured to provide a stress that at least partially counteracts or compensates for the type and / or direction of stress in the other. For example, the first stressor sub-layer 160a (6) may be an AlO film, and the second stressor sub-layer 160b (6) may be an SiO film (e.g., having tensile and compressive stresses respectively), and may be alternately formed as a two-layer stack in a repeating layer structure using a relatively simple and stable ALD process.

[0155] As shown in FIG. 10, the first stressor sub-layer 160a (6) may include tensile stress (indicated by opposing arrows pointing in a direction away from each other along the X direction), whereas the second stressor sub-layer 160b (6) is the first stressor sub-layer 160a (6)may include a compressive stress (indicated by opposing arrows facing each other along the X direction) that can at least partially compensate for the tensile stress, or vice versa, whereby the overall or collective stress of the multilayer environmental barrier 160 (6) is reduced or minimized. The material, thickness, and / or manufacturing process of each stressor sublayer 160a (6) , 160b (6) may be selected such that the stress in each sublayer 160a (6) , 160b (6) etc. is at least partially counteracted by the immediately above and / or below sublayers. Thus, the stress direction of each sublayer is shown by way of example only and it will be understood that it can be varied to provide the desired type and / or direction of stress by changing the deposition conditions and post-treatment (e.g., annealing). More generally, a sublayer may be described and illustrated herein with respect to a particular stress type (e.g., tensile or compressive) and / or direction of stress (e.g., X, Y, and / or Z directions), but a sublayer may have a stress type opposite to that shown and / or a different direction depending on the selected manufacturing process and / or conditions.

[0156] In the example of FIG. 10, the material of the first stressor sublayer 160a (6) may be selected and deposited to have a tensile stress such that the sublayer 160a (6) is induced, for example, by the inherent forces from the underlying layer. For example, in some embodiments, one or more selective passivation layers 150 (e.g., CVD-based SiN) may be formed on the surface of the semiconductor body 190 prior to the multilayer environmental barrier 160 (6) to passivate the surface condition and / or improve the electrical properties along the surface of the semiconductor body 190. The passivation layer 150 may also protect against metal corrosion of the gate 110, source 115, and drain 105 contacts. However, the passivation layer 150 may introduce additional stress (e.g., compressive stress from a SiN-based passivation layer 150).

[0157] Referring further to FIG. 10, the second stressor sublayer 160b (6) is made of a material such that the sublayer 160b (6) has a compressive stress, for example, to compensate for or otherwise oppose the tensile stress of the underlying first sublayer 160a (6) and may be selected and deposited. In some embodiments, the passivation layer 150 may be omitted, and the stressor sublayers 160a (6) and 160b (6) of the multilayer environmental barrier 160 (6) may be formed directly on the surfaces of the semiconductor body 190 and the gate 110, source contact 115, and drain contact 105, and may be formed conformally, for example, with substantially uniform respective thicknesses T1 and T2. The stressor sublayers 160a (6) and 160b (6) of the multilayer environmental barrier 160 may be implemented in the stack in any order, such that the stress of each sublayer at least partially opposes or compensates for the stress of the layer above or below it in the stack, as will be understood.

[0158] The multilayer environmental barrier 160 (6) The stressor sublayers 160a (6) and 160b (6) defining the repeating layer structure may have the same or different thicknesses from each other. In some embodiments, at least two of the sublayers of each period of the multilayer environmental barrier 160 (6) may have different thicknesses from each other. In particular, FIG. 10 shows a two-layer periodic layer structure, in which case the first tensile stress material sublayer 160a (6) may be deposited with a thickness T1 greater than the thickness T2 of the second compressive stress material sublayer 160b (6) . Similarly, the multilayer environmental barrier 160 including a three-layer periodic layer structure or a four-layer periodic layer structure (6) may include three sublayers or four sublayers, respectively, in which case at least two of the sublayers in each period may have different thicknesses and / or stresses.

[0159] The first sub-layer 160a (6) and the thickness T1 of the second sub-layer 160b (6) may be varied depending on or based on the magnitude of the stress in each sub-layer and the compensating stress of the sub-layer above or below it. For example, the thickness T1 of the first sub-layer 160a (6) and the thickness T2 of the second sub-layer 160b (6) may be about 1:1, about 1:2, about 1:5, about 1:8, or about 1:10 or more. That is, the thickness ratio of the stressor sub-layers 160a (6) , 160b (6) may depend on or be based on the respective stresses of the different materials of the stressor sub-layers 160a (6) , 160b (6) and the effects provided to the layer above or below it. It will be understood that the relative sizes or dimensions are shown by way of example only and are not intended to be limiting with respect to atomic size, density, or other properties of the layers. Also, although shown primarily with respect to uniaxial or biaxial strain (e.g., in the X and / or Y directions), it will be understood that the sub-layers described herein may be strained in additional directions and / or directions different from those specifically shown (e.g., triaxial strain in the X, Y, and Z directions).

[0160] In some embodiments, the multilayer environmental barrier 160 (6) may be configured to provide stress reduction in combination with diffusion barrier properties (e.g., moisture protection). Thus, the thickness T1 of the first sub-layer 160a (6) and the thickness T2 of the second sub-layer 160b (6) may be about 2:1, about 5:1, about 8:1, or about 10:1 or more, as described above with respect to the embodiments of FIGS. 5A - 5E.

[0161] For example, as described above with reference to FIG. 5A, the first stressor sub-layer 160a (6) may include a material of relatively high density (e.g., AlO, HfO, ZrO, or other metal-rich insulating material), and the second stressor sub-layer 160b (6)may include a relatively low-density material (e.g., SiO, SiN, or other metal-deficient insulating material). Stressor sub-layers 160a (6) , 160b (6) of one or more may have a higher density than SiN, while stressor sub-layers 160a (6) , 160b (6) of another may have a density equal to or less than SiN. When configured to provide stress reduction in combination with moisture protection, the first high-density material sub-layer 160a (6) may first be deposited with a greater thickness T1, and then the second low-density material sub-layer 160b (6) is deposited with a smaller thickness T2, whereby the first stressor sub-layer 160a (6) is between the second stressor sub-layer 160b (6) and the semiconductor body 190.

[0162] In some embodiments, as described above with reference to FIG. 5B, the first and second stressor sub-layers 160a (6) , 160b (6) may each be an oxide material alternately laminated to define a periodic repeating layer structure. For example, as described above with reference to FIG. 5C, the first and second stressor sub-layers 160a (6) , 160b (6) may include an insulating metal oxide material or layer (e.g., AlO, HfO, or ZrO) and an insulating non-metal (e.g., semi-metal) oxide material or layer (e.g., SiO) alternately laminated in a periodic repeating layer structure, and the metal oxide sub-layer may improve the susceptibility of the non-metal oxide sub-layer to oxidation, etching, and / or corrosion. In some embodiments, as described above with reference to FIG. 5D, the first and second stressor sub-layers 160a (6) , 160b (6) may each include a nitride material alternately laminated to define a periodic repeating layer structure, and each nitride material of the sub-layers may have different material compositions from each other.

[0163] Multilayer environmental barrier 160 (6) of stressor sublayer 160a (6) 、160b (6) is not necessarily limited to an insulating layer. For example, as described above with reference to FIG. 5E, one or more metal layers may be formed in a stack to provide a desired tensile stress or compressive stress in one or more desired directions, for example, based on the selection and / or deposition process of materials such as those described herein. Thus, the multilayer environmental barrier 160 (6) is a first sublayer 160a of an insulating metal oxide material (e.g., AlO, HfO, or ZrO) alternately laminated in a periodic repeating layer structure (6) and a second sublayer 160b of a metal material (e.g., Al, Au) (6) and may include a metal sublayer 160b (6) which may provide a more effective barrier against moisture ingress.

[0164] The multilayer environmental barrier 160 according to an embodiment of the present invention (6) will be understood not to be limited to the specific sublayer material combinations described with respect to the above examples. For example, in some embodiments, the stressor sublayers 160a (6) 、160b (6) may include organic and inorganic materials alternately laminated to define the multilayer environmental barrier 160 (6) More generally, the multilayer environmental barrier 160 (6) may include any combination of sublayers configured to at least partially react against the stress of the sublayers above and / or below it.

[0165] In some embodiments, two or more sublayers of the multilayer environmental barrier 160 (6) may be formed by a conformal deposition process such as ALD (including, but not limited to, thermal ALD and plasma-enhanced ALD (PEALD) processes). For example, the stressor sublayers 160a shown in FIG. 10 (6) 、160b (6)may be formed according to the operations shown in FIGS. 7A-7D. The ALD process conformally deposits a first stressor sublayer 160a (shown more generally as 160a) on a transistor structure including a gate 110, a source contact 115, and a drain contact 105 on a semiconductor body 190 (shown with respect to a HEMT device). (6) and a second stressor sublayer 160b (shown more generally as 160b) is conformally deposited on the surface of the first insulating sublayer 160a. (6) This is done to conformally deposit a second stressor sublayer 160b (shown more generally as 160b) on the surface of the first stressor sublayer 160a. More specifically, a thin film multilayer environmental barrier 160 including stressor sublayers 160a and 160b that are alternately positioned in a repeating (e.g., bilayer) layer structure is deposited with substantially uniform thickness and high conformality over an underlying complex shape or structure as shown in FIG. 7D by alternately exposing to reactant A (as shown in FIG. 7B) and reactant B (as shown in FIG. 7C). Additional reactants may be included in the alternating exposures to deposit a three- or four-layer repeating layer structure. In some embodiments, at lower temperatures, the ALD processes shown in FIGS. 7B and 7C may produce amorphous stressor sublayer films, which may then be crystallized. For example, the first stressor sublayer 160a may be deposited as amorphous AlOx, which may be crystallized to form Al2O3. The second stressor sublayer 160b may be deposited as amorphous SiOx, which may be crystallized to form SiO2.

[0166] Although mainly described in the above examples with respect to ALD-based manufacturing, it will be understood that the stressor sublayers 160a (6) and 160b (6) of the multilayer environmental barrier 160 (6) may be formed by deposition methods other than ALD. For example, CVD may be used to form the multilayer film 160 as described herein in some embodiments. However, thinner CVD-based sublayers 160a (6) and 160b (6) ​(6) may be too porous to provide the desired moisture barrier performance, while the thicker CVD-based sublayers 160a (6) and 160b (6) may increase the stress for each sublayer. Also, the quality of the CVD-based barrier film 160 can be improved by manufacturing at higher temperatures, but such temperatures can be detrimental to the characteristics and / or operation of the device in the underlying semiconductor layer structure 190.

[0167] FIG. 11 is a graph showing normalized stress measurements over temperature changes during heating and cooling for a conventional single-layer film formed by CVD (also referred to herein as a CVD-based single-layer film) and a multilayer environmental barrier formed by ALD according to some embodiments of the present invention, with the initial stress normalized to zero. For example, a high-accelerated life test (HAST) process may involve heating and cooling of the device over an operating temperature range of up to about 400 degrees Celsius (°C).

[0168] As shown in FIG. 11, a conventional CVD-based single-layer film (e.g., a SiN-based film) may exhibit a stress change 1110 of about 235 megapascals (MPa) during heating and cooling over a normalized operating temperature range from room temperature (25 °C) to the maximum device operating temperature. In contrast, FIG. 11 shows that an ALD-based multilayer AlOx and SiOx environmental barrier film according to some embodiments of the present invention may exhibit a stress change 1160 of only about 40 MPa during heating and cooling over the same room temperature to maximum device operating temperature range. Thus, the environmental barrier films according to some embodiments of the present invention may include reduced stress (and a smaller change in stress) over the temperature range that can be experienced during device operation due to the overall compensated stress provided by its plurality of stressor sublayers compared to a CVD-based single-layer SiN film. That is, the multilayer environmental barrier films according to embodiments of the present invention may result in a lower level of stress and / or a smaller change in stress (and thus greater stability) over device operating conditions than some conventional single-layer films that can reduce the operating life of the device.

[0169] The multilayer environmental barriers and single-layer films shown in the graph of FIG. 11 may have respective thicknesses and / or other properties that provide one or more similar diffusion barrier characteristics (e.g., similar or equal moisture protection). For example, the prior art may use CVD-based SiNx to provide an environmental barrier film, which may require a greater thickness (e.g., from about 5000 angstroms to about 10,000 angstroms) to provide a desired level of moisture protection, and thus may result in a higher uniaxial stress (e.g., a difference of about 235 MPa before and after heating and cooling in this example). In contrast, multilayer environmental barrier films as described herein (e.g., including alternating layers of ALD-based AlOx and SiOx) can provide a significant reduction in stress (less or even negligible due to measurement tolerances) at comparable or superior moisture robustness with a smaller overall thickness in some examples (e.g., from about 500 angstroms to about 3500 angstroms, e.g., from about 1000 angstroms to about 3000 angstroms or from about 1500 angstroms to about 2500 angstroms). In other words, the combined stress of the sublayers 160a, 160b of the multilayer environmental barrier 160 may be less than the combined stress of one or more SiN layers that provide similar diffusion barrier characteristics over a temperature range from about room temperature (25° C.) to the maximum device operating temperature in some embodiments. The sublayers can be deposited using a non-ALD process in some embodiments.

[0170] Multilayer environmental barrier stacks according to embodiments of the present invention (e.g., 2-layer stacks, 3-layer stacks, 4-layer stacks, etc.) can thus provide equivalent or superior diffusion barrier characteristics with lower combined stress and / or a smaller thickness compared to SiN films. As noted above, the multilayer environmental barriers are not limited to alternating AlOx and SiOx sublayers, and alternatively may include HfO, ZrO, and / or SiN sublayers, and / or other sublayers, depending on the desired compensating stress and / or direction.

[0171] Embodiments of the present invention that include a multilayer environmental barrier structure as described herein may provide improved performance in passive and / or active RF devices. However, embodiments of the present invention are not limited to RF applications and may be used in a variety of other applications, including any semiconductor IC technology that may require moisture robustness. For example, embodiments of the present invention may be used in applications having operating frequencies in the range from less than about 6 GHz to the Ku-band (6 - 18 GHz) and Ka-band designs (e.g., 26 - 40 GHz). Certain embodiments of the present invention may be used in various cellular infrastructure (CIFR) RF power products (including, but not limited to, 5W, 10W, 20W, 40W, 60W, 80W, and different frequency bands) for, e.g., 5G and base station applications, including macro (e.g., 20 - 80W and different frequency bands) average power applications. Embodiments of the present invention may be applied to radar, monolithic microwave integrated circuit (MMIC) type applications, dielectric crossover devices, and split gate devices. More generally, embodiments of the present invention may be used in any semiconductor IC technology that requires moisture robustness and / or stress reduction.

[0172] The present invention is described with reference to the accompanying drawings, in which embodiments of the invention are shown. However, the present invention should not be construed as being limited to the embodiments shown herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. The same numbers refer to the same elements throughout.

[0173] When an element such as a layer, region, or substrate is described as being "on" or extending "onto" another element, it will be understood that the element can be directly on or extend directly onto the other element or that intervening elements may be present. In contrast, when an element is described as being "directly on" or extending "directly onto" another element, no intervening elements are present. When an element is described as being "connected" or "coupled" to another element, it will also be understood that the element can be directly connected or coupled to the other element or that intervening elements may be present. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, no intervening elements are present.

[0174] For the purpose of describing various elements, terms such as first, second, etc. may be used in this specification, but it will also be understood that these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present invention, the first element can be called the second element, and similarly, the second element can be called the first element.

[0175] Furthermore, relative terms such as "lower" or "lower side" and "upper" or "upper side" may be used in this specification to describe the relationship of one element to another element shown in the drawings. It will be understood that relative terms are intended to include different orientations of the device in addition to the orientation shown in the drawings. For example, if the device in one of the drawings is inverted, an element described as being "below" another element will be oriented "above" the other element. Thus, the exemplary term "below" includes both the "below" and "above" orientations depending on the particular orientation of the drawing. Similarly, if the device in one of the drawings is inverted, an element described as being "beneath" or "lower side" of another element will be oriented "above" the other element. Thus, the exemplary terms "beneath" or "lower side" can include both the upper and lower orientations.

[0176] The terms used in the description of the invention herein are for the purpose of describing particular embodiments only and are not intended to limit the invention. As used in the description of the invention and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and / or" used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. It will further be understood that the terms "comprises" and / or "comprising", when used herein, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0177] Embodiments of the invention are described herein with reference to schematic cross - sectional views that are idealized embodiments (and intermediate structures) of the invention. Thus, for example, variations from the shape of the figures as a result of manufacturing techniques and / or tolerances are expected. Accordingly, embodiments of the invention should not be construed as being limited to the particular shapes of regions shown herein and may include, for example, departures in shape resulting from manufacturing. For example, an implanted region shown as rectangular generally has rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change from the implanted region to the non - implanted region. Similarly, an implanted region formed by implantation may, in some implantations, result in a region between the implanted region and the surface through which the implantation occurs. Thus, the regions shown in the figures are essentially schematic and their shapes are not intended to represent the actual shape of regions of the device and are not intended to limit the scope of the invention.

[0178] Unless otherwise defined, all terms used in disclosing embodiments of the invention, including technical and scientific terms, shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs, and shall not necessarily be limited to the specific definitions known at the time of the invention described herein. Accordingly, these terms may include equivalent terms generated after such time. Terms defined as in a commonly used dictionary shall be interpreted as having a meaning consistent with their meaning in the context of the present specification and the relevant art and shall not be interpreted in an idealized or overly formal sense unless explicitly so defined herein. All publications, patent applications, patents, and other references mentioned in this specification are hereby incorporated by reference in their entirety.

[0179] In the drawings and the specification, typical embodiments of the invention are disclosed and specific terms are employed, but these terms are used only in a general and descriptive sense and not for purposes of limitation.

Claims

1. A semiconductor die, comprising: a semiconductor body; and a multilayer environmental barrier on the semiconductor body, the multilayer environmental barrier including first and second sublayers of first and second oxide materials, respectively, the first oxide material having a higher density and a greater thickness than the second oxide material. A semiconductor die comprising the foregoing.

2. The semiconductor die of claim 1, wherein the first and second sublayers include atomic layer deposition (ALD) layers.

3. The semiconductor die of claim 1, wherein at least one of the first or second oxide materials has a higher density than silicon nitride.

4. The semiconductor die of claim 1, wherein at least one of the first or second oxide materials includes an insulating metal oxide.

5. The semiconductor die of claim 4, wherein the first and second sublayers are included in a repeating layer structure, and the first and second oxide materials include the insulating metal oxide and a non-metal oxide, respectively.

6. The semiconductor die of claim 5, wherein the insulating metal oxide includes at least one of aluminum oxide, zirconium oxide, or hafnium oxide.

7. The semiconductor die of claim 5, wherein the insulating metal oxide includes aluminum oxide and the non-metal oxide includes silicon oxide.

8. The semiconductor die of claim 5, wherein a ratio of a thickness of the first sublayer to a thickness of the second sublayer is 2:1 or greater, 5:1 or greater, or 8:1 or greater.

9. The semiconductor die of claim 4, further comprising a passivation layer between the semiconductor body and the multilayer environmental barrier, the passivation layer including silicon nitride.

10. The semiconductor die of claim 9, wherein a surface of the multilayer environmental barrier opposite the passivation layer includes a layer of silicon oxide or silicon nitride.

11. The semiconductor die of claim 1, wherein the first oxide material has a diffusion coefficient with respect to water that is different from that of the second oxide material.

12. a gate, a source contact, and a drain contact on the semiconductor body; and a passivation layer extending over the gate, the source contact, and the drain contact. The semiconductor die further comprises the foregoing. The semiconductor die according to claim 1, wherein the first and second sub-layers conformally extend on the passivation layer along the gate, the source contact, and the drain contact with substantially uniform respective thicknesses.

13. The semiconductor die according to claim 1, wherein the first and second sub-layers are included in a repeating layer structure, and the multi-layer environmental barrier includes at least two of the repeating layer structures, at least ten of the repeating layer structures, or at least twenty of the repeating layer structures.

14. The semiconductor die according to claim 13, wherein a total thickness of the multi-layer environmental barrier is from 500 angstroms to 3000 angstroms.

15. The repeating layer structure is a two-layer structure in which the first and second sub-layers are stacked, a three-layer structure in which the first sub-layer, the second sub-layer, and a third sub-layer are stacked, and / or a four-layer structure in which the first sub-layer, the second sub-layer, the third sub-layer, and a fourth sub-layer are stacked The semiconductor die according to claim 13.

16. A semiconductor die, comprising: a semiconductor body; and a multi-layer environmental barrier on the semiconductor body, the multi-layer environmental barrier including a repeating layer structure including two or more sub-layers of respective insulating materials wherein at least one of the respective insulating materials has a density higher than that of silicon nitride, and the two or more sub-layers include atomic layer deposition (ALD) layers.

17. The semiconductor die according to claim 16, wherein the multi-layer environmental barrier includes at least two of the repeating layer structures, at least ten of the repeating layer structures, or at least twenty of the repeating layer structures.

18. The semiconductor die according to claim 16, wherein the density and thickness of at least one of the respective insulating materials are higher than the density and thickness of at least one other of the respective insulating materials.

19. The semiconductor die according to claim 18, wherein at least one of the respective insulating materials includes a metal oxide, and at least one other of the respective insulating materials includes a non-metal oxide.

20. The semiconductor die according to claim 19, wherein the metal oxide includes aluminum oxide, zirconium oxide, or hafnium oxide.

21. The semiconductor die according to claim 20, wherein the non-metal oxide includes silicon oxide.

22. ​ The semiconductor die according to claim 21, further comprising a passivation layer between the semiconductor body and the multilayer environmental barrier, the passivation layer including silicon nitride.

23. The semiconductor die according to claim 17, wherein a ratio of thicknesses of each of first and second sub-layers among the two or more sub-layers is 2:1 or more, 5:1 or more, or 8:1 or more.

24. A gate, a source contact, and a drain contact on the semiconductor body, and a passivation layer extending over the gate, the source contact, and the drain contact are further provided, the two or more sub-layers conformally extending over the passivation layer with substantially uniform respective thicknesses along the gate, the source contact, and the drain contact, the semiconductor die according to claim 16.

25. The semiconductor die according to claim 16, wherein at least two of the respective insulating materials have different diffusion coefficients with respect to water.

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