Protection Structure for a Semiconductor Device Having Sensor Arrangements

Abstract

A protective structure for a semiconductor device including a sensor arrangement is disclosed. The semiconductor device includes a sensor region 34, e.g., a current sensor region occupying a portion of the total active area of ​​the device. The current sensor region may be configured to provide monitoring of the device load current during operation. A semiconductor device according to the present disclosure includes one or more protective structures configured to enable the semiconductor device to withstand transient voltage events without device failure. The protective structure includes an insulating layer 52 disposed in a transition region 26T between the device region 32 and the sensor region 34 of the semiconductor device. The insulating layer may have a breakdown voltage higher than the breakdown voltage of the gate insulating layer 40.

Description

Technical Field

[0001] This invention was made with government support under Contract No. DE-EE0006521 awarded by the Energy Department. The United States Government has certain rights in this invention.

[0002] This disclosure relates to semiconductor devices, and more particularly to a protection structure for semiconductor devices having sensor arrangements.

Background Art

[0003] Semiconductor devices such as transistors and diodes are ubiquitous in modern electronic devices. Wide-bandgap semiconductor material systems such as gallium nitride (GaN) and silicon carbide (SiC) are increasingly being used in semiconductor devices to push the boundaries of device performance in areas such as switching speed, power handling capability, and thermal conductivity. Examples include individual devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), Schottky barrier diodes, PiN diodes, high electron mobility transistors (HEMTs), and integrated circuits such as monolithic microwave integrated circuits (MMICs) that include one or more individual devices.

[0004] Semiconductor devices for power-switching applications typically include a device region of a semiconductor die that may in some cases be surrounded by an edge termination region. The device region forms the active portion or active region, while the edge termination region forms the non-active portion of the power semiconductor device that can serve to reduce the concentration of the electric field along the device edge for preventing breakdown at low reverse voltages. The active regions of some semiconductor devices can include a number of unit cells that are electrically coupled in parallel to each other between one or more electrodes to provide the device with selective current conduction and voltage blocking capabilities.

[0005] Current sensing in semiconductor devices for power - switching applications is a method for monitoring the operating load current in order to detect and mitigate potential failure mechanisms such as over - current or short - circuit events. In the case of MOSFETs or metal - insulator - semiconductor field - effect transistors (MISFETs), current sensing may be achieved by providing an additional source contact for a small number of active region unit cells. The additional source contact is arranged to form an additional path for a proportionally small amount of the total device load current. The amount of load current along the additional path is measured and may be used to calculate the total load current along the rest of the device. While current sensing arrangements within semiconductor devices have been proposed, conventional structures may not be suitable for withstanding various adverse operating conditions that may be experienced.

[0006] The technology continues to seek improved semiconductor devices having current sensing that can overcome the problems associated with conventional semiconductor devices.

Summary of the Invention

Means for Solving the Problems

[0007] The present disclosure relates to semiconductor devices, and more particularly to a protection structure for semiconductor devices including a sensor arrangement. The semiconductor device can include a sensor region, for example, a current sensor region that occupies a portion of the device's all - active area. The current sensor region may be configured to provide monitoring of the device load current during operation. The semiconductor device according to the present disclosure includes one or more protection structures configured to enable the semiconductor device to withstand transient voltage events without device failure. The protection structure can include an insulating layer provided in a transition region between the device region and the sensor region of the semiconductor device. In the case of an insulated - gate semiconductor device, the insulating layer of the protection structure can include a material having a breakdown voltage higher than the breakdown voltage of the gate insulating layer.

[0008] In one aspect, a semiconductor device includes: a drift region; a device region including a first portion of the drift region; a sensor region including a second portion of the drift region; and a transition region disposed between the device region and the sensor region, the transition region including: a gate contact; a gate insulating layer disposed between the gate contact and the drift region; and an insulating layer disposed between the gate contact and the drift region and having a breakdown voltage higher than that of the gate insulating layer. The sensor region can form a current sensor. In an embodiment, the first portion of the drift region is electrically connected between a first contact and a second contact, and the second portion of the drift region is electrically connected between the first contact and a sensor contact. In an embodiment, the semiconductor device includes a metal-oxide-semiconductor field-effect transistor (MOSFET), the first contact is a drift contact, and the second contact is a source contact. In an embodiment, there is no insulating layer on the upper surface of the drift region within the transition region. The breakdown voltage of the insulating layer may be at least 1.5 times higher than that of the gate insulating layer, or within the range of 1.5 times to 200 times higher than that of the gate insulating layer, or within the range of 1.5 times to 200 times higher than that of the gate insulating layer. In an embodiment, the thickness of the insulating layer is at least 1.5 times thicker than that of the gate insulating layer, or within the range of 1.5 times to 100 times thicker than that of the gate insulating layer. In an embodiment, the thickness of the insulating layer is at least 2 times thicker than that of the gate insulating layer, or within the range of 2 times to 100 times thicker than that of the gate insulating layer. In an embodiment, the insulating layer forms a ring around the lateral edge of the sensor region. In an embodiment, a portion of the insulating layer has a thickness thicker than that of another portion of the insulating layer. In an embodiment, the drift region includes a doped region aligned with the transition region, the doped region having a doping type opposite to that of the drift region. In an embodiment, the insulating layer is on the doped region and the width of the insulating layer is smaller than the width of the doped region. In an embodiment, the insulating layer is on the doped region and the width of the insulating layer is the same as the width of the doped region.

[0009] In another aspect, a silicon carbide (SiC) MOSFET device includes a device region and a current sensor region, and the SiC MOSFET device is configured to withstand a voltage change rate (dV / dt) over time of at least 10 kilovolts per microsecond (kV / μs). In one embodiment, the dV / dt is at least 30 kV / μs, or at least 50 kV / μs, or at least 100 kV / μs, or in the range from 10 kV / μs to 100 kV / μs, or in the range from 10 kV / μs to 200 kV / μs. In one embodiment, the SiC MOSFET device is configured to withstand a dV / dt in the range from 1 cycle to 1000 cycles. In one embodiment, the MOSFET device further includes: a drift region forming a part of the current sensor region and the device region, wherein the current sensor region is laterally spaced from the device region by a transition region; a gate contact and a gate insulating layer, wherein the gate insulating layer is between the gate contact and the drift region; and an insulating layer in the transition region, wherein the insulating layer is disposed between the gate contact and the drift region and has a breakdown voltage higher than the voltage of the gate insulating layer. In one embodiment, the thickness of the insulating layer is in the range from 1.5 times to 50 times the thickness of the gate insulating layer.

[0010] In another aspect, a semiconductor device comprises: a drift region; a device region including a first portion of the drift region; a sensor region including a second portion of the drift region; and a transition region disposed between the device region and the sensor region, the transition region comprising: a gate contact; a gate insulating layer disposed between the gate contact and the drift region; and an insulating layer disposed between the gate contact and the drift region and having a thickness greater than the thickness of the gate insulating layer. In one embodiment, the thickness of the insulating layer is at least 1.5 times greater than the thickness of the gate insulating layer, or within a range from 1.5 times to 100 times greater than the thickness of the gate insulating layer. In one embodiment, the thickness of the insulating layer is at least 2 times greater than the thickness of the gate insulating layer, or within a range from 2 times to 100 times greater than the thickness of the gate insulating layer. In one embodiment, the sensor region forms a current sensor. In one embodiment, the first portion of the drift region is electrically connected between a first contact and a second contact, and the second portion of the drift region is electrically connected between the first contact and a sensor contact. In one embodiment, the semiconductor device comprises a MOSFET, the first contact is a drift contact, and the second contact is a source contact.

[0011] In another aspect, any of the foregoing aspects, individually or in combination, and / or various separate aspects and features as described herein may be combined for additional advantages. Any of the various features and elements as disclosed herein may be combined with one or more other disclosed features and elements, unless otherwise indicated herein to the contrary.

[0012] Those skilled in the art will recognize the scope of the present disclosure and will understand further aspects of the present disclosure after reading the following detailed description of the preferred embodiments in relation to the accompanying drawings.

[0013] The accompanying drawings, which are incorporated herein and form a part hereof, illustrate some aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

Brief Description of the Drawings

[0014]

Figure 1

Figure 2A

Figure 2B

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Embodiments for Carrying Out the Invention

[0015] The embodiments described below represent the information necessary for one of ordinary skill in the art to carry out the embodiments and illustrate the best mode of carrying out the embodiments. Reading the following description in consideration of the accompanying drawing figures, one of ordinary skill in the art will understand the disclosed concepts and recognize the application of these concepts that are not specifically addressed herein. It should be understood that these concepts and applications are within the scope of the present disclosure and the appended claims.

[0016] Although the terms first, second, etc. may be used herein to describe various elements, it should be understood that these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present disclosure, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0017] When an element such as a layer, region, or substrate is said to be "on" or to "extend onto" another element, it should be understood that it may be directly on or extend directly into the other element, or intervening elements may also be present. In contrast, when an element is said to be "directly on" or to "extend directly onto" another element, there are no intervening elements. Similarly, when an element such as a layer, region, or substrate is said to be "over" or to "extend over" another element, it should be understood that it may be directly over or extend directly over the other element, or intervening elements may also be present. In contrast, when an element is said to be "directly over" or to "extend directly over" another element, there are no intervening elements. When an element is said to be "connected" or "coupled" to another element, it should also be understood that it may be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is said to be "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0018] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as illustrated in the figures. It should be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0019] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" include plural referents as well, unless the context clearly dictates otherwise. It is further to be understood that when the terms "comprises", "comprising", "includes" and / or "including" are used in this specification, they specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0020] Unless defined otherwise, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It is further understood that terms used herein are to be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and that they are not to be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0021] The embodiments are described herein with reference to schematic illustrations of embodiments of the disclosure. As such, the actual dimensions of layers and elements may differ, and for example, variations from the shapes of the illustrations are expected as a result of manufacturing techniques and / or tolerances. For example, regions illustrated or described as square or rectangular may have rounded or curved outlines, and regions shown as straight may have some irregularity. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the exact shape of the regions of the device nor to limit the scope of the disclosure. Additionally, the size of a structure or region may be exaggerated relative to other structures or regions for illustrative purposes and thus may be provided to illustrate the general structure of the subject matter and may or may not be drawn to scale. Common elements between multiple figures may be shown herein using common element numbers and may not be described again later.

[0022] The present disclosure relates to a semiconductor device and, more particularly, to a protection structure for a semiconductor device including a sensor arrangement. The semiconductor device can include a sensor region, for example, a current sensor region that occupies a portion of the device's all-active area. The current sensor region may be configured to provide monitoring of the device load current during operation. The semiconductor device according to the present disclosure includes one or more protection structures configured to enable the semiconductor device to withstand transient voltage events without device failure. The protection structure can include an insulating layer provided in a transition region between the device region and the sensor region of the semiconductor device. In an example of an insulated-gate semiconductor device, the insulating layer of the protection structure can include a material having a breakdown voltage higher than the breakdown voltage of the gate insulating layer.

[0023] FIG. 1 is an explanatory top view layout diagram of an exemplary semiconductor device 10 according to an embodiment of the present disclosure. For illustration purposes, semiconductor device 10 is a vertical metal-oxide-semiconductor field-effect transistor (MOSFET) device including a passivation structure 12 having openings for gate contact 14 and several source contacts 16. Gate contact 14 and source contact 16 may also be referred to as gate contact pads and source contact pads, respectively. Although a MOSFET is illustrated, the principles of the present disclosure are applicable to other semiconductor devices, such as, among others, other MOSFETs, metal-insulator field-effect transistors (MISFETs), diodes, Schottky diodes, junction barrier Schottky (JBS) diodes, PiN diodes, and insulated gate bipolar transistors (IGBTs). Semiconductor device 10 may include wide bandgap semiconductor devices, such as silicon carbide (SiC)-based devices, and even further 4H-SiC-based devices. Semiconductor device 10 is a vertical power device with a drain contact pad (not shown) located on the back side of device 10. Gate contact 14 and source contact 16 may be provided as surfaces for coupling semiconductor device 10 to an external circuit. An edge termination region 18 may be disposed along the outer periphery of device 10. Edge termination region 18 may be disposed to reduce the concentration of the electric field at the edge of semiconductor device 10 to improve the performance of semiconductor device 10. For example, edge termination region 18 can increase the breakdown voltage of semiconductor device 10 and / or reduce the leakage current of semiconductor device 10 over time. As an example, edge termination region 18 can include one or more guard rings, junction termination extensions (JTEs), and combinations thereof.

[0024] The semiconductor device 10 can further include a sensor contact 20, or a sensor contact pad. The sensor contact 20 can provide a contact for any type of sensor that is at least partially incorporated within the semiconductor device 10, such as a temperature sensor, a strain sensor, or a current sensor. In the case of a current sensor, the current sensor region corresponding to the sensor contact 20 can occupy an area of the semiconductor device 10 that would otherwise form part of the active region 10' for the semiconductor device 10. In the example of FIG. 1, the edge termination region 18 can serve to demarcate the active region 10' of the semiconductor device 10 from the non-active region 10" of the semiconductor device 10, and the sensor contact 20 can define a current sensor region that would otherwise form part of the active region 10'. In this regard, the sensor contact 20 can generally have a size that is smaller than the size of the remaining active region of the semiconductor device 10. The sensor contact 20 provides a contact pad that can be electrically connected, for example, by wire bonding or other electrical connections, to one or more external circuit elements for sensor monitoring. In the case of a current sensor, the sensor contact 20 can be electrically connected to one or more external circuit elements for monitoring a portion of the load current flowing through the sensor region of the semiconductor device 10 that is electrically coupled to the sensor contact 20.

[0025] FIGS. 2A and 2B depict equivalent circuits related to an implementation of a current sensor for a MOSFET or MISFET arrangement according to the principles of the present disclosure. FIG. 2A illustrates an equivalent circuit 22 in which the source contact 20 of FIG. 1 is electrically coupled to a sense resistor (R sense ). The dashed rectangle in FIG. 2A represents the semiconductor device 10 of FIG. 1, with the remainder of the equivalent circuit 22 being external to the semiconductor device 10. By forming a sensor contact (20 in FIG. 1) as an alternative source contact, the semiconductor device 10 thereby includes a device MOSFET (M D ) and a sensing MOSFET (M sense ) that are connected to a common drain and a common gate. The MOSFET (MD and M S ) For each of the source connection parts, the current flow (I D ) from the drain is such that the current flow through the MOSFET (M D and M sense ) may be divided across the whole and are connected in parallel. The ratio of the current flow from the source of the sensing MOSFET to the current flow from the source of the device MOSFET corresponds to the ratio of the area of the semiconductor device 10 occupied by the sensor region to the area of the semiconductor device 10 occupied by the active region. As an example, FIG. 2A illustrates an embodiment in which the ratio of the current flow is set at 1:250 based on the relative areas of the active region and the sensor region. In this way, when a current of 1 ampere (A) flows through the semiconductor device 10, a current of 4 milliamperes (mA) will flow from the source path of the sensing MOSFET (M sense ). By placing a sense resistor (R sense ) along the source path from the sensing MOSFET (M sense ), a corresponding sense voltage (V sense ) is measured and may be correlated to the load current of the device MOSFET (M D ) according to the ratio explained above. Other current sensing configurations are possible using the layout of the semiconductor device 10. For example, FIG. 2B illustrates an equivalent circuit 24 for a virtual ground configuration with respect to a portion outside the semiconductor device 10. Virtual ground sensing may be used in applications where a higher value sense voltage (V sense ) is required. In this configuration, an operational amplifier (OA) and a feedback resistor (Rf) are coupled to the source path from the sensing MOSFET (M sense ). In this way, the sense voltage (V sense ) may be calculated based on the output of the feedback resistor (Rf) and the operational amplifier (OA).

[0026] FIG. 3 illustrates a cross-sectional view of a portion of a semiconductor device 26 including the sensor contact 20 of FIG. 1. As an example, the semiconductor device 26 is arranged as a planar MOSFET, but the principles of the present disclosure are applicable to other semiconductor devices including, among others, trench MOSFETs, MISFETs, diodes, Schottky diodes, JBS diodes, PiN diodes, and IGBTs. The semiconductor device 26 includes a substrate 28 and a drift region 30 on the substrate 28. The drift region 30 can include one or more drift layers of a wide bandgap semiconductor material, such as SiC. The substrate 28 may have a doping concentration between 1×10 17 cm -3 and 1×10 20 cm -3 . In various embodiments, the doping concentration of the substrate 28 may be provided in any small range between 1×10 17 cm -3 and 1×10 20 cm -3 . For example, the doping concentration of the substrate 28 may be between 1×10 18 -3 cmand 1×10 20 -3 cm, between 1×10 19 -3 cmand 1×10 20 -3 cm, between 1×10 17 -3 cmand 1×10 19 -3 cm, between 1×10 17 -3 cmand 1×10 18 -3 cm, between 1×10 18 -3 cmand 1×10 19 -3 cm , and between 1×10 14

[0027] . The drift region 30 may have a doping concentration between 1×10 14 cm -3 and 1×10 18 cm -3may have a doping concentration therebetween. In various embodiments, the doping concentration of the drift region 30 is 1×10 14 cm -3 and 1×10 18 cm -3 and may be provided in any small range therebetween. For example, the doping concentration of the drift region 30 is 1×10 15 cm -3 and 1×10 18 cm -3 between, 1×10 16 cm -3 and 1×10 18 cm -3 between, 1×10 17 cm -3 and 1×10 18 cm -3 between, 1×10 14 cm -3 and 1×10 17 cm -3 between, 1×10 14 cm -3 and 1×10 16 cm -3 between, 1×10 14 cm -3 and 1×10 15 cm -3 between, 1×10 15 cm -3 and 1×10 17 cm -3 between, 1×10 15 cm -3 and 1×10 16 cm -3 between, and 1×10 16 cm -3 and 1×10 17 cm -3 between may be.

[0028] The vertical dashed line is provided to indicate one or more transition regions 26 of the semiconductor device 26 that demarcate the device region 32 from the sensor region 34 T For an embodiment having a single integrated sensor - contact 20 as shown in the top - view of FIG. 1, in FIG. 3 the transition region 26 indicated by the dashed line Tmay be a continuous transition region 26 surrounding the sensor contact 20. T The semiconductor device 26 can include a number of unit cells in both a device region 32 and a sensor region 34 that are electrically coupled in parallel with each other as illustrated by the equivalent circuits of FIGS. 2A and 2B. In FIG. 3, each MOSFET cell includes a pair of junction implantation portions 36 provided on the upper surface 30A of the drift region 30, specifically, the drift region 30 opposite to the substrate 28. The junction implantation portion 36 includes a first well region 36A having a doping type opposite to the doping type of the drift region 30 and a second well region 36B having the same doping type as the doping type of the drift region 30. The junction implantation portions 36 may be separated from each other by a junction field effect transistor (JFET) region 38. The JFET region 38 has the same doping type as the doping type of the drift region 30 and, in some embodiments, has a higher doping concentration than the doping type of the drift region 30. A number of source contacts 16 are provided over the entire junction implantation portion 36 on the upper surface 30A of the drift region 30 within the device region 32 such that each source contact 16 contacts a portion of the first well region 36A and the second well region 36B. In a similar manner, sensor contacts 20 are provided over the entire junction implantation portion 36 on the upper surface 30A of the drift region 30 of the sensor region 34 such that each sensor contact 20 contacts a portion of the corresponding first well region 36A and the second well region 36B. In this regard, the sensor contact 20 can form another source contact for the sensor region 34. In one embodiment, the drift region 30 and the second well region 36B can include n-type doping while the first well region 36A includes p-type doping, although the opposite polarity configuration is also applicable to the present disclosure.

[0029] The gate insulating layer 40, or the gate oxide layer depending on the device type, is provided on the upper surface 30A of the drift region 30 opposite the substrate 28 over the entire JFET region 38 and a part of each one of the junction implantation portions 36, so that the gate insulating layer 40 partially overlaps with each one of the second well regions 36B. The gate insulating layer 40 can include a thin layer of silicon dioxide in some embodiments, for example, in a MOSFET configuration where the gate insulating layer 40 may be referred to as a gate oxide layer. In other embodiments, the gate insulating layer 40 can include any insulating material, including non-oxide insulating materials and other oxide materials beyond silicon dioxide. The gate contact 42 is provided on the gate insulating layer 40. As shown, the gate contact 42 and the gate oxide may be provided across the transition region 26 T for both MOSFET cells in the device region 32 and the sensor region 34. The gate contact 42 for each of the MOSFET cells in both the device region 32 and the sensor region 34 may be coupled to the same gate contact pad 14 in FIG. 1. In an alternative configuration, the semiconductor device 26 can embody a trench MOSFET where the portions of the gate contact 42 and the gate insulating layer 40 can be present in the trench of the drift region 30 without departing from the principles of the present disclosure. The passivation layer 44 is provided above the gate contact 42 to provide electrical insulation from the source contact 16 and the sensor contact 20. In some embodiments, the passivation layer 44 can include one or more dielectric layers referred to as an intermetallic dielectric. The MOSFET cells may be arranged throughout the device region 32 and the sensor region 34, or may be arranged in a desired pattern with one or more other semiconductor devices (e.g., diodes) to provide a desired function.

[0030] The drain contact 46 is provided on the surface of the substrate 28 opposite to the drift region 30. Accordingly, the portion of the drift region 30 and the corresponding MOSFET cell disposed in the device region 32 are electrically connected between the drain contact 46 and the source contact 16. In a similar manner, the portion of the drift region 30 and the corresponding MOSFET cell disposed in the sensor region 34 are electrically connected between the drain contact 46 and the sensor contact 20. Although only a few MOSFET cells are illustrated, the ratio of the number of MOSFET cells in the sensor region 34 to the number of MOSFET cells in the device region 32 may be on the order of 1:1, or 1:100, or 1:250, or 1:1,000,000 depending on the desired current ratio for the sensor region 34. In one embodiment, the sensor region 34 may be arranged to occupy at most 20%, or at most 10%, or at most 5% of the available active area of the semiconductor device 26 within the edge termination region. For current sensing applications, the sensor region 34 may be referred to as a current sensor region. Transition region 26 T A doped region 48 of the drift region 30 aligned with T may be provided. The doped region 48 may have a doping type that is the same as the doping type of the first well region 36A and opposite to the doping type of the drift region 30. In this regard, the doped region 48 extends across the transition region 26 T and may be configured to shield a portion of the gate contact 42. However, in this layout, the semiconductor device 26 may be vulnerable to transient voltage events that may occur during operation and / or device testing. In particular, a large voltage change rate over time (dV / dt) may be induced during a switching event. A large dV / dt may cause breakdown or other defects and damage to the gate insulating layer 40 within the transition region 26 T .

[0031] FIG. 4 is similar to the semiconductor device 26 of FIG. 3 and shows the transition region 26 to shield the gate insulating layer 40 from transient voltage events, defects, and other related damage TA cross-sectional view of a portion of a semiconductor device 50 further including a protection structure disposed therein is illustrated. An insulating layer 52 is provided on the upper surface 30A of the drift region 30 to provide protection for the gate insulating layer 40. The insulating layer 52 may be further provided on the upper surface 30A of the drift region 30 within an area where the upper surface 30A includes the doped region 48. In one embodiment, the insulating layer 52 may be formed on the drift region 30 before the gate insulating layer 40 and the gate contact 42 are formed, thereby disposing the insulating layer 52 between the gate contact 42 and the drift region 30 within the transition region 26 T In this regard, the insulating layer 52 prevents the thin gate insulating layer 40 from completely covering the upper surface 30A of the drift region 30 within the transition region 26 T As a result, there is no gate insulating layer 40 on at least a portion of the upper surface 30A within the transition region 26 T In addition, the gate insulating layer 40 may not be provided between the insulating layer 52 and the gate contact 42 within the transition region 26 T thereby reducing the overall presence of the gate insulating layer 40. In any of the arrangements described above, the insulating layer 52 provides a shield or barrier that reduces the impact of transient voltage events along the transition region 26 T In particular, weak spots formed by the interface between the gate insulating layer 40 and the upper surface 30A of the drift region 30 along the transition region 26 T are reduced.

[0032] In one embodiment, the insulating layer 52 includes a structure having a breakdown voltage higher than the breakdown voltage of the gate insulating layer 40. For example, the breakdown voltage of the insulating layer 52 is at least 1.5 times higher, or at least 2 times higher, or at least 3 times higher, or at least 5 times higher, or at least 10 times higher, or at least 50 times higher, or at least 100 times higher, or at least 200 times higher than the breakdown voltage of the gate insulating layer 40, or may be any range having an end point defined by any of the previous values. For example, the breakdown voltage of the insulating layer 52 may be in the range from 1.5 times higher to 200 times higher than the breakdown voltage of the gate insulating layer 40, or in the range from 1.5 times higher to 100 times higher, or in the range from 5 times higher to 100 times, or in the range from 5 times higher to 200 times higher than the breakdown voltage of the gate insulating layer 40. In a specific example, the insulating layer 52 has a breakdown voltage in the range from 650 volts (V) to 750 V, while the gate insulating layer 40 has a breakdown voltage in the range from 40 V to 60 V. In one embodiment, the insulating layer 52 can include another material having a breakdown voltage higher than the material of the gate insulating layer 40. In such an embodiment, the thicknesses of the insulating layer 52 and the gate insulating layer 40 may be the same or different as long as the insulating layer 52 has a higher breakdown voltage. In other embodiments, the insulating layer 52 and the gate insulating layer 40 can include the same material, and a higher breakdown voltage is achieved by providing an insulating layer 52 having a thickness or height from the drift region 30 that is thicker than the corresponding thickness or height of the gate insulating layer 40. For example, the thickness of the insulating layer 52 is at least 1.5 times, or at least 2 times, or at least 3 times, or at least 100 times the thickness of the gate insulating layer 40, or in the range from 1.5 times to 50 times the thickness of the gate insulating layer 40, or in the range from 1.5 times to 100 times, or in the range from 2 times to 50 times, or in the range from 2 times to 100 times the thickness of the gate insulating layer 40. In a specific example, the insulating layer 52 has a thickness in the range from 550 nanometers (nm) to 650 nm, and the gate insulating layer 40 has a thickness in the range from 30 nm to 50 nm.Regarding MOSFET applications, the gate insulating layer 40 can include a gate oxide, and the insulating layer 52 can include a thicker field oxide layer as described above. In such embodiments, both the gate insulating layer 40 and the insulating layer 52 can include silicon dioxide among other gate oxides used in MOSFET applications.

[0033] By having the protection structure provided by the insulating layer 52, the overall structure of the semiconductor device 50 is more robust against handling transient voltage events, including one or more dV / dt events that may be caused during high-speed switching. For example, a SiC MOSFET device having the insulating layer 52 of the present disclosure can be configured to withstand or be rated for a dV / dt of at least 10 kilovolts per microsecond (kV / μs) without device failure. In further embodiments thereof, the SiC MOSFET device can withstand at least 30 kV / μs, or at least 50 kV / μs, or at least 100 kV / μs, or in the range from 10 kV / μs to 100 kV / μs, or in the range from 10 kV / μs to 200 kV / μs, or in the range from 50 kV / μs to 150 kV / μs, or in the range from 100 kV / μs to 200 kV / μs, or in any range having an endpoint determined by any of the previous values without device failure. In still further embodiments thereof, the SiC MOSFET device can withstand any of the dV / dt values over at least 1000 switching cycles up to a single switching cycle. In any of the embodiments described above, an exemplary SiC MOSFET can include a 4H-SiC MOSFET device.

[0034] FIG. 5 is a top view layout explanatory diagram of a semiconductor device 54 illustrating a protective structure arrangement of an insulating layer 52 with respect to a sensor contact 20 according to an embodiment of the present disclosure. A portion of the semiconductor device 54 is given in an exploded view to the left of the explanatory diagram. For explanatory purposes, the overlying sensor contact 20, source contact 16, and passivation structure 12 are omitted in the image portion of the exploded view. Instead, a portion 20' of the sensor contact 20, or an extension thereof, that forms an ohmic contact to the drift region 30, is illustrated as an array that forms parts of unit cells of the sensor region 34 as previously described. In a similar manner, a portion 16' of the source contact 16, or an extension thereof, that forms an ohmic contact to the drift region 30, is illustrated as an array that forms parts of unit cells of the device region 32. The portion 16' can also be patterned under the passivation structure 12 and represent the contact metal outside the source contact 16. As illustrated, the insulating layer 52 can form one or more continuous rings around the lateral edges of the sensor contact 20 and the sensor region 34 to provide a demarcation between the sensor region 34 and the device region 32.

[0035] FIG. 6 illustrates a cross-sectional view of a portion of a semiconductor device 56 similar to the semiconductor device 50 of FIG. 4 with respect to an embodiment where the insulating layer 52 forms a non-flat shape. In FIG. 6, a thicker portion 52' of the insulating layer 52 is formed along the center of the insulating layer 52 to form one or more non-flat surfaces of the insulating layer 52 that are opposite the drift region 30. In this way, the increased amount of the protective structure provided by the insulating layer 52 does not increase the lateral footprint of the insulating layer 52 with respect to the drift region 30 and the transition region 26 T6, the thickened portion 52' forms a stepped profile for the insulating layer 52. In other embodiments, the thickened portion 52' may form a peak that is graded in one or more of a linear and / or curved manner toward a lateral edge of the insulating layer 52. Although the thickened portion 52' is illustrated in the center of the insulating layer 52, the thickened portion 52' may be located near either the sensor region 34 or the device region 32, depending on the embodiment. In further embodiments, the insulating layer 52 may be formed with multiple thickened portions 52'. In FIG. 6, the thickened portion 52' forms a stepped profile for the insulating layer 52. In other embodiments, the thickened portion 52' may form a peak that is graded in one or more of a linear and / or curved manner toward a lateral edge of the insulating layer 52.

[0036] 7 illustrates a cross-sectional view of a portion of a semiconductor device 58 similar to the semiconductor device 50 of FIG. 4 for an embodiment in which the insulating layer 52 is formed to cover a greater portion of the top surface 30A of the drift region 30. As shown, the insulating layer 52 may be formed with a lateral width that is close to or the same as the lateral width of the doped region 48 of the drift region 30. In this manner, the amount of material for the gate insulating layer 40 is reduced relative to the lateral width of the transition region 26. T For embodiments in which the gate insulating layer 40 does not form over the insulating layer 52, the gate insulating layer 40 may therefore be disposed over the transition region 26 to further reduce the effect from transient voltage events. T 7 with a lateral width the same as the lateral width of doped region 48, insulating layer 52 may be formed with an increased width that is narrower than the width of doped region 48. For example, insulating layer 52 may be formed with a width that is at least 50%, or at least 75%, or at least 90%, or within a range of 50% to 100% of the width of doped region 48 in various embodiments.

[0037] While the present disclosure provides exemplary embodiments that include MOSFETs, the principles of the present disclosure are also applicable to other semiconductor devices, such as, among others, MOSFETs, diodes, Schottky diodes, JBS diodes, PiN diodes, and IGBTs. The semiconductor devices of the present disclosure can embody wide bandgap semiconductor devices, such as SiC-based devices.

[0038] It is contemplated that any of the foregoing aspects, and / or various separate aspects and features as described herein, may be combined for additional advantages. Any of the various embodiments as disclosed herein may be combined with one or more other disclosed embodiments as long as not otherwise indicated herein to the contrary.

[0039] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the scope of the appended claims.

Claims

1. A drift region, A device region including a first portion of the drift region, A sensor region including a second portion of the drift region, A transition region disposed between the device region and the sensor region, A semiconductor device comprising: wherein the transition region comprises: A gate contact, A gate insulating layer disposed between the gate contact and the drift region, An insulating layer disposed between the gate contact and the drift region, the insulating layer having a breakdown voltage higher than the breakdown voltage of the gate insulating layer, Comprising, The semiconductor device, wherein the insulating layer includes a stepped profile in cross-section between the gate contact and the drift region in the transition region.

2. The semiconductor device according to claim 1, wherein the sensor region forms a current sensor.

3. The semiconductor device according to claim 1, wherein the first portion of the drift region is electrically connected between a first contact and a second contact, and the second portion of the drift region is electrically connected between the first contact and a sensor contact.

4. The semiconductor device according to claim 3, comprising a metal-oxide-semiconductor field effect transistor (MOSFET), wherein the first contact is a drift contact and the second contact is a source contact.

5. The semiconductor device according to claim 1, wherein the breakdown voltage of the insulating layer is at least 1.5 times higher than the breakdown voltage of the gate insulating layer, and the breakdown voltage of the insulating layer is in the range of 650 volts to 750 volts.

6. The semiconductor device according to claim 1, wherein the thickness of the insulating layer is at least 1.5 times thicker than the thickness of the gate insulating layer, and the thickness of the insulating layer is in the range of 550 nanometers to 650 nanometers.

7. The semiconductor device according to claim 1, wherein the insulating layer forms a ring around a lateral edge of the sensor region.

8. A drift region, A device region including a first portion of the drift region, A sensor region including a second portion of the drift region, A transition region disposed between the device region and the sensor region, A semiconductor device comprising: wherein the transition region comprises: A gate contact, A gate insulating layer disposed between the gate contact and the drift region, An insulating layer disposed between the gate contact and the drift region, the insulating layer having a breakdown voltage higher than the breakdown voltage of the gate insulating layer, Comprising The insulating layer includes a material different from that of the gate insulating layer, a semiconductor device.

9. The semiconductor device according to claim 1, wherein the drift region includes a doped region aligned with the transition region, and the doped region has a doping type opposite to the doping type of the drift region.

10. A drift region, A device region including a first portion of the drift region, A sensor region including a second portion of the drift region, And a transition region disposed between the device region and the sensor region A semiconductor device comprising: wherein the transition region A gate contact, A gate insulating layer disposed between the gate contact and the drift region, An insulating layer disposed between the gate contact and the drift region, the insulating layer having a breakdown voltage higher than the breakdown voltage of the gate insulating layer, Comprising The drift region includes a doped region aligned with the transition region, the doped region having a doping type opposite to the doping type of the drift region, The insulating layer is on the doped region, and the width of the insulating layer is the same as the width of the doped region, a semiconductor device.

11. The semiconductor device is a silicon carbide (SiC) metal-oxide-semiconductor field effect transistor (MOSFET) device including the device region and the sensor region, and the SiC MOSFET device is configured to withstand a voltage change rate (dV / dt) over time of at least 30 kilovolts per microsecond (kV / μs). The semiconductor device according to claim 1.

12. The semiconductor device according to claim 1, wherein the insulating layer includes a lower portion having opposing lower side surfaces and an upper portion having opposing upper side surfaces.

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