Semiconductor module

Abstract

To provide a semiconductor module in which the insulation property of a terminal to receive power supply can be enhanced.SOLUTION: A semiconductor module 1 includes a negative electrode terminal 31u that is connected to the negative polarity side of DC power, a positive electrode terminal 21u that is disposed above the negative electrode terminal 31u while an exposed portion 314 including one end 311 of the negative electrode terminal 31u is in an exposed state and that is connected to the positive polarity side of DC power, an insulation sheet 61u that is disposed between the negative electrode terminal 31u and the positive electrode terminal 21u with an exposed portion 612 exposed between the one end 311 of the negative electrode terminal 31u and one end 211 of the positive electrode terminal 21u and that insulates the negative electrode terminal 31u from the positive electrode terminal 21u, and a first dielectric portion 71u that is formed so as to cover at least a corner 212 of the one end 211 of the positive electrode terminal 21u in contact with the insulation sheet 61u.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention relates to a semiconductor module applied to a power conversion device or the like.

Background Art

[0002] In recent years, due to the promotion of energy conservation and the strengthening of carbon dioxide (CO2) emission regulations, the development and popularization of hybrid vehicles and electric vehicles powered by electricity in the automotive industry have been accelerating. The inverters used for power control of hybrid vehicles and electric vehicles are installed in a limited space, and weight reduction and efficiency improvement while being conscious of low fuel consumption are required. In addition, a power semiconductor module adapted to the output of a battery or a motor is demanded.

[0003] The power semiconductor module has a structure in which laminated wiring is provided from the inside to the outside, and has a positive terminal and a negative terminal (PN terminals) for external input, and insulating paper sandwiched between the PN terminals. Further, the power semiconductor module has a shape in which the PN terminals having such a structure are insert-molded with polyphenylene sulfide resin (PPS).

[0004] Patent Document 1 discloses a semiconductor device including a front conductive plate selectively disposed on an insulating substrate, a semiconductor chip disposed on the front conductive plate, a solid insulator disposed on the semiconductor chip, a case provided so as to surround the insulating substrate, and a flexible insulator filled in the case. In the semiconductor device disclosed in Patent Document 1, the solid insulator has a coefficient of thermal expansion intermediate between the coefficient of thermal expansion of the front conductive plate and the coefficient of thermal expansion of the insulating substrate.

[0005] Patent Document 2 discloses that a conductor layer provided on the surface of the insulating sheet on the side where the second metal member is provided has at least a portion extending in the direction of the outer peripheral edge of the insulating sheet from the point where a line extending the outer peripheral edge of the second metal member in the lamination direction intersects the surface of the insulating sheet, and by having an outer peripheral edge inside the outer peripheral edge of the insulating sheet, the potential difference between the second metal member and the insulating sheet is reduced, and the electric field strength in the region where the insulating sheet, the second metal member, and the sealing resin are in contact is kept low.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0007] In the technical field of semiconductor modules, generally, in order to ensure insulation performance, an insulation distance is set according to the standards of the International Electrotechnical Commission (IEC). However, depending on the shape of the PN terminals provided in the semiconductor module, when unnecessary edges are generated on the PN terminals during the manufacturing process, there is a problem that the insulation reliability of the PN terminals decreases.

[0008] An object of the present invention is to provide a semiconductor module capable of improving the insulation of terminals to which power is supplied.

Means for Solving the Problems

[0009] To achieve the above object, a semiconductor module according to one aspect of the present invention includes a first power supply terminal connected to a first polarity side of DC power, a second power supply terminal disposed above the first power supply terminal with a part including one end of the first power supply terminal exposed and connected to a second polarity side of the DC power, an insulating sheet disposed between the first power supply terminal and the second power supply terminal with a part exposed between one end of the first power supply terminal and one end of the second power supply terminal to insulate the first power supply terminal and the second power supply terminal, and a first dielectric portion formed to cover at least a corner portion of the one end of the second power supply terminal in contact with the insulating sheet. , the second dielectric part and comprises , the second power supply terminal has a through hole formed by penetrating a part so that the insulating sheet is exposed, and the second dielectric part is formed by covering at least an end portion on the insulating sheet side of the inner wall surface forming the through hole .

Advantages of the Invention

[0010] According to one aspect of the present invention, it is possible to improve the insulation of the terminal to which power is supplied.

Brief Description of the Drawings

[0011]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

DETAILED DESCRIPTION OF THE INVENTION

[0012] Each embodiment of the present invention illustrates an apparatus and method for embodying the technical idea of the present invention. The technical idea of the present invention does not specify the material, shape, structure, arrangement, etc. of the components as the following. The technical idea of the present invention can be variously modified within the technical scope defined by the claims described in the claims.

[0013] 〔First Embodiment〕 The semiconductor module according to the first embodiment of the present invention will be described with reference to FIGS. 1 to 5. First, the schematic configuration of the semiconductor module according to the present embodiment will be described with reference to FIGS. 1 to 5. In the present embodiment, a power conversion module capable of DC-AC conversion will be described as an example of the semiconductor module. In FIG. 1, for ease of understanding, illustrations of an inverter circuit, wiring patterns, etc. mounted on a laminated substrate provided in the semiconductor module according to the present embodiment are omitted.

[0014] As shown in Fig. 1, the semiconductor module 1 according to this embodiment includes a case 10 having a rectangular shape in plan view. The case 10 has a storage portion 11 for storing the inverter portion for the U phase, a storage portion 12 for storing the inverter portion for the V phase, and a storage portion 13 for storing the inverter portion for the W phase. The semiconductor module 1 has a laminated substrate 111 for the U phase stored in the storage portion 11 and an inverter circuit for the U phase (not shown in Fig. 1, see Fig. 2) mounted on the laminated substrate 111. The semiconductor module 1 has a laminated substrate 121 for the V phase stored in the storage portion 12 and an inverter circuit for the V phase (not shown in Fig. 1, see Fig. 2) mounted on the laminated substrate 121. The semiconductor module 1 has a laminated substrate 131 for the W phase stored in the storage portion 13 and an inverter circuit for the W phase (not shown in Fig. 1, see Fig. 2) mounted on the laminated substrate 131.

[0015] The case 10 is arranged so as to surround semiconductor elements (details will be described later), laminated substrates 111, 121, 131, a plurality of wiring patterns (details will be described later), and a plurality of connection members (details will be described later) inside the case 10. The case 10 is mounted on a heat dissipation base or a cooler (both not shown) and is mechanically fixed to the heat dissipation base or the cooler by a case bonding material (not shown). Thereby, the case 10 can release the heat generated from the semiconductor elements to the outside of the case 10.

[0016] The semiconductor module 1 includes a negative terminal 31u (an example of a first power supply terminal) of the U phase connected to the first polarity side of the DC power. Further, the semiconductor module 1 is disposed above the negative terminal 31u with an exposed portion 314 (an example of a part) including one end 311 of the negative terminal 31u exposed, and includes a positive terminal 21u (an example of a second power supply terminal) connected to the second polarity side of the DC power. In the present embodiment, the first polarity side connected to the negative terminal 31u is the negative side of the DC power, and the second polarity side connected to the positive terminal 21u is the positive side of the DC power. The negative terminal 31u and the positive terminal 21u are provided at one end of the longitudinal side of the case 10 on one of both sides of the housing portion 11. Further, the semiconductor module 1 includes an output terminal 81u for outputting U-phase AC power. The output terminal 81u is provided at the other end of the longitudinal side of the case 10 on the other of both sides of the housing portion 11. The positive terminal 21u and the negative terminal 31u are disposed to face the output terminal 81u with the housing portion 11 interposed therebetween.

[0017] Also, the semiconductor module 1 has an insulating sheet 61u disposed between the negative terminal 31u and the positive terminal 21u with an exposed portion 612 (an example of a part) exposed between one end 311 of the negative terminal 31u and one end 211 of the positive terminal 21u, for insulating the negative terminal 31u and the positive terminal 21u. Further, the semiconductor module 1 includes a first dielectric portion 71u formed to cover at least a corner portion 212 (not shown in FIG. 1, see FIG. 4) of one end 211 of the positive terminal 21u in contact with the insulating sheet 61u.

[0018] The semiconductor module 1 includes a negative terminal 31v (an example of a first power supply terminal) connected to the negative polarity side of the DC power. Further, the semiconductor module 1 is disposed above the negative terminal 31v with an exposed portion 314 (an example of a part) including one end 311 of the negative terminal 31v exposed, and includes a positive terminal 21v (an example of a second power supply terminal) connected to the positive polarity side of the DC power. In the present embodiment, the first polarity side connected to the negative terminal 31v is the negative side of the DC power, and the second polarity side connected to the positive terminal 21v is the positive side of the DC power. The negative terminal 31v and the positive terminal 21v are provided at one end of the longitudinal side of the case 10 on one side of both sides of the housing portion 12. Further, the semiconductor module 1 includes an output terminal 81v from which V-phase AC power is output. The output terminal 81v is provided at the other end of the longitudinal side of the case 10 on the other side of both sides of the housing portion 12. The positive terminal 21v and the negative terminal 31v are disposed opposite to the output terminal 81v with the housing portion 12 interposed therebetween.

[0019] Also, the semiconductor module 1 has an insulating sheet 61v disposed between the negative terminal 31v and the positive terminal 21v with an exposed portion 612 (an example of a part) exposed between one end 311 of the negative terminal 31v and one end 211 of the positive terminal 21v, for insulating the negative terminal 31v and the positive terminal 21v. Further, the semiconductor module 1 includes a first dielectric portion 71v formed to cover at least a corner portion (not shown) of one end 211 of the positive terminal 21v in contact with the insulating sheet 61v. The corner portion of one end 211 of the positive terminal 21v corresponds to the corner portion 212 of the positive terminal 21u.

[0020] The semiconductor module 1 includes a negative terminal 31w (an example of a first power supply terminal) of the W phase connected to the first polarity side of the DC power. Further, the semiconductor module 1 includes a positive terminal 21w (an example of a second power supply terminal) disposed above the negative terminal 31w with an exposed portion 314 (an example of a part) including one end 311 of the negative terminal 31w exposed, and connected to the second polarity side of the DC power. In the present embodiment, the first polarity side connected to the negative terminal 31w is the negative side of the DC power, and the second polarity side connected to the positive terminal 21w is the positive side of the DC power. The negative terminal 31w and the positive terminal 21w are provided at one end of the longitudinal side of the case 10 on one of both sides of the housing portion 13. Further, the semiconductor module 1 includes an output terminal 81w for outputting W-phase AC power. The output terminal 81w is provided at the other end of the longitudinal side of the case 10 on the other of both sides of the housing portion 13. The positive terminal 21w and the negative terminal 31w are disposed facing the output terminal 81w with the housing portion 13 interposed therebetween.

[0021] Further, the semiconductor module 1 has an insulating sheet 61w disposed between the negative terminal 31w and the positive terminal 21w with an exposed portion 612 (an example of a part) exposed between one end 311 of the negative terminal 31w and one end 211 of the positive terminal 21w, and insulating the negative terminal 31w and the positive terminal 21w. Furthermore, the semiconductor module 1 includes a first dielectric portion 71w formed to cover at least a corner portion 212 of one end 211 of the positive terminal 21w in contact with the insulating sheet 61w.

[0022] The case 10 is formed by insert molding in which a thermoplastic resin heated and melted is injected into an injection mold into which the positive terminal 21u, 21v, 21w, the insulating sheets 61u, 61v, 61w and the negative terminal 31u, 31v, 31w are inserted, and the inserted positive terminal 21u, 21v, 21w, the insulating sheets 61u, 61v, 61w and the negative terminal 31u, 31v, 31w are integrated with the resin. Examples of the thermoplastic resin include polyphenylene sulfide (PPS), polybutylene terephthalate (PBT) resin, polybutylene succinate (PBS) resin, polyamide (PA) resin, acrylonitrile butadiene styrene (ABS) resin and the like. Further, the first dielectric portions 71u, 71v, 71w are formed by applying, for example, a liquid in which a dielectric material having a predetermined relative permittivity is dispersed in the resin to a predetermined position by a dispenser or spin coating after the case 10 is molded. As the dielectric material, titanium oxide or a titanate-based material can be used, and as a specific titanate-based material, one or more selected from barium titanate, strontium titanate, calcium titanate, magnesium titanate can be used.

[0023] Next, the circuit configurations of the inverter circuits 112, 122, 132 provided in the semiconductor module 1 will be described with reference to FIG. 2. Since the inverter circuits 112, 122, 132 have the same configuration as each other, the circuit configuration of the inverter circuits 112, 122, 132 will be described taking the inverter circuit 112 as an example.

[0024] As shown in FIG. 2, the inverter circuit 112 provided in the semiconductor module 1 includes a plurality of semiconductor elements Sup11, Sup12, Sup21, Sup22 and semiconductor elements Slo11, Slo12, Slo21, Slo22 connected in series between the negative terminal 31u and the positive terminal 21u. In the inverter circuit 112, the semiconductor elements Sup11, Sup12, Sup21, Sup22 are connected in parallel, and the semiconductor elements Slo11, Slo12, Slo21, Slo22 are connected in parallel. The semiconductor elements Sup11, Sup12, Sup21, Sup22 connected in parallel and the semiconductor elements Slo11, Slo12, Slo21, Slo22 connected in parallel are connected in series between the negative terminal 31u and the positive terminal 21u. In the inverter circuit 112, the connection portion between the semiconductor elements Sup11, Sup12, Sup21, Sup22 connected in parallel and the semiconductor elements Slo11, Slo12, Slo21, Slo22 connected in parallel is connected to the output terminal 81u from which U-phase AC power is output. That is, in the inverter circuit 112, the semiconductor elements Sup11, Sup12, Sup21, Sup22 constitute the upper arm Uup of the U-phase AC power, and the semiconductor elements Slo11, Slo12, Slo21, Slo22 constitute the lower arm Ulo of the U-phase AC power.

[0025] The inverter circuit 122 provided in the semiconductor module 1 has the same configuration as the inverter circuit 112 when the negative terminal 31u is replaced with the negative terminal 31v, the positive terminal 21u is replaced with the positive terminal 21v, and the output terminal 81u is replaced with the output terminal 81v. In the inverter circuit 122, the semiconductor elements Sup11, Sup12, Sup21, Sup22 constitute the upper arm Vup of the V-phase AC power, and the semiconductor elements Slo11, Slo12, Slo21, Slo22 constitute the lower arm Vlo of the V-phase AC power.

[0026] The inverter circuit 132 provided in the semiconductor module 1 has the same configuration as the inverter circuit 112 when the negative terminal 31u is read as the negative terminal 31w, the positive terminal 21u is read as the positive terminal 21w, and the output terminal 81u is read as the output terminal 81w. In the inverter circuit 132, the semiconductor elements Sup11, Sup12, Sup21, and Sup22 constitute the upper arm Wup of the W-phase AC power, and the semiconductor elements Slo11, Slo12, Slo21, and Slo22 constitute the lower arm Wlo of the W-phase AC power.

[0027] For example, a motor (not shown) that is the driving target of the semiconductor module 1 is connected to the output terminal 81u, the output terminal 81v, and the output terminal 81w. Thereby, the semiconductor module 1 can supply U-phase AC power to the motor via the output terminal 81u of the inverter circuit 112, can supply V-phase AC power to the motor via the output terminal 81v of the inverter circuit 122, and can supply W-phase AC power to the motor via the output terminal 81w of the inverter circuit 132.

[0028] As shown in FIG. 2, the semiconductor element Sup11 has, for example, a transistor Qup11 that is an N-type MOSFET, and a freewheeling diode Dup11 connected in anti-parallel to the transistor Qup11. The transistor Qup11 and the freewheeling diode Dup11 are formed on, for example, a single semiconductor substrate and are integrated into one chip.

[0029] The semiconductor element Sup12 has, for example, a transistor Qup12 that is an N-type MOSFET, and a freewheeling diode Dup12 connected in anti-parallel to the transistor Qup12. The transistor Qup12 and the freewheeling diode Dup12 are formed on, for example, a single semiconductor substrate and are integrated into one chip.

[0030] The semiconductor element Sup21 has, for example, a transistor Qup21 that is an N-type MOSFET, and a freewheeling diode Dup21 connected in anti-parallel to the transistor Qup21. The transistor Qup21 and the freewheeling diode Dup21 are formed on, for example, a single semiconductor substrate and are integrated into one chip.

[0031] The semiconductor element Sup22 has a transistor Qup22 which is an N-type MOSFET, for example, and a freewheeling diode Dup22 connected in antiparallel to the transistor Qup22. The transistor Qup22 and the freewheeling diode Dup22 are formed on one semiconductor substrate and integrated into one chip, for example.

[0032] The semiconductor element Slo11 has a transistor Qlo11 which is an N-type MOSFET, for example, and a freewheeling diode Dlo11 connected in antiparallel to the transistor Qlo11. The transistor Qlo11 and the freewheeling diode Dlo11 are formed on one semiconductor substrate and integrated into one chip, for example.

[0033] The semiconductor element Slo12 has a transistor Qlo12 which is an N-type MOSFET, for example, and a freewheeling diode Dlo12 connected in antiparallel to the transistor Qlo12. The transistor Qlo12 and the freewheeling diode Dlo12 are formed on one semiconductor substrate and integrated into one chip, for example.

[0034] The semiconductor element Slo21 has a transistor Qlo21 which is an N-type MOSFET, for example, and a freewheeling diode Dlo21 connected in antiparallel to the transistor Qlo21. The transistor Qlo21 and the freewheeling diode Dlo21 are formed on one semiconductor substrate and integrated into one chip, for example.

[0035] The semiconductor element Slo22 has a transistor Qlo22 which is an N-type MOSFET, for example, and a freewheeling diode Dlo22 connected in antiparallel to the transistor Qlo22. The transistor Qlo22 and the freewheeling diode Dlo22 are formed on one semiconductor substrate and integrated into one chip, for example.

[0036] Each of the transistors Qup11, Qup12, Qup21, Qup22 and the transistors Qlo11, Qlo12, Qlo21, Qlo22 is composed of a wide-bandgap semiconductor device including, for example, SiC, GaN, diamond, gallium nitride-based materials, gallium oxide-based materials, AlN, AlGaN or ZnO.

[0037] The gate of the transistor Qup11 is connected to the gate signal input terminal Gup11. The reference signal input terminal Rup11 is connected to the source of the transistor Qup11. The gate of the transistor Qup12 is connected to the gate signal input terminal Gup12. The reference signal input terminal Rup12 is connected to the source of the transistor Qup12. The gate of the transistor Qup21 is connected to the gate signal input terminal Gup21. The reference signal input terminal Rup21 is connected to the source of the transistor Qup21. The gate of the transistor Qup22 is connected to the gate signal input terminal Gup22. The reference signal input terminal Rup22 is connected to the source of the transistor Qup22.

[0038] The gate of the transistor Qlo11 is connected to the gate signal input terminal Glo11. The reference signal input terminal Rlo11 is connected to the source of the transistor Qlo11. The gate of the transistor Qlo12 is connected to the gate signal input terminal Glo12. The reference signal input terminal Rlo12 is connected to the source of the transistor Qlo12. The gate of the transistor Qlo21 is connected to the gate signal input terminal Glo21. The reference signal input terminal Rlo21 is connected to the source of the transistor Qlo21. The gate of the transistor Qlo22 is connected to the gate signal input terminal Glo22. The reference signal input terminal Rlo22 is connected to the source of the transistor Qlo22.

[0039] The gate signal input terminals Gup11, Gup12, Gup21, Gup22, the reference signal input terminals Rup11, Rup12, Rup21, Rup22, the gate signal input terminals Glo11, Glo12, Glo21, Glo22 and the reference signal input terminals Rlo11, Rlo12, Rlo21, Rlo22 are each connected to a control circuit (not shown) that controls the inverter circuits 112, 122, 132. The control circuit generates gate pulse signals for each of the semiconductor elements Sup11, Sup12, Sup21, Sup22 and the semiconductor elements Slo11, Slo12, Slo21, Slo22 by modulating the command value and the reference waveform.

[0040] The gate pulse signal is applied between the gate signal input terminal Gup11 and the reference signal input terminal Rup11, between the gate signal input terminal Gup12 and the reference signal input terminal Rup12, between the gate signal input terminal Gup21 and the reference signal input terminal Rup21, and between the gate signal input terminal Gup22 and the reference signal input terminal Rup22, respectively. Therefore, the gate pulse signal is applied to Qup11, Qup12, Qup21, Qup22 as the gate-source voltage.

[0041] Also, the gate pulse signal is applied between the gate signal input terminal Glo11 and the reference signal input terminal Rlo11, between the gate signal input terminal Glo12 and the reference signal input terminal Rlo12, between the gate signal input terminal Glo21 and the reference signal input terminal Rlo21, and between the gate signal input terminal Glo22 and the reference signal input terminal Rlo22, respectively. Therefore, the gate pulse signal is applied to Qlo11, Qlo12, Qlo21, Qlo22 as the gate-source voltage.

[0042] Transistors Qup11, Qup12, Qup21, Qup22 and transistors Qlo11, Qlo12, Qlo21, Qlo22 turn on when the voltage level of the gate pulse signal is at a high level, for example, and turn off when the voltage level of the gate pulse signal is at a low level. Although detailed description is omitted, transistors Qup11, Qup12, Qup21, Qup22 and transistors Qlo11, Qlo12, Qlo21, Qlo22 provided in each of the inverter circuits 112, 122, 132 repeat on-states and off-states at a predetermined timing and combination. Thereby, the semiconductor module 1 can supply U-phase AC power, V-phase AC power, and W-phase AC power whose phases are shifted from each other by a predetermined amount from the output terminals 81u, 81v, 81w of the inverter circuits 112, 122, 132 to the motor.

[0043] Next, the laminated substrates 111, 121, 131 will be described with reference to FIGS. 1 and 2 and using FIG. 3. The laminated substrates 111, 121, 131 have the same configuration as each other. For this reason, hereinafter, the laminated substrates 111, 121, 131 will be described taking the laminated substrate 111 as an example.

[0044] As shown in FIG. 3, the laminated substrate 111 has a rectangular insulating substrate 40 and a heat dissipation pattern layer (not shown) having a predetermined shape formed on the lower surface of the insulating substrate 40. The laminated substrate 111 has a positive electrode side input terminal pattern 41, 42 formed on one short side of both short sides of the insulating substrate 40 and a negative electrode side input terminal pattern 43. The negative electrode side input terminal pattern 43 is disposed between the positive electrode side input terminal pattern 41 and the positive electrode side input terminal pattern 42. The laminated substrate 111 has an output terminal pattern 49 formed on the other short side of the insulating substrate 40. The output terminal pattern 49 is disposed to face the negative electrode side input terminal pattern 43.

[0045] The laminated substrate 111 has a positive electrode portion pattern 44 formed on the insulating substrate 40 on one of the two long sides of the insulating substrate 40. The positive electrode portion pattern 44 is arranged to extend between the two short sides of the insulating substrate 40 along one long side of the insulating substrate 40. A positive electrode side input terminal pattern 41 is formed on one end portion of the positive electrode portion pattern 44. Thereby, the positive electrode portion pattern 44 and the positive electrode side input terminal pattern 41 are electrically connected.

[0046] The laminated substrate 111 has a positive electrode portion pattern 45 formed on the insulating substrate 40 on the other long side of the insulating substrate 40. The positive electrode portion pattern 45 is arranged to extend between the two short sides of the insulating substrate 40 along the other long side of the insulating substrate 40. A positive electrode side input terminal pattern 42 is formed on one end portion of the positive electrode portion pattern 45. Thereby, the positive electrode portion pattern 45 and the positive electrode side input terminal pattern 42 are electrically connected.

[0047] The laminated substrate 111 has a negative electrode side input terminal pattern 43 formed on the end portion of the negative electrode portion pattern 46 on one short side of the insulating substrate 40. The negative electrode portion pattern 46 and the negative electrode side input terminal pattern 43 are electrically connected. The negative electrode portion pattern 46 has a bifurcated shape in which the end portion opposite to the negative electrode side input terminal pattern 43 side extends along each of the positive electrode portion patterns 44 and 45.

[0048] The laminated substrate 111 has an output portion pattern 47 formed on the insulating substrate 40 and extending from the other short side of the insulating substrate 40 toward the central portion. The output portion pattern 47 is arranged to be sandwiched between the bifurcated portions of the negative electrode portion pattern 46 at the central portion of the laminated substrate 111. An output terminal pattern 49 is formed on the end portion of the output portion pattern 47 on the other short side of the insulating substrate 40. Thereby, the output portion pattern 47 and the output terminal pattern 49 are electrically connected.

[0049] As shown in FIG. 3, semiconductor elements Sup11 and Sup12 are mounted in a state of being electrically connected to the positive electrode portion pattern 44 near the ends of both ends of the positive electrode portion pattern 44, which are opposite to the positive electrode side input terminal pattern 41 side. Further, connection members 51 and 52 made of, for example, copper bars are disposed between the semiconductor elements Sup11 and Sup12 and the output portion pattern 47. The connection member 51 is electrically connected to each of the semiconductor element Sup11 and the output portion pattern 47. Thereby, the connection member 51 can electrically connect the semiconductor element Sup11 and the output portion pattern 47. Further, the connection member 52 is electrically connected to each of the semiconductor element Sup12 and the output portion pattern 47. Thereby, the connection member 52 can electrically connect the semiconductor element Sup12 and the output portion pattern 47.

[0050] Near the ends of both ends of the positive electrode portion pattern 45, which are opposite to the positive electrode side input terminal pattern 42 side, semiconductor elements Sup21 and Sup22 are mounted in a state of being electrically connected to the positive electrode portion pattern 45. Further, connection members 55 and 56 made of, for example, copper bars are disposed between the semiconductor elements Sup21 and Sup22 and the output portion pattern 47. The connection member 55 is electrically connected to each of the semiconductor element Sup21 and the output portion pattern 47. Thereby, the connection member 55 can electrically connect the semiconductor element Sup21 and the output portion pattern 47. Further, the connection member 56 is electrically connected to each of the semiconductor element Sup22 and the output portion pattern 47. Thereby, the connection member 56 can electrically connect the semiconductor element Sup22 and the output portion pattern 47.

[0051] Semiconductor elements Slo11, Slo12, Slo21, and Slo22 are mounted in a state of being electrically connected to the output portion pattern 47 at the portion of the output portion pattern 47 disposed at the center of the multilayer substrate 111. Further, connection members 53, 54, 57, and 58 made of, for example, copper bars are disposed between Slo11, Slo12, Slo21, Slo22 and the negative electrode portion pattern 46.

[0052] The connection member 53 is electrically connected to each of the semiconductor element Slo11 and the negative electrode portion pattern 46. Thereby, the connection member 53 can electrically connect the semiconductor element Slo11 and the negative electrode portion pattern 46. The connection member 54 is electrically connected to each of the semiconductor element Slo12 and the negative electrode portion pattern 46. Thereby, the connection member 54 can electrically connect the semiconductor element Slo12 and the negative electrode portion pattern 46. The connection member 57 is electrically connected to each of the semiconductor element Slo21 and the negative electrode portion pattern 46. Thereby, the connection member 57 can electrically connect the semiconductor element Slo21 and the negative electrode portion pattern 46. The connection member 58 is electrically connected to each of the semiconductor element Slo22 and the negative electrode portion pattern 46. Thereby, the connection member 58 can electrically connect the semiconductor element Slo22 and the negative electrode portion pattern 46.

[0053] The positive electrode side input terminal pattern 41 is electrically connected and mounted with the positive electrode terminal 21u (see FIG. 1). The output terminal pattern 49 is electrically connected and mounted with the output terminal 81u (see FIG. 1). Therefore, the semiconductor elements Sup11 and Sup12 are connected in parallel between the positive electrode terminal 21u and the output terminal 81u via the positive electrode side input terminal pattern 41 and the positive electrode portion pattern 44, the connection members 51, 52, the output portion pattern 47, and the output terminal pattern 49.

[0054] The positive electrode side input terminal pattern 42 is electrically connected and mounted with the positive electrode terminal 21u (see FIG. 1). Therefore, the semiconductor elements Sup21 and Sup22 are connected in parallel between the positive electrode terminal 21u and the output terminal 81u via the positive electrode side input terminal pattern 42 and the positive electrode portion pattern 45, the connection members 55, 56, the output portion pattern 47, and the output terminal pattern 49.

[0055] A negative terminal 31u (see FIG. 1) is electrically connected and mounted to a negative electrode side input terminal pattern 43. Therefore, the semiconductor elements Slo11 and Slo12 are connected in parallel between an output terminal 81u and the negative terminal 31u via an output unit pattern 47, an output terminal pattern 49, connection members 53, 54, a negative electrode part pattern 46, and the negative electrode side input terminal pattern 43. Also, the semiconductor elements Slo21 and Slo22 are connected in parallel between the output terminal 81u and the negative terminal 31u via the output unit pattern 47, the output terminal pattern 49, connection members 57, 58, the negative electrode part pattern 46, and the negative electrode side input terminal pattern 43. Thereby, the inverter circuit 112 has a half-bridge circuit configuration.

[0056] Although illustration is omitted, the laminated substrates 121, 131 also have the same configuration as the laminated substrate 111. Therefore, the inverter circuits 122, 132 have a half-bridge circuit configuration. Thus, the semiconductor module 1 is configured as a 6in1 module in which an inverter circuit 112 for the U phase having a half-bridge circuit configuration, an inverter circuit 122 for the V phase having a half-bridge circuit configuration, and an inverter circuit 132 for the W phase having a half-bridge circuit configuration are integrated into one module.

[0057] The positive electrode part patterns 44, 45, the negative electrode part pattern 46, and the output unit pattern 47 are formed adjacent to each other while maintaining a predetermined insulation interval so as not to short-circuit with each other. Also, the positive electrode part patterns 44, 45, the negative electrode part pattern 46, and the output unit pattern 47 are all or partially sealed and fixed by an insulating mold resin (not shown) provided in the case 10 (see FIG. 1). Thereby, the insulation of the positive electrode part patterns 44, 45, the negative electrode side input terminal pattern 43, and the output unit pattern 47 is further improved.

[0058] The stacked substrate 111 is mounted on a heat dissipation base or a cooler, and is thermally and mechanically joined to the heat dissipation base or the cooler by a substrate bottom bonding material (not shown). Also, as described above, the case 10 is mechanically fixed to the heat dissipation base or the cooler. Therefore, the semiconductor module 1 can release the heat generated by the semiconductor elements Sup11, Sup12, Sup21, Sup22, Slo11, Slo12, Slo21, Slo22 to the heat dissipation base or the cooler through the stacked substrate 111 and the case 10. Thereby, the semiconductor module 1 can prevent the semiconductor elements Sup11, Sup12, Sup21, Sup22, Slo11, Slo12, Slo21, Slo22 from being damaged due to heat generation.

[0059] (Configuration of the first power supply terminal and the second power supply terminal) Next, the configurations of the negative terminals 31u, 31v, 31w (an example of the first power supply terminal), the positive terminals 21u, 21v, 21w (an example of the second power supply terminal), and the insulating sheets 61u, 61v, 61w provided in the semiconductor module 1 according to the present embodiment will be described with reference to FIGS. 1 to 3 and using FIGS. 4 and 5. Note that in FIG. 4, the illustration of the stacked substrate 111 is omitted.

[0060] The negative terminals 31u, 31v, 31w have the same configuration. Therefore, the configuration of the negative terminals 31u, 31v, 31w will be described taking the negative terminal 31u as an example. Also, the positive terminals 21u, 21v, 21w have the same configuration. Therefore, the configuration of the positive terminals 21u, 21v, 21w will be described taking the positive terminal 21u as an example. The insulating sheets 61u, 61v, 61w have the same configuration. Therefore, the configuration of the insulating sheets 61u, 61v, 61w will be described taking the negative terminal 31u as an example.

[0061] As shown in FIG. 4, the negative electrode terminal 31u, the insulating sheet 61u, and the positive electrode terminal 21u are provided in the case 10 in a stacked state. The insulating sheet 61u is disposed sandwiched between the negative electrode terminal 31u and the positive electrode terminal 21u in a state of being in contact with each of the negative electrode terminal 31u and the positive electrode terminal 21u. Thereby, electrical insulation between the negative electrode terminal 31u and the positive electrode terminal 21u is ensured by the insulating sheet 61u.

[0062] The negative electrode terminal 31u, the insulating sheet 61u, and the positive electrode terminal 21u are arranged with a part thereof exposed to the outside, and a part of the remaining part is arranged in the storage portion 11 in a state of being covered with a mold resin. A gap corresponding to the thickness of the insulating sheet 61u is provided between the portions of the negative electrode terminal 31u and the positive electrode terminal 21u arranged on the storage portion 11 side. When the mold resin is also formed between this gap, insulation between the negative electrode terminal 31u and the positive electrode terminal 21u is ensured.

[0063] As shown in FIG. 4, the negative electrode terminal 31u has a flat plate shape. The negative electrode terminal 31u has protrusions 312 and 313 formed on the side disposed in the storage portion 11. The protrusions 312 and 313 are arranged on the negative electrode side input terminal pattern 43 when the laminated substrate 111 is arranged in the storage portion 11 (see FIG. 1). The protrusions 312 and 313 are mechanically and electrically connected to the negative electrode side input terminal pattern 43 by, for example, soldering. Thereby, the semiconductor elements Slo11, Slo12, Slo21, and Slo22 are connected to the negative electrode side of the DC power through the negative electrode terminal 31u, the negative electrode side input terminal pattern 43, and the negative electrode portion pattern 46. In the present embodiment, two protrusions 312 and 313 are provided so as to facilitate the connection between the negative electrode terminal 31u and the laminated substrate 111, but the number of protrusions may be one.

[0064] The positive electrode terminal 21u has a flat plate shape. The positive electrode terminal 21u has protruding portions 214 and 215 formed on the side disposed in the housing portion 11. The protruding portion 214 is mechanically and electrically connected to the positive electrode side input terminal pattern 41, for example, by soldering. The protruding portion 215 is mechanically and electrically connected to the positive electrode side input terminal pattern 42, for example, by soldering. Thereby, the semiconductor elements Sup11, Sup12, Sup21, and Sup22 are connected to the positive electrode side of the DC power via the positive electrode terminal 21u, the positive electrode side input terminal patterns 41 and 42, and the positive electrode portion patterns 44 and 45.

[0065] The positive electrode terminal 21u is formed such that the length in the direction in which the protruding portions 214 and 215 extend is shorter than that of the negative electrode terminal 31u. Therefore, as shown in FIG. 1, when one ends of the protruding portions 214 and 215 and one ends of the protruding portions 312 and 313 are arranged to be substantially flush, one end 311 of the negative electrode terminal 31u protrudes toward the one end portion on the longitudinal side of the case 10 with respect to one end 211 of the positive electrode terminal.

[0066] Returning to FIG. 4, the insulating sheet 61u is arranged such that one end 611 is positioned between one end 211 of the positive electrode terminal 21u and one end 311 of the negative electrode terminal 31u. For this reason, the insulating sheet 61u has an exposed portion 612 having a predetermined spread and exposed to the outside between one end 211 of the positive electrode terminal 21u and one end 311 of the negative electrode terminal 31u. Thereby, at one end portion on the longitudinal side of the case 10, the positive electrode terminal 21u, the insulating sheet 61u, and the negative electrode terminal 31u are laminated and arranged in a stepped manner.

[0067] The positive terminal 21u and the negative terminal 31u are formed of, for example, copper or a copper alloy. The positive terminal 21u and the negative terminal 31u have a thickness of, for example, 0.6 mm or more, and may have a thickness of 0.8 mm or more and 1.2 mm or less. The insulating sheet 61u may be a single sheet or a plurality of laminated sheets. The insulating sheet 61u has a thickness, for example, thinner than the thicknesses of the positive terminal 21u and the negative terminal 31u. The insulating sheet 61u may have a thickness of, for example, 0.05 mm or more. The insulating sheet 61u may be formed of, for example, aramid fiber, glass fiber, ceramic, polyimide, mica, or a composite material of one or more of these materials.

[0068] The positive terminal 21u is formed of a metal material such as copper and has an exposed portion 213 that is exposed to the outside. Therefore, the positive terminal 21u can be electrically and mechanically connected to the positive side of the DC power. Similarly, the negative terminal 31u is formed of a metal material such as copper and has an exposed portion 314 that is exposed to the outside. Therefore, the negative terminal 31u can be electrically and mechanically connected to the negative side of the DC power. An exposed portion 612 of the insulating sheet 61u is disposed between the exposed portion 213 of the positive terminal 21u and the exposed portion 314 of the negative terminal 31u. Therefore, the insulation distance between the exposed portion 213 of the positive terminal 21u and the exposed portion 314 of the negative terminal 31u is ensured by the exposed portion 612 of the insulating sheet 61u.

[0069] As shown in FIG. 4, the first dielectric portion 71u is formed to cover at least the corner portion 212 of one end 211 of the positive terminal 21u. The corner portion 212 is the corner portion of the one end 211 that contacts the insulating sheet 61u. In the present embodiment, the first dielectric portion 71u is formed across a region exposed to the outside from the case 10 and a part of the insulating sheet 61u in the entire region of the one end 211 including the corner portion 212 (see FIGS. 1 and 4). As long as the first dielectric portion 71u is formed to cover the corner portion 212, it may be formed across a part of the exposed portion 213 of the positive terminal 21u and a part of the insulating sheet 61u. Although details will be described later, the first dielectric portion 71u has, for example, a higher relative permittivity than the insulating sheet 61u. If the insulating sheet 61u has a relative permittivity of, for example, 3.2 to 3.8, the first dielectric portion 71u has a relative permittivity greater than 3.8 and 30, for example.

[0070] Here, the operation and effect of the first dielectric portion 71u will be described. In the semiconductor module 1, it is difficult to avoid a structure in which the exposed portion 213 of the positive terminal 21u is disposed on the insulating sheet 61u in order to connect the positive terminal 21u to the positive side of the DC power. For this reason, the corner portion 212 of the one end 211 of the positive terminal 21u becomes a triple point where the insulating sheet 61u and the first dielectric portion 71u, which are two insulators having different relative permittivities from the positive terminal 21u which is a conductor, intersect at one point. Further, even when the first dielectric portion 71u is not formed, the corner portion 212 of the one end 211 of the positive terminal 21u becomes a triple point where the insulating sheet 61u and air, which are two insulators having different relative permittivities from the positive terminal 21u which is a conductor, intersect at one point.

[0071] The triple point is a portion where the electric field is most likely to concentrate. For this reason, when a positive voltage of DC power is applied to the positive terminal 21u and a negative voltage of DC power is applied to the negative terminal 31u, the electric field generated from the one end 211 of the positive terminal 21u toward the negative terminal 31u side is likely to concentrate on the corner portion 212 of the one end 211 corresponding to the triple point.

[0072] When the insulating sheet 61u is formed of insulating paper or the like and has minute spaces inside, if the first dielectric portion 71u is not formed, discharge may occur in the minute spaces due to electric field concentration at the corner portion 212, and insulation breakdown may be caused by the progress of migration due to this discharge.

[0073] Also, when the relative dielectric constants of two insulators are εr1 and εr2 (εr1 < εr2), and the angle formed by the insulator with the relative dielectric constant εr1 and the metal conductor is lower than 90°, the electric field strength at the triple point becomes infinite. Therefore, there is concern that discharge may occur at the triple point even under a low voltage. The relative dielectric constant of the insulating sheet 61u is higher than that of air. For this reason, if one end 211 of the positive electrode terminal 21u is inclined toward the insulating sheet 61u due to the influence of the processing accuracy of the positive electrode terminal 21u or the like, when the first dielectric portion 71u is not formed, at the corner portion 212 of one end 211 corresponding to the triple point, the angle formed by the air with a low relative dielectric constant and one end 211 becomes smaller than 90°. Therefore, when the first dielectric portion 71u is not formed, there is concern that discharge may occur at the corner portion 212 of one end 211 of the positive electrode terminal 21u.

[0074]

Table 1

[0075] Table 1 shows an example of the simulation results of the electric field strength and the electric field relaxation rate when the first dielectric part 71u is formed covering the corner part 212 of the positive electrode terminal 21u. In Table 1, the first dielectric part 71u has the shape shown in FIG. 4, the peripheral environment of the semiconductor module 1 is air, a voltage of 1200 V is applied to the positive electrode terminal 21u, and a voltage of 0 V is applied to the negative electrode terminal 31u. The "relative permittivity" shown in Table 1 represents the relative permittivity at the corner part 212. The "1" of the "relative permittivity" corresponds to the case where the first dielectric part 71u is not formed (i.e., the structure of the conventional semiconductor module), and the others correspond to the case where the first dielectric part 71u is formed (i.e., the structure of the semiconductor module 1 according to the present embodiment). The "electric field strength MV / m" shown in Table 1 represents the electric field strength at the corner part 212. The "electric field relaxation rate [%]" shown in Table 1 represents the ratio at which the electric field strength is relaxed by the formation of the first dielectric part 71u.

[0076] As shown in Table 1, when the first dielectric part 71u is formed covering the corner part 212 of the positive electrode terminal 21u corresponding to the triple point (i.e., when the relative permittivity is from 10 to 35), compared with the case where the first dielectric part 71u is not formed, the electric field strength decreases and the electric field relaxation rate increases. Also, as shown in Table 1, as the relative permittivity of the first dielectric part 71u increases from 10 to 35, the electric field strength monotonically decreases from 5.60 [MV / m] to 4.11 [MV / m] and the electric field relaxation rate monotonically increases from 52 [%] to 64 [%]. When the relative permittivity is 1, i.e., when the first dielectric part 71u is not formed, the electric field strength is 11.5 [MV / m]. Therefore, by forming the first dielectric part 71u in the range of relative permittivity from 10 to 35, the electric field strength at the corner part 212 of the positive electrode terminal 21u decreases.

[0077] In Table 1, the minimum value of the relative permittivity of the first dielectric part 71u is 10. However, considering the characteristic that the electric field strength decreases as the relative permittivity increases, it is preferable that the first dielectric part 71u has a relative permittivity higher than that of the insulating sheet 61u. Thereby, the semiconductor module 1 can achieve a decrease in the electric field strength and an increase in electric field relaxation at the corner part 212 of the positive electrode terminal 21u.

[0078] The relative permittivity of the first dielectric part 71u can be adjusted, for example, by the forming material for forming the first dielectric part 71u. Therefore, from the viewpoint of material selection of the first dielectric part 71u, it is preferable that the relative permittivity of the first dielectric part 71u is 30 or less. Thus, the first dielectric part 71u may have a relative permittivity higher than that of the insulating sheet 61u and 30 [F / m] or less.

[0079] In this way, by providing the first dielectric part 71u, the semiconductor module 1 can shift the location where the electric field concentrates from the corner part 212 corresponding to the triple point to relieve the electric field concentration, and improve the reliability of the positive electrode terminal 21u and the negative electrode terminal 31u corresponding to the power supply terminals. Further, even if the insulating sheet 61u has minute spaces inside, the generation of discharge in the minute spaces can be suppressed, so that the semiconductor module 1 can improve the reliability of the positive electrode terminal 21u and the negative electrode terminal 31u.

[0080] Also, even if one end 211 of the positive electrode terminal 21u is inclined toward the insulating sheet 61u, by forming the first dielectric part 71u covering the corner part 212, the insulator forming an angle smaller than 90° together with the one end 211 at the corner part 212 of the one end 211 corresponding to the triple point becomes the first dielectric part 71u. Since the first dielectric part 71u has a higher relative permittivity than the insulating sheet 61u, even if the angle formed by the one end 211 and the first dielectric part 71u at the corner part 212 is smaller than 90°, the possibility of discharge occurring is extremely low. Thereby, the semiconductor module 1 can improve the reliability of the positive electrode terminal 21u and the negative electrode terminal 31u.

[0081] As shown in FIG. 5, the positive electrode terminal 21u has a through hole 213a formed by partially penetrating so that the insulating sheet 61u is exposed. The semiconductor module 1 includes a second dielectric part 72u formed to cover at least an end part 213c on the insulating sheet 61u side of an inner wall surface 213b forming the through hole 213a. The second dielectric part 72u has a relative dielectric constant higher than that of the insulating sheet 61u. As the dielectric material for forming the second dielectric part 72u, similar to the first dielectric part 71u, titanium oxide or a titanate-based material can be used. As specific titanate-based materials, one or more selected from barium titanate, strontium titanate, calcium titanate, and magnesium titanate can be used. The first dielectric part 71u and the second dielectric part 72u may be formed of the same material or different materials. Two through holes 213a are formed at predetermined positions of the exposed part 213 of the positive electrode terminal 21u (see FIG. 1). The through hole 213a is used to position the positive electrode terminal 21u in an injection mold when insert molding the case 10.

[0082] As shown in FIG. 5, the end part 213c on the insulating sheet 61u side of the inner wall surface 213b forming the through hole 213a is a triple point where the insulating sheet 61u and the second dielectric part 72u, which are two insulators having different relative dielectric constants from the positive electrode terminal 21u which is a conductor, intersect at one point. For this reason, when the second dielectric part 72u is not formed in the through hole 213a, at the end part 213c of the inner wall surface 213b, the positive electrode terminal 21u, the insulating sheet 61u, and the air in the through hole 213a intersect. Therefore, the same problem as the corner part 212 of one end 211 of the positive electrode terminal 21u when the first dielectric part 71u is not provided may occur.

[0083] Therefore, the semiconductor module 1 includes a second dielectric portion 72u formed in the through hole 213a and having a relative dielectric constant higher than that of the insulating sheet 61u. As a result, the second dielectric portion 72u can obtain the same effects as those of the first dielectric portion 71u with respect to the end portion 213c of the inner wall surface 213b as the first dielectric portion 71u has with respect to the corner portion 212 of one end 211 of the positive terminal 21u. For this reason, the semiconductor module 1 can shift the location where the electric field concentrates away from the end portion 213c corresponding to the triple point, relieve the electric field concentration, and improve the reliability of the positive terminal 21u and the negative terminal 31u.

[0084] Although detailed description is omitted, the positive terminal 21v, the insulating sheet 61v, the negative terminal 31v, the first dielectric portion 71v, and the second dielectric portion 72v have the same configuration as the positive terminal 21u, the insulating sheet 61u, the negative terminal 31u, the first dielectric portion 71u, and the second dielectric portion 72u. For this reason, the semiconductor module 1 can improve the reliability of the positive terminal 21v and the negative terminal 31v. Further, the positive terminal 21w, the insulating sheet 61w, the negative terminal 31w, the first dielectric portion 71w, and the second dielectric portion 72w have the same configuration as the positive terminal 21u, the insulating sheet 61u, the negative terminal 31u, the first dielectric portion 71u, and the second dielectric portion 72u. For this reason, the semiconductor module 1 can improve the reliability of the positive terminal 21w and the negative terminal 31w.

[0085] As described above, the semiconductor module 1 according to the present embodiment includes negative terminals 31u, 31v, 31w connected to the negative polarity side of DC power, and positive terminals 21u, 21v, 21w disposed above the negative terminals 31u, 31v, 31w with an exposed portion 314 including one end 311 of the negative terminals 31u, 31v, 31w exposed and connected to the positive polarity side of the DC power. An insulating sheet 61u is disposed between the negative terminals 31u, 31v, 31w and the positive terminals 21u, 21v, 21w with an exposed portion 612 exposed between one end 311 of the negative terminals 31u, 31v, 31w and one end 211 of the positive terminals 21u, 21v, 21w to insulate the negative terminals 31u, 31v, 31w and the positive terminals 21u, 21v, 21w. First dielectric portions 71u, 71v, 71w are formed to cover at least the corner portions 212 of one end 211 of the positive terminals 21u, 21w, 21w in contact with the insulating sheets 61u, 61v, 61w.

[0086] Thereby, the semiconductor module 1 can improve the insulation properties of the positive terminals 21u, 21v, 21w and the negative terminals 31u, 31v, 31w to which power is supplied.

[0087] 〔Second Embodiment〕 The semiconductor module according to the second embodiment of the present invention will be described with reference to FIGS. 6 to 8. First, the schematic configuration of the semiconductor module according to the present embodiment will be described with reference to FIGS. 6 to 8. In the present embodiment, a power conversion module capable of DC-AC conversion will be described as an example of the semiconductor module. In FIG. 6, for ease of understanding, illustrations of an inverter circuit, wiring patterns, etc. mounted on the laminated substrate provided in the semiconductor module according to the present embodiment are omitted. Further, in the description of the semiconductor module according to the present embodiment, components having the same operations and functions as those of the semiconductor module 1 according to the first embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0088] As shown in FIG. 6, the semiconductor module 2 according to the present embodiment includes a positive terminal 21u (an example of a first power supply terminal) connected to the first polarity side of the DC power. Further, the semiconductor module 2 is disposed above the positive terminal 21u in a state where an exposed portion 213 (an example of a part) including one end 211 of the positive terminal 21u is exposed, and includes a negative terminal 31u (an example of a second power supply terminal) connected to the second polarity side of the DC power. In the present embodiment, the first polarity side connected to the positive terminal 21u is the positive side of the DC power, and the second polarity side connected to the negative terminal 31u is the negative side of the DC power. The positive terminal 21u and the negative terminal 31u are provided at one end of the longitudinal side of the case 10 on one of both sides of the housing portion 11.

[0089] Further, the semiconductor module 2 has an insulating sheet 61u disposed between the positive terminal 21u and the negative terminal 31u in a state where an exposed portion 612 (an example of a part) is exposed between one end 211 of the positive terminal 21u and one end 311 of the negative terminal 31u, and insulating the positive terminal 21u and the negative terminal 31u. Furthermore, the semiconductor module 2 includes a first dielectric portion 71u formed to cover at least a corner portion 315 (not shown in FIG. 6, see FIG. 7) of one end 311 of the negative terminal 31u that contacts the insulating sheet 61u.

[0090] The semiconductor module 2 includes a positive terminal 21v (an example of a first power supply terminal) connected to the first polarity side of the DC power. Further, the semiconductor module 2 is disposed above the positive terminal 21v in a state where an exposed portion 314 (an example of a part) including one end 311 of the positive terminal 21v is exposed, and includes a negative terminal 31v (an example of a second power supply terminal) connected to the second polarity side of the DC power. In the present embodiment, the first polarity side connected to the positive terminal 21v is the positive side of the DC power, and the second polarity side connected to the negative terminal 31v is the negative side of the DC power. The positive terminal 21v and the negative terminal 31v are provided at one end of the longitudinal side of the case 10 on one of both sides of the housing portion 12.

[0091] Further, the semiconductor module 2 is disposed between the positive electrode terminal 21v and the negative electrode terminal 31v with an exposed portion 612 (an example of a part) exposed between one end 211 of the positive electrode terminal 21v and one end 311 of the negative electrode terminal 31v, and has an insulating sheet 61v that insulates the positive electrode terminal 21v and the negative electrode terminal 31v. Further, the semiconductor module 2 includes a first dielectric portion 71v formed to cover at least a corner portion (not shown) of one end 311 of the negative electrode terminal 31v that contacts the insulating sheet 61v. The corner portion of one end 311 of the negative electrode terminal 31v corresponds to the corner portion 315 of the negative electrode terminal 31u.

[0092] The semiconductor module 2 includes a positive electrode terminal 21w (an example of a first power supply terminal) of the W phase connected to the first polarity side of the DC power. Further, the semiconductor module 2 is disposed above the positive electrode terminal 21w with an exposed portion 213 (an example of a part) including one end 211 of the positive electrode terminal 21w exposed, and includes a negative electrode terminal 31w (an example of a second power supply terminal) connected to the second polarity side of the DC power. In the present embodiment, the first polarity side connected to the positive electrode terminal 21w is the positive electrode side of the DC power, and the second polarity side connected to the negative electrode terminal 31w is the negative electrode side of the DC power. The positive electrode terminal 21w and the negative electrode terminal 31w are provided at one end of the longitudinal side of the case 10 on one side of both sides of the housing portion 13.

[0093] Further, the semiconductor module 2 is disposed between the positive electrode terminal 21w and the negative electrode terminal 31w with an exposed portion 612 (an example of a part) exposed between one end 211 of the positive electrode terminal 21w and one end 311 of the negative electrode terminal 31w, and has an insulating sheet 61w that insulates the positive electrode terminal 21w and the negative electrode terminal 31w. Further, the semiconductor module 2 includes a first dielectric portion 71w formed to cover at least a corner portion (not shown) of one end 311 of the negative electrode terminal 31w that contacts the insulating sheet 61w. The corner portion of one end 311 of the negative electrode terminal 31w corresponds to the corner portion 315 of the negative electrode terminal 31u.

[0094] The laminated substrates 111, 121, 131 in the present embodiment have the same configuration as the laminated substrates 111, 121, 131 in the first embodiment, and thus the description thereof is omitted.

[0095] (Configuration of the first power supply terminal and the second power supply terminal) Next, with reference to FIG. 6, the configurations of the positive terminals 21u, 21v, 21w (an example of the first power supply terminal), the negative terminals 31u, 31v, 31w (an example of the second power supply terminal), and the insulating sheets 61u, 61v, 61w provided in the semiconductor module 2 according to the present embodiment will be described with reference to FIGS. 7 and 8. In FIG. 7, the illustration of the laminated substrate 111 is omitted.

[0096] In the positive terminal 21u in the present embodiment, in order to connect the protruding portions 214, 215 to the positive electrode side input terminal patterns 41, 42 (see FIG. 3) provided on the laminated substrate 111 from below the insulating sheet 61u, a part of the shape on the protruding portions 214, 215 side is different from the shape of the positive terminal 21u in the first embodiment. Also, in the negative terminal 31u in the present embodiment, in order to connect the protruding portions 312, 313 to the negative electrode side input terminal pattern 43 (see FIG. 3) provided on the laminated substrate 111 from the information of the insulating sheet 61u, a part of the shape on the protruding portions 312, 313 side is different from the shape of the positive terminal 21u in the first embodiment.

[0097] In the positive terminal 21v in the present embodiment, in order to connect the protruding portions 214, 215 to the positive electrode side input terminal patterns 41, 42 (not shown, see FIG. 3) provided on the laminated substrate 121 from below the insulating sheet 61v, a part of the shape on the protruding portions 214, 215 side is different from the shape of the positive terminal 21v in the first embodiment. Also, in the negative terminal 31v in the present embodiment, in order to connect the protruding portions 312, 313 to the negative electrode side input terminal pattern 43 (not shown, see FIG. 3) provided on the laminated substrate 121 from the information of the insulating sheet 61v, a part of the shape on the protruding portions 312, 313 side is different from the shape of the positive terminal 21v in the first embodiment.

[0098] In this embodiment, the positive electrode terminal 21w has a shape of a part on the side of the protruding portions 214 and 215 that is different from the shape of the positive electrode terminal 21w in the first embodiment in order to connect the protruding portions 214 and 215 to the positive electrode side input terminal patterns 41 and 42 (not shown, see FIG. 3) provided on the laminated substrate 131 from below the insulating sheet 61w. Further, in this embodiment, the negative electrode terminal 31w has a shape of a part on the side of the protruding portions 312 and 313 that is different from the shape of the positive electrode terminal 21w in the first embodiment in order to connect the protruding portions 312 and 313 to the negative electrode side input terminal pattern 43 (not shown, see FIG. 3) provided on the laminated substrate 131 from the information of the insulating sheet 61w.

[0099] In the semiconductor module 2, unlike the semiconductor module 1 according to the first embodiment, the negative electrode terminal 31u is disposed on the insulating sheet 61u. For this reason, in the semiconductor module 2, it is difficult to avoid a structure in which the exposed portion 314 of the negative electrode terminal 31u is disposed on the insulating sheet 61u in order to connect the negative electrode terminal 31u to the negative electrode side of the DC power. Therefore, as shown in FIG. 7, the corner portion 315 of one end 311 of the negative electrode terminal 31u becomes a triple point where the insulating sheet 61u and the first dielectric portion 71u, which are two insulators having different relative dielectric constants from the negative electrode terminal 31u which is a conductor, intersect at one point. Further, even when the first dielectric portion 71u is not formed, the corner portion 315 of one end 311 of the negative electrode terminal 31u becomes a triple point where the insulating sheet 61u and the air, which are two insulators having different relative dielectric constants from the negative electrode terminal 31u which is a conductor, intersect at one point.

[0100]

Table 2

[0101] Table 2 is a table showing an example of the simulation results of the electric field strength and the electric field relaxation rate when the first dielectric part 71u is formed covering the corner part 315 of the negative electrode terminal 31u. In Table 2, the peripheral environment of the semiconductor module 2 is air, the first dielectric part 71u has the shape shown in FIG. 7, a voltage of 1200 V is applied to the positive electrode terminal 21u, and a voltage of 0 V is applied to the negative electrode terminal 31u. The shape of the first dielectric part 71u in the simulation is a shape formed across the region exposed to the outside from Case 10 in the entire region of one end 311 including the corner part 315 and a part of the insulating sheet 61u. Since each item shown in Table 2 is the same as each item shown in Table 1, the description is omitted.

[0102] As shown in Table 2, when the first dielectric part 71u is formed covering the corner part 315 of the negative electrode terminal 31u corresponding to the triple point (that is, when the relative permittivity is from 10 to 35), compared with the case where the first dielectric part 71u is not formed, the electric field strength decreases and the electric field relaxation rate increases. Also, as shown in Table 2, when the relative permittivity of the first dielectric part 71u is from 10 to 30, as the relative permittivity increases from 10 to 30, the electric field strength monotonically decreases from 5.90 [MV / m] to 4.30 [MV / m] and the electric field relaxation rate monotonically increases from 49 [%] to 63 [%]. In Table 2, the minimum value of the relative permittivity of the first dielectric part 71u is 10, but considering the characteristic that the electric field strength decreases as the relative permittivity increases, it is preferable that the first dielectric part 71u has a relative permittivity higher than that of the insulating sheet 61u. Thereby, the semiconductor module 2 can achieve a decrease in the electric field strength and an increase in the electric field relaxation at the corner part 315 of the negative electrode terminal 31u.

[0103] Also, when the relative permittivity of the first dielectric portion 71u becomes 30 or more, the electric field strength saturates at 4.30 [MV / m], and the electric field relaxation rate saturates at 63 [%]. The relative permittivity of the first dielectric portion 71u can be adjusted, for example, by the forming material that forms the first dielectric portion 71u. Therefore, from the perspective of material selection for the first dielectric portion 71u, the relative permittivity of the first dielectric portion 71u may be 30 or less. Thus, the first dielectric portion 71u may have a relative permittivity higher than that of the insulating sheet 61u and also 30 [F / m] or less.

[0104] In this way, even in the structure where the negative electrode terminal 31u is disposed on the insulating sheet 61u, the same operations and effects as those of the structure where the positive electrode terminal 21u is disposed on the insulating sheet 61u can be obtained. That is, by including the first dielectric portion 71u, the semiconductor module 2 can obtain the same operations and effects as the semiconductor module 1 according to the first embodiment.

[0105] As shown in FIG. 8, the negative electrode terminal 31u has a through hole 314a formed by penetrating a part thereof so that the insulating sheet 61u is exposed, and the semiconductor module 2 includes a second dielectric portion 72u formed to cover at least an end portion 314c on the insulating sheet 61u side of an inner wall surface 314b forming the through hole 314a. The second dielectric portion 72u has a relative permittivity higher than that of the insulating sheet 61u. Two through holes 314a are formed at predetermined positions of an exposed portion 314 of the negative electrode terminal 31u (see FIG. 6). The through hole 314a is used to position the negative electrode terminal 31u in an injection mold when insert molding the case 10.

[0106] As shown in FIG. 8, the end portion 314c on the insulating sheet 61u side of the inner wall surface 314b forming the through hole 314a is a triple point where the insulating sheet 61u and the second dielectric portion 72u, which are two insulators with different relative dielectric constants from the negative electrode terminal 31u that is a conductor, intersect at one point. For this reason, when the second dielectric portion 72u is not formed in the through hole 314a, at the end portion 314c of the inner wall surface 314b, the negative electrode terminal 31u, the insulating sheet 61u, and the air in the through hole 314a intersect, so the same problems as those of the corner portion 315 of one end 311 of the negative electrode terminal 31u when the first dielectric portion 71u is not provided may occur.

[0107] However, the semiconductor module 2 includes a second dielectric portion 72u that is formed in the through hole 314a and has a relative dielectric constant higher than that of the insulating sheet 61u. Thereby, the second dielectric portion 72u can obtain the same actions and effects as those of the first dielectric portion 71u with respect to the corner portion 315 of one end 311 of the negative electrode terminal 31u with respect to the end portion 314c of the inner wall surface 314b. For this reason, the semiconductor module 2 can shift the location where the electric field concentrates from the end portion 314c corresponding to the triple point to relieve the electric field concentration, and improve the reliability of the positive electrode terminal 21u and the negative electrode terminal 31u.

[0108] Although detailed description is omitted, the positive electrode terminal 21v, the insulating sheet 61v, the negative electrode terminal 31v, the first dielectric portion 71v, and the second dielectric portion 72v have the same configuration as the positive electrode terminal 21u, the insulating sheet 61u, the negative electrode terminal 31u, the first dielectric portion 71u, and the second dielectric portion 72u. For this reason, the semiconductor module 2 can improve the reliability of the positive electrode terminal 21v and the negative electrode terminal 31v. Also, the positive electrode terminal 21w, the insulating sheet 61w, the negative electrode terminal 31w, the first dielectric portion 71w, and the second dielectric portion 72w have the same configuration as the positive electrode terminal 21u, the insulating sheet 61u, the negative electrode terminal 31u, the first dielectric portion 71u, and the second dielectric portion 72u. For this reason, the semiconductor module 2 can improve the reliability of the positive electrode terminal 21w and the negative electrode terminal 31w.

[0109] As described above, the semiconductor module 2 according to the present embodiment includes positive terminals 21u, 21v, 21w connected to the positive polarity side of DC power, negative terminals 31u, 31v, 31w disposed above the positive terminals 21u, 21v, 21w with an exposed portion 213 including one end 211 of the positive terminals 21u, 21v, 21w exposed and connected to the negative polarity side of the DC power, and an insulating sheet 61u disposed between the positive terminals 21u, 21v, 21w and the negative terminals 31u, 31v, 31w with an exposed portion 612 exposed between one end 211 of the positive terminals 21u, 21v, 21w and one end 311 of the negative terminals 31u, 31v, 31w for insulating the positive terminals 21u, 21v, 21w and the negative terminals 31u, 31v, 31w, and first dielectric portions 71u, 71v, 71w formed to cover at least corner portions 315 of one end 311 of the negative terminals 31u, 31v, 31w in contact with the insulating sheets 61u, 61v, 61w.

[0110] Thereby, the semiconductor module 2 can improve the insulation performance of the positive terminals 21u, 21v, 21w and the negative terminals 31u, 31v, 31w to which power is supplied.

[0111] The present invention is not limited to the above-described embodiments, and various modifications are possible. In the first and second embodiments described above, the transistors provided in the semiconductor elements are composed of wide bandgap semiconductor elements, but may be composed of IGBTs.

[0112] The technical scope of the present invention is not limited to the illustrated and described exemplary embodiments, but also includes all embodiments that bring about the same effects as those intended by the present invention. Furthermore, the technical scope of the present invention is not limited to the combinations of the features of the invention defined by the claims, but may be defined by any desired combination of the specific features among all the disclosed features.

Description of Reference Numerals

[0113] 1, 2 Semiconductor modules 10 Case 11, 12, 13 Storage portions Positive terminal 21u, 21v, 21w Negative terminal 31u, 31v, 31w Insulating substrate 40 Positive input terminal pattern 41, 42 Negative input terminal pattern 43 Positive part pattern 44, 45 Negative part pattern 46 Output part pattern 47 Output terminal pattern 49 Connection members 51, 52, 53, 54, 55, 56, 57, 58 Insulating sheet 61u, 61v, 61w First dielectric part 71u, 71v, 71w Second dielectric part 72u, 72v, 72w Output terminals 81u, 81v, 81w Stacked substrates 111, 121, 131 Inverter circuits 112, 122, 132 One end 211, 311, 611 Corner part 212, 315 Exposed part 213, 314, 612 Through holes 213a, 314a Inner wall surface 213b, 314b End part 213c, 314c Protruding parts 214, 215, 312, 313

Claims

1. a first power supply terminal connected to the first polarity side of the DC power; a second power supply terminal disposed above the first power supply terminal with a part including one end of the first power supply terminal exposed and connected to the second polarity side of the DC power; an insulating sheet disposed between the first power supply terminal and the second power supply terminal with a part exposed between one end of the first power supply terminal and one end of the second power supply terminal, for insulating the first power supply terminal and the second power supply terminal; a first dielectric part formed to cover at least a corner of one end of the second power supply terminal in contact with the insulating sheet; a second dielectric part comprising; the second power supply terminal has a through hole formed by penetrating a part so that the insulating sheet is exposed; the second dielectric part is formed to cover at least an end on the insulating sheet side of an inner wall surface forming the through hole a semiconductor module.

2. the first dielectric part has a relative permittivity higher than that of the insulating sheet the semiconductor module according to claim 1.

3. the second dielectric part has a relative permittivity higher than that of the insulating sheet the semiconductor module according to claim 1 or 2.

4. either the first polarity side is the negative pole side of the DC power and the second polarity side is the positive pole side of the DC power, or the first polarity side is the positive pole side of the DC power and the second polarity side is the negative pole side of the DC power the semiconductor module according to any one of claims 1 to 3.

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