Circuit board

Abstract

[Problem] The purpose of the present disclosure is to improve a heat-dissipating characteristic of a circuit board having a thin-film capacitor. [Solution] A circuit board 1 is provided with a board 10 comprising a ceramics plate 11 as a base material, and a thin-film capacitor 20 mounted on the board 10 with a mounting surface 20a facing a conductor layer 12 of the board 10. The thin-film capacitor 20 comprises a dielectric layer 21, and capacitor electrodes 22, 23 formed on front and back surfaces of the dielectric layer 21. The capacitor electrode 22 is connected to a wiring pattern 12a included in the conductor layer 12. The capacitor electrode 23 or a terminal electrode connected thereto is exposed on an upper surface 20b opposite the mounting surface 20a.

Description

Technical Field

[0001] The present invention relates to a circuit board, and more particularly to a circuit board having a configuration in which a thin-film capacitor is mounted on a substrate made of a ceramic plate as a base material.

Background Art

[0002] Patent Document 1 discloses a circuit board having a structure in which a chip capacitor is mounted on a DBC (Direct Bonded Cupper) substrate. Since the DBC substrate is made of a ceramic plate, it is possible to obtain extremely high heat dissipation compared to a general printed circuit board using a resin material.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, since a general chip capacitor is used in the circuit board described in Patent Document 1, the heat dissipation characteristics of the heat generated by the chip capacitor are not sufficient.

[0005] Therefore, an object of the present invention is to provide a circuit board capable of obtaining higher heat dissipation characteristics.

Means for Solving the Problems

[0006] The circuit board according to the present invention includes a ceramic board, a first conductor layer formed on one surface of the ceramic board, a second conductor layer formed on the other surface of the ceramic board, a thin film capacitor mounted on the board such that the mounting surface faces the first conductor layer, the first conductor layer includes a first wiring pattern, the thin film capacitor includes a dielectric layer, a first capacitor electrode formed on one surface of the dielectric layer, and a second capacitor electrode formed on the other surface of the dielectric layer, the first capacitor electrode is connected to the first wiring pattern, and the second capacitor electrode or a terminal electrode connected thereto is exposed on the upper surface opposite to the mounting surface.

[0007] According to the present invention, since the thin film capacitor is mounted on a board made of a ceramic board and the second capacitor electrode of the thin film capacitor or a terminal electrode connected thereto is exposed on the upper surface, it is possible to obtain high heat dissipation characteristics.

[0008] In the present invention, the exposed area of the second capacitor electrode or the terminal electrode may be larger than the area of the first capacitor electrode. According to this, the heat dissipation characteristics through the second capacitor electrode or the terminal electrode are further improved.

[0009] In the present invention, the first conductor layer may further include a second wiring pattern, and the second capacitor electrode may be connected to the second wiring pattern. According to this, it is possible to surface-mount the thin film capacitor on the board.

[0010] In the present invention, the first conductor layer may further include a second wiring pattern, the thin film capacitor may further include a third capacitor electrode formed on one surface of the dielectric layer, and the third capacitor electrode may be connected to the second wiring pattern. According to this, since a configuration in which two capacitors are connected in series can be obtained, the voltage applied to the dielectric layer is dispersed.

[0011] The circuit board according to the present invention further includes a semiconductor element mounted on one surface of the board. The second capacitor electrode or the terminal electrode of the thin film capacitor and the semiconductor element may be connected to each other via bonding wires. According to this, it becomes possible to directly connect the semiconductor element and the thin film capacitor. In this case, a plurality of bonding wires may be provided. According to this, the connection reliability is improved.

Effect of the Invention

[0012] Thus, according to the present invention, it becomes possible to provide a circuit board capable of obtaining higher heat dissipation characteristics.

Brief Description of the Drawings

[0013]

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Embodiments for Carrying Out the Invention

[0014] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0015] <The First Embodiment> FIG. 1 is a schematic cross-sectional view for explaining the configuration of the circuit board 1 according to the first embodiment of the present invention.

[0016] As shown in FIG. 1, the circuit board 1 according to the first embodiment includes a substrate 10 and a thin-film capacitor 20 mounted on the substrate 10. The substrate 10 has a ceramic plate 11 as a base material, a conductor layer 12 formed on one surface 11a of the ceramic plate 11, and a conductor layer 13 formed on the other surface 11b of the ceramic plate 11. As the material of the ceramic plate 11, metal oxides or metal nitrides such as Al2O3, AlN, and Si3N4 can be used. As the materials of the conductor layers 12 and 13, good conductors such as Cu and Al can be used. When Cu is used as the material of the conductor layers 12 and 13, the substrate 10 constitutes a DBC (Direct Bonded Cupper) substrate. When Al is used as the material of the conductor layers 12 and 13, the substrate 10 constitutes a DBA (Direct Bonded Aluminum) substrate.

[0017] FIG. 2 is a schematic perspective view for explaining the structure of the substrate 10. As shown in FIG. 2, while a plurality of wiring patterns are provided in the conductor layer 12, the conductor layer 13 is a solid pattern. The conductor layer 13 is fixed to a metal heat sink or the like (not shown). As shown in FIG. 1, the conductor layer 12 includes wiring patterns 12a and 12b.

[0018] FIG. 3 is a schematic cross-sectional view for explaining the configuration of the thin-film capacitor 20.

[0019] As shown in FIG. 3, the thin-film capacitor 20 has a dielectric layer 21, a capacitor electrode 22 formed on one surface 21a of the dielectric layer 21, a capacitor electrode 23 formed on the other surface 21b of the dielectric layer 21, and a passivation layer 24 provided so as to embed the dielectric layer 21 and the capacitor electrode 22. The capacitor electrodes 22 and 23 overlap each other with the dielectric layer 21 interposed therebetween, whereby a predetermined capacitance is obtained.

[0020] The dielectric layer 21 is made of, for example, a perovskite-based dielectric material. Examples of the perovskite-based dielectric material include BaTiO3 (barium titanate), (Ba 1-X SrX )TiO3 (barium strontium titanate), (Ba 1-X Ca X )TiO3, PbTiO3, Pb(Zr X Ti 1-X )O3, (Sr 1-X Ca X )(Ti 1-Y Zr Y )O3, Ba(Mg 1 / 3 Ta 2 / 3 )O3 and other ferroelectric or paraelectric materials with a perovskite structure, such as composite perovskite relaxor ferroelectric materials represented by Pb(Mg 1 / 3 Nb 2 / 3 )O3, bismuth layered compounds represented by Bi4Ti3O 12 , SrBi2Ta2O9, etc., tungsten bronze ferroelectric materials represented by (Sr 1-X Ba X )Nb2O6, PbNb2O6, etc. Here, in the perovskite structure, perovskite relaxor ferroelectric material, bismuth layered compound, and tungsten bronze ferroelectric material, the ratio of the A site to the B site is usually an integer ratio, but for property improvement, it may be intentionally shifted from the integer ratio. In addition, for controlling the properties of the dielectric layer 21, an additive substance may be appropriately contained as a sub-component in the dielectric layer 21. The relative permittivity (ε r ) of the dielectric layer 21 is, for example, 10 or more. The larger the relative permittivity of the dielectric layer 21, the more preferable, and its upper limit value is not particularly limited. Furthermore, the higher the breakdown voltage of the dielectric layer 21, the more preferable, and its upper limit is not particularly limited. The thickness of the dielectric layer 21 is, for example, about 10 nm to 6000 nm.

[0021] The capacitor electrodes 22 and 23 are metal foils made of a high melting point metal such as nickel (Ni). Among these, the capacitor electrode 23 also functions as a support for ensuring the mechanical strength of the thin film capacitor 20. The surface of the capacitor electrode 23 opposite to the surface in contact with the dielectric layer 21 constitutes the upper surface 20b of the thin film capacitor 20. In the manufacturing process of the thin film capacitor 20, the dielectric layer 21 and the capacitor electrode 22 are laminated in this order on the surface of the capacitor electrode 23 which is a support. For this reason, the area of the dielectric layer 21 is smaller than the area of the capacitor electrode 23, and the area of the capacitor electrode 22 is smaller than the area of the dielectric layer 21. The surface of the passivation layer 24 constitutes the mounting surface 20a of the thin film capacitor 20. The passivation layer 24 is made of resin or the like.

[0022] Terminal electrodes 25 and 26 are provided on the mounting surface 20a of the thin film capacitor 20. The terminal electrode 25 is connected to the capacitor electrode 22 via a via conductor 25a that penetrates the passivation layer 24. Further, an opening 27 is provided in the dielectric layer 21 and the capacitor electrode 22. And the terminal electrode 26 is connected to the capacitor electrode 23 via a via conductor 26a that penetrates the passivation layer 24 so as to pass through the opening 27. Thereby, as shown in FIG. 4, a configuration in which one capacitor is connected between the terminal electrodes 25 and 26 is obtained. As the material of the terminal electrodes 25 and 26 and the via conductors 25a and 26a, a good conductor such as Cu can be used. The surfaces of the terminal electrodes 25 and 26 may be covered with a surface treatment layer such as an ENEPIG film.

[0023] The thin film capacitor 20 having such a configuration is mounted on the substrate 10 such that the mounting surface 20a faces the conductor layer 12 as shown in FIG. 1. Thereby, the terminal electrode 25 of the thin film capacitor 20 is connected to the wiring pattern 12a, and the terminal electrode 26 of the thin film capacitor 20 is connected to the wiring pattern 12b. The connection between the terminal electrodes 25 and 26 and the wiring patterns 12a and 12b is performed via the solder 28.

[0024] With such a configuration, the heat generated by driving the thin-film capacitor 20 under a high voltage is dissipated not only to the substrate 10 side through the terminal electrodes 25 and 26, but also from the upper surface 20b which is the exposed surface of the capacitor electrode 23. Moreover, since the entire back surface and side surfaces of the capacitor electrode 23 are exposed and the exposed area is larger than the area of the capacitor electrode 22, the heat dissipation characteristics through the capacitor electrode 23 become extremely high. As a result, it is possible to obtain high heat dissipation as compared with the case where a chip capacitor such as an MLCC (Multilayered Ceramic Capacitors) is used instead of the thin-film capacitor 20.

[0025] <Second Embodiment> FIG. 5 is a schematic cross-sectional view for explaining the configuration of the circuit board 2 according to the second embodiment of the present invention.

[0026] As shown in FIG. 5, the circuit board 2 according to the second embodiment is different from the circuit board 1 according to the first embodiment in that a thin-film capacitor 30 is mounted on the substrate 10 instead of the thin-film capacitor 20. Since the other basic configuration is the same as that of the circuit board 1 according to the first embodiment, the same elements are denoted by the same reference numerals and redundant explanations are omitted.

[0027] FIG. 6 is a schematic cross-sectional view for explaining the configuration of the thin-film capacitor 30.

[0028] As shown in FIG. 6, the thin-film capacitor 30 includes dielectric layers 31A and 31B, a capacitor electrode 32 positioned between one surface 31Aa of the dielectric layer 31A and one surface 31Ba of the dielectric layer 31B, a capacitor electrode 33A formed on the other surface 31Ab of the dielectric layer 31A, a capacitor electrode 33B formed on the other surface 31Bb of the dielectric layer 31B, and a passivation layer 34 provided so as to embed the dielectric layers 31A and 31B and the capacitor electrodes 32 and 33B. The capacitor electrodes 32, 33A, and 33B overlap each other via the dielectric layers 31A and 31B, thereby obtaining a predetermined capacitance. As the material of the dielectric layers 31A and 31B, the same material as the above-described dielectric layer 21 can be used. As the material of the capacitor electrodes 32, 33A, and 33B, the same material as the above-described capacitor electrodes 22 and 23 can be used.

[0029] The capacitor electrode 33A also functions as a support for ensuring the mechanical strength of the thin-film capacitor 20. The surface of the capacitor electrode 33A opposite to the surface in contact with the dielectric layer 31A constitutes the upper surface 30b of the thin-film capacitor 30. In the manufacturing process of the thin-film capacitor 30, the dielectric layer 31A, the capacitor electrode 32, the dielectric layer 31B, and the capacitor electrode 33B are laminated in this order on the surface of the capacitor electrode 33A which is a support. For this reason, the area of the dielectric layer 31A is smaller than the area of the capacitor electrode 33A, the area of the capacitor electrode 32 is smaller than the area of the dielectric layer 31A, the area of the dielectric layer 31B is smaller than the area of the capacitor electrode 32, and the area of the capacitor electrode 33B is smaller than the area of the dielectric layer 31B. The surface of the passivation layer 34 constitutes the mounting surface 30a of the thin-film capacitor 30.

[0030] The dielectric layer 31B and the capacitor electrode 33B are provided with an opening 37A. Further, the dielectric layer 31A, the capacitor electrode 32, the dielectric layer 31B, and the capacitor electrode 33B are provided with an opening 37B. Terminal electrodes 35 and 36 are provided on the mounting surface 30a of the thin film capacitor 30. The terminal electrode 35 is connected to the capacitor electrode 32 via a via conductor 35a that penetrates the passivation layer 34 so as to pass through the opening 37A. Also, the terminal electrode 36 is connected to the capacitor electrodes 33A and 33B via a via conductor 36a that penetrates the passivation layer 34 so as to pass through the opening 37B. Thereby, as shown in FIG. 7, a configuration in which two capacitors are connected in parallel between the terminal electrodes 35 and 36 is obtained. The surfaces of the terminal electrodes 35 and 36 may be covered with a surface treatment layer such as an ENEPIG film.

[0031] As shown in FIG. 5, the thin film capacitor 30 having such a configuration is mounted on the substrate 10 such that the mounting surface 30a faces the conductor layer 12. Thereby, the terminal electrode 35 of the thin film capacitor 30 is connected to the wiring pattern 12a, and the terminal electrode 36 of the thin film capacitor 30 is connected to the wiring pattern 12b. The connection between the terminal electrodes 35 and 36 and the wiring patterns 12a and 12b is performed via solder 38.

[0032] Thus, since the circuit board 2 according to the present embodiment uses the thin film capacitor 30 having a configuration in which two capacitors are connected in parallel, it is possible to obtain a larger capacitance than the circuit board 1 according to the first embodiment. The number of capacitors connected in parallel is not particularly limited, and may be three or more.

[0033] <The Third Embodiment> FIG. 8 is a schematic cross-sectional view for explaining the configuration of a circuit board 3 according to the third embodiment of the present invention.

[0034] As shown in FIG. 8, the circuit board 3 according to the third embodiment is different from the circuit board 1 according to the first embodiment in that a thin-film capacitor 40 is mounted on the substrate 10 instead of the thin-film capacitor 20. Since the other basic configuration is the same as that of the circuit board 1 according to the first embodiment, the same elements are denoted by the same reference numerals, and redundant descriptions are omitted.

[0035] FIG. 9 is a schematic cross-sectional view for explaining the configuration of the thin-film capacitor 40.

[0036] As shown in FIG. 9, the thin-film capacitor 40 includes a dielectric layer 41, capacitor electrodes 42A and 42B formed on one surface 41a of the dielectric layer 41, a capacitor electrode 43 formed on the other surface 41b of the dielectric layer 41, and a passivation layer 44 provided so as to embed the dielectric layer 41 and the capacitor electrodes 42A and 42B. The capacitor electrodes 42A and 42B are formed at different planar positions on one surface 41a of the dielectric layer 41, and both overlap the capacitor electrode 43 with the dielectric layer 41 interposed therebetween. As the material of the dielectric layer 41, the same material as the dielectric layer 21 described above can be used. As the materials of the capacitor electrodes 42A, 42B, and 43, the same materials as the capacitor electrodes 22 and 23 described above can be used.

[0037] The capacitor electrode 43 also functions as a support for ensuring the mechanical strength of the thin-film capacitor 40. The surface of the capacitor electrode 43 opposite to the surface in contact with the dielectric layer 41 constitutes the upper surface 40b of the thin-film capacitor 40. In the manufacturing process of the thin-film capacitor 40, the dielectric layer 41 and the capacitor electrodes 42A and 42B are laminated in this order on the surface of the capacitor electrode 43 which is the support. The surface of the passivation layer 44 constitutes the mounting surface 40a of the thin-film capacitor 40.

[0038] On the mounting surface 40a of the thin film capacitor 40, terminal electrodes 45 and 46 are provided. The terminal electrode 45 is connected to the capacitor electrode 42A via a via conductor 45a that penetrates the passivation layer 44. Also, the terminal electrode 46 is connected to the capacitor electrode 42B via a via conductor 46a that penetrates the passivation layer 44. As a result, as shown in FIG. 10, a configuration in which two capacitors are connected in series between the terminal electrodes 45 and 46 is obtained. The surfaces of the terminal electrodes 45 and 46 may be covered with a surface treatment layer such as an ENEPIG film.

[0039] As shown in FIG. 8, the thin film capacitor 40 having such a configuration is mounted on the substrate 10 such that the mounting surface 40a faces the conductor layer 12. Thereby, the terminal electrode 45 of the thin film capacitor 40 is connected to the wiring pattern 12a, and the terminal electrode 46 of the thin film capacitor 40 is connected to the wiring pattern 12b. The connection between the terminal electrodes 45 and 46 and the wiring patterns 12a and 12b is performed via solder 48.

[0040] Thus, since the circuit board 3 according to the present embodiment uses the thin film capacitor 40 having a configuration in which two capacitors are connected in series, the voltage applied to the dielectric layer 41 is dispersed compared to the circuit board 1 according to the first embodiment. For this reason, it is possible to obtain a higher withstand voltage compared to the circuit board 1 according to the first embodiment. The number of capacitors connected in series is not particularly limited, and may be three or more.

[0041] <Fourth Embodiment> FIG. 11 is a schematic cross-sectional view for explaining the configuration of a circuit board 4A according to the fourth embodiment of the present invention.

[0042] As shown in FIG. 11, the circuit board 4A according to the fourth embodiment is different from the circuit board 1 according to the first embodiment in that a thin-film capacitor 50A is mounted on the substrate 10 instead of the thin-film capacitor 20, and a semiconductor element 60 is mounted on the substrate 10. Since the other basic configurations are the same as those of the circuit board 1 according to the first embodiment, the same elements are denoted by the same reference numerals, and redundant descriptions are omitted. The conductor layer 12 of the substrate 10 includes a wiring pattern 12c, and the semiconductor element 60 is mounted on the wiring pattern 12c via solder 61. The type of the semiconductor element 60 is not particularly limited, and a power device of a type in which current flows vertically with respect to a semiconductor substrate, such as an IGBT, can be used. As the material of the semiconductor substrate used for the semiconductor element 60, in addition to Si, SiC, GaN, etc. can be used.

[0043] FIG. 12 is a schematic cross-sectional view for explaining the configuration of the thin-film capacitor 50A.

[0044] As shown in FIG. 12, the thin-film capacitor 50A has a dielectric layer 51, a capacitor electrode 52 formed on one surface 51a of the dielectric layer 51, a capacitor electrode 53 formed on the other surface 51b of the dielectric layer 51, and a passivation layer 54 provided so as to embed the dielectric layer 51 and the capacitor electrode 52. The capacitor electrodes 52 and 53 overlap each other with the dielectric layer 51 therebetween, whereby a predetermined capacitance is obtained. As the materials of the capacitor electrodes 52 and 53, the same materials as those of the capacitor electrodes 22 and 23 described above may be used, or Cu may be used as the material of the capacitor electrode 52 and Ni may be used as the material of the capacitor electrode 53.

[0045] The capacitor electrode 53 also functions as a support for ensuring the mechanical strength of the thin film capacitor 50A. The surface of the capacitor electrode 53 opposite to the surface in contact with the dielectric layer 51 constitutes the upper surface 50b of the thin film capacitor 50A. In the manufacturing process of the thin film capacitor 50A, the dielectric layer 51 and the capacitor electrode 52 are laminated in this order on the surface of the capacitor electrode 53 which is a support. For this reason, the area of the dielectric layer 51 is smaller than the area of the capacitor electrode 53, and the area of the capacitor electrode 52 is smaller than the area of the dielectric layer 51. The surface of the passivation layer 54 constitutes the mounting surface 50a of the thin film capacitor 50A.

[0046] A terminal electrode 55 is provided on the mounting surface 50a of the thin film capacitor 50A. The terminal electrode 55 is connected to the capacitor electrode 52 via a via conductor 55a that penetrates the passivation layer 54. Thereby, a configuration in which one capacitor is connected between the terminal electrode 55 and the capacitor electrode 53 is obtained. The surface of the terminal electrode 55 may be covered with a surface treatment layer such as an ENEPIG film.

[0047] The thin film capacitor 50A having such a configuration is mounted on the substrate 10 such that the mounting surface 50a faces the conductor layer 12 as shown in FIG. 11. Thereby, the terminal electrode 55 of the thin film capacitor 50A is connected to the wiring pattern 12a via the solder 58. On the other hand, the capacitor electrode 53 that constitutes the upper surface 50b is connected to a bonding pad 62 provided on the upper surface of the semiconductor element 60 via a bonding wire 63 made of Al or the like. Thereby, a configuration in which the thin film capacitor 50A is connected between the wiring pattern 12a and the semiconductor element 60 is obtained.

[0048] According to this embodiment, since the capacitor electrode 53 that constitutes the upper surface 50b is used as a bonding pad, it is possible to directly connect the thin-film capacitor 50A and the semiconductor element 60 without passing through the substrate 10. Moreover, the area of the capacitor electrode 53 is larger than that of the capacitor electrode 52, and thus the upper surface 50b of the thin-film capacitor 50A has a sufficient area, making the bonding operation easy. Also, since there is no need to provide an opening in the dielectric layer 51, it is possible to obtain a larger capacitance. Further, since the number of terminal electrodes 55 provided on the mounting surface 50a side is one, a sufficient area for the terminal electrode 55 can be ensured. Thereby, the heat dissipation property from the thin-film capacitor 50A to the substrate 10 through the terminal electrode 55 is also enhanced. In this embodiment, the film thickness of the capacitor electrode 53 may be designed to be thicker than the capacitor electrodes 23, 33A, and 43 in the first to third embodiments. According to this, since the capacitor electrode 53 functions as a heat sink, the heat dissipation property is improved, and the damage applied to the thin-film capacitor 50A during wire bonding can be alleviated.

[0049] FIG. 13 is a schematic cross-sectional view for explaining the configuration of a circuit board 4B according to a modification of the fourth embodiment.

[0050] As shown in FIG. 13, the circuit board 4B according to the modification is different from the circuit board 4A according to the fourth embodiment in that a thin-film capacitor 50B is mounted on the substrate 10 instead of the thin-film capacitor 50A. Since the other basic configurations are the same as those of the circuit board 4A according to the fourth embodiment, the same elements are denoted by the same reference numerals, and duplicate descriptions are omitted.

[0051] FIG. 14 is a schematic cross-sectional view for explaining the configuration of the thin-film capacitor 50B.

[0052] As shown in FIG. 14, the thin-film capacitor 50B is different from the thin-film capacitor 50A in that the surface of the capacitor electrode 53 is covered with a metal film 53B made of Sn or the like. Since the other basic configurations are the same as those of the thin-film capacitor 50A, the same elements are denoted by the same reference numerals, and duplicate explanations are omitted. The metal film 53B serves to reduce the surface roughness of the upper surface 50b of the thin-film capacitor 50B and to enhance the adhesion of the bonding wire 63. The surface roughness Ra of the metal film 53B may be less than 100 nm. Thus, it is not essential to expose the surface of the capacitor electrode 53 as it is, and it may be covered with the metal film 53B. In this case, the metal film 53B may be regarded as a part of the capacitor electrode 53. Incidentally, instead of covering the surface of the capacitor electrode 53 with the metal film 53B, the surface roughness of the upper surface 50b may be reduced by polishing the surface of the capacitor electrode 53.

[0053] <Fifth Embodiment> FIG. 15 is a schematic cross-sectional view for explaining the configuration of the circuit board 5 according to the fifth embodiment of the present invention.

[0054] As shown in FIG. 15, the circuit board 5 according to the fifth embodiment is different from the circuit board 4A according to the fourth embodiment in that a plurality of bonding wires 63 are provided in parallel. Since the other basic configurations are the same as those of the circuit board 4A according to the fourth embodiment, the same elements are denoted by the same reference numerals, and duplicate explanations are omitted.

[0055] According to the present embodiment, since the thin-film capacitor 50A and the semiconductor element 60 are connected by a plurality of bonding wires 63, the connection reliability is improved and the heat dissipation through the bonding wires 63 is also enhanced.

[0056] <Sixth Embodiment> FIG. 16 is a schematic cross-sectional view for explaining the configuration of the circuit board 6 according to the sixth embodiment of the present invention.

[0057] As shown in FIG. 16, the circuit board 6 according to the sixth embodiment is different from the circuit board 5 according to the fifth embodiment in that the thin-film capacitor 50A is mounted upside down. Since the other basic configurations are the same as those of the circuit board 5 according to the fifth embodiment, the same elements are denoted by the same reference numerals, and redundant descriptions are omitted.

[0058] In the present embodiment, the surface of the capacitor electrode 53 constitutes the mounting surface 50a, and the surface of the passivation layer 54 constitutes the upper surface 50b. The capacitor electrode 53 is connected to the wiring pattern 12a via the solder 58, and the terminal electrode 55 is connected to the semiconductor element 60 via a plurality of bonding wires 63. Thus, the thin-film capacitor 50A may be mounted on the substrate 10 with its front and back reversed.

[0059] <Seventh Embodiment> FIG. 17 is a schematic cross-sectional view for explaining the configuration of a circuit board 7 according to the seventh embodiment of the present invention.

[0060] As shown in FIG. 17, the circuit board 7 according to the seventh embodiment is different from the circuit board 6 according to the sixth embodiment in that a thin-film capacitor 70 is mounted on the substrate 10 instead of the thin-film capacitor 50A. Since the other basic configurations are the same as those of the circuit board 6 according to the sixth embodiment, the same elements are denoted by the same reference numerals, and redundant descriptions are omitted.

[0061] FIG. 18 is a schematic cross-sectional view for explaining the configuration of the thin-film capacitor 70.

[0062] As shown in FIG. 18, the thin film capacitor 70 includes a dielectric layer 71, a capacitor electrode 72 formed on one surface 71a of the dielectric layer 71, a capacitor electrode 73 formed on the other surface 71b of the dielectric layer 71, a passivation layer 74 provided so as to embed the dielectric layer 71, and a terminal electrode 75 provided on a surface of the capacitor electrode 73 opposite to the surface in contact with the dielectric layer 71. The capacitor electrodes 72 and 73 overlap each other via the dielectric layer 71, thereby obtaining a predetermined capacitance. As the materials of the capacitor electrodes 72 and 73, the same materials as the capacitor electrodes 53 and 52 described above can be used respectively.

[0063] The capacitor electrode 72 also functions as a support for ensuring the mechanical strength of the thin film capacitor 70. The surface of the capacitor electrode 72 opposite to the surface in contact with the dielectric layer 71 constitutes the mounting surface 70a of the thin film capacitor 70. On the other hand, the surface of the terminal electrode 75 constitutes the upper surface 70b of the thin film capacitor 70. The surface of the terminal electrode 75 may be covered with a surface treatment layer such as an ENEPIG film.

[0064] The thin film capacitor 70 having such a configuration is mounted on the substrate 10 as shown in FIG. 17 such that the mounting surface 70a faces the conductor layer 12. Thereby, the capacitor electrode 72 of the thin film capacitor 70 is connected to the wiring pattern 12a via the solder 78. On the other hand, the terminal electrode 75 constituting the upper surface 70b is connected to the bonding pad 62 provided on the upper surface of the semiconductor element 60 via a plurality of bonding wires 63. Thereby, a configuration in which the thin film capacitor 70 is connected between the wiring pattern 12a and the semiconductor element 60 is obtained.

[0065] According to the present embodiment, since substantially the entire surface of the capacitor electrode 73 is in contact with the terminal electrode 75 and the contact area between the two is very large, the heat dissipation characteristics via the terminal electrode 75 are enhanced. In addition, in the case of the present embodiment, since substantially the entire surface of the capacitor electrode 73 is in contact with the terminal electrode 75, the terminal electrode 75 may be regarded as a part of the capacitor electrode.

[0066] Although the preferred embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the present invention, and it goes without saying that those are also included in the scope of the present invention.

Explanation of Reference Numerals

[0067] 1 to 3, 4A, 4B, 5 to 7 Circuit boards 10 Substrate 11 Ceramic plate 11a, 11b Surfaces of the ceramic plate 12, 13 Conductor layers 12a to 12c Wiring patterns 20, 30, 40, 50A, 50B, 70 Thin film capacitors 20a, 30a, 40a, 50a, 70a Mounting surfaces 20b, 30b, 40b, 50b, 70b Upper surfaces 21, 31A, 31B, 41, 51, 71 Dielectric layers 21a, 21b, 31Aa, 31Ab, 31Ba, 31Bb, 41a, 41b, 51a, 51b, 71a, 71b Surfaces of the dielectric layers 22, 23, 32, 33A, 33B, 42A, 42B, 43, 52, 53, 72, 73 Capacitor electrodes 24, 34, 44, 54, 74 Passivation layers 25, 26, 35, 36, 45, 46, 55, 75 Terminal electrodes 25a, 26a, 35a, 36a, 45a, 46a, 55a Via conductors 27, 37A, 37B Openings 28, 38, 48, 58, 61, 78 Solder 53B Metal film 60 Semiconductor element 62 Bonding pad 63 Bonding wire

Claims

1. A substrate having a ceramic plate, a first conductor layer formed on one surface of the ceramic plate, and a second conductor layer formed on the other surface of the ceramic plate, A thin film capacitor mounted on the substrate such that the mounting surface faces the first conductor layer, The first conductor layer includes first and second wiring patterns, The second conductor layer includes at least the first wiring pattern, the second wiring pattern, and a solid pattern overlapping the thin film capacitor, The thin film capacitor includes a dielectric layer having one surface facing the substrate and the other surface located on the opposite side of the one surface, a first capacitor electrode formed on the one surface of the dielectric layer, a second capacitor electrode formed on the other surface of the dielectric layer, a first terminal electrode connected to the first capacitor electrode, and a second terminal electrode connected to the second capacitor electrode through an opening provided in the dielectric layer, The first terminal electrode is connected to the first wiring pattern, The second terminal electrode is connected to the second wiring pattern, A circuit board, wherein the second capacitor electrode is exposed on the upper surface opposite to the mounting surface.

2. The circuit board according to claim 1, wherein an exposed area of the second capacitor electrode is larger than an area of the first capacitor electrode.

3. Further comprising a semiconductor element mounted on the one surface of the substrate, The circuit board according to claim 1 or 2, wherein the second capacitor electrode of the thin film capacitor and the semiconductor element are connected to each other via a bonding wire.

4. The circuit board according to claim 3, wherein a plurality of the bonding wires are provided.

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