High-speed sampler

Abstract

The regeneration circuit includes a first inverting circuit and a second inverting circuit. The regeneration circuit also includes a first transistor coupled to an input of the second inverting circuit, a second transistor coupled to an input of the first inverting circuit, a third transistor, and a fourth transistor. A gate of the first transistor and a gate of the fourth transistor are coupled to the first input, and a gate of the second transistor and a gate of the fourth transistor are coupled to the second input. The regeneration circuit further includes a first switch and a second switch. The first switch and the third transistor are coupled in series between the first rail and the first transistor, and the second switch and the fourth transistor are coupled in series between the first rail and the second transistor.

Description

Technical Field

[0001] Cross - Reference to Related Applications

[0001] This application claims the priority and benefit of non - provisional patent application Ser. No. 17 / 805,211, filed with the United States Patent and Trademark Office on June 2, 2022, and the entire content thereof is incorporated herein by reference in its entirety as if fully set forth below and for all applicable purposes.

Background Art

[0002] Field

[0002] Aspects of the present disclosure generally relate to samplers, and more particularly to high - speed samplers.

[0003] Background

[0003] High - speed samplers can be used in high - speed serializer / deserializer (SerDes) applications. For example, a sampler can be used in a high - speed SerDes to sample a high - speed signal received by a receiver. The sampler can include a regenerative circuit that provides regenerative feedback to the sampler to quickly capture data bits from the received signal. It is desirable to increase the speed of the sampler to sample signals at higher data rates and / or increase the sensitivity of the sampler to capture data bits from small signals.

Summary of the Invention

[0004]

[0004] Below, a simplified summary of one or more implementations is presented to provide a basic understanding of such implementations. This "Summary of the Invention" is not an overview of the broad scope of all contemplated implementations, nor is it intended to identify key or critical elements of all implementations or to delineate the scope of all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as an introduction to the "Detailed Description of the Invention" presented later.

[0005]

[0005] The first aspect relates to a playback circuit. The playback circuit includes a first inverter circuit having an input and an output, and a second inverter circuit having an input and an output. The playback circuit also includes a first transistor coupled to the input of the second inverter circuit, wherein the gate of the first transistor is coupled to the first input, and a second transistor coupled to the input of the first inverter circuit, wherein the gate of the second transistor is coupled to the second input. The playback circuit further includes a third transistor whose gate is coupled to the first input, and a fourth transistor whose gate is coupled to the second input. The playback circuit further includes a first switch, wherein the first switch and the third transistor are serially coupled between the first rail and the first transistor, and a second switch, wherein the second switch and the fourth transistor are serially coupled between the first rail and the second transistor.

[0006]

[0006] The second aspect relates to a playback circuit. The playback circuit includes a first inverter circuit having an input and an output, a second inverter circuit having an input and an output, a first transistor coupled to the input of the second inverter circuit, wherein the gate of the first transistor is coupled to the first input, and a second transistor coupled to the input of the first inverter circuit, wherein the gate of the second transistor is coupled to the second input. The playback circuit also includes a pull-up circuit coupled to the inputs of the first inverter circuit and the second inverter circuit, and a pull-down circuit coupled to the inputs of the first inverter circuit and the second inverter circuit.

[0007]

[0007] The third aspect relates to a method of operating a playback circuit of a sampler. The playback circuit includes a first inverter circuit having an input and an output, a second inverter circuit having an input and an output, a first transistor coupled to the input of the second inverter circuit, a second transistor coupled to the input of the first inverter circuit, a third transistor, and a fourth transistor. The method includes disabling the playback feedback of the first inverter circuit and the second inverter circuit during a reset phase. The method also includes enabling the playback feedback of the first inverter circuit and the second inverter circuit during a playback phase, driving the gates of the first transistor and the third transistor with a first voltage, driving the gates of the second transistor and the fourth transistor with a second voltage, and coupling the third transistor to the output of the first inverter circuit or coupling the fourth transistor to the output of the second inverter circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008]

Figure 1

[0008] An example of a sampler including an input circuit and a playback circuit according to a particular aspect of the present disclosure is shown.

Figure 2A

[0009] An exemplary implementation of an input circuit according to a particular aspect of the present disclosure is shown.

Figure 2B

[0010] An exemplary implementation of a playback circuit according to a particular aspect of the present disclosure is shown.

Figure 2C

[0011] Another exemplary implementation of a playback circuit according to a particular aspect of the present disclosure is shown.

Figure 3A

[0012] A timing diagram showing an example of a voltage output from an input circuit to a playback circuit according to a particular aspect of the present disclosure is shown.

Figure 3B

[0013] A timing diagram showing another example of a voltage output from an input circuit to a playback circuit according to a particular aspect of the present disclosure is shown.

Figure 4

[0014] An example of a playback circuit including a pull-up circuit according to a particular aspect of the present disclosure is shown.

Figure 5A

[0015] An example of a playback circuit including a pull-down circuit according to a specific aspect of the present disclosure is shown.

Figure 5B

[0016] Another example of a playback circuit including a pull-down circuit according to a specific aspect of the present disclosure is shown.

Figure 6

[0017] An example of a playback circuit including an input transistor that provides a pull-up path according to a specific aspect of the present disclosure is shown.

Figure 7

[0018] An exemplary implementation form of an input transistor according to a specific aspect of the present disclosure is shown.

Figure 8

[0019] An exemplary implementation form of a switch in a playback circuit according to a specific aspect of the present disclosure is shown.

Figure 9A

[0020] An exemplary implementation form of a first inverter circuit in a playback circuit according to a specific aspect of the present disclosure is shown.

Figure 9B

[0021] An exemplary implementation form of a second inverter circuit in a playback circuit according to a specific aspect of the present disclosure is shown.

Figure 10

[0022] An exemplary implementation form of a switch in an input circuit according to a specific aspect of the present disclosure is shown.

Figure 11

[0023] An example of a system in which a specific aspect of the present disclosure can be used is shown according to a specific aspect of the present disclosure.

Figure 12

[0024] It is a flowchart showing a method of operating a playback circuit according to a specific aspect of the present disclosure.

Embodiments for Carrying Out the Invention

[0009]

[0025] In connection with the accompanying drawings, the "Modes for Carrying Out the Invention" described below are intended as descriptions of various configurations and are not intended to represent the only configuration capable of practicing the concepts described in this specification. The "Modes for Carrying Out the Invention" include specific details aimed at providing a complete understanding of various concepts. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some cases, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0010]

[0026] FIG. 1 shows an example of a sampler 110 according to a particular aspect of the present disclosure. The sampler 110 can be used, for example, in high-speed SerDes to sample an incoming data signal. The sampler 110 may also be referred to as a sense amplifier or by another term. The sampler 110 includes an input circuit 120 and a regeneration circuit 150. The input circuit 120 may also be referred to as an input stage or by another term, and the regeneration circuit 150 may also be referred to as a regeneration stage, a latch (e.g., a cross-coupled latch), or by another term.

[0011]

[0027] As shown in FIG. 1, the input circuit 120 has a first input 130, a second input 135, a first output 140, and a second output 145. The regeneration circuit 150 has a first input 160, a second input 165, a first output 170, and a second output 175. The first input 160 of the regeneration circuit 150 is coupled to the first input 140 of the input circuit 120, and the second input 165 of the regeneration circuit 150 is coupled to the second output 145 of the input circuit 120.

[0012]

[0028] In this example, the input circuit 120 is configured to receive a differential input signal (e.g., a differential data signal) including a first input voltage INP and a second input voltage INN. The first input voltage INP is received at the first input 130, and the second input voltage INN is received at the second input 135. The differential input signal may have a small differential voltage (i.e., a small difference between the first input voltage INP and the second input voltage INN) whose polarity of the differential voltage represents a bit value. In an example of SerDes, the sampler 110 may be integrated on a first chip coupled to a second chip via a link, and the sampler may receive the differential input signal from a transmitter on the second chip via the link.

[0013]

[0029] Based on the first input voltage INP and the second input voltage INN, the input circuit 120 generates a first voltage DINT at the first output 140 and a second voltage NDINT at the second output 145. As will be further described below, the input circuit 120 is configured to set the first voltage DINT and the second voltage NDINT to a reset voltage (e.g., a supply voltage) during a reset phase, and to change (e.g., discharge) the first voltage DINT and the second voltage NDINT at different rates based on the first input voltage INP and the second input voltage INN during a playback phase.

[0014]

[0030] The reproduction circuit 150 is configured to receive a first voltage DINT at a first input 160 and a second voltage NDINT at a second input 165. As will be further described below, during the reproduction phase, the reproduction circuit 150 is configured to convert the first voltage DINT and the second voltage NDINT into a differential output voltage using reproduction feedback. The differential output signal includes a first output voltage OUTP at a first output 170 and a second output voltage OUTN at a second output 175, and the polarity of the differential output voltage represents the captured (i.e., determined) bit value. The reproduction circuit 150 is desirably configured to quickly convert the first voltage DINT and the second voltage NDINT into a large differential output voltage (i.e., a large difference between the first output voltage OUTP and the second output voltage OUTN) during the reproduction phase in order to quickly determine the bit value for high-speed applications.

[0015]

[0031] The first output 170 and the second output 175 of the reproduction circuit 150 may be coupled to a latch (not shown) configured to latch the captured bit value from the sampler 110. The latch may include a set-reset (SR) latch or another type of latch.

[0016]

[0032] Figure 2A shows an exemplary implementation of the input circuit 120 according to a particular aspect. The input circuit 120 includes a first input transistor 210, a second input transistor 220, a first switch 230, a second switch 240, and a third switch 245. The second switch 240 is coupled between the upper rail 280 and the first input transistor 210, and the third switch 245 is coupled between the upper rail 280 and the second input transistor 220. The first input transistor 210 is coupled between the second switch 240 and the node 226, and the second input transistor 220 is coupled between the third switch 245 and the node 226. The first switch 230 is coupled between the node 226 and the lower rail 285. In one example, the upper rail 280 may supply a supply voltage VCC, and the lower rail 285 may be coupled to ground. Generally, the upper rail 280 is at a higher potential than the lower rail 285. The upper rail 280 may also be referred to as a supply rail or another term.

[0017]

[0033] In the example shown in FIG. 2A, the first input transistor 210 is implemented as a first n-type field effect transistor (NFET), and the second input transistor 220 is implemented as a second NFET. It should be understood that the first input transistor 210 and the second input transistor 220 are not limited to NFETs and may be implemented with other types of transistors. In this example, the second switch 240 is coupled between the upper rail 280 and the drain of the first input transistor 210, and the first switch 230 is coupled between the source of the first input transistor 210 and the lower rail 285. The gate of the first input transistor 210 is coupled to the first input 130 of the input circuit 120 and thus receives the first input voltage INP. Also, in this example, the third switch 245 is coupled between the upper rail 280 and the drain of the second input transistor 220, and the first switch 230 is coupled between the source of the second input transistor 220 and the lower rail 285. The gate of the second input transistor 220 is coupled to the second input 135 of the input circuit 120 and thus receives the second input voltage INN.

[0018]

[0034] The first switch 230 has a control input 235 that is driven by a timing signal, the second switch 240 has a control input 242 that is driven by a timing signal, and the third switch 245 has a control input 247 that is driven by a timing signal. In one example, the first switch 230 is configured to turn on when the timing signal is high and turn off when the timing signal is low, and each of the second switch 240 and the third switch 245 is configured to turn on when the timing signal is low and turn off when the timing signal is high. In the example shown in FIG. 2A, the timing signal is a clock signal CLK. As used herein, a "clock signal" is a periodic signal that oscillates between a high logic state and a low logic state. In a particular aspect, the high logic state (i.e., the logic state of 1) may correspond to a voltage substantially equal to the supply voltage VCC, and the low logic state (i.e., the logic state of zero) may correspond to a voltage substantially equal to ground.

[0019]

[0035] As used herein, a "control input" of a switch is an input that controls the on / off state of the switch based on a signal (e.g., a voltage signal) at the control input. In the case of an example where the switch is implemented by a transistor, the control input is located at the gate of the transistor. In one example, the first switch 230 may be implemented using an NFET, and each of the second switch 240 and the third switch 245 may be implemented using their respective PFETs. However, it should be understood that the present disclosure is not limited to this embodiment.

[0020]

[0036] In this example, the first output 140 is coupled to a first node 222 between the second switch 240 and the first input transistor 210, and the second output 145 is coupled to a second node 224 between the third switch 245 and the second input transistor 220. As described above, the input circuit 120 outputs a first voltage DINT at the first output 140 and a second voltage NDINT at the second output 145. In the example of FIG. 1, the first output 140 is coupled to the drain of the first input transistor 210, and the second output 145 is coupled to the drain of the second input transistor 220.

[0021]

[0037] FIG. 2B shows an exemplary implementation of the playback circuit 150 according to a particular aspect. In this example, the playback circuit 150 includes a first input transistor 250, a second input transistor 255, a first switch 290, a second switch 295, a first inverter circuit 260, and a second inverter circuit 270. As further discussed below, the first inverter circuit 260 and the second inverter circuit 270 are cross-coupled during the playback phase to provide playback feedback. As used herein, an "inverter circuit" is a circuit configured to invert the logical state (i.e., logic level or logic value) at the input of the inverter circuit and output the inverted logical state at the output of the inverter circuit. The logical state can be represented by a voltage where a low voltage (e.g., approximately ground) represents a logical state of zero and a high voltage (e.g., approximately the supply voltage) represents a logical state of one. In a particular aspect, the inverter circuit has a threshold voltage, and when the voltage at the input of the inverter circuit is below the threshold voltage, the output of the inverter circuit transitions from low to high, and when the voltage at the input of the inverter circuit is above the threshold voltage, the output of the inverter circuit transitions from high to low. The inverter circuit may also be referred to as an inverter, an inverter circuit, or by another term.

[0022]

[0038] The first inverter circuit 260 has an input 262, an output 264, a first supply terminal 266, and a second supply terminal 268. The second inverter circuit 270 has an input 272, an output 274, a first supply terminal 276, and a second supply terminal 278. The first supply terminal 266 of the first inverter circuit 260 and the first supply terminal 276 of the second inverter circuit 270 are coupled to the upper rail 280. The second supply terminal 268 of the first inverter circuit 260 and the second supply terminal 278 of the second inverter circuit 270 are coupled to the lower rail 285 (e.g., ground).

[0023]

[0039] The first switch 290 is coupled between the input 272 of the second inverter circuit 270 and the output 264 of the first inverter circuit 260, and the second switch 295 is coupled between the input 262 of the first inverter circuit 260 and the output 274 of the second inverter circuit 270. When the first switch 290 and the second switch 295 are turned on, the first inverter circuit 260 and the second inverter circuit 270 are cross-coupled, and the input 272 of the second inverter circuit 260 is coupled to the output 264 of the first inverter circuit 260 via the first switch 290, and the input 262 of the first inverter circuit 270 is coupled to the output 274 of the second inverter circuit 270 via the second switch 295. As will be further described below, the first switch 290 and the second switch 295 are turned on during the regeneration phase to enable the regeneration feedback of the first inverter circuit 260 and the second inverter circuit 270, and the first switch 290 and the second switch 295 are turned off during the reset phase to disable the regeneration feedback of the first inverter circuit 260 and the second inverter circuit 270. Each of the first switch 290 and the second switch 295 can be implemented using respective transistors (e.g., respective NFETs), respective transmission gates, or another type of switch.

[0024]

[0040] The first input transistor 250 is coupled between the input 272 of the second inverter circuit 270 and the lower rail 285. The gate of the first input transistor 250 is coupled to the first input 160 of the playback circuit 150. Thus, the gate of the first input transistor 250 is configured to receive the first voltage DINT (i.e., the first input signal to the playback circuit 150). In one example, the first input transistor 250 is configured to turn on when the voltage DINT exceeds the threshold voltage of the first input transistor 250 and turn off when the voltage DINT is below the threshold voltage of the first input transistor 250. In the example shown in FIG. 2B, the first input transistor 250 is implemented as an NFET, the drain of the first input transistor 250 is coupled to the input 272 of the second inverter circuit 270, and the source of the first input transistor 250 is coupled to the lower rail 285. Also, the first switch 290 is coupled between the output 264 of the first inverter circuit 260 and the drain of the first input transistor 250. It should be understood that the first input transistor 250 can also be implemented using another type of transistor. In this example, the first output 170 is coupled to the output 264 of the first inverter circuit 260.

[0025]

[0041] The second input transistor 255 is coupled between the input 262 of the first inverter circuit 260 and the lower rail 285. The gate of the second input transistor 255 is coupled to the second input 165 of the playback circuit 150. Thus, the gate of the second input transistor 255 is configured to receive a second voltage NDINT (i.e., the second input signal to the playback circuit 150). In one example, the second input transistor 255 is configured to turn on when the voltage NDINT exceeds the threshold voltage of the second input transistor 255 and turn off when the voltage NDINT is below the threshold voltage of the second input transistor 255. In the example shown in FIG. 2B, the second input transistor 255 is implemented with an NFET, the drain of the second input transistor 255 is coupled to the input 262 of the first inverter circuit 260, and the source of the second input transistor 255 is coupled to the lower rail 285. Also, the second switch 295 is coupled between the output 274 of the second inverter circuit 270 and the drain of the second input transistor 255. It should be understood that the second input transistor 255 may also be implemented using another type of transistor. In this example, the second output 175 is coupled to the output 274 of the second inverter circuit 270.

[0026]

[0042] In the example of FIG. 2B, the first switch 290 has a control input 292 driven by a timing signal, and the second switch 295 has a control input 297 driven by a timing signal (e.g., a clock signal CLK). In one example, the first switch 290 and the second switch 295 are configured to turn on when the timing signal is high and turn off when the timing signal is low. Thus, in this example, when the first switch 230 of the input circuit 120 turns on, the first switch 290 and the second switch 295 turn on, and when the second switch 240 and the third switch 245 of the input circuit 120 turn on, the first switch 290 and the second switch 295 turn off. In an example where each of the first switch 290 and the second switch 295 is implemented with a respective transistor, the control inputs 292 and 297 of each of the first switch 290 and the second switch 295 are located at the gates of the respective transistors. In one example, each of the first switch 290 and the second switch 295 can be implemented using a respective NFET.

[0027]

[0043] Here, an exemplary operation of the sampler 110 will be discussed according to a particular aspect.

[0028]

[0044] When the timing signal (e.g., clock signal CLK) is low, the sampler 110 is in the reset phase. In the reset phase, the first switch 230 of the input circuit 120 is turned off. As a result, the first switch 230 disconnects the first input transistor 210 and the second input transistor 220 of the input circuit 120 from the lower rail 285 (e.g., ground). The second switch 240 and the third switch 245 are turned on. As a result, the second switch 240 couples the first output 140 to the upper rail 280, and the third switch 245 couples the second output 145 to the upper rail 280. Thereby, the input circuit 120 pulls up the first output 140 and the second output 145 to the supply voltage VCC on the upper rail 280. Accordingly, both the first voltage DINT input to the gate of the first input transistor 250 of the playback circuit 150 and the second voltage NDINT input to the gate of the second input transistor 255 of the playback circuit 150 are pulled up to VCC during the reset phase.

[0029]

[0045] Also, in the reset phase, the first switch 290 and the second switch 295 of the playback circuit 150 are turned off. As a result, the playback feedback in the playback circuit 150 is invalidated (i.e., the cross-coupling of the inverter circuits 260 and 270 is disconnected). In addition, (assuming that VCC is greater than the threshold voltages of the first input transistor 250 and the second input transistor 255), since both the voltage DINT and the voltage NDINT are pulled up to the supply voltage VCC, both the first input transistor 250 and the second input transistor 255 of the playback circuit 150 are turned on. As a result, the inputs 262 and 272 of the inverter circuits 260 and 270 are pulled low (e.g., to ground). Thereby, the outputs 264 and 274 of the inverter circuits 260 and 270 are pulled high. In this example, the first output 170 and the second output 175 of the playback circuit 150 are also pulled high.

[0030]

[0046] When a timing signal (e.g., clock signal CLK) transitions from low to high, the sampler 110 transitions to the playback phase. During the playback phase, the input circuit 120 senses a differential input signal (e.g., differential data signal) at inputs 130 and 135 of the input circuit 120. FIG. 3A shows an example of voltages DINT and NDINT during the playback phase when the input voltage INP is higher than the input voltage INN, which may represent a bit value of 1. In this example, the timing signal (e.g., clock signal CLK) transitions from low to high at time T1. Also, in this example, the first input transistor 250 and the second input transistor 255 have the same threshold voltage 310 shown in FIG. 3.

[0031]

[0047] At time T1, the first switch 230 is turned on, and the second switch 240 and the third switch 245 are turned off. Thereby, the first input transistor 210 can pull down the voltage DINT based on the input voltage INP at the first input transistor 210, and the second input transistor 220 can pull down the voltage NDINT based on the input voltage INN at the second input transistor 220. In this example, the voltage DINT is pulled down (i.e., at a rate faster than the voltage NDINT. This is because in this example, the first input transistor 210 is driven by a higher voltage than the second input transistor 220 (i.e., INP>INN).

[0032]

[0048] At time T2, the voltage DINT falls below the threshold voltage 310, whereby the first input transistor 250 of the reproduction circuit 150 is turned off. Since the voltage NDINT still exceeds the threshold voltage at time T2, the second input transistor 255 of the reproduction circuit 150 remains on at time T2. Starting from time T2, the reproduction feedback of the reproduction circuit 150 pulls up the first output 170 and pulls down the second output 175 (for example, pulls the first output 170 towards the supply voltage VCC and pulls the second output 175 towards the ground). The pull-up of the first output 170 and the pull-down of the second output 175 generate a differential output voltage at the outputs 170 and 175, where the output voltage OUTP is higher than the output voltage OUTN, which may represent a bit value of 1.

[0033]

[0049] FIG. 3A shows the voltages DINT and NDINT when the input voltage INP is higher than the input voltage INN. FIG. 3B shows the voltages DINT and NDINT when the input voltage INN is higher than the input voltage INP. In this case, the voltage NDINT at the second output 145 of the input circuit 120 drops at a faster rate than the voltage DINT at the first output 140 of the input circuit 120 during the reproduction phase. As a result, the voltage NDINT falls below the threshold voltage 310 before the voltage DINT, turning off the second input transistor 255 before the first input transistor 250. When this occurs, the reproduction feedback of the reproduction circuit 150 pulls up the second output 175 and pulls down the first output 170, resulting in a large differential output voltage where the output voltage OUTN is higher than the output voltage OUTP, which may represent a zero bit determination.

[0034]

[0050] In both cases, in order to quickly determine (i.e., capture) the bit value, it is desirable for the playback circuit 150 to quickly generate a large differential output voltage at outputs 170 and 175 during the playback phase. Latches (e.g., SR latches) coupled to outputs 170 and 175 of the playback circuit 150 can latch the bit value determined as described above. When the timing signal transitions from high to low, the sampler 110 re-enters the reset phase and resets the sampler 110 for the next bit value.

[0035]

[0051] As described above, in the example of FIG. 2B, the first switch 290 and the second switch 295 are used to enable the playback feedback of the first inverter circuit 260 and the second inverter circuit 270 during the playback phase and disable the playback feedback of the first inverter circuit 260 and the second inverter circuit 270 during the reset phase. The first switch 290 and the second switch 295 disable the playback feedback during the reset phase by disconnecting the cross-coupling of the first inverter circuit 260 and the second inverter circuit 270 when the first switch 290 and the second switch 295 are turned off. However, it should be understood that the present disclosure is not limited to this embodiment. In general, the playback feedback of the first inverter circuit 260 and the second inverter circuit 270 can be enabled or disabled using one or more switches arranged at one or more locations within the playback circuit 150, and the one or more switches are controlled by a timing signal (e.g., the clock signal CLK).

[0036]

[0052] In this regard, FIG. 2C shows an exemplary implementation in which the playback circuit 150 includes a switch 296 coupled between the upper rail 280 and the power terminals 266 and 276 of the inverter circuits 260 and 270. In this example, the first switch 290 and the second switch 295 shown in FIG. 2B are omitted, the output 264 of the first inverter circuit 260 is coupled to the first input transistor 250, and the output 274 of the second inverter circuit 270 is coupled to the second input transistor 255. The switch 296 may be implemented using a PFET and has a control input 298 driven by an inversion of a timing signal (e.g., an inverted clock signal CLKb). In this example, the switch 296 is configured to be off during the reset phase and on during the playback phase. Turning off the switch 296 during the reset phase removes power from the inverter circuits 260 and 270 from the upper rail 280, thereby invalidating the playback feedback of the first inverter circuit 260 and the second inverter circuit 270. It should be understood that the present disclosure is not limited to the examples shown in FIGS. 2B and 2C.

[0037]

[0053] FIG. 4 shows an example in which, according to a particular aspect, the playback circuit 150 further includes a pull-up circuit 405. The pull-up circuit 405 is configured to provide an additional pull-up path during the playback phase to increase the playback gain of the playback circuit 150. The pull-up circuit 405 includes a first pull-up transistor 410 and a second pull-up transistor 420 according to a particular aspect of the present disclosure.

[0038]

[0054] In the example of FIG. 4, the first pull-up transistor 410 is implemented by a first PFET, and the second pull-up transistor 420 is implemented by a second PFET. The source of the first pull-up transistor 410 is coupled to rail 280, the drain of the first pull-up transistor 410 is coupled to the input 262 of the first inverter circuit 260, and the gate of the first pull-up transistor 410 is coupled to the output 264 of the first inverter circuit 260. The source of the second pull-up transistor 420 is coupled to rail 280, the drain of the second pull-up transistor 420 is coupled to the input 272 of the second inverter circuit 270, and the gate of the second pull-up transistor 420 is coupled to the output 274 of the second inverter circuit 270.

[0039]

[0055] Here, an exemplary operation of the pull-up circuit 405 will be discussed according to a particular aspect.

[0040]

[0056] During the regeneration phase, if the voltage DINT drops faster than the voltage NDINT (for example, if INP > INN at inputs 130 and 135 of the input circuit 120), the first input transistor 250 turns off before the second input transistor 255. This triggers the regeneration feedback of the regeneration circuit 150 to pull up the first output 170 and pull down the second output 175. Since the gate of the second pull-up transistor 420 is coupled to the second output 175, the pull-down of the second output 175 turns on the second pull-up transistor 420. Thereby, the second pull-up transistor 420 pulls up the input 272 of the second inverter circuit 270 towards the supply voltage VCC on the rail 280, which helps the second inverter circuit 270 drive the output 274 of the second inverter circuit 270 low. Since the output 274 of the second inverter circuit 270 is coupled to the second output 175, driving the output 274 of the second inverter circuit 270 low helps further pull down the second output 175, thereby increasing the regeneration gain of the regeneration circuit 150. Thus, in this case, the pull-up circuit 405 provides an additional pull-up path between the rail 280 and the input 272 of the second inverter circuit 270 during the regeneration phase, which increases the regeneration gain.

[0041]

[0057] If the voltage NDINT drops faster than the voltage DINT during the regeneration phase (e.g., when INN > INP at inputs 130 and 135 of the input circuit 120), the second input transistor 255 turns off before the first input transistor 250. This triggers the regeneration feedback of the regeneration circuit 150 to pull up the second output 175 and pull down the first output 170. Since the gate of the first pull-up transistor 410 is coupled to the first output 170, the pull-down of the first output 170 turns on the first pull-up transistor 410. Thereby, the first pull-up transistor 410 pulls up the input 262 of the first inverter circuit 260 towards the supply voltage VCC on the rail 280, which helps the first inverter circuit 260 drive the output 264 of the first inverter circuit 260 low. Since the output 264 of the first inverter circuit 260 is coupled to the first output 170, driving the output 264 of the first inverter circuit 260 lower helps pull down the first output 170 further, thereby increasing the regeneration gain of the regeneration circuit 150. Thus, in this case, the pull-up circuit 405 provides an additional pull-up path between the rail 280 and the input 262 of the first inverter circuit 260 during the regeneration phase, which increases the regeneration gain.

[0042]

[0058] Thus, the pull-up circuit 405 is configured to provide an additional pull-up path during the regeneration phase to increase the regeneration gain of the regeneration circuit 150. The pull-up path is between the rail 280 and the input 272 of the second inverter circuit 270 when the voltage DINT drops faster than the voltage NDINT (e.g., when INP > INN), and the pull-up path is between the rail 280 and the input 262 of the first inverter circuit 260 when the voltage NDINT drops faster than the voltage DINT (e.g., when INN > INP).

[0043]

[0059] To further increase the playback gain of the playback circuit 150, a pull-down circuit can be added to the playback circuit 150. In this regard, FIG. 5A shows an example in which the playback circuit 150 further includes a pull-down circuit 505 according to a particular aspect. The pull-down circuit 505 is configured to provide an additional pull-down path during the playback phase to increase the playback gain of the playback circuit 150, which increases the signal strength at the outputs 170 and 175 of the playback circuit 150. The pull-down circuit 505 can be used in combination with the pull-up circuit 405 to increase the playback gain, as further described below. The pull-down circuit 505 includes a first pull-down transistor 510 and a second pull-down transistor 520 according to a particular aspect of the present disclosure.

[0044]

[0060] In the example of FIG. 5A, the first pull-down transistor 510 is implemented as a first NFET, and the second pull-down transistor 520 is implemented as a second NFET. The drain of the first pull-down transistor 510 is coupled to the input 262 of the first inverter circuit 260, the source of the first pull-down transistor 510 is coupled to the lower rail 285 (e.g., ground), and the gate of the first pull-down transistor 510 is coupled to the input 272 of the second inverter circuit 270 and the first output 170. The drain of the second pull-down transistor 520 is coupled to the input 272 of the second inverter circuit 270, the source of the second pull-down transistor 520 is coupled to the lower rail 285, and the gate of the second pull-down transistor 520 is coupled to the input 262 of the first inverter circuit 260 and the second output 175. In other words, the first pull-down transistor 510 and the second pull-down transistor 520 are cross-coupled.

[0045]

[0061] Now, the exemplary operation of the pull-down circuit 505 will be discussed according to a particular aspect.

[0046]

[0062] When the voltage DINT drops faster than the voltage NDINT during the regeneration phase (for example, when INP > INN at inputs 130 and 135 of the input circuit 120), the first input transistor 250 turns off before the second input transistor 255. This triggers the regeneration feedback of the regeneration circuit 150 to pull up the first output 170 and pull down the second output 175. Since the gate of the first pull-down transistor 510 is coupled to the first output 170, the pull-up of the first output 170 turns on the first pull-down transistor 510. Thereby, the first pull-down transistor 510 pulls down the input 262 of the first inverter circuit 260, which helps the first inverter circuit 260 drive the output 264 high. Since the output 264 of the first inverter circuit 260 is coupled to the first output 170, driving the output 264 of the first inverter circuit 260 high helps further pull up the first output 170, thereby increasing the regeneration gain. Thus, in this case, the pull-down circuit 505 provides an additional pull-down path between the input 262 of the first inverter circuit 260 and the lower rail 285 (e.g., ground) during the regeneration phase, which increases the regeneration gain.

[0047]

[0063] When the voltage NDINT drops faster than the voltage DINT during the regeneration phase (e.g., when INN > INP at inputs 130 and 135 of the input circuit 120), the second input transistor 255 turns off before the first input transistor 250. This triggers the regeneration feedback of the regeneration circuit 150 to pull up the second output 175 and pull down the first output 170. Since the gate of the second pull-down transistor 520 is coupled to the second output 175, the pull-up of the second output 175 turns on the second pull-down transistor 520. Thereby, the second pull-down transistor 520 pulls down the input 272 of the second inverter circuit 270, which helps the second inverter circuit 270 drive the output 274 high. Since the output 274 of the second inverter circuit 270 is coupled to the second output 175, driving the output 274 of the second inverter circuit 270 high helps further pull up the second output 175, thereby increasing the regeneration gain. Thus, in this case, the pull-down circuit 505 provides an additional pull-down path between the input 272 of the second inverter circuit 270 and the lower rail 285 (e.g., ground) during the regeneration phase, which increases the regeneration gain.

[0048]

[0064] Therefore, the pull-down circuit 505 is configured to provide an additional pull-down path during the regeneration phase to increase the regeneration gain of the regeneration circuit 150. The pull-down path is between the input 262 of the first inverter circuit 260 and the lower rail 285 (e.g., ground) when the voltage DINT drops faster than the voltage NDINT (e.g., when INP > INN), and the pull-down path is between the input 272 of the second inverter circuit 270 when the voltage NDINT drops faster than the voltage DINT (e.g., when INN > INP).

[0049]

[0065] The pull-down circuit 505 can be used in combination with the pull-up circuit 405 to increase the playback gain of the playback circuit 150, which increases the signal strength at the outputs 170 and 175 of the playback circuit 150. For example, when the voltage DINT drops faster than the voltage NDINT (e.g., INP>INN), the pull-up circuit 405 provides an additional pull-up path for pulling up the input 272 of the second inverter circuit 270, while the pull-down circuit 505 provides an additional pull-down path for pulling down the input 262 of the first inverter circuit 260. When the voltage NDINT drops faster than the voltage DINT (e.g., INN>INP), the pull-up circuit 405 provides an additional pull-up path for pulling up the input 272 of the second inverter circuit 270, while the pull-down circuit 505 provides an additional pull-down path for pulling down the input 262 of the first inverter circuit 260. Thus, in these aspects, depending on which of the voltages DINT and NDINT drops faster, and thus depending on the input voltages INP and INN of the input circuit 120, the pull-up circuit 405 pulls up one of the inputs of the inverter circuits 260 and 270, and the pull-down circuit 505 pulls down the other input of the inverter circuits 260 and 270.

[0050]

[0066] Another advantage of the pull-up circuit 405 and the pull-down circuit 505 is that these circuits continue to provide a playback gain during the first part of the reset phase before the input transistors 250 and 255 are turned on (i.e., before the input circuit 120 raises the voltages DINT and NDINT above the threshold voltages of the input transistors 250 and 255). This is because the pull-up circuit 405 and the pull-down circuit 505 continue to provide an additional pull-up path and an additional pull-down path even if the switches 290 and 295 are turned off by a timing signal (e.g., a clock signal CLK). The continued playback gain during the first part of the reset phase allows the differential output voltage of the playback circuit 150 to continue to increase in order to better determine the corresponding bit value.

[0051]

[0067] It should be understood that the pull-down circuit 505 is not limited to the exemplary implementation shown in FIG. 5A. In this regard, FIG. 5B shows another exemplary implementation in which the gate of the first pull-down transistor 510 is coupled to the output 264 of the first inverter circuit 260 and the gate of the second pull-down transistor 520 is coupled to the output 274 of the second inverter circuit 270. Similar to the exemplary implementation shown in FIG. 5A, the pull-down transistors 510 and 520 in this example provide an additional pull-down path to increase the playback gain.

[0052]

[0068] As described above, the pull-up circuit 405 increases the playback gain of the playback circuit 150 by providing an additional pull-up path during the playback phase. By increasing the size (e.g., channel width) of the pull-up transistors 410 and 420, the strength of the pull-up path can be increased to further increase the playback gain of the playback circuit 150. However, increasing the size of the pull-up transistors 410 and 420 increases the reset time of the playback circuit 150, as will be further discussed below, resulting in a trade-off between playback and reset.

[0053]

[0069] At the start of the reset phase, input circuit 120 raises voltages DINT and NDINT, which are input to input transistors 250 and 255 of playback circuit 150. When voltages DINT and NDINT rise to the threshold voltages of input transistors 250 and 255, input transistors 250 and 255 turn on and pull both inputs 262 and 272 of inverters 260 and 270 low. However, one of pull-up transistors 410 and 420 is initially on and resists the ability of input transistors 250 and 255 to pull both inputs 262 and 272 of inverters 260 and 270 low, which increases the reset time. To further increase the playback gain, increasing the size of pull-up transistors 410 and 420 worsens this problem by making it more difficult for input transistors 250 and 255 to pull both inputs 262 and 272 of inverters 260 and 270 low to reset playback circuit 150. Thus, there is a trade-off between playback and reset associated with pull-up transistors 410 and 420.

[0054]

[0070] To address the above, FIG. 6 shows an example where playback circuit 150 further includes a third input transistor 610 and a fourth input transistor 620, which, as further described below, mitigate the trade-off between playback and reset and increase sensitivity. In this example, playback circuit 150 also includes a third switch 630 and a fourth switch 640.

[0055]

[0071] The gate of the third input transistor 610 is coupled to the first input 160 of the playback circuit 150 and thus receives the first voltage DINT. The third input transistor 610 and the third switch 630 are coupled in series between the rail 280 and the first output 170 of the playback circuit 150. In the example of FIG. 6, the third input transistors 610 are implemented with respective PFETs, the source of the third input transistor 610 is coupled to the rail 280, and the third switch 630 is coupled between the drain of the third input transistor 610 and the first input transistor 250. In an example where the third input transistors 610 are implemented with respective PFETs, the third input transistor 610 may be configured to turn on when the first voltage DINT falls below VCC-Vt3, where Vt3 is the threshold voltage of the third input transistor 610.

[0056]

[0072] The third switch 630 has a control input 635 coupled to the input 262 of the first inverter circuit 260. In certain aspects, the third switch 630 is configured to turn on when the voltage at the control input 635 falls below the threshold of the third switch 630 and to turn off when the voltage at the control input 635 rises above the threshold of the third switch 630, as further described below. The third switch 630 may be implemented with respective PFETs or with another type of switch.

[0057]

[0073] The gate of the fourth input transistor 620 is coupled to the second input 165 of the playback circuit 150 and thus receives the second voltage NDINT. The fourth input transistor 620 and the fourth switch 640 are coupled in series between rail 280 and the second output 175 of the playback circuit 150. In the example of FIG. 6, the fourth input transistors 620 are implemented with respective PFETs, the source of the fourth input transistor 620 is coupled to rail 280, and the fourth switch 640 is coupled between the drain of the fourth input transistor 620 and the second input transistor 255. In an example where the fourth input transistors 620 are implemented with respective PFETs, the fourth input transistor 620 may be configured to turn on when the second voltage NDINT falls below VCC - Vt4, where Vt4 is the threshold voltage of the fourth input transistor 620. In certain embodiments, Vt3 and Vt4 may be approximately equal.

[0058]

[0074] The fourth switch 640 has a control input 645 coupled to the input 272 of the second inverter circuit 270. In certain embodiments, the fourth switch 640 is configured to turn on when the voltage at the control input 645 falls below the threshold of the fourth switch 640 and turn off when the voltage at the control input 645 exceeds the threshold of the fourth switch 640, as further described below. The fourth switch 640 may be implemented with respective PFETs or another type of switch.

[0059]

[0075] Here, the exemplary operation of the exemplary playback circuit 150 shown in FIG. 6 will be discussed according to certain embodiments.

[0060]

[0076] During the reset phase, as discussed above, the input circuit 120 pulls the voltages DINT and NDINT to the supply voltage VCC. As a result, the first input transistors 250 and 255 of the playback circuit 150 turn on, and the inputs 262 and 272 of the inverter circuits 260 and 270 are pulled low. Further, since these transistors are implemented as PFETs, the third and fourth input transistors 610 and 620 of the playback circuit 150 turn off. Thus, in this example, the inputs 262 and 272 of the inverter circuits 260 and 270 are reset to low (e.g., approximately ground). Additionally, both the third switch 630 and the fourth switch 640 are on. This is because the input transistors 610 and 620 pull the control inputs 635 and 645 of the third and fourth switches 630 and 640 low during the reset phase.

[0061]

[0077] When the sampler 110 transitions to the playback phase, a timing signal (e.g., the clock signal CLK) turns on the first switch 290 and the second switch 295, enabling the playback feedback loop through the inverter circuits 260 and 270. At the start of the playback phase, both the first input transistors 250 and 255 are on, and both the third and fourth input transistors 610 and 620 are off. Additionally, both the third switch 630 and the fourth switch 640 are on.

[0062]

[0078] When the input voltage INP is higher than the input voltage INN, the first voltage DINT decreases (i.e., discharges) at a rate faster than the second voltage NDINT. As a result, the first input transistor 250 turns off before the second input transistor 255, and the third input transistor 610 turns on before the fourth input transistor 620. Turning off the first input transistor 250 triggers the playback feedback of the playback circuit 150 to pull up the first output 170 and pull down the second output 175 (e.g., pull the first output 170 towards the supply voltage VCC and pull the second output 175 towards the ground). By turning on the third input transistor 610, the third input transistor 610 pulls up the first output 170 through the (turned-on) third switch 630. Therefore, in this case, the third input transistor 610 and the third switch 630 provide an additional pull-up path for pulling up the first output 170, which increases the playback gain.

[0063]

[0079] Since the control input 645 of the fourth switch 640 is coupled to the first output 170, the pull-up of the first output 170 turns off the fourth switch 640. This prevents the fourth input transistor 620 from pulling up the second output 175 when the fourth input transistor 620 finally turns on (i.e., when NDINT falls below VCC - Vt4), and allows the playback of the playback circuit 150 to pull the second output 175 low.

[0064]

[0080] When the input voltage INN is higher than the input voltage INP, the second voltage NDINT decreases (i.e., discharges) at a rate faster than the first voltage DINT. As a result, the second input transistor 255 turns off before the first input transistor 250, and the fourth input transistor 620 turns on before the third input transistor 610. Turning off the second input transistor 255 triggers the playback feedback of the playback circuit 150 to pull up the second output 175 and pull down the first output 170 (e.g., pull the second output 175 towards the supply voltage VCC and pull the first output 170 towards the ground). By turning on the fourth input transistor 620, the fourth input transistor 620 pulls up the second output 175 via the (turned-on) fourth switch 640. Therefore, in this case, the fourth input transistor 620 and the fourth switch 640 provide an additional pull-up path for pulling up the second output 175, which increases the playback gain.

[0065]

[0081] Since the control input 635 of the third switch 630 is coupled to the second output 175, the pull-up of the second output 175 turns off the third switch 630. This prevents the third input transistor 610 from pulling up the first output 170 when the third input transistor 610 finally turns on (i.e., when DINT falls below VCC - Vt3), and allows the playback of the playback circuit 150 to pull the first output 170 low.

[0066]

[0082] Accordingly, the third input transistor 610 and the fourth input transistor 620 provide an additional pull-up path during the playback phase to increase the playback gain of the playback circuit 150. When the voltage DINT drops faster than the voltage NDINT (e.g., INP > INN), the third input transistor 610 provides an additional pull-up path between the first output 170 and the rail 280 via the third switch 630. When the voltage NDINT drops faster than the voltage DINT (e.g., INN > INP), the fourth input transistor 620 provides an additional pull-up path between the second output 175 and the rail 280 via the fourth switch 640.

[0067]

[0083] The third input transistor 610 and the fourth input transistor 620 enable a higher playback gain to be achieved without the need for the playback circuit 150 to increase the size (e.g., channel width) of the first pull-up transistor 410 and the second pull-up transistor 420, thereby relaxing the trade-off between playback and reset associated with the pull-up transistors 410 and 420. This is because the third input transistor 610 and the fourth input transistor 620 provide an additional pull-up path during the playback phase in parallel with the additional pull-up path provided by the pull-up transistors 410 and 420. This increases the pull-up strength of playback in the playback circuit 150 without the need to increase the size of the first pull-up transistor 410 and the second pull-up transistor 420.

[0068]

[0084] In addition, the input circuit 120 turns off both the third input transistor 610 and the fourth input transistor 620 during the reset phase, allowing the first input transistor 250 and the second input transistor 255 to pull the inputs 262 and 272 of both the inversion circuits 260 and 270 low during the reset phase to reset the reproduction circuit 150. This is because the input circuit 120 pulls the voltages DINT and NDINT to the supply voltage VCC during the reset phase, thereby turning off both the third input transistor 610 and the fourth input transistor 620. When the input circuit 120 turns off the third input transistor 610 and the fourth input transistor 620 during the reset phase, these transistors no longer resist the ability of the first input transistor 250 and the second input transistor 255 to pull the inputs 262 and 272 of both the inversion circuits 260 and 270 low during the reset phase. This further reduces the trade-off between reproduction and reset.

[0069]

[0085] The third input transistor 610 and the fourth input transistor 620 also increase the sensitivity of the sampler 110. This is because the gates of the third input transistor 610 and the fourth input transistor 620 are driven by the voltages DINT and NDINT respectively generated based on the sensed input voltages INP and INN.

[0070]

[0086] In the example shown in FIG. 6, the third switch 630 is coupled between the third input transistor 610 and the first input transistor 250. However, it should be understood that the present disclosure is not limited to this embodiment. For example, in some implementations, the third switch 630 is coupled between the third input transistor 610 and the upper rail 280, and the third input transistor 610 may be coupled between the third switch 630 and the first input transistor 250. Generally, the third input transistor 610 and the third switch 630 are serially coupled between the upper rail 280 and the first input transistor 250, and either the third input transistor 610 or the third switch 630 is on the upper side. Also, in some implementations, the fourth switch 640 is coupled between the fourth input transistor 620 and the upper rail 280, and the fourth input transistor 620 may be coupled between the fourth switch 640 and the second input transistor 255. Generally, the fourth input transistor 620 and the fourth switch 640 are serially coupled between the upper rail 280 and the second input transistor 255, and either the fourth input transistor 620 or the fourth switch 640 is on the upper side.

[0071]

[0087] FIG. 7 shows an exemplary implementation of the third switch 630 and the fourth switch 640. In this example, the third switch 630 is implemented by a first PFET 710 coupled between the drain of the third input transistor 610 and the first input transistor 250, and the gate of the first PFET 710 is coupled to the input 262 of the first inverter circuit 260. Also, in this example, the fourth switch 640 includes a second PFET 720 coupled between the drain of the fourth input transistor 620 and the second input transistor 255, and the gate of the second PFET 720 is coupled to the input 272 of the second inverter circuit 270. It should be understood that the third switch 630 and the fourth switch 640 are not limited to the exemplary implementation shown in FIG. 7, and each of the third switch 630 and the fourth switch 640 may be implemented by another type of transistor, transmission gate, or another type of switch.

[0072]

[0088] FIG. 8 shows an example in which the first switch 290 is implemented by the first NFET 810 and the second switch 295 is implemented by the second NFET 820. In this example, one of the source and drain of the first NFET 810 is coupled to the first input transistor 250 (e.g., the drain of the first input transistor 250), the other of the source and drain of the first NFET 810 is coupled to the output 264 of the first inverter circuit 260, and the gate of the first NFET 810 is coupled to a control input 292 for receiving a timing signal (e.g., the clock signal CLK). One of the source and drain of the second NFET 820 is coupled to the second input transistor 255 (e.g., the drain of the second input transistor 255), the other of the source and drain of the second NFET 820 is coupled to the output 274 of the second inverter circuit 270, and the gate of the second NFET 820 is coupled to a control input 297 for receiving a timing signal (e.g., the clock signal CLK). In this example, the first switch 290 and the second switch 295 turn on when the timing signal is high and turn off when the timing signal is low. The first switch 290 and the second switch 295 are not limited to the exemplary implementation shown in FIG. 8, and it should be understood that each of the first switch 290 and the second switch 295 may be implemented by another type of transistor, transmission gate, or another type of switch.

[0073]

[0089] In the examples shown in FIGS. 4 to 8, the playback circuit 150 includes a first switch 290 and a second switch 295 for enabling the playback feedback of the inversion circuits 260 and 270 during the playback phase and disabling the playback feedback of the inversion circuits 260 and 270 during the reset phase. However, it should be understood that the present disclosure is not limited to this embodiment. For example, in other implementations, the first switch 290 and the second switch 295 may be omitted, and the switch 296 shown in FIG. 2C may be used to enable or disable the playback feedback of the inversion circuits 260 and 270. In this example, the output 264 of the first inversion circuit 260 is coupled to the first input transistor 250, and the output 274 of the second inversion circuit 270 is coupled to the second input transistor 255. Generally, one or more switches may be arranged at one or more locations within the playback circuit 150 to enable or disable the playback feedback of the inversion circuits 260 and 270.

[0074]

[0090] FIG. 9A shows an exemplary implementation of the first inversion circuit 260 according to a particular aspect. In this example, the first inversion circuit 260 is a complementary inversion circuit including a PFET 910 and an NFET 920. The source of the PFET 910 is coupled to the first supply terminal 266, the drain of the PFET 910 is coupled to the output 264, and the gate of the PFET 910 is coupled to the input 262. The drain of the NFET 920 is coupled to the output 264, the gate of the NFET 920 is coupled to the input 262, and the source of the NFET 920 is coupled to the second supply terminal 268. It should be understood that the first inversion circuit 260 is not limited to the example shown in FIG. 9A.

[0075]

[0091] FIG. 9B shows an exemplary implementation of a second inverter circuit 270 according to a particular embodiment. In this example, the second inverter circuit 270 is a complementary inverter circuit including a PFET 930 and an NFET 940. The source of the PFET 930 is coupled to a first supply terminal 276, the drain of the PFET 930 is coupled to an output 274, and the gate of the PFET 930 is coupled to an input 272. The drain of the NFET 940 is coupled to the output 274, the gate of the NFET 940 is coupled to the input 272, and the source of the NFET 940 is coupled to a second supply terminal 278. It should be understood that the second inverter circuit 270 is not limited to the example shown in FIG. 9B.

[0076]

[0092] FIG. 10 shows an exemplary implementation of a first switch 230, a second switch 240, and a third switch 245 within an input circuit 120 according to a particular embodiment. In this example, the first switch 230 is implemented by an NFET 1010, the drain of the NFET 1010 is coupled to the sources of input transistors 210 and 220, the gate of the NFET 1010 is coupled to a control input 235, and the source of the NFET 1010 is coupled to a lower rail 285 (e.g., ground). The second switch 240 is implemented by a first PFET 1015, the source of the first PFET 1015 is coupled to an upper rail 280, the gate of the first PFET 1015 is coupled to a control input 242, and the drain of the first PFET 1015 is coupled to the drain of the first input transistor 210. The third switch 245 is implemented by a second PFET 1020, the source of the second PFET 1020 is coupled to the upper rail 280, the gate of the second PFET 1020 is coupled to a control input 247, and the drain of the second PFET 1020 is coupled to the drain of the second input transistor 220. In this example, the first switch 230 turns on when the timing signal is high and turns off when the timing signal is low. Also, in this example, the second switch 240 and the third switch 24 turn on when the timing signal is low and turn off when the timing signal is high. It should be understood that the first switch 230, the second switch 240, and the third switch 245 are not limited to the exemplary implementation shown in FIG. 10.

[0077]

[0093] FIG. 11 shows an example of a system 1105 in which an aspect of the present disclosure may be used. In this example, the system 1105 includes a first chip 1110 and a second chip 1115, and SerDes may be used for communication between the first chip 1110 and the second chip 1115. The first chip 1110 includes a serializer 1120, a driver 1130, a first output pin 1140, and a second output pin 1142. The second chip 1115 includes a first receive pin 1150, a second receive pin 1152, a receiver 1160, a sampler 1170, a latch 1170, and a deserialzier 1180.

[0078]

[0094] In this example, the first chip 1110 and the second chip 1115 are coupled via a differential serial link including a first line 1144 and a second line 1146. The first line 1144 is coupled between the first output pin 1140 and the first receive pin 1150, and the second line 1146 is coupled between the second output pin 1142 and the second receive pin 1152. Each of the first line 1144 and the second line 1146 may be implemented with a metal line, wire, etc. on a substrate (e.g., a printed circuit board).

[0079]

[0095] On the first chip 1110, serializer 1120 is configured to receive a parallel data stream (e.g., from a processor on the first chip 1110) and convert the parallel data stream into a serial data stream, which is output at output 1125 of serializer 1120. Driver 1130 has an input 1132 coupled to output 1125 of serializer 1120, a first output 1134 coupled to a first output pin 1140, and a second output 1136 coupled to a second output pin 1142. Driver 1130 is configured to receive the serial data stream, convert the serial data stream into a differential signal, and drive first line 1144 and second line 1146 of the differential serial link with the differential data signal to transmit the differential signal to the second chip 1115. It should be understood that the first chip 1110 may include additional components (e.g., impedance matching networks coupled to output pins 1140 and 1142, a pre-driver coupled between serializer 1120 and driver 1130, etc.) not shown in FIG. 11.

[0080]

[0096] On the second chip 1115, receiver 1160 has a first input 1162 coupled to a first receive pin 1150, a second input 1164 coupled to a second receive pin 1152, a first output 1166 coupled to a first input 130 of sampler 110, and a second output 1168 coupled to a second input 135 of sampler 110. Receiver 1160 may include at least one of an amplifier and an equalizer (e.g., to compensate for frequency-dependent signal attenuation between the first chip 1110 and the second chip 1115). Sampler 110, as described above, receives the differential signal from receiver 1160 and makes bit decisions based on the differential signal.

[0081]

[0097] In the example of FIG. 11, the first output 170 of sampler 110 is coupled to the first input 1172 of latch 1170, and the second output 175 of sampler 110 is coupled to the second input 1174 of latch 1170. Latch 1170 has an output 1176 coupled to the input 1182 of deserializator 1180. Latch 1170 is configured to latch the bit decisions from sampler 110 and output the corresponding bits to deserializator 1180. Deserializator 1180 is configured to convert the bits into a parallel data stream, and the data stream can be output to one or more components (not shown) on the second chip 1115 for further processing. It should be understood that the second chip 1115 may include additional components not shown in FIG. 11 (e.g., impedance matching networks coupled to receive pins 1150 and 1152, clock recovery circuits, etc.).

[0082]

[0098] In the example of FIG. 11, the second chip 1115 also includes a timing signal circuit 1190 configured to generate a timing signal (e.g., clock signal CLK) for sampler 110 and output the timing signal at output 1194. Output 1194 can be coupled to the control inputs of switches 230, 240, and 245 in input circuit 120 and to the control inputs of switches 290 and 295 in the playback circuit 150 of sampler 110.

[0083]

[0099] In certain embodiments, timing signal circuit 1190 can use clock data recovery to recover a timing signal (e.g., clock signal CLK) based on the bit decisions of sampler 110. The input 1192 of timing signal circuit 1190 can be coupled to the output of latch 1170 (as shown in the example of FIG. 11), or can be coupled to one or both of the outputs 170 and 175 of sampler 110 to receive the bit decisions.

[0084]

[0100] In certain embodiments, the timing signal circuit 1190 may include a clock generator, which may include a phase locked loop (PLL), a delay locked loop (DLL), an oscillator, or any combination thereof to generate a timing signal (e.g., a clock signal CLK). It should be understood that the timing signal circuit 1190 may be implemented using various types of clock generators.

[0085]

[0101] FIG. 12 shows a method 1200 for operating a playback circuit of a sampler according to a particular embodiment. The playback circuit (e.g., playback circuit 150) includes a first inverter circuit (e.g., first inverter circuit 260) having an input and an output, a second inverter circuit (e.g., second inverter circuit 270) having an input and an output, a first transistor (e.g., first input transistor 250) coupled to the input of the second inverter circuit, a second transistor (e.g., second input transistor 255) coupled to the input of the first inverter circuit, a third transistor (e.g., third input transistor 610), and a fourth transistor (e.g., fourth input transistor 620).

[0086]

[0102] In block 1210, during the reset phase, the playback feedback of the first and second inverter circuits is disabled. For example, disabling the playback feedback of the first and second inverter circuits may include disconnecting the output of the first inverter circuit from the first transistor and disconnecting the output of the second inverter circuit from the second transistor. For example, the output of the first inverter circuit can be disconnected from the first transistor by turning off the first switch 290 (e.g., using a timing signal), and the output of the second inverter circuit can be disconnected from the second transistor by turning off the second switch 295 (e.g., using a timing signal). In another example, disabling the playback feedback of the first and second inverter circuits may include turning off the switch 296 shown in FIG. 2C.

[0087]

[0103] In block 1220, during the playback phase, the playback feedback of the first inverter circuit and the second inverter circuit is enabled. For example, enabling the playback feedback of the first inverter circuit and the second inverter circuit may include coupling the output of the first inverter circuit to the first transistor and coupling the output of the second inverter circuit to the second transistor. For example, the output of the first inverter circuit may be coupled to the first transistor by turning on the first switch 290 (e.g., using a timing signal), and the output of the second inverter circuit may be coupled to the second transistor by turning on the second switch 295 (e.g., using a timing signal). In another example, enabling the playback feedback of the first inverter circuit and the second inverter circuit may include turning on the switch 296 shown in FIG. 2C.

[0088]

[0104] In block 1230, during the playback phase, the gates of the first transistor and the third transistor are driven by a first voltage. For example, the input circuit 120 may drive the gates of the first transistor and the third transistor with a first voltage DINT.

[0089]

[0105] In block 1240, during the playback phase, the gates of the second transistor and the fourth transistor are driven by a second voltage. For example, the input circuit 120 may drive the gates of the second transistor and the fourth transistor with a second voltage NDINT.

[0090]

[0106] In block 1250, during the playback phase, the third transistor is coupled to the output of the first inverter circuit, or the fourth transistor is coupled to the output of the second inverter circuit. For example, the third switch 630 can couple the third transistor to the output of the first inverter circuit, or the fourth switch 640 can couple the fourth transistor to the output of the second inverter circuit.

[0091]

[0107] In certain embodiments, during the playback phase, the first voltage decreases at a first rate, the second voltage decreases at a second rate, and the first rate is different from the second rate. For example, the first rate can be based on a first input signal (e.g., INP) to the sampler, and the second rate can be based on a second input signal (e.g., INN) to the sampler. In one example, the first input transistor 210 of the input circuit 120 can discharge the first node 222 based on the first input signal INP to decrease the first voltage DINT at the first rate, and the second input transistor 220 of the input circuit 120 can discharge the second node 224 based on the second input signal INN to decrease the second voltage NDINT at the second rate. In this example, the gate of the first input transistor 210 can be driven by the first input signal INP, and the gate of the second input transistor 220 can be driven by the second input signal INN.

[0092]

[0108] In certain embodiments, when the first input signal is greater than the second input signal (e.g., INP > INN), the first rate is greater than the second rate, and when the second input signal is greater than the first input signal (e.g., INN > INP), the second rate is greater than the first rate.

[0093]

[0109] In certain embodiments, coupling a third transistor to the output of the first inverter circuit or coupling a fourth transistor to the output of the second inverter circuit includes coupling the third transistor to the output of the first inverter circuit based on the voltage at the input of the first inverter circuit or coupling the fourth transistor to the output of the second inverter circuit based on the voltage at the input of the second inverter circuit. For example, the control input 635 of the third switch 630 can be coupled to the input 262 of the first inverter circuit 260, and the control input 645 of the fourth switch 640 can be coupled to the input 272 of the second inverter circuit 270.

[0094]

[0110] Method 1200 may also include pulling up the first voltage and the second voltage to the supply voltage during the reset phase. For example, by turning on the second switch 240 and the third switch 245 of the input circuit 120 during the reset phase, the first voltage DINT and the second voltage NDINT can be pulled up to the supply voltage VCC.

[0095]

[0111] In the following numbered clauses, implementation examples will be described.

[0112] Clause 1.

[0113] A first inverter circuit having an input and an output,

[0114] A second inverter circuit having an input and an output,

[0115] A first transistor coupled to the input of the second inverter circuit, wherein the gate of the first transistor is coupled to the first input, the first transistor;

[0116] A second transistor coupled to the input of the first inverter circuit, wherein the gate of the second transistor is coupled to the second input, the second transistor;

[0117] A third transistor, wherein the gate of the third transistor is coupled to the first input, the third transistor;

[0118] A fourth transistor, wherein the gate of the fourth transistor is coupled to the second input, the fourth transistor;

[0119] A first switch, wherein the first switch and the third transistor are coupled in series between the first rail and the first transistor, the first switch;

[0120] A second switch, wherein the second switch and the fourth transistor are coupled in series between the first rail and the second transistor, the second switch, a playback circuit comprising.

[0121] Clause 2.

[0122] The first switch is coupled between the drain of the third transistor and the drain of the first transistor,

[0123] The playback circuit according to clause 1, wherein the second switch is coupled between the drain of the fourth transistor and the drain of the second transistor.

[0124] Clause 3.

[0125] The source of the third transistor is coupled to the first rail,

[0126] The source of the fourth transistor is coupled to the first rail,

[0127] The source of the first transistor is coupled to the second rail,

[0128] The playback circuit according to clause 2, wherein the source of the second transistor is coupled to the second rail.

[0129] Clause 4. The playback circuit according to clause 3, wherein the second rail is coupled to ground.

[0130] Clause 5.

[0131] The first transistor comprises a first n-type field effect transistor (NFET),

[0132] The second transistor comprises a second NFET,

[0133] The third transistor comprises a first p-type field effect transistor (PFET),

[0134] The playback circuit according to any one of clauses 1 to 4, wherein the fourth transistor comprises a second PFET.

[0135] Clause 6.

[0136] The first switch has a control input coupled to the input of the first inverter circuit,

[0137] The playback circuit according to any one of clauses 1 to 5, wherein the second switch has a control input coupled to the input of the second inverter circuit.

[0138] Clause 7.

[0139] The first switch comprises a first p-type field effect transistor (PFET) having a gate coupled to the input of the first inverter circuit.

[0140] The playback circuit according to clause 6, wherein the second switch comprises a second PFET having a gate coupled to the input of the second inverter circuit.

[0141] Clause 8.

[0142] A third switch coupled between the first transistor and the output of the first inverter circuit,

[0143] The playback circuit according to any one of clauses 1 to 7, further comprising a fourth switch coupled between the second transistor and the output of the second inverter circuit.

[0144] Clause 9.

[0145] The third switch has a control input configured to receive a timing signal,

[0146] The playback circuit according to clause 8, wherein the fourth switch has a control input configured to receive a timing signal.

[0147] Clause 10. The playback circuit according to clause 9, wherein the timing signal includes a clock signal.

[0148] Clause 11.

[0149] A first inverter circuit having an input and an output,

[0150] A second inverter circuit having an input and an output,

[0151] A first transistor coupled to the input of the second inverter circuit, wherein the gate of the first transistor is coupled to the first input, the first transistor,

[0152] A second transistor coupled to the input of the first inverter circuit, wherein the gate of the second transistor is coupled to the second input, the second transistor,

[0153] A pull-up circuit coupled to the input of the first inverter circuit and the input of the second inverter circuit,

[0154] A reproduction circuit comprising a pull-down circuit coupled to the input of the first inverter and the input of the second inverter.

[0155] Clause 12. The pull-up circuit is

[0156] A third transistor coupled between the input of the first inverter and the rail, wherein the gate of the third transistor is coupled to the output of the first inverter, the third transistor;

[0157] A fourth transistor coupled between the input of the second inverter and the rail, wherein the gate of the fourth transistor is coupled to the output of the second inverter, the reproduction circuit according to clause 11 comprising the fourth transistor.

[0158] Clause 13.

[0159] The third transistor comprises a first p-type field effect transistor (PFET),

[0160] The fourth transistor comprises a second PFET, the reproduction circuit according to clause 12.

[0161] Clause 14.

[0162] The source of the first PFET is coupled to the rail, the drain of the first PFET is coupled to the input of the first inverter,

[0163] The source of the second PFET is coupled to the rail, the drain of the second PFET is coupled to the input of the second inverter, the reproduction circuit according to clause 13.

[0164] Clause 15. The pull-down circuit is

[0165] A third transistor coupled between the input of the first inverter and the rail, wherein the gate of the third transistor is coupled to the input of the second inverter or the output of the first inverter, the third transistor;

[0166] A fourth transistor coupled between the input of the second inverter and the rail, wherein the gate of the fourth transistor is coupled to the input of the first inverter or the output of the second inverter, the reproduction circuit according to clause 11 comprising the fourth transistor.

[0167] Clause 16.

[0168] The third transistor includes a first n-type field effect transistor (NFET),

[0169] The fourth transistor includes a second NFET, and the playback circuit according to Clause 15.

[0170] Clause 17.

[0171] The drain of the first NFET is coupled to the input of the first inverter circuit, and the source of the first NFET is coupled to the rail,

[0172] The drain of the second NFET is coupled to the input of the second inverter circuit, and the source of the second NFET is coupled to the rail, and the playback circuit according to Clause 16.

[0173] Clause 18. The playback circuit according to any one of Clauses 15 to 17, wherein the rail is coupled to ground.

[0174] Clause 19.

[0175] A first switch coupled between the first transistor and the output of the first inverter circuit,

[0176] A second switch coupled between the second transistor and the output of the second inverter circuit, and the playback circuit according to any one of Clauses 11 to 18.

[0177] Clause 20.

[0178] The first switch has a control input configured to receive a timing signal,

[0179] The second switch has a control input configured to receive a timing signal, and the playback circuit according to Clause 19.

[0180] A method of operating a playback circuit of a sampler, the playback circuit including a first inverter circuit having an input and an output, a second inverter circuit having an input and an output, a first transistor coupled to the input of the second inverter circuit, a second transistor coupled to the input of the first inverter circuit, a third transistor, and a fourth transistor, the method comprising

[0181] During the reset phase,

[0182] disabling the playback feedback of the first inverter circuit and the second inverter circuit;

[0183] During the playback phase,

[0184] enabling the playback feedback of the first inverter circuit and the second inverter circuit;

[0185] driving the gates of the first transistor and the third transistor with a first voltage;

[0186] driving the gates of the second transistor and the fourth transistor with a second voltage;

[0187] coupling the third transistor to the output of the first inverter circuit, or coupling the fourth transistor to the output of the second inverter circuit. A method including this.

[0188] Clause 22. During the playback phase, the first voltage decreases at a first rate, the second voltage decreases at a second rate, and the first rate is different from the second rate. The method according to clause 21.

[0189] Clause 23. The first rate is based on a first input signal to the sampler, and the second rate is based on a second input signal to the sampler. The method according to clause 22.

[0190] Clause 24. When the first input signal is greater than the second input signal, the first rate is greater than the second rate; when the second input signal is greater than the first input signal, the second rate is greater than the first rate. The method according to clause 23.

[0191] Clause 25. Coupling the third transistor to the output of the first inverter circuit, or coupling the fourth transistor to the output of the second inverter circuit,

[0192] when the first rate is greater than the second rate, coupling the third transistor to the output of the first inverter circuit,

[0193] The method according to any one of clauses 22 to 24, including coupling a fourth transistor to the output of the second inverter when the second rate is greater than the first rate.

[0194] Clause 26. Coupling a third transistor to the output of the first inverter or coupling a fourth transistor to the output of the second inverter is

[0195] The method according to any one of clauses 22 to 25, including coupling a third transistor to the output of the first inverter based on the voltage at the input of the first inverter or coupling a fourth transistor to the output of the second inverter based on the voltage at the input of the second inverter.

[0196] Clause 27. The method according to any one of clauses 21 to 26, further including pulling up a first voltage and a second voltage to a supply voltage during a reset phase.

[0197] Clause 28.

[0198] The first transistor comprises a first n-type field effect transistor (NFET),

[0199] The second transistor comprises a second NFET,

[0200] The third transistor comprises a first p-type field effect transistor (PFET),

[0201] The method according to any one of clauses 21 to 27, wherein the fourth transistor comprises a second PFET.

[0202] Clause 29.

[0203] Disabling the regeneration feedback of the first inverter and the second inverter is

[0204] Disconnecting the output of the first inverter from the first transistor,

[0205] Disconnecting the output of the second inverter from the second transistor, and

[0206] Enabling the regeneration feedback of the first inverter and the second inverter is

[0207] coupling the output of the first inverter circuit to the first transistor;

[0208] The method according to any one of clauses 21 to 28, comprising coupling the output of the second inverter circuit to the second transistor.

[0209] Clause 30. The pull-down circuit

[0210] A fifth transistor coupled between the input of the first inverter circuit and the second rail, wherein the gate of the fifth transistor is coupled to the input of the second inverter circuit or the output of the first inverter circuit;

[0211] A sixth transistor coupled between the input of the second inverter circuit and the second rail, wherein the gate of the sixth transistor is coupled to the input of the first inverter circuit or the output of the second inverter circuit. The method according to any one of clauses 12 to 14, comprising:

[0212] Clause 31.

[0213] The fifth transistor comprises a first n-type field effect transistor (NFET);

[0214] The sixth transistor comprises a second NFET. The playback circuit according to clause 30.

[0215] Clause 32.

[0216] The drain of the first NFET is coupled to the input of the first inverter circuit, and the source of the first NFET is coupled to the rail;

[0217] The drain of the second NFET is coupled to the input of the second inverter circuit, and the source of the second NFET is coupled to the rail. The playback circuit according to clause 31.

[0218] Clause 33. The playback circuit according to any one of clauses 30 to 32, wherein the second rail is coupled to ground.

[0096]

[0219] It should be understood that the present disclosure is not limited to the exemplary terminology used above to describe the various aspects of the present disclosure.

[0097]

[0220] Any reference in this specification to an element using terms such as "first", "second", etc. generally does not limit the quantity or order of those elements. Rather, these terms are used in this specification as a convenient way to distinguish two or more elements, or examples of elements. Thus, a reference to a first and a second element does not mean that only two elements can be employed, or that the first element must precede the second element. Further, it should be understood that the notations such as "first", "second", etc. in this specification do not necessarily match the notations such as "first", "second", etc. in the claims.

[0098]

[0221] Within the scope of this disclosure, the term "exemplary" is used to mean "serving as an example, instance, or illustration". None of the implementations or aspects described herein as "exemplary" should necessarily be construed as being more preferred or advantageous than other aspects of this disclosure. Similarly, the term "aspect" does not require that all aspects of this disclosure include the features, advantages, or modes of operation being described. The term "about" as used herein with respect to a stated value or property is intended to indicate within 10% of the stated value or property.

[0099]

[0222] The foregoing description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the embodiments described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein. The invention described in the claims of the present application at the time of filing is appended below. [C1] A first inverter circuit having an input and an output, a second inverter circuit having an input and an output, a first transistor coupled to the input of the second inverter circuit, wherein the gate of the first transistor is coupled to a first input, the first transistor; a second transistor coupled to the input of the first inverter circuit, wherein the gate of the second transistor is coupled to a second input, the second transistor; a third transistor, wherein the gate of the third transistor is coupled to the first input, the third transistor; a fourth transistor, wherein the gate of the fourth transistor is coupled to the second input, the fourth transistor; a first switch, wherein the first switch and the third transistor are serially coupled between a first rail and the first transistor, the first switch; a second switch, wherein the second switch and the fourth transistor are serially coupled between the first rail and the second transistor, the second switch, and a playback circuit comprising the same. [C2] The first switch is coupled between the drain of the third transistor and the drain of the first transistor, the second switch is coupled between the drain of the fourth transistor and the drain of the second transistor, the playback circuit according to [C1]. [C3] The source of the third transistor is coupled to the first rail, the source of the fourth transistor is coupled to the first rail, the source of the first transistor is coupled to a second rail, the source of the second transistor is coupled to the second rail, the playback circuit according to claim 2 of [C2]. [C4] The second rail is coupled to ground, the playback circuit according to [C3]. [C5] The first transistor comprises a first n-type field effect transistor (NFET), the second transistor comprises a second NFET, The third transistor includes a first p-type field effect transistor (PFET), The reproduction circuit according to [C1], wherein the fourth transistor includes a second PFET. [C6] The first switch has a control input coupled to the input of the first inverter circuit, The reproduction circuit according to [C1], wherein the second switch has a control input coupled to the input of the second inverter circuit. [C7] The first switch includes a first p-type field effect transistor (PFET) having a gate coupled to the input of the first inverter circuit, The reproduction circuit according to [C6], wherein the second switch includes a second PFET having a gate coupled to the input of the second inverter circuit. [C8] A third switch coupled between the first transistor and the output of the first inverter circuit, The reproduction circuit according to [C1], further comprising a fourth switch coupled between the second transistor and the output of the second inverter circuit. [C9] The third switch has a control input configured to receive a timing signal, The reproduction circuit according to [C8], wherein the fourth switch has a control input configured to receive the timing signal. [C10] The reproduction circuit according to [C9], wherein the timing signal includes a clock signal. [C11] A first inverter circuit having an input and an output, A second inverter circuit having an input and an output, A first transistor coupled to the input of the second inverter circuit, wherein the gate of the first transistor is coupled to a first input, the first transistor, A second transistor coupled to the input of the first inverter circuit, wherein the gate of the second transistor is coupled to a second input, the second transistor, A pull-up circuit coupled to the input of the first inverter circuit and the input of the second inverter circuit, A reproduction circuit comprising a pull-down circuit coupled to the input of the first inverter circuit and the input of the second inverter circuit. [C12] The pull-up circuit is A third transistor coupled between the input of the first inverter circuit and a rail, wherein the gate of the third transistor is coupled to the output of the first inverter circuit, the third transistor A fourth transistor coupled between the input of the second inverter and the rail, wherein the gate of the fourth transistor is coupled to the output of the second inverter, and the playback circuit according to [C11]. [C13] The third transistor includes a first p-type field effect transistor (PFET), The fourth transistor includes a second PFET, and the playback circuit according to [C12]. [C14] The source of the first PFET is coupled to the rail, and the drain of the first PFET is coupled to the input of the first inverter, The source of the second PFET is coupled to the rail, and the drain of the second PFET is coupled to the input of the second inverter, and the playback circuit according to [C13]. [C15] The pull-down circuit is A third transistor coupled between the input of the first inverter and the rail, wherein the gate of the third transistor is coupled to the input of the second inverter or the output of the first inverter, and the third transistor, A fourth transistor coupled between the input of the second inverter and the rail, wherein the gate of the fourth transistor is coupled to the input of the first inverter or the output of the second inverter, and the playback circuit according to [C11]. [C16] The third transistor includes a first n-type field effect transistor (NFET), The fourth transistor includes a second NFET, and the playback circuit according to [C15]. [C17] The drain of the first NFET is coupled to the input of the first inverter, and the source of the first NFET is coupled to the rail, The drain of the second NFET is coupled to the input of the second inverter, and the source of the second NFET is coupled to the rail, and the playback circuit according to [C16]. [C18] The rail is coupled to ground, and the playback circuit according to [C15]. [C19] A first switch coupled between the first transistor and the output of the first inverter, A second switch coupled between the second transistor and the output of the second inverter, and the playback circuit according to [C11]. [C20] The first switch has a control input configured to receive a timing signal, The reproduction circuit according to [C19], wherein the second switch has a control input configured to receive the timing signal. [C21] A method of operating a reproduction circuit of a sampler, the reproduction circuit including a first inverter circuit having an input and an output, a second inverter circuit having an input and an output, a first transistor coupled to the input of the second inverter circuit, a second transistor coupled to the input of the first inverter circuit, a third transistor, and a fourth transistor, the method comprising: During a reset phase, Invalidating the reproduction feedback of the first inverter circuit and the second inverter circuit; During a reproduction phase, Enabling the reproduction feedback of the first inverter circuit and the second inverter circuit; Driving the gates of the first transistor and the third transistor with a first voltage; Driving the gates of the second transistor and the fourth transistor with a second voltage; Coupling the third transistor to the output of the first inverter circuit, or coupling the fourth transistor to the output of the second inverter circuit. [C22] The method according to [C21], wherein during the reproduction phase, the first voltage decreases at a first rate, the second voltage decreases at a second rate, and the first rate is different from the second rate. [C23] The method according to [C22], wherein the first rate is based on a first input signal to the sampler and the second rate is based on a second input signal to the sampler. [C24] The method according to [C23], wherein when the first input signal is greater than the second input signal, the first rate is greater than the second rate, and when the second input signal is greater than the first input signal, the second rate is greater than the first rate. [C25] Coupling the third transistor to the output of the first inverter circuit, or coupling the fourth transistor to the output of the second inverter circuit, When the first rate is greater than the second rate, coupling the third transistor to the output of the first inverter circuit, The method according to [C22], comprising coupling the fourth transistor to the output of the second inverter circuit when the second rate is greater than the first rate. [C26] Coupling the third transistor to the output of the first inverter circuit, or coupling the fourth transistor to the output of the second inverter circuit, The method according to [C22], comprising coupling the third transistor to the output of the first inverter circuit based on the voltage at the input of the first inverter circuit, or coupling the fourth transistor to the output of the second inverter circuit based on the voltage at the input of the second inverter circuit. [C27] The method according to [C21], further comprising pulling up the first voltage and the second voltage to a supply voltage during the reset phase. [C28] The first transistor comprises a first n-type field effect transistor (NFET), the second transistor comprises a second NFET, The third transistor comprises a first p-type field effect transistor (PFET), and the fourth transistor comprises a second PFET, according to the method of [C21]. [C29] Disabling the regenerative feedback of the first inverter circuit and the second inverter circuit, Disconnecting the output of the first inverter circuit from the first transistor, Disconnecting the output of the second inverter circuit from the second transistor, Enabling the regenerative feedback of the first inverter circuit and the second inverter circuit, Coupling the output of the first inverter circuit to the first transistor, The method according to [C21], comprising coupling the output of the second inverter circuit to the second transistor.

Claims

1. A first inverter circuit having an input and an output; A second inverter circuit having an input and an output; A first transistor coupled to the input of the second inverter circuit, wherein the gate of the first transistor is coupled to a first input; A second transistor coupled to the input of the first inverter circuit, wherein the gate of the second transistor is coupled to a second input; A third transistor, wherein the gate of the third transistor is coupled to the first input; A fourth transistor, wherein the gate of the fourth transistor is coupled to the second input; A first switch, wherein the first switch and the third transistor are serially coupled between a first rail and the input of the second inverter circuit; A second switch, wherein the second switch and the fourth transistor are serially coupled between the first rail and the input of the first inverter circuit, wherein the output of the first inverter circuit is electrically coupled to the input of the second inverter circuit, and the output of the second inverter circuit is electrically coupled to the input of the first inverter circuit; wherein the first switch has a control input coupled to the input of the first inverter circuit, and the second switch has a control input coupled to the input of the second inverter circuit; A playback circuit.

2. The first switch is coupled between the drain of the third transistor and the drain of the first transistor; The second switch is coupled between the drain of the fourth transistor and the drain of the second transistor, according to the playback circuit of Claim 1.

3. The source of the third transistor is coupled to the first rail; The source of the fourth transistor is coupled to the first rail; The source of the first transistor is coupled to a second rail; The source of the second transistor is coupled to the second rail, according to the playback circuit of Claim 2.

4. The second rail is coupled to ground, according to the playback circuit of Claim 3.

5. The first transistor comprises a first n-type field effect transistor (NFET); The second transistor includes a second NFET, The third transistor includes a first p-type field effect transistor (PFET), The reproduction circuit according to claim 1, wherein the fourth transistor includes a second PFET.

6. The first switch includes a first p-type field effect transistor (PFET) having a gate coupled to the input of the first inverter circuit, The reproduction circuit according to claim 1, wherein the second switch includes a second PFET having a gate coupled to the input of the second inverter circuit.

7. A third switch coupled between the input of the second inverter circuit and the output of the first inverter circuit, The reproduction circuit according to claim 1, further comprising a fourth switch coupled between the input of the first inverter circuit and the output of the second inverter circuit.

8. The third switch has a control input configured to receive a timing signal, The reproduction circuit according to claim 7, wherein the fourth switch has a control input configured to receive the timing signal.

9. The reproduction circuit according to claim 8, wherein the timing signal includes a clock signal.

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