Indium Phosphide Substrate and Semiconductor Epitaxial Wafer

Abstract

Provided are an indium phosphide substrate and a semiconductor epitaxial wafer capable of achieving both improvement in wafer alignment accuracy and suppression of chipping occurrence using an orientation flat. A disk-shaped indium phosphide substrate having a main surface, a back surface, and an orientation flat, wherein a chamfer width from the orientation flat on the main surface side is less than 90 μm, and chamfer widths from the orientation flat on the back surface side, from the edge portion on the main surface side, and from the edge portion on the back surface side are each 90 μm or more.

Description

Technical Field

[0001] The present invention relates to an indium phosphide substrate and a semiconductor epitaxial wafer.

Background Art

[0002] Indium phosphide (InP) is a III-V compound semiconductor material composed of group III indium (In) and group V phosphorus (P). Its characteristics as a semiconductor material include a bandgap of 1.35 eV and an electron mobility of ~5400 cm 2 / V·s, and it has the property that the electron mobility under high electric fields is higher than that of other common semiconductor materials such as silicon and gallium arsenide. Also, the stable crystal structure under normal temperature and pressure is a cubic zinc blende type structure, and its lattice constant has the characteristic of being larger compared to compound semiconductors such as gallium arsenide (GaAs) and gallium phosphide (GaP).

[0003] The ingot of indium phosphide used as the raw material for the indium phosphide substrate is usually sliced to a predetermined thickness, ground into a desired shape, and after appropriate mechanical polishing, it is subjected to etching, precision polishing (polishing), etc. to remove polishing debris and damage caused by polishing.

[0004] Generally, in order to indicate the crystal orientation of the indium phosphide substrate, for example, an orientation flat method is used as disclosed in Patent Document 1, in which an arcuate portion of a predetermined region of a circular substrate (wafer) is cut off to expose a surface having a specific plane orientation. A short line segment indicating the orientation is called an orientation flat. In the wafer process, various processes are performed by determining the orientation of the wafer based on the orientation flat.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] In the wafer process, the orientation flat serves as a reference for determining the orientation of the wafer. Specifically, for example, two parallel columnar jigs are pressed against the orientation flat to use the orientation flat as a reference for determining the orientation of the wafer.

[0007] Thus, the orientation flat serves as a reference for determining the orientation of the wafer, and its accuracy (alignment accuracy) is very important. However, if the distance from the intersection line between the plane including the orientation flat and the plane including the main surface to the main surface is large due to, for example, the main surface side of the orientation flat being worn, it becomes difficult to accurately determine the orientation of the wafer as described above. On the other hand, on the back side, if the distance from the intersection line between the plane including the orientation flat and the plane including the back surface to the back surface is small, there is a risk of defects such as chipping occurring.

[0008] Here, conventionally, at the edge portion of the wafer including the orientation flat, chamfering of the same shape is performed on both the main surface side and the back surface side, and there is a problem that it is difficult to achieve both improvement in the alignment accuracy of the wafer using the above-described orientation flat and suppression of chipping occurrence.

[0009] The present invention has been made to solve the above problems, and an object thereof is to provide an indium phosphide substrate and a semiconductor epitaxial wafer capable of achieving both improvement in the alignment accuracy of a wafer using an orientation flat and suppression of chipping occurrence.

Means for Solving the Problems

[0010] The above problems are solved by the embodiments of the present invention specified as follows. 1. A disk-shaped indium phosphide substrate having a main surface, a back surface, and an orientation flat, wherein the chamfering width from the orientation flat on the main surface side is less than 90 μm, and the indium phosphide substrate, wherein the chamfering width from the orientation flat on the back surface side, the chamfering width from the edge portion on the main surface side, and the chamfering width from the edge portion on the back surface side are each 90 μm or more. 2. The indium phosphide substrate according to 1, wherein the chamfering width from the orientation flat on the main surface side is less than 60 μm, and the chamfering width from the orientation flat on the back surface side, the chamfering width from the edge portion on the main surface side, and the chamfering width from the edge portion on the back surface side are each 100 μm or more. 3. The orientation flat is a surface inclined from the back surface, and a surface having a curvature starting from the position where the surface inclined from the back surface ends The indium phosphide substrate according to 1 or 2, which has. 4. The edge portion on the back surface side is a surface inclined from the back surface, and a surface having a curvature starting from the position where the surface inclined from the back surface ends The indium phosphide substrate according to any one of 1 to 3, which has. 5. The edge portion on the main surface side is a surface inclined from the main surface, and a surface having a curvature starting from the position where the surface inclined from the main surface ends The indium phosphide substrate according to any one of 1 to 4, which has. 6. A semiconductor epitaxial wafer having the indium phosphide substrate according to any one of 1 to 5 and an epitaxial crystal layer provided on the main surface of the indium phosphide substrate.

Advantages of the Invention

[0011] According to an embodiment of the present invention, it is possible to provide an indium phosphide substrate and a semiconductor epitaxial wafer that can achieve both improvement in wafer alignment accuracy using an orientation flat and suppression of chipping occurrence.

Brief Description of the Drawings

[0012]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Embodiments for Carrying Out the Invention

[0013] 〔Indium Phosphide Substrate〕 Hereinafter, the configuration of the indium phosphide substrate of the present embodiment will be described. FIG. 1(A) shows a schematic cross-sectional view of an indium phosphide substrate (InP substrate) according to an embodiment of the present invention, and FIG. 1(B) shows a schematic plan view. Note that FIG. 1 is a drawing for understanding the main surface, back surface, orientation flat, and edge portion of the indium phosphide substrate according to an embodiment of the present invention, and these do not directly show the indium phosphide substrate according to the embodiment of the present invention.

[0014] The indium phosphide substrate of the present embodiment is a disk-shaped substrate having a main surface, a back surface, and an edge portion. A part of the edge portion has an orientation flat (OF) indicating the crystal orientation. The edge portion may further have an index flat (IF) for distinguishing between the main surface and the back surface of the substrate.

[0015] The main surface of the indium phosphide substrate can be a surface for forming an epitaxial crystal layer. The surface for forming the epitaxial crystal layer is the surface on which epitaxial growth is actually carried out when the indium phosphide substrate of the present embodiment is used as a substrate for epitaxial growth for the formation of a semiconductor element structure.

[0016] The maximum diameter of the main surface of the indium phosphide substrate is not particularly limited, but it may be 49 to 152.4 mm, or may be 49 to 101 mm.

[0017] The thickness of the indium phosphide substrate is not particularly limited, but for example, it is preferably 300 to 900 μm, and more preferably 300 to 700 μm. Particularly when the aperture is large, if the indium phosphide substrate is less than 300 μm, there is a risk of cracking, and if it exceeds 900 μm, there may be a problem that the base crystal becomes wasted.

[0018] The indium phosphide substrate of the present embodiment contains Zn (zinc) as a dopant (impurity) such that the carrier concentration is 1×10 16 cm -3 or more and 1×10 19 cm -3 or less, may contain S (sulfur) such that the carrier concentration is 1×10 16 cm -3 or more and 1×10 19 cm -3 or less, may contain Sn (tin) such that the carrier concentration is 1×10 16 cm -3 or more and 1×10 19 cm -3 or less, may contain Fe (iron) such that the carrier concentration is 1×10 6 cm -3Above 1×10 9 cm -3 It may be included so as to be below.

[0019] FIG. 2 shows an example of a cross-sectional schematic view of an indium phosphide substrate according to an embodiment of the present invention. In the cross-section of the wafer edge, as shown in FIG. 2, the corners of the rectangle are chamfered (beveled) and are curved.

[0020] In the indium phosphide substrate according to the embodiment of the present invention, the chamfer width W1 from the orientation flat on the main surface side is controlled to be less than 90 μm. The orientation flat is a reference for determining the orientation of the wafer. When the chamfer width W1 from the orientation flat on the main surface side is less than 90 μm, the alignment accuracy of the wafer of the orientation flat is improved. The chamfer width W1 from the orientation flat on the main surface side is preferably less than 60 μm, more preferably less than 30 μm, and still more preferably less than 10 μm.

[0021] In the indium phosphide substrate according to an embodiment of the present invention, the chamfer width w2 from the orientation flat on the back surface side, the chamfer width w3 from the edge portion on the main surface side, and the chamfer width w4 from the edge portion on the back surface side are each controlled to be 90 μm or more. When the chamfer width w2 from the orientation flat on the back surface side, the chamfer width w3 from the edge portion on the main surface side, and the chamfer width w4 from the edge portion on the back surface side are each 90 μm or more, the occurrence of defects such as chipping can be favorably suppressed. The chamfer width w2 from the orientation flat on the back surface side, the chamfer width w3 from the edge portion on the main surface side, and the chamfer width w4 from the edge portion on the back surface side are each preferably 100 μm or more, more preferably 150 μm or more, and even more preferably 200 μm or more. The upper limit of the chamfer width w2 from the orientation flat on the back surface side, the chamfer width w3 from the edge portion on the main surface side, and the chamfer width w4 from the edge portion on the back surface side is preferably 600 μm or less, and more preferably 300 μm or less, from the viewpoint of the effective area of the indium phosphide substrate.

[0022] The chamfer width w2 from the orientation flat on the back surface side, the chamfer width w3 from the edge portion on the main surface side, and the chamfer width w4 from the edge portion on the back surface side may each be the same value as each other or may be different values from each other. Also, from the viewpoint of manufacturing efficiency, it is preferable that the chamfer width w2 from the orientation flat on the back surface side and the chamfer width w4 from the edge portion on the back surface side are the same value. Further, the chamfer width w3 from the edge portion on the main surface side and the chamfer width w4 from the edge portion on the back surface side are each formed over the entire circumference of the edge portion other than the orientation flat in the disk-shaped indium phosphide substrate.

[0023] FIG. 3 shows a schematic cross-sectional view of the orientation flat side of an indium phosphide substrate according to an embodiment of the present invention. The orientation flat of the indium phosphide substrate according to the embodiment of the present invention preferably has a surface inclined from the back surface and a surface having a curvature starting from a position where the surface inclined from the back surface ends. Here, the "surface having a curvature starting from a position where the surface inclined from the back surface ends" is, as shown in FIG. 3, a surface having a curvature from the position where the surface inclined from the back surface ends to the central position of the orientation flat, and is a surface that forms an arc region of the orientation flat. With such a configuration, compared to the case where the entire surface of the orientation flat has a curved surface, the inclined surface can reach a position further away from the orientation flat, so that the occurrence of chipping can be more effectively suppressed.

[0024] Further, the edge portion on the back surface side of the indium phosphide substrate according to the embodiment of the present invention (the edge portion excluding the orientation flat) preferably has a surface inclined from the back surface and a surface having a curvature starting from a position where the surface inclined from the back surface ends. The "surface having a curvature starting from a position where the surface inclined from the back surface ends" is as described above with reference to FIG. 3. With such a configuration, compared to the case where the entire surface of the edge portion other than the orientation flat on the back surface side has a curved surface, the inclined surface can reach a position further away from the edge portion, so that the occurrence of chipping can be more effectively suppressed.

[0025] The chamfered width from the orientation flat on the back surface side and the chamfered width from the edge portion on the back surface side of the surface inclined from the back surface of the edge portion excluding the above-mentioned orientation flat or the surface having a curvature starting from the position where the surface inclined from the back surface ends can be appropriately designed as long as they are each 90 μm or more. For example, although not particularly limited, the surface inclined from the back surface may occupy 5 to 20% of the thickness of the substrate, and the inclination angle of the surface having a curvature starting from the position where the surface inclined from the back surface ends may be 5 to 30°. Also, the radius of curvature R of the surface having a curvature starting from the position where the surface inclined from the back surface ends is not particularly limited, but may be 100 to 300 μm.

[0026] Further, the edge portion (the edge portion excluding the orientation flat) on the main surface side of the indium phosphide substrate according to the embodiment of the present invention preferably has a surface inclined from the main surface and a surface having a curvature starting from the position where the surface inclined from the main surface ends. The "surface having a curvature starting from the position where the surface inclined from the main surface ends" is as described above. With such a configuration, compared with the case where the entire surface of the edge portion other than the orientation flat on the main surface side is a surface having a curvature, the inclined surface can reach a position farther from the edge portion, so that the occurrence of chipping can be more effectively suppressed. The surface inclined from the main surface may occupy 5 to 20% of the thickness of the substrate, and the inclination angle of the surface inclined from the main surface may be 5 to 30°. Also, the radius of curvature R of the surface having a curvature starting from the position where the surface inclined from the main surface ends is not particularly limited, but may be 100 to 300 μm.

[0027] 〔Method for manufacturing indium phosphide substrate〕 Next, the method for manufacturing an indium phosphide substrate according to the embodiment of the present invention will be described. As a method for manufacturing an indium phosphide substrate, first, an ingot of indium phosphide is produced by a known method. Next, the indium phosphide ingot is ground into a cylinder. At this time, an orientation flat (OF) is formed at a predetermined position on the outer peripheral portion of the wafer. Next, a wafer having a main surface and a back surface is cut out from the ground indium phosphide ingot. At this time, both ends of the crystal of the indium phosphide ingot are cut along a predetermined crystal plane using a wire saw or the like, and a plurality of wafers are cut out to a predetermined thickness.

[0028] Next, in order to remove the machined damaged layer generated in the cutting process by the wire saw, the cut wafer is subjected to double-sided etching (primary etching) with a predetermined etching solution. The wafer can be etched by immersing the entire wafer in the etching solution. Note that the primary etching may be omitted.

[0029] Next, chamfering of the outer peripheral portion of the wafer is performed. As shown in FIG. 4, the chamfering of the outer peripheral portion of the wafer is performed by placing the wafer on a support base, adsorbing it to the support base, rotating it while rotating a grindstone that rotates in the opposite direction to the wafer against the outer peripheral portion of the wafer, and machining it into a desired shape. As the grindstone, it is preferable to use a grindstone with a grit size of #600 to #2000.

[0030] Here, FIG. 5 shows a schematic diagram illustrating the chamfering of the outer peripheral portion of the wafer using a grinding stone. FIG. 5 is an image diagram for showing the chamfering on the main surface side of the wafer, the grinding of the outer peripheral portion, and the chamfering on the back surface side. The side surface of the contact portion of the grinding stone with the wafer has a central flat surface and surfaces (inclined surfaces) that extend inclined so as to spread vertically upward and downward from the flat surface as shown in FIG. 5, and the chamfering on the main surface side and the back surface side of the wafer is performed using the inclined surfaces. The grinding stone is fixed in the vertical direction, and by moving the wafer up and down with a support base, the edge portion of the rotating wafer is ground. By finely changing the contact position of the wafer with the inclined surface of the grinding stone between the orientation flat of the wafer and the edge portion other than the orientation flat, fine control of the chamfering width can be performed. As a result, the chamfering width W1 from the orientation flat on the main surface side can be made less than 90 μm, and the chamfering widths W2 from the orientation flat on the back surface side, W3 from the edge portion on the main surface side, and W4 from the edge portion on the back surface side can be controlled to be 90 μm or more, respectively. Also, for the orientation flat or the edge portion other than the orientation flat, it can be processed into a shape having a surface inclined from the back surface and a surface having a curvature starting from the position where the surface inclined from the back surface ends.

[0031] After chamfering, at least one surface of the wafer, preferably both surfaces, may be polished. This polishing process is also called a lapping process, and by polishing with a predetermined polishing agent, the unevenness on the wafer surface is removed while maintaining the flatness of the wafer.

[0032] Subsequently, both surfaces of the wafer are etched (secondary etching) with a predetermined etching solution. The wafer can be etched by immersing the entire wafer in the etching solution. Next, the main surface of the wafer is polished with a polishing material for mirror polishing to finish it into a mirror surface. Next, by performing cleaning, an indium phosphide substrate according to an embodiment of the present invention is manufactured.

[0033] 〔Semiconductor Epitaxial Wafer〕 An epitaxial crystal layer can be formed and a semiconductor epitaxial wafer can be fabricated by epitaxially growing a semiconductor thin film on the main surface of an indium phosphide substrate according to an embodiment of the present invention by a known method. As an example of such epitaxial growth, a HEMT structure in which an InAlAs buffer layer, an InGaAs channel layer, an InAlAs spacer layer, and an InP electron supply layer are epitaxially grown on the main surface of an indium phosphide substrate may be formed. When fabricating a semiconductor epitaxial wafer having such a HEMT structure, generally, a mirror-finished indium phosphide substrate is subjected to an etching treatment with an etching solution such as sulfuric acid / hydrogen peroxide water to remove impurities such as silicon (Si) attached to the substrate surface. With the back surface of the indium phosphide substrate after this etching treatment in contact with and supported by a susceptor, an epitaxial film is formed on the main surface of the indium phosphide substrate by molecular beam epitaxy (MBE) or metal organic chemical vapor deposition (MOCVD).

Example

[0034] Examples are provided below to better understand the present invention and its advantages, but the present invention is not limited to these examples.

[0035] (Example 1) First, a single crystal ingot of indium phosphide grown with a predetermined diameter was prepared. Next, the outer periphery of the single crystal ingot of indium phosphide was ground to form a cylinder. At this time, an orientation flat (OF) was formed at a predetermined position on the outer peripheral portion of the wafer.

[0036] Next, a wafer having a main surface and a back surface was cut out from the ground indium phosphide ingot. At this time, both ends of the crystal of the indium phosphide ingot were cut along a predetermined crystal plane using a wire saw, and a plurality of wafers were cut out to a predetermined thickness. In the process of cutting out the wafer, while reciprocating the wire, a new wire was continuously fed, and indium phosphide was moved to the wire saw. The wafer diameter of the wafer fabricated here was 51.8 mm, and the wafer thickness was 350 μm.

[0037] Next, in order to remove the processed and deteriorated layer generated in the cutting process by the wire saw, the cut wafer was etched from both sides with a mixed solution of an aqueous phosphoric acid solution of 85% by mass and an aqueous hydrogen peroxide solution of 30% by mass (primary etching). The wafer was etched by immersing the entire wafer in the etching solution.

[0038] Next, chamfering of the outer peripheral portion of the wafer was performed. As shown in FIG. 4, the chamfering of the outer peripheral portion of the wafer was performed by grinding while rotating the wafer in a state where the wafer was placed on a support base and adsorbed to the support base, and bringing a grinding wheel rotating in the opposite direction to the wafer into contact with the outer peripheral portion of the wafer. The side surface of the contact portion of the grinding wheel with the wafer had a flat surface at the center and surfaces (inclined surfaces) inclined and extending in the vertical direction from the flat surface as shown in FIG. 5. The chamfering of the main surface side and the back surface side of the wafer was performed using the inclined surfaces. The grit size of the grinding wheel used was #1200. Subsequently, chamfering of the OF portion was performed. In the case of chamfering the OF portion, the grinding wheel distance and the vertical position of the support base of the wafer were controlled, programmed, and sequence-controlled so that the linear OF portion of the wafer and the rotating grinding wheel were always in contact. In the chamfering of the OF portion, the grit size of the grinding wheel was set to #1200. In this way, the chamfering width W1 was controlled by always grinding the chamfering of the linear OF portion with the grinding wheel in contact with the OF portion and controlling the grinding amount at that time with good controllability.

[0039] Next, both surfaces of the chamfered wafer were polished (lapped). At this time, by polishing with an abrasive, the unevenness on the wafer surface was removed while maintaining the flatness of the wafer.

[0040] Next, the polished wafer was etched with a mixed solution of an 85% by mass phosphoric acid aqueous solution, a 30% by mass hydrogen peroxide aqueous solution, and ultrapure water from both sides with a total etching amount of 8 to 15 μm in thickness (secondary etching). The wafer was etched by immersing the entire wafer in the etching solution.

[0041] Next, the main surface of the wafer was polished (polished) with a polishing material for mirror polishing to finish it into a mirror surface, and then washed to produce a disk-shaped indium phosphide substrate having an orientation flat according to Example 1. The indium phosphide substrate according to Example 1 had a maximum diameter of the main surface of 50.8 mm and a thickness of 350 μm.

[0042] (Comparative Example 1) As Comparative Example 1, a disk-shaped indium phosphide substrate having an orientation flat was produced in the same manner as in Example 1 described above, except that the chamfering width was controlled to the value shown in Table 1 in the chamfering step of the outer peripheral portion of the wafer.

[0043] (Evaluation) The side surfaces of the indium phosphide substrates according to Example 1 and Comparative Example 1 were measured at a magnification of 2 using a wafer edge profile measuring device (Wafer Edge Profile Checker model EPRO-212EN V4 manufactured by SPEED FAM). The measurement results are shown in Table 1.

[0044]

Table 1

[0045] Next, using the orientation flats of the indium phosphide substrates according to Example 1 and Comparative Example 1, alignment is performed using an optical microscope from above the substrates. As a result, it is considered that the indium phosphide substrate according to Example 1 can accurately fix (align) the installation position of the substrate. On the other hand, for the indium phosphide substrate according to Comparative Example 1, even when aligning the substrate with an optical microscope, the chamfer width of the OF portion is large, it is difficult to accurately focus on the end of the OF, and it is considered that the installation position of the substrate cannot be accurately fixed (aligned). From the above, as in Example 1, when the chamfer width from the orientation flat on the main surface side is less than 90 μm, the alignment accuracy of the wafer using the orientation flat is improved, and as in Comparative Example 1, when the chamfer width from the orientation flat on the main surface side is 90 μm or more, it can be seen that the alignment accuracy of the wafer using the orientation flat decreases. Also, for the indium phosphide substrate according to Example 1, since the chamfer width W2 from the orientation flat on the back surface side, the chamfer width W3 from the edge portion on the main surface side, and the chamfer width W4 from the edge portion on the back surface side are each 90 μm or more, it can be seen that chipping generation is well suppressed.

[0046] According to an embodiment of the present invention, it is possible to achieve both an improvement in the alignment accuracy of a wafer using an orientation flat and suppression of chipping generation. Since the InP substrate is a member used as a material for light-emitting and light-receiving elements for optical communication, etc., an embodiment of the present invention may contribute to the advancement of optical communication technology. For this reason, an embodiment of the present invention may contribute to Goal 9 of the Sustainable Development Goals (SDGs) led by the United Nations, "Build resilient infrastructure, promote inclusive and sustainable industrialization, and foster innovation."

Claims

1. A disk-shaped indium phosphide substrate having a main surface, a back surface, and an orientation flat, wherein the chamfering width from the orientation flat on the main surface side is 33 μm or more and less than 90 μm, and the chamfering width from the orientation flat on the back surface side, the chamfering width from the edge portion on the main surface side, and the chamfering width from the edge portion on the back surface side are each 90 μm or more. An indium phosphide substrate.

2. The indium phosphide substrate according to claim 1, wherein the chamfering width from the orientation flat on the main surface side is 33 μm or more and less than 60 μm, and the chamfering width from the orientation flat on the back surface side, the chamfering width from the edge portion on the main surface side, and the chamfering width from the edge portion on the back surface side are each 100 μm or more.

3. The orientation flat has a surface inclined from the back surface, and a surface having a curvature starting from the position where the surface inclined from the back surface ends The indium phosphide substrate according to claim 1.

4. The edge portion on the back surface side has a surface inclined from the back surface, and a surface having a curvature starting from the position where the surface inclined from the back surface ends The indium phosphide substrate according to claim 1.

5. The edge portion on the main surface side has a surface inclined from the main surface, and a surface having a curvature starting from the position where the surface inclined from the main surface ends The indium phosphide substrate according to claim 1.

6. A semiconductor epitaxial wafer having the indium phosphide substrate according to any one of claims 1 to 5 and an epitaxial crystal layer provided on the main surface of the indium phosphide substrate.

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