Method for Evaluating Semiconductor Sample

Abstract

To provide a new method for evaluating semiconductor samples with which it is possible to determine with good accuracy the lifetime value of semiconductor epitaxial layers on a semiconductor substrate.SOLUTION: Provided is a method for evaluating a semiconductor sample that has a semiconductor epitaxial layer on a semiconductor single crystal substrate. The method includes: producing a laminate structure by forming a p+ layer or a n+ layer whose conductivity type is the same as or different from the semiconductor epitaxial layer on the semiconductor epitaxial layer or in the surface region of the semiconductor epitaxial layer, the semiconductor single crystal substrate being a n+ substrate and the semiconductor epitaxial layer being a n- layer, the semiconductor single crystal substrate being a p+ substrate and the semiconductor epitaxial layer being a p- layer, the semiconductor single crystal substrate being a n+ substrate and the semiconductor epitaxial layer being a p- layer, or the semiconductor single crystal substrate being a p+ substrate and the semiconductor epitaxial layer being a n- layer; forming a p+ / n- / n+ diode, n+ / p- / p+ diode, p+ / p- / n+ diode, or n+ / n- / p+ diode having a mesa structure by pattering processing of the laminate structure; performing OCVD measurement with regards to the diodes; and determining the lifetime value of the semiconductor epitaxial layer by a prescribed formula from the measurement results obtained by the OCVD measurement.SELECTED DRAWING: None

Description

Technical Field

[0001] The present invention relates to a method for evaluating a semiconductor sample.

Background Art

[0002] Regarding a semiconductor sample having a semiconductor epitaxial layer on a semiconductor substrate, methods for obtaining the lifetime value (specifically, the recombination lifetime value) of the semiconductor epitaxial layer have been proposed in Patent Document 1 and Non-Patent Document 1.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Non-Patent Documents

[0004]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In the method described in Patent Document 1, the lifetime value is obtained by the μ-PCD (μ-wave photo conductivity decay) method. On the other hand, in the method described in Non-Patent Document 1, the lifetime value is obtained by OCVD (open-circuit voltage decay) measurement.

[0006] If the lifetime value of the semiconductor epitaxial layer of the semiconductor sample can be accurately obtained, it is desirable from the viewpoints of quality control of the semiconductor sample, manufacturing process management, and the like.

[0007] One aspect of the present invention aims to provide a new method for evaluating a semiconductor sample, which can accurately determine the lifetime value of a semiconductor epitaxial layer on a semiconductor substrate.

[0008] In the measurement of the lifetime value by the μ-PCD method described in Patent Document 1, the diffusion of the injected carriers in the semiconductor epitaxial layer into the semiconductor substrate can cause a decrease in the measurement accuracy of the lifetime value. Further, in the μ-PCD method, since the change in the conductivity in the entire thickness direction of the semiconductor sample after carrier injection is detected by microwaves, it is not possible to detect the change in the conductivity of only the semiconductor epitaxial layer. Also, depending on the resistivity of the substrate, microwaves are totally reflected, and in this case, it is difficult to accurately evaluate the lifetime value of only the semiconductor epitaxial layer. In consideration of the above points, the present inventors focused on the measurement of the lifetime value by the OCVD method and conducted intensive studies to improve its measurement accuracy. As a result, the following new evaluation method was found.

[0009] That is, one aspect of the present invention is as follows. [1] A method for evaluating a semiconductor sample having a semiconductor epitaxial layer on a semiconductor single crystal substrate, wherein the semiconductor single crystal substrate is an n + substrate and the semiconductor epitaxial layer is an n - layer, or the semiconductor single crystal substrate is a p + substrate and the semiconductor epitaxial layer is a p - layer, or the semiconductor single crystal substrate is an n + substrate and the semiconductor epitaxial layer is a p - layer, or the semiconductor single crystal substrate is a p + substrate and the semiconductor epitaxial layer is an n - layer, and on the semiconductor epitaxial layer or in the surface layer region of the semiconductor epitaxial layer, a p + layer or an n layer having the same or different conductivity type as the semiconductor epitaxial layer+ Fabricating a stacked structure by forming layers, Performing a patterning process on the stacked structure to obtain a mesa structure having a p + / n - / n + diode, n + / p - / p + / p diode, p + / p - / n + diode or n + / n - / p + Forming a diode, Performing OCVD measurement on the diode, and From the measurement results obtained by the OCVD measurement, for the state of n s >N d - For the state of, the lifetime value of the semiconductor epitaxial layer is obtained by the following formula (A) for n s <N d - For the state of, the lifetime value of the semiconductor epitaxial layer is obtained by the following formula (C), A method for evaluating a semiconductor sample, including.

Equation

Number

Number

Number

Number

Effect of the Invention

[0010] According to one aspect of the present invention, a new evaluation method of a semiconductor sample can be provided, which can accurately obtain the lifetime value of a semiconductor epitaxial layer on a semiconductor substrate.

Brief Description of the Drawings

[0011]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Mode for Carrying Out the Invention

[0012] The evaluation method of the above semiconductor sample will be further described in detail below.

[0013] <Semiconductor sample> The semiconductor sample evaluated by the above evaluation method is a semiconductor sample having a semiconductor epitaxial layer on a semiconductor single crystal substrate. In the present invention and this specification, the "semiconductor epitaxial layer" refers to an epitaxial layer of a semiconductor single crystal, and is simply also referred to as an "epitaxial layer". For example, the above semiconductor can be silicon, the above semiconductor single crystal substrate can be a silicon single crystal substrate, and the above semiconductor epitaxial layer can be a silicon epitaxial layer.

[0014] The shape of the semiconductor sample can be, for example, a wafer shape. That is, in one form, the semiconductor sample can be an epitaxial wafer. Also, in another form, the shape of the semiconductor sample can be any shape other than a wafer shape. For example, the semiconductor sample can also be a semiconductor sample cut out from an epitaxial wafer into any shape and size.

[0015] One form of the semiconductor sample is a semiconductor sample in which the semiconductor single crystal substrate is an n + substrate and the epitaxial layer is an n - layer. That is, it is a semiconductor sample having an n-type epitaxial layer with a lower dopant concentration and a higher resistivity than the substrate on an n-type semiconductor single crystal substrate. n + The dopant concentration of the substrate is preferably high, for example, in the range of 5×10 15 ~5×10 21 atoms / cm 3 . The dopant concentration described in this specification is a value measured by a known method. The dopant concentration of the n - epitaxial layer is preferably, for example, in the range of 4×10 12 ~5×10 14 atoms / cm 3 . Examples of the dopant for the n-type substrate and the n-type epitaxial layer include group V elements such as phosphorus (P), arsenic (As), and antimony (Sb).

[0016] Also, another form of the semiconductor sample is a semiconductor sample in which the semiconductor single crystal substrate is a p + substrate and the epitaxial layer is a p - layer. That is, it is a semiconductor sample having a p-type epitaxial layer with a lower dopant concentration and a higher resistivity than the substrate on a p-type semiconductor single crystal substrate. p + The dopant concentration of the substrate is preferably high, for example, in the range of 1×10 16 ~4×10 21 atoms / cm 3 . The dopant concentration of the p - epitaxial layer is, for example, 1×1013 ~1×10 15 atoms / cm 3 It is preferably in the range of. Examples of the dopant for the p-type substrate and the p-type epitaxial layer include group III elements such as boron (B).

[0017] Another form of the semiconductor sample is a semiconductor single crystal substrate that is an n + substrate and an epitaxial layer that is a p - layer. That is, it is a semiconductor sample having a p-type epitaxial layer with a lower dopant concentration and a higher resistivity than the substrate on an n-type semiconductor single crystal substrate. The dopant concentration of the n + substrate is preferably high. For example, 5×10 15 ~5×10 21 atoms / cm 3 It is preferably in the range of. The dopant concentration of the p - epitaxial layer is, for example, 1×10 13 ~1×10 15 atoms / cm 3 It is preferably in the range of. Examples of the dopant for the n-type substrate include group V elements such as phosphorus (P), arsenic (As), and antimony (Sb). Examples of the dopant for the p-type epitaxial layer include group III elements such as boron (B).

[0018] Another form of the semiconductor sample is a semiconductor single crystal substrate that is a p + substrate and an epitaxial layer that is an n - layer. That is, it is a semiconductor sample having an n-type epitaxial layer with a lower dopant concentration and a higher resistivity than the substrate on a p-type semiconductor single crystal substrate. The dopant concentration of the p + substrate is preferably high. For example, 1×10 16 ~4×10 21 atoms / cm 3 It is preferably in the range of. The dopant concentration of the n - epitaxial layer is, for example, 4×10 12 ~5×10 14 atoms / cm 3It is preferably within the range. Examples of the dopant for the p-type substrate include group III elements such as boron (B). Examples of the dopant for the n-type epitaxial layer include group V elements such as phosphorus (P), arsenic (As), and antimony (Sb).

[0019] Regarding the dopant concentration, the greater the difference between the dopant concentration of the semiconductor single crystal substrate and the dopant concentration of the epitaxial layer, the higher the built-in potential generated by the semiconductor single crystal substrate and the epitaxial layer, and thus the carriers can be more strongly confined by the epitaxial layer, and the measurement accuracy of the lifetime value can be further improved. From this point of view, the ratio of the dopant concentration (semiconductor single crystal substrate / epitaxial layer) is preferably 100 or more.

[0020] The thickness of the semiconductor single crystal substrate is not particularly limited and can be, for example, in the range of 610 to 795 μm. The thickness of the epitaxial layer is also not particularly limited. When the epitaxial layer is thin, due to the influence of the diffusion of carriers immediately after carrier injection, the injected carriers tend to diffuse easily into the epitaxial layer or the layer formed in the surface layer region of the epitaxial layer. From this point of view, the thickness of the epitaxial layer is preferably, for example, 10 μm or more. Also, the thickness of the epitaxial layer can be, for example, 100 μm or less. The size of the semiconductor sample is not particularly limited as long as it is a size that can be introduced into the measuring device for measuring the lifetime value.

[0021] <Fabrication of Diodes> In the above evaluation method, the semiconductor sample is processed by the method described in detail below to form a mesa structure of p + / n - / n + diode, an n + / p - / p + diode, a p + / p - / n + diode or an n + / n- / p + Fabricate a diode and perform OCVD measurement on this diode.

[0022] (Fabrication of laminated structure) First, a laminated structure is fabricated by forming a layer having the same or different conductivity type as the epitaxial layer and having a lower resistivity than the epitaxial layer on or in the surface region of the epitaxial layer of the semiconductor sample. That is, For a semiconductor sample in which the semiconductor single crystal substrate is an n + substrate and the epitaxial layer is an n - layer, a p + layer is formed, For a semiconductor sample in which the semiconductor single crystal substrate is a p + substrate and the epitaxial layer is a p - layer, an n + layer is formed, For a semiconductor sample in which the semiconductor single crystal substrate is an n + substrate and the epitaxial layer is a p - layer, a p + layer is formed, For a semiconductor sample in which the semiconductor single crystal substrate is a p + substrate and the epitaxial layer is an n - layer, an n + layer is formed. From the viewpoint of increasing the carrier injection amount into the epitaxial layer, it is preferable that the sheet resistance of the formed layer is small (in other words, the dopant concentration is high). For example, the dopant concentration per unit area of the formed layer is 1.0×10 13 atoms / cm 2 or more and 1.0×10 17 atoms / cm 2 or less.

[0023] n + For a semiconductor sample having an n - epitaxial layer on an n + substrate, the formed p p +The formation of the layer can be carried out by the CVD method in one form, and it is more preferable to form the p + layer by epitaxial growth. In another form, ion implantation is performed on the surface layer region of the n + epitaxial layer on the n - substrate, so that the surface layer region of the n + epitaxial layer on the n - substrate can be made into a p + layer. From the viewpoint of maintaining the thickness of the epitaxial layer, the CVD method is preferable. The above p + layer can be a p + semiconductor epitaxial layer formed by epitaxial growth on the n - epitaxial layer on the n + substrate.

[0024] For a semiconductor sample having a p + epitaxial layer on the p - substrate, the formed n + layer can be a semiconductor single crystal layer, and it is preferably a semiconductor epitaxial layer. Regarding the formation of the n + layer here, reference can be made to the description regarding the formation of the above p + layer. The above n + layer is preferably an n + semiconductor epitaxial layer formed by epitaxial growth on the p - epitaxial layer on the p + substrate.

[0025] For a semiconductor sample having a p + epitaxial layer on the n - substrate, the formed p + layer can be a semiconductor single crystal layer, and it is preferably a semiconductor epitaxial layer. Regarding the formation of the p + layer here, reference can be made to the description regarding the formation of the above p + layer. The above p + layer is preferably a p + semiconductor epitaxial layer formed by epitaxial growth on the p - epitaxial layer on the n +It is preferably a semiconductor epitaxial layer.

[0026] p + On the substrate, n - Regarding a semiconductor sample having an epitaxial layer, the formed n + layer can be a semiconductor single crystal layer, and is preferably a semiconductor epitaxial layer. Here, for the formation of the n + layer, reference can be made to the description regarding the formation of the above p + layer. For the above n + layer, it is the p + n on the p substrate - An n semiconductor epitaxial layer formed by epitaxial growth on the epitaxial layer + is preferably a semiconductor epitaxial layer.

[0027] The above p + layer and the above n + layer thickness can each be, for example, 1 μm or more and 10 μm or less and respectively.

[0028] (Patterning process of the above laminated structure) Thereafter, by patterning the laminated structure fabricated above, a plurality of diodes having a mesa structure are formed. The above diodes When the semiconductor single crystal substrate is an n + substrate and the semiconductor epitaxial layer is an n - epitaxial layer, it is a "p + / n - / n + diode", When the semiconductor single crystal substrate is a p + substrate and the semiconductor epitaxial layer is a p - epitaxial layer, it is an "n + / p - / p + diode", When the semiconductor single crystal substrate is an n + substrate and the semiconductor epitaxial layer is a p - epitaxial layer, it is a "p + / p - / n+ is a "diode", a semiconductor single crystal substrate is p + substrate and a semiconductor epitaxial layer is n - in the case of an epitaxial layer, "n + / n - / p + diode". The patterning process can be performed by known methods, such as photolithography and etching. In the formed diode, the junction area of the pn junction can be in the range of, for example, 0.01 to 1 cm 2 . Here, the "junction area" refers to the area of the junction interface between the p + layer and the n - epitaxial layer, the junction interface between the n + layer and the p - epitaxial layer, the junction interface between the p - epitaxial layer and the n + substrate, or the junction interface between the n - epitaxial layer and the p + substrate. The junction area can be adjusted by the mask used during photolithography. The mesa structure is preferably a forward mesa structure. The forward mesa structure is a mesa structure in which the upper side of the substantially trapezoidal cross-sectional shape is shorter than the lower side. As an example, FIG. 1 shows an example of forming a plurality of p + / n - / n 2 diodes with a forward mesa structure having a junction area of 0.04 cm + (0.2 cm × 0.2 cm) on an epitaxial wafer (having an n - semiconductor single crystal substrate with an n + semiconductor epitaxial layer) with a diameter of 200 mm. However, the example shown in FIG. 1 is only an example, and the number and formation positions of the formed p + / n - / n + diodes are not limited to the example shown in FIG. 1. The number and formation positions of the formed p + / n - / n +The total number of diodes is one or more, and can be plural, i.e., two or more, for example, three or more, four or more, five or more, etc., but is not particularly limited. p + / n - / n + The diode should be formed at least at a position where the lifetime value of the epitaxial layer is to be measured. In the above, referring to FIG. 1, the "p + / n - / n + " diode was described as an example, but the "n + / p - / p + diode", "p + / p - / n + diode" or "n + / n - / p + diode" is the same as the above.

[0029] After forming the diode having the mesa structure as described above, OCVD measurement is performed. In order to apply a voltage in the OCVD measurement, electrodes that become ohmic are formed on the back surface of the semiconductor single crystal substrate and on the surface of the diode (i.e., on the epitaxial layer or on the surface of the p + layer or n + layer formed in the surface layer region of the epitaxial layer), respectively. In this way, a sample for lifetime measurement can be fabricated. The electrodes can be formed on each of the above surfaces, for example, by vapor depositing a metal. As the metal, for the electrode formed on the surface of the n-type semiconductor, Ti, Al, Sb, Pb, Mg, Sm, etc. are preferable, and for the electrode formed on the surface of the p-type semiconductor, Au, Pt, Pd, etc. are preferable.

[0030] <OCVD Measurement> For the diode fabricated by processing the semiconductor sample to be evaluated as described above, OCVD measurement is performed.

[0031] Figure 2 shows a schematic diagram of a measurement circuit for OCVD measurement. The measurement circuit shown in Figure 2 includes a power supply 1, a switch 2, and an oscilloscope 3. Although not shown, in some cases, a resistor or the like that determines a constant current value flowing through the diode may be inserted in series in the circuit. The OCVD measurement can be performed according to the following measurement procedure. Apply a forward voltage from the power supply 1 to the diode to inject carriers. After applying the voltage, open the switch 2. When the switch 2 is opened, no current flows through the diode, so a voltage is generated between the electrodes due to the recombination of excess carriers accumulated in the diode. The voltage slope changes between the high-level injection state and the low-level injection state depending on the carrier density inside the diode. Measure the time change (voltage decay) of the voltage across both ends of the diode using the oscilloscope 3.

[0032] Regarding OCVD measurement, as described in Non-Patent Document 1 (M. Tapajna et al, Journal of ELECTRICAL ENGINEERING, vol55, 9-10, pp.239-244, 2004), conventionally, from the voltage decay after applying a forward voltage to the diode, the lifetime value has been calculated by the following formula (H) in the case of high-level injection and by the following formula (I) in the case of low-level injection. In the following formulas, τ h is the lifetime value in the high-level injection state, τ l is the lifetime value in the low-level injection state, q is the elementary charge, k is the Boltzmann constant, T is the absolute temperature, and dV / dt is the slope of the voltage decay of OCVD.

[0033]

Equation

[0034]

Equation

[0035] In contrast, as a result of intensive studies by the present inventors, in order to improve the measurement accuracy of the lifetime value of the epitaxial layer by OCVD measurement, it is considered that the influence of carriers (injected carriers: electrons or holes) injected into the epitaxial layer in the diode during OCVD measurement diffusing into the p + layer or p + substrate and n + layer or n + substrate, and the influence of minority carriers being injected from the depletion layer formed by the pn junction into the epitaxial layer should be removed using mathematical formulas. FIG. 3 is an image diagram of carrier diffusion and injection in a p + / n - / n + diode. Note that FIG. 3 shows an example of a p + / n - / n + diode, but it goes without saying that carrier diffusion and injection also occur in an n + / p - / p + diode, a p + / p - / n + diode, or an n + / n - / p + diode. Regarding the above-mentioned influence of carrier diffusion and injection, the degree of influence varies depending on the dopant concentration and thickness of the semiconductor single crystal substrate, the epitaxial layer, and the p + layer or n + layer located thereon or in its surface region. For example, regarding the phenomenon of injected carriers in the epitaxial layer diffusing, when the dopant concentration of the p + layer or n + layer located on or in the surface region of the epitaxial layer is low or the thickness is thin, and when the thickness of the epitaxial layer is thin, the influence becomes large. As a result, since the overall voltage decay becomes faster, in the conventional lifetime calculation method, the lifetime value becomes small for both the high-level injection state and the low-level injection state. On the other hand, for a p + / n - / n +Diode, n + / p - / p + Diode, p + / p - / n + Diode or n + / n - / p + The phenomenon in which minority carriers are injected from the depletion layer of a diode into an epitaxial layer is the p that forms a pn junction + layer, p + substrate, n + layer or n + When the dopant concentration of the substrate is low and the dopant concentration of the epitaxial layer is low or the thickness is thin, the influence becomes large. As a result, the voltage decay becomes slow in the low-level injection state, so that in the conventional lifetime calculation method, the lifetime value becomes large for the low-level injection state. Therefore, when calculating the lifetime value of an epitaxial layer by the conventional lifetime calculation method, the dopant concentration and thickness of the semiconductor single crystal substrate, the epitaxial layer, and the p located above or in the surface region thereof + layer or n + layer vary the influence on the calculation result, so that the measurement accuracy of the lifetime value of the epitaxial layer decreases. On the other hand, as described above, by removing those influences using a mathematical formula, the measurement accuracy of the lifetime value of the epitaxial layer can be improved.

[0036] The above-mentioned mathematical formulas are the following formula (A) and the following formula (C). The following formula (A) is a mathematical formula applied to the state of n s >N d - That is, it is a mathematical formula applied to the high-level injection state. The following formula (C) is a mathematical formula applied to the state of n s <N d - That is, it is a mathematical formula applied to the low-level injection state. For a specific example of the calculation method of the lifetime value using the following formula (A) and the following formula (C), reference can be made to the examples described later.

[0037]

Number

[0038]

Number

[0039]

Number

[0040]

Number

Number

[0041] n s >N d - In the state of (high-level injection state) where n s <N d -In this state (low level injection state), the injected carrier density in the epitaxial layer is lower than the dopant density of the epitaxial layer. In the diode voltage attenuation, which is the result of OCVD measurement, an inflection point appears at the boundary between the high level injection state and the low level injection state. Figure 4 shows an image of the voltage attenuation during OCVD measurement and the inflection point that is the boundary between the high level injection state and the low level injection state. A specific example of a method for determining the high level injection state and the low level injection state will be shown in the examples described later.

[0042] As described above, according to the above evaluation method, the carriers injected into the epitaxial layer in the diode during the OCVD measurement are p + Layer or p + Substrate and n + Layer or n + The effect of diffusion into the substrate and the effect of minority carriers being injected into the epitaxial layer from the depletion layer formed by the pn junction can be removed by the formula. As a result, it becomes possible to accurately measure the lifetime value of the silicon epitaxial layer. For example, in one embodiment, the above evaluation method can be used to obtain in-plane distribution information of the lifetime value of the epitaxial layer of the same semiconductor sample. This can provide, for example, information on the in-plane distribution of metal contamination in the epitaxial layer. In addition, in one embodiment, the above evaluation method can be used to obtain lifetime values for the epitaxial layers of multiple semiconductor samples, thereby providing information on the differences in the lifetime values of the epitaxial layers of multiple semiconductor samples. Specifically, for example, the above evaluation method can be used to obtain lifetime values for the epitaxial layers of multiple semiconductor samples, thereby providing information on the differences in the lifetime values of the epitaxial layers of multiple semiconductor samples. This can provide, for example, information on the differences in the metal contamination levels of multiple semiconductor samples. EXAMPLES

[0043] The present invention will be further described below with reference to examples, although the present invention is not limited to the embodiments shown in the examples.

[0044] [Fabrication of Samples for Lifetime Measurement] n / n silicon epitaxial wafers A and B (n + with a diameter of 200 mm, fabricated in the same epitaxial growth furnace + on a single crystal silicon substrate - having an n silicon epitaxial layer) were used - On the n silicon epitaxial layer, a p silicon epitaxial layer was formed by CVD method with different thicknesses. In this way, a laminated structure having a pn junction was fabricated on each of wafers A and B. Fig. 5 shows the cross-sectional structures of wafers A and B on which the laminated structure having a pn junction was fabricated. In Fig. 5, "epi layer" indicates "silicon epitaxial layer". + Subsequently, by patterning the above laminated structure by photolithography and Chemical Dry Etching (CDE), as shown in Fig. 1, p / n / n diodes having a sequential mesa structure were fabricated on each wafer. Subsequently, by patterning the above laminated structure by photolithography and Chemical Dry Etching (CDE), as shown in Fig. 1, p / n / n diodes having a sequential mesa structure were fabricated on each wafer. + / n - / n + A plurality of p / n / n diodes were fabricated on each wafer. The junction area of the fabricated p / n / n diodes is 0.04 cm + / n - / n + (0.2 cm × 0.2 cm). 2 (0.2 cm × 0.2 cm). Subsequently, for each of wafers A and B, gold was deposited on the surface of the epitaxial layer, and titanium was deposited on the surface of the backside substrate, thereby providing electrode layers on the front and back surfaces. + Subsequently, for each of wafers A and B, gold was deposited on the surface of the epitaxial layer, and titanium was deposited on the surface of the backside substrate, thereby providing electrode layers on the front and back surfaces. In this way, samples for lifetime measurement were fabricated. The sample containing wafer A is called sample A, and the sample containing wafer B is called sample B.

[0045] [OCVD Measurement] For samples A and B, OCVD measurements were performed on four p / n / n diodes 1 to 4 respectively, and voltage decay was obtained. The position of p / n / n diode 1 of sample A is the same as that of p / n / n diode 1 of sample B. + / n - / n + For samples A and B, OCVD measurements were performed on four p / n / n diodes 1 to 4 respectively, and voltage decay was obtained. The position of p / n / n diode 1 of sample A is the same as that of p / n / n diode 1 of sample B. + / n - / n + The position of p / n / n diode 1 of sample A is the same as that of p / n / n diode 1 of sample B. + / n- / n + It is the same as the position of Diode 1. In this regard, for other p + / n - / n + The same applies to the diodes.

[0046] In FIG. 6, the p of Sample A + / n - / n + Diode 1 and the p of Sample B + / n - / n + The measurement results of the voltage decay in the OCVD measurement of Diode 1 at room temperature (T = 300K) are shown. When comparing the voltage decays of Sample A and Sample B, the voltage decay of Sample A is faster. For example, in the voltage decay of Sample A, A is less than 0.3V in 1×10 -4 seconds, while in Sample B, it is about 0.3V. The cause of this difference is the carrier diffusion and injection described above.

[0047] [Comparative Example 1] For Sample A and Sample B, the lifetime values of the silicon epitaxial layer were calculated by the previously shown equations (H) and (I), respectively. Regarding equations (H) and (I), the variable that needs to be obtained from the experimental results is the slope dV / dt of the voltage decay. The others are the temperature, which is a physical constant or an experimental condition, and these are known values. dV / dt was calculated in the range of 0.46 to 0.43V for the voltage decay in the high-level injection state and 0.43 to 0.40V for the low-level injection state to obtain the lifetime value of the epitaxial layer. Regarding the voltage range used for the above dV / dt calculation, the inflection point was determined by differentiating the entire voltage decay shown in FIG. 6, and ±0.03V before and after the inflection point was determined as the high-level region and the low-level injection region. The details of the determination method of this inflection point and the epitaxial layer lifetime calculation region will be described later. The lifetime values of the epitaxial layers of Sample A and Sample B obtained by the above method are shown in FIG. 7. As shown in FIG. 7, for sample A and sample B, the calculation results of the lifetime values of the epitaxial layers in the high-level injection state and the low-level injection state are shown for p + / n - / n + When comparing each of diodes 1 to 4, there are differences in the values. This difference is considered to be due to the different effects of carrier diffusion and injection caused by the differences in the p + silicon epitaxial layers formed on the wafer.

[0048] [Method for Determining Inflection Point and Lifetime Calculation Region] As an example, for the p + / n - / n + The calculation results of the voltage decay of diode 4 and its derivative dV / dt are shown in FIG. 8. Focusing on the derivative of the voltage decay, after the value of dV / dt increases with time, a maximum value appears. After that, the value decreases, and after a minimum value appears, the value increases again. The ideal voltage decay assumed by OCVD is, as shown in FIG. 4, a linear voltage decay with no change in the slope of the voltage decay. Since 0.48V and 0.37V corresponding to the maximum and minimum values of dV / dt in FIG. 8 are points where there is no change in the slope of the voltage decay, it can be judged that it is close to the ideal state. Therefore, in Comparative Example 1 and Example 1 described later, the lifetime value of the epitaxial layer was calculated in the region between these ideal voltage values. Also, the inflection point, which is the boundary between the high-level injection state and the low-level injection state, was rounded to 0.43V by rounding 0.425V, which corresponds to the midpoint of the voltage values of 0.48 to 0.37V. As described above, the difference between the high-level injection state and the low-level injection state is a difference in the state of the injected carrier density in the epitaxial layer, and the injected carrier density is a value that depends on voltage as can be seen from equations (B), (E), and (G). Therefore, it is considered appropriate to obtain the inflection point from a value directly related to the injected carrier density. Therefore, as described above, the inflection point was set as the midpoint of the voltage value instead of time.

[0049] [Example 1] For each of Sample A and Sample B, the lifetime values of the silicon epitaxial layer were calculated by the above-described formulas (A) to (G). In the formulas, the values that need to be obtained from the experimental results are the slope dV / dt of the voltage decay and the injection carrier density n for formula (A) (high-level injection state). s For formula (C) (low-level injection state), they are the slope dV / dt of the voltage decay, the injection carrier density n s and the slope dQ / dt of the areal density of carriers supplied from the depletion layer to the silicon epitaxial layer with respect to time. The variables in these formulas were determined as follows. The others are values of physical constants or experimental conditions, similar to formulas (H) and (I). <Formula (A)> dV / dt: The slope was determined in the range of 0.46 to 0.43 V of the voltage decay. n s : n was determined using formula (B) from 0.445 V corresponding to the midpoint of the range of 0.46 to 0.43 V where the voltage decay was determined. s <Formula (C)> dV / dt: The slope was determined in the range of 0.43 to 0.40 V of the voltage decay. n s : n was determined using formula (E) from 0.415 V corresponding to the midpoint of the range of 0.43 to 0.40 V where the voltage decay was determined. s dQ / dt: Q was determined using formula (D) in the range of 0.43 to 0.40 V of the voltage decay, and then the slope dQ / dt was determined in the same range of 0.43 to 0.40 V.

[0050] As described above, the experimentally determined dV / dt, n s and dQ / dt were respectively substituted into formulas (A) and (C) together with the values of other physical constants and experimental conditions, and the lifetime values of the epitaxial layer with the influence of carrier diffusion and injection removed as described above were calculated. The results are shown in Figure 9.

[0051] Comparing the lifetime value calculated in Example 1 with the lifetime value of the epitaxial layer calculated in Comparative Example 1, p + / n - / n​​+ The results of comparing each of the diodes 1 to 4 are shown in FIG. 10. FIG. 10 shows, for each of Example 1 and Comparative Example 1, the ratio of the lifetime values of Sample A and Sample B for each diode (the lifetime value of the silicon epitaxial layer calculated for Sample B / the lifetime value of the silicon epitaxial layer calculated for Sample A). In FIG. 10, “epi layer” indicates “silicon epitaxial layer”. In the high-level injection state, in Example 1 as compared with Comparative Example 1, since the ratio of the lifetime values of Sample A and Sample B is closer to 1, it can be confirmed that the difference in the lifetime values between Sample A and Sample B is smaller. This is because in Example 1, by using Equation (A), the influence of the diffusion of the injected carriers in the epitaxial layer into the p + layer and n + substrate was removed, indicating that the lifetime values of the silicon epitaxial layers of Sample A and Sample B were accurately obtained. Regarding the low-level injection state as well, in Example 1 as compared with Comparative Example 1, since the ratio of the lifetime values of Sample A and Sample B is closer to 1, it can be confirmed that the difference in the lifetime values between Sample A and Sample B is smaller. This is because in Example 1, by using Equation (C), the influence of the diffusion of the injected carriers in the epitaxial layer into the p + layer and n + substrate, as well as the influence of carriers being injected from the depletion layer formed by the pn junction into the epitaxial layer, was removed, indicating that the lifetime values of the epitaxial layers of Sample A and Sample B were accurately obtained.

Industrial Applicability

[0052] One aspect of the present invention is useful in the technical field of semiconductor wafers and the like.

Claims

1. A method for evaluating a semiconductor sample having a semiconductor epitaxial layer on a single crystal semiconductor substrate, The semiconductor single crystal substrate is n ＋ substrate and the semiconductor epitaxial layer is n － layer, or the semiconductor single crystal substrate is p ＋ substrate and the semiconductor epitaxial layer is p － layer, or The semiconductor single crystal substrate is an n ＋ substrate and the semiconductor epitaxial layer is a p － layer, or The semiconductor single crystal substrate is p ＋ substrate and the semiconductor epitaxial layer is n － layer, On the semiconductor epitaxial layer or in the surface layer region of the semiconductor epitaxial layer, a p ＋ layer or an n ＋ layer having the same or different conductivity type from that of the semiconductor epitaxial layer is formed to produce a stacked structure. By patterning the laminated structure, a p having a mesa structure ＋ / n － / n ＋ diode, n ＋ / p － / p ＋ diode, p ＋ / p － / n ＋ diode or n ＋ / n － / p ＋ is formed, performing an OCVD measurement on the diode, and From the measurement results obtained by the above OCV D measurement, for the state where n ｓ > N ｄ － Regarding this state, according to the following formula (A), for n ｓ < N ｄ － Regarding this state, according to the following formula (C), to obtain the lifetime value of the semiconductor epitaxial layer A method for evaluating a semiconductor sample, including. 【Number 1】 (In formula (A), τ ｈ : Lifetime value of the semiconductor epitaxial layer, q: Elementary charge, k: Boltzmann constant, T: Absolute temperature, dV / dt: Slope of the voltage decay of the OCV D, L: Thickness of the semiconductor epitaxial layer, D ｎ : Electron diffusion coefficient, D ｐ : Hole diffusion coefficient, N Ｄ : n ＋ substrate or n ＋ layer carrier density, t ｎ : n ＋ substrate or n ＋ layer thickness, N Ａ : p ＋ substrate or p ＋ layer carrier density, t ｐ : p ＋ substrate or p ＋ layer thickness, n ｓ : Injection carrier density, which is obtained by the following formula (B).) 【Number 2】 (In formula (B), n ｉ : true carrier density, V: OCVD voltage, q: elementary charge, k: Boltzmann constant, T: absolute temperature) 【Number 3】 (In formula (C), τ ｌ : Lifetime value of the semiconductor epitaxial layer, q: Elementary charge, k: Boltzmann constant, T: Absolute temperature, dV / dt: Slope of the voltage decay of OCV D, L: Thickness of the semiconductor epitaxial layer, D ｎ : Diffusion coefficient of electrons, D ｐ : Diffusion coefficient of holes, N ｄ － : Dopant density of the semiconductor epitaxial layer, t ｐ : p ＋ substrate or p ＋ layer thickness, N Ｄ : n ＋ substrate or n ＋ layer dopant density, N Ａ : p ＋ substrate or p ＋ layer dopant density, t ｎ : n ＋ substrate or n ＋ layer thickness, Q: Areal density of carriers supplied from the depletion layer to the semiconductor epitaxial layer, n ｓ : Injection carrier density, Q and n ｓ are obtained by the following formula (D) and the following formula (E) when the semiconductor epitaxial layer is n-type, and are obtained by the following formula (F) and the following formula (G) when the semiconductor epitaxial layer is p-type.) 【Number 4】 【Number 5】 (In Formula (D) to Formula (G), ε: permittivity of the semiconductor, n ｉ : intrinsic carrier density, q: elementary charge, k: Boltzmann constant, T: absolute temperature, V: OCV-D voltage, N ｄ － : dopant density of the semiconductor epitaxial layer, N Ａ : p ＋ substrate or p ＋ layer dopant density, N Ｄ : n ＋ substrate or n ＋ layer dopant density)

2. The method for evaluating a semiconductor sample according to claim 1, wherein the semiconductor sample is a silicon epitaxial wafer.

3. The p ＋ layer or the n ＋ layer included in the laminated structure is manufactured by a CVD method, and the method for evaluating a semiconductor sample according to claim 1 or 2 includes this.

Images