Semiconductor integrated device and its manufacturing method

Abstract

Provided are a semiconductor integrated device and a manufacturing method thereof that can achieve impedance matching not only in the low frequency range but also in a wide high frequency range for a transmission line connected between a semiconductor circuit for ultra-high speed wideband optical communication and a coaxial line of a package that houses the semiconductor circuit. [Solution] A semiconductor integrated device S includes a semiconductor integrated chip 1 in which an area for mounting a semiconductor circuit 11, an area for forming a pattern of a transmission line 12, and an area for connecting a coaxial line are arranged on an upper surface 1T of a substrate in that order, and a metal table 3 on which the semiconductor integrated chip 1 is mounted and which is in contact with a lower surface 1B of the substrate, wherein the metal table 3 forms a trench structure 31 as an air layer on one surface in contact with the lower surface 1B of the substrate and at a position opposite the pattern of the transmission line 12, and the ground surface 13 is removed on the lower surface 1B of the substrate at a position opposite the pattern of the transmission line 12.

Description

[Technical Field]

[0001] The present disclosure relates to a transmission line structure connected between a semiconductor circuit for ultra-high speed, wideband optical communications and a coaxial input / output port of a package that houses the semiconductor circuit. [Background technology]

[0002] Research and development into ultra-high-speed, wide-band optical communications is progressing. Optical communications transmission rates currently reach 50 Gbaud, with 100-200 Gbaud expected in the future. System evaluation of optical communications requires measurement accuracy that exceeds the system's operating speed.

[0003] Optical transmission and reception involve EO conversion and OE conversion, respectively. A semiconductor circuit is used as the optical-electrical front end, and a coaxial line is used as the electrical input / output port. A transmission line is connected between the semiconductor circuit and the coaxial line.

[0004] Compared to RF technologies such as microwaves, ultra-high-speed broadband optical communication technology requires broadband performance from low to high speeds, and requires advanced transmission lines that minimize reflection and loss. [Prior art documents] [Non-patent literature]

[0005] [Non-Patent Document 1] Institute of Electronics, Information and Communication Engineers "Knowledge Base", Group 9 (Electronic Materials and Devices), Part 7 (Microwave Transmission and Circuit Devices), Chapter 2 (Planar Waveguides), 2010. Summary of the Invention [Problem to be solved by the invention]

[0006] Currently, the standard for coaxial lines is 0.8 mm, which has the widest bandwidth, and the coaxial line alone can be used in bandwidths up to 150 GHz. However, when transmission lines are included, this does not necessarily mean that the line can be used in bandwidths up to 150 GHz.

[0007] The configuration of a conventional semiconductor integrated device is shown in Figure 1. The semiconductor integrated device S comprises a semiconductor integrated chip 1 and a coaxial line 2. The semiconductor integrated chip 1 has an area on one surface of a substrate where a semiconductor circuit 11 is mounted, an area where a pattern of a transmission line 12 is formed, and an area where the coaxial line 2 is connected, arranged in that order. The coaxial line 2 (the outer periphery of the air coaxial conductor is not shown) has a pin 21 connected to the pattern of the transmission line 12 by a fixing part 22 (solder, conductive epoxy, etc.).

[0008] 2 and 3 show examples of transmission line parameters and characteristic simulations for a transmission line (microstrip line: MSL) mounted on a semiconductor integrated device of the prior art. When a 0.8 mm coaxial line 2 is applied, the diameter of the pin 21 is 0.127 mm, and the signal line width W of the transmission line 12 is S is set to 160 μm, which is wider than the diameter of the pin 21. In the low frequency range, the characteristic impedance of the transmission line 12 is adjusted to 50 Ω, so that the thickness T of the substrate is set to 160 μm, which is wider than the signal line width W of the transmission line 12. S The substrate is made of alumina, and the signal line length of the transmission line 12 is 1.2 mm.

[0009] Looking at the S-parameters of the transmission line 12 simulated under 50 Ω port conditions, S11, which indicates the reflection of the transmission line 12, does not exceed -20 dB in the low frequency range up to 50 GHz, but peaks exceed -20 dB in the band above 60 GHz up to 150 GHz. The characteristic impedance of the transmission line 12 is nearly matched to 50 Ω in the low frequency range up to 50 GHz, but is not matched to 50 Ω at all in the band above 60 GHz up to 150 GHz, and increases to over 70 Ω as the frequency changes to 150 GHz.

[0010] The increase in the characteristic impedance of the transmission line 12 is caused by the fact that, in addition to the fundamental mode, there are higher-order modes propagating through the transmission line 12, and the higher the frequency, the stronger the influence of the higher-order modes becomes. As a result, the higher the frequency, the more difficult it becomes to achieve impedance matching between the transmission line 12 and the coaxial line 2, and between the transmission line 12 and the semiconductor circuit 11, and the greater the reflection becomes.

[0011] Furthermore, in addition to the mismatch in the characteristic impedance of the transmission line 12, there is also the effect of parasitic reactance due to the pin 21 of the coaxial line 2 in the region where the coaxial line 2 is connected, which increases reflection. Therefore, the end of the pattern of the transmission line 12 is moved back from the end of the substrate, but the parasitic reactance is not reduced very much. Alternatively, the end of the substrate is moved away from the pin 21 of the coaxial line 2, but the higher the frequency, the more difficult it becomes to ensure precision during manufacturing.

[0012] Therefore, in order to solve the above-mentioned problems, the present disclosure aims to achieve impedance matching not only in the low frequency range but also in a wide high frequency range for a transmission line connected between a semiconductor circuit for ultra-high speed wideband optical communication and a coaxial line of a package in which the semiconductor circuit is housed. [Means for solving the problem]

[0013] To solve this problem, we decided to place an air layer on both the air side and the substrate side of the transmission line pattern, so that the characteristic impedance of the transmission line remains almost unchanged from the designed value in the low frequency range, even in the wide high frequency range.

[0014] Specifically, the present disclosure relates to a semiconductor integrated device comprising: a semiconductor integrated chip having an area on one side of a substrate where a semiconductor circuit is mounted, an area on which a transmission line pattern is formed, and an area on which a coaxial line is connected, in that order; and a metal table on which the semiconductor integrated chip is mounted and which is in contact with the other side of the substrate, wherein the metal table has a trench structure as an air layer formed on one side that is in contact with the other side of the substrate and at a position facing the transmission line pattern, and the other side of the substrate has a ground plane removed at a position facing the transmission line pattern.

[0015] With this configuration, impedance matching can be achieved not only in the low frequency range but also in a wide range of high frequencies for the transmission line connected between the semiconductor circuit for ultra-high speed wideband optical communications and the coaxial line of the package that houses the semiconductor circuit, while also suppressing propagation loss due to skin resistance.

[0016] The present disclosure also provides a semiconductor integrated device, wherein the thickness of the substrate is equal to or less than half the signal line width of the transmission line.

[0017] With this configuration, when viewed from the transmission line pattern, the thickness of the air layer, which is arranged not only on the air side but also on the substrate side, can be designed with the substrate thickness (which in conventional technology was fixed to match the signal line width of the transmission line) as one of the degrees of freedom in designing the thickness of the air layer.

[0018] The present disclosure also provides a semiconductor integrated device characterized in that the depth of the trench structure is approximately equal to or greater than the thickness of the substrate.

[0019] With this configuration, the depth of the trench structure (which in conventional technology is not formed in the metal table on which the substrate is mounted) can be designed as one of the degrees of freedom in designing the thickness of the air layer that is placed not only on the air side but also on the substrate side when viewed from the transmission line pattern.

[0020] The present disclosure also provides a semiconductor integrated device characterized in that the width of the trench structure is larger than the removed width of the ground plane on the other side of the substrate.

[0021] With this configuration, when viewed from the transmission line pattern, the width of the air layer positioned on the substrate side can be sufficiently secured, and a margin for misalignment can be secured between the removed portion of the ground surface on the other side of the substrate and the trench structure formed in the metal table.

[0022] The present disclosure also provides a semiconductor integrated device, characterized in that the removal of the ground surface on the other side of the substrate and the formation of the trench structure are performed in an extension of an area where a pattern of the transmission line is formed in an area where the coaxial line is connected, and the width of the removal of the ground surface on the other side of the substrate and the width of the trench structure are larger in the area where the coaxial line is connected than in the area where the pattern of the transmission line is formed.

[0023] This configuration reduces the effect of the magnitude of parasitic reactance (usually capacitance: the parasitic capacitance between the pin of the coaxial line and the ground plane on the other side of the substrate and the metal table) in the area where the coaxial line is connected, thereby reducing reflections.

[0024] The present disclosure also provides a semiconductor integrated device, wherein the transmission line is a microstrip line that does not have a ground plane formed on one side of the substrate, or a coplanar line that has a ground plane formed on one side of the substrate.

[0025] This configuration enables impedance matching to be achieved for a microstrip line or a coplanar line with a ground plane not only in the low frequency range but also in a wide high frequency range, while also suppressing propagation loss due to skin resistance.

[0026] The present disclosure also provides a method for manufacturing the semiconductor integrated device described above, comprising the steps of: a pin fixing step of fixing a pin of the coaxial line to the metal table; a chip mounting step of mounting the semiconductor integrated chip on the metal table; a position adjusting step of adjusting the position of the semiconductor integrated chip with respect to the metal table so that the position of the pattern of the transmission line is aligned with the position of the pin of the coaxial line and so that the entire removed width of the ground surface on the other side of the substrate is included in part of the width of the trench structure; and a continuity fixing step of continuity fixing the pin of the coaxial line to the pattern of the transmission line.

[0027] With this configuration, when viewed from the transmission line pattern, the width of the air layer positioned on the substrate side can be sufficiently secured, and a margin for misalignment can be secured between the removed portion of the ground surface on the other side of the substrate and the trench structure formed in the metal table.

[0028] The above-disclosed inventions can be combined as much as possible. [Effects of the Invention]

[0029] In this way, the present disclosure makes it possible to achieve impedance matching for a transmission line connected between a semiconductor circuit for ultra-high-speed wideband optical communications and a coaxial line of a package that houses the semiconductor circuit, not only in the low frequency range but also in a wide high frequency range. [Brief explanation of the drawings]

[0030] [Figure 1] FIG. 1 is a diagram showing the configuration of a semiconductor integrated device according to a prior art; [Figure 2] FIG. 1 is a diagram showing transmission line parameters for a transmission line mounted on a semiconductor integrated device according to the prior art; [Figure 3] FIG. 10 is a diagram showing an example of a characteristic simulation of a transmission line mounted on a semiconductor integrated device according to the prior art; [Figure 4] 1 is a diagram showing a configuration of a semiconductor integrated device according to a first embodiment. [Figure 5] It is a diagram showing parameters of a transmission line mounted on a semiconductor integrated device according to the first embodiment. [Figure 6] It is a diagram showing an example of characteristic simulation for a transmission line mounted on a semiconductor integrated device according to the first embodiment. [Figure 7] It is a diagram showing the configuration of a semiconductor integrated device according to the second embodiment. [Figure 8] It is a diagram showing parameters of a transmission line mounted on a semiconductor integrated device according to the second embodiment. [Figure 9] It is a diagram showing an example of characteristic simulation for a transmission line mounted on a semiconductor integrated device according to the second embodiment. [Figure 10] It is a diagram showing an example of characteristic simulation for a transmission line mounted on a semiconductor integrated device according to the second embodiment. [Figure 11] It is a diagram showing the configuration of a semiconductor integrated device of a comparative example. [Figure 12] It is a diagram showing the configuration of a semiconductor integrated device according to the third embodiment. [Figure 13] It is a diagram showing an example of characteristic simulation for a coaxial + transmission line mounted on a semiconductor integrated device of a comparative example and the third embodiment.

Embodiments for Carrying Out the Invention

[0031] Embodiments of the present disclosure will be described with reference to the accompanying drawings. The embodiments described below are examples of carrying out the present disclosure, and the present disclosure is not limited to the following embodiments.

[0032] (Configuration and Characteristics of a Semiconductor Integrated Device According to the First Embodiment) The configuration of the semiconductor integrated device of the first embodiment is shown in Fig. 4. The semiconductor integrated device S includes a semiconductor integrated chip 1, a coaxial line 2 (not shown in Fig. 4), and a metal table 3. The semiconductor integrated chip 1 has an area where a semiconductor circuit 11 is mounted, an area where a pattern of a transmission line 12 is formed, and an area where the coaxial line 2 is connected, arranged in this order on the upper surface 1T of the substrate. The metal table 3 has the semiconductor integrated chip 1 mounted thereon and is in contact with the lower surface 1B of the substrate.

[0033] The transmission line 12 is a microstrip line with no ground plane formed on the upper surface 1T of the substrate. The metal table 3 has a trench structure 31 formed as an air space on one surface that contacts the lower surface 1B of the substrate and at a position facing the pattern of the transmission line 12. The lower surface 1B of the substrate has a ground removal surface 14 formed at a position facing the pattern of the transmission line 12. At the position facing the pattern of the transmission line 12, the bottom surface of the trench structure 31 of the metal table 3, rather than the ground removal surface 14 on the lower surface 1B of the substrate, corresponds to the ground plane 13 on the lower surface 1B of the substrate.

[0034] In the region where the pattern of the transmission line 12 is formed, the width W of the trench structure 31 is T1 is the width W of the ground removal surface 14 on the bottom surface 1B of the board. C1 The removal of the ground plane 13 on the lower surface 1B of the substrate and the formation of the trench structure 31 are performed in the region where the coaxial line 2 is connected, as an extension of the region where the pattern of the transmission line 12 is formed, and these will be described in the third embodiment.

[0035] 5 and 6 show transmission line parameters and characteristic simulation examples for the transmission line (microstrip line: MSL) mounted on the semiconductor integrated device of the first embodiment. When a 0.8 mm coaxial line 2 is applied, the diameter of the pin 21 is 0.127 mm, and the signal line width W of the transmission line 12 is 0.127 mm. S is set to 160 μm, which is sufficiently wider than the diameter of the pin 21. In the low frequency range, the thickness T of the substrate is set to 50 μm, which is the signal line width W of the transmission line 12. SThin it to approximately 70 μm, which is about 1 / 2 of it, and set the depth D of the trench structure 31 to 100 μm, which is larger than the thickness T of the substrate. The material of the substrate is alumina, and the signal line length of the transmission line 12 is 1.2 mm.

[0036] Looking at the S-parameters of the transmission line 12 simulated under the 50 Ω port condition, S11 indicating the reflection of the transmission line 12 does not exceed -20 dB in the low-frequency range up to 50 GHz, and also does not exceed -20 dB in the frequency band from 60 GHz to 150 GHz. S21 indicating the transmission of the transmission line 12 has only a change such that the transmission loss due to reflection is not a problem.

[0037] This is because an air layer is arranged not only on the air side but also on the substrate side when viewed from the pattern of the transmission line 12. That is, not only in the low-frequency range but also widely in the high-frequency range, the mode propagating through the transmission line 12 is hardly affected by the higher-order mode, so the change in the characteristic impedance of the transmission line 12 can be suppressed small without increasing. Thus, the effective dielectric constant of the transmission line 12 (in the first embodiment, lower by the amount of the air layer compared to the value of the prior art) and, consequently, the characteristic impedance of the transmission line 12 hardly change from the value designed in the low-frequency range even widely in the high-frequency range.

[0038] Here, the characteristic impedance Z0_pv of the transmission line 12 is defined by the transmission power and line voltage of the transmission line 12. Then, the real part of the characteristic impedance Z0_pv of the transmission line 12 is approximately matched to 50 Ω in the low-frequency range up to 50 GHz, and is also approximately matched to 50 Ω in the band above 60 GHz, up to 150 GHz. In other words, impedance matching is achieved between the transmission line 12 and the coaxial line 2, and between the transmission line 12 and the semiconductor circuit 11. Then, the reflection coefficient Γ of the transmission line 12 (corresponding to an infinitely long transmission line) is defined as Γ = (Z0_pv - Z0) / (Z0_pv + Z0) (Z0 is the characteristic impedance to be matched, here 50 Ω). Then, the reflection coefficient Γ of the transmission line 12 (corresponding to an infinitely long transmission line) does not exceed −20 dB in the low frequency range up to 50 GHz, and does not exceed −20 dB even in the band above 60 GHz up to 150 GHz.

[0039] On the other hand, the signal line width W of the transmission line 12 S is designed to be sufficiently wider than the diameter of the pin 21 of the coaxial line 2, and is not scaled down to fit a wide high-frequency range. Therefore, the propagation loss due to the skin resistance of the transmission line 12 remains almost unchanged from the value in the prior art. The substrate may be made of silicon, silicon carbide, or the like, and if the substrate has a low intrinsic dielectric constant, the effect of the first embodiment can be easily achieved. Even if the substrate has a high intrinsic dielectric constant, the effect of the first embodiment can be achieved by reducing the effective dielectric constant of the transmission line 12.

[0040] As described above, for the transmission line 12 connected between the semiconductor circuit 11 for ultra-high-speed broadband optical communication and the coaxial line 2 of the package in which the semiconductor circuit 11 is housed, impedance matching can be achieved not only in the low-frequency range but also in the high-frequency range of 150 GHz or less, the reflection coefficient can be suppressed to -20 dB or less, and the propagation loss due to skin resistance can also be suppressed. However, since the transmission line 12 is a microstrip line in which a ground plane is not formed on the upper surface 1T of the substrate, the unipolar planar semiconductor circuit 11 needs to be connected to the ground plane 13 on the lower surface 1B of the substrate in order to secure a ground, and it is necessary to connect with a ground via or the like.

[0041] (Configuration and Characteristics of Semiconductor Integrated Device of Second Embodiment) In the second embodiment, differences from the first embodiment will be described. The configuration of the semiconductor integrated device of the second embodiment is shown in FIG. 7. The transmission line 12 is a coplanar line in which a ground plane 15 (conducted with the lower surface 1B of the substrate through the side surface of the substrate) is formed on the upper surface 1T of the substrate.

[0042] Regarding the transmission line (ground coplanar line: G-CPW) mounted on the semiconductor integrated device of the second embodiment, examples of transmission line parameters and characteristic simulations are shown in FIGS. 8 to 10. The signal line width W of the transmission line 12 S is set to 140 μm, the gap width W of the coplanar line G1 is set to 70 μm, the thickness T of the substrate is made as thin as 70 μm as in the first embodiment, and the depth D of the trench structure 31 is set to 100 μm as in the first embodiment. The material of the substrate is alumina, and the signal line length of the transmission line 12 is 1.2 mm.

[0043] First, let us look at Figure 9. Looking at the S parameters of transmission line 12 simulated under 50 Ω port conditions, S11, which indicates the reflection of transmission line 12, does not exceed -20 dB even in the band from 60 GHz to 150 GHz. S21, which indicates the transmission of transmission line 12, changes only to the extent that the transmission loss due to reflection does not become an issue. The real part of the characteristic impedance Z0_pv of transmission line 12 is nearly consistent with 50 Ω even in the band from 60 GHz to 150 GHz. The reflection coefficient Γ of transmission line 12 (equivalent to an infinitely long transmission line) does not exceed -20 dB even in the band from 60 GHz to 150 GHz.

[0044] 10 will be described. S11 around 140 GHz has a peak value of −26.0 dB when (substrate thickness T, trench structure 31 depth D)=(70 μm, 100 μm), −26.9 dB when (substrate thickness T, trench structure 31 depth D)=(70 μm, 80 μm), −26.1 dB when (substrate thickness T, trench structure 31 depth D)=(70 μm, 60 μm), −31.8 dB when (substrate thickness T, trench structure 31 depth D)=(48 μm, 100 μm), and −15.6 dB when (substrate thickness T, trench structure 31 depth D)=(100 μm, 100 μm).

[0045] Therefore, in order for S11 to not exceed -20 dB in the band of 60 GHz or more up to 150 GHz, the thickness T of the substrate is set to be equal to or smaller than the signal line width W of the transmission line 12. S It is desirable that the depth D of the trench structure 31 is equal to or greater than the thickness T of the substrate so that S11 does not exceed -20 dB even in the band of 60 GHz or more up to 150 GHz. Note that when (substrate thickness T, depth D of trench structure 31) = (100 μm, 100 μm), S11 near 140 GHz exceeded -20 dB (although this is lower than -10 dB in the prior art), because the thickness T of the substrate is larger than the gap width W of the coplanar line. G1 It is thought to be larger than

[0046] Thus, as seen from the pattern of the transmission line 12, as a degree of freedom in designing the thickness of the air layer, which is arranged not only on the air side but also on the substrate side, the thickness T of the substrate (in the prior art, fixed according to the signal line width W of the transmission line 12 S can be designed), and the depth D of the trench structure 31 (not formed in the metal table 3 on which the substrate is mounted in the prior art) can be designed. Since the transmission line 12 is a coplanar line in which the ground plane 15 is formed on the upper surface 1T of the substrate, the unipolar pattern semiconductor circuit 11 only needs to be connected to the ground plane 15 on the upper surface 1T of the substrate to secure the ground.

[0047] (Configuration and characteristics of the semiconductor integrated device according to the third embodiment) In the third embodiment, differences from the second embodiment will be described. First, problems of the comparative example for the third embodiment will be described. Next, means of the third embodiment compared with the comparative example will be described.

[0048] The configuration of the semiconductor integrated device of the comparative example is shown in FIG. 11. The formation of the gap in the pattern of the transmission line 12, the removal of the ground plane 13 on the lower surface 1B of the substrate, and the formation of the trench structure 31 are performed in the extension of the region where the pattern of the transmission line 12 is formed in the region where the coaxial line 2 is connected. Here, in the region where the pattern of the transmission line 12 is formed and the region where the coaxial line 2 is connected, the width W of the trench structure 31 T is larger than the width W of the ground removal surface 14 on the lower surface 1B of the substrate C .

[0049] And the gap width of the pattern of the transmission line 12 is larger in the region (W G2 ) where the coaxial line 2 is connected than in the region (W G1 ) where the pattern of the transmission line 12 is formed. On the other hand, the width of the ground removal surface 14 on the lower surface 1B of the substrate and the width of the trench structure 31 are equal in the region (W C , W T ) where the coaxial line 2 is connected than in the region (W C , W T ) where the pattern of the transmission line 12 is formed.

[0050] Regarding the coaxial + transmission line (ground coplanar waveguide line: G-CPW) mounted on the semiconductor integrated device of the comparative example, a characteristic simulation example is shown in the upper part of FIG. 13. S11 indicating the reflection of the transmission line 12 does not exceed -20 dB even in the frequency band from 60 GHz to 150 GHz. S21 indicating the transmission of the transmission line 12 has only a change such that the transmission loss due to reflection is not a problem. However, the reason for the degradation compared to the upper part of FIG. 10 (at 150 GHz, S11 degrades from -25 dB to -20 dB) is that only the influence of the parasitic reactance (usually capacitance) between the pin 21 of the coaxial line 2 and the ground plane 15 on the upper surface 1T of the substrate in the region where the coaxial line 2 is connected has been reduced.

[0051] The configuration of the semiconductor integrated device of the third embodiment is shown in FIG. 12. The formation of the gap of the pattern of the transmission line 12, the removal of the ground plane 13 on the lower surface 1B of the substrate, and the formation of the trench structure 31 are performed in the extension of the region where the pattern of the transmission line 12 is formed in the region where the coaxial line 2 is connected. Here, in the region where the pattern of the transmission line 12 is formed and the region where the coaxial line 2 is connected, the width W of the trench structure 31 T1、T2 is larger than the width W of the ground removal surface 14 on the lower surface 1B of the substrate. C1、C2

[0052] And the gap width of the pattern of the transmission line 12 is larger in the region (W G2 ) where the coaxial line 2 is connected than in the region (W G1 ) where the pattern of the transmission line 12 is formed. Further, the width of the ground removal surface 14 on the lower surface 1B of the substrate and the width of the trench structure 31 are also larger in the region (W C2 , W T2 ) where the coaxial line 2 is connected than in the region (W C1 , W T1 ) where the pattern of the transmission line 12 is formed.

[0053] A characteristic simulation example of a coaxial transmission line (G-CPW: Ground Coplanar Line) mounted on the semiconductor integrated device of the third embodiment is shown in the lower part of FIG. 13. S11, which indicates the reflection of the transmission line 12, does not exceed −20 dB even in the frequency band from 60 GHz to 150 GHz. S21, which indicates the transmission of the transmission line 12, changes only to the extent that the transmission loss due to reflection is not a problem. The reason for the improvement compared to the upper part of FIG. 13 (S11 improves from −20 dB to −30 dB at 150 GHz) is that the influence of parasitic reactance (usually capacitance) between the pin 21 of the coaxial line 2 and the ground plane 13 and metal table 3 on the bottom surface 1B of the substrate in the region where the coaxial line 2 is connected is also reduced. Note that the sharp resonance peak is due to the boundary condition of the metal wall in the simulation and is suppressed by the radio wave absorber in the actual device.

[0054] In this way, the influence of the magnitude of the parasitic reactance (usually capacitance: the parasitic capacitance between the pin 21 of the coaxial line 2 and the ground plane 13 on the bottom surface 1B of the substrate and the metal table 3) in the area where the coaxial line 2 is connected can be reduced, thereby reducing reflections.

[0055] Finally, a method for manufacturing the semiconductor integrated device S will be described. First, the pins 21 of the coaxial line 2 (the outer periphery of the air coaxial conductor is not shown) are fixed to the metal table 3. Next, the semiconductor integrated chip 1 is mounted on the metal table 3. Next, the position of the semiconductor integrated chip 1 is adjusted relative to the metal table 3. Here, the position of the pattern of the transmission line 12 is aligned with the position of the pins 21 of the coaxial line 2. Then, the width W of the ground removal surface 14 on the bottom surface 1B of the substrate is adjusted. C1 , W C2 The entire structure is divided into two parts by the width W of the trench structure 31. T1 , W T2 Next, the pin 21 of the coaxial line 2 is fixed to the pattern of the transmission line 12 by a fixing portion 22 (solder, conductive epoxy, or the like).

[0056] In this way, when viewed from the pattern of the transmission line 12, in order to ensure a sufficient width of the air layer disposed on the substrate side, it is possible to secure a margin for misalignment between the ground removal surface 14 of the lower surface 1B of the substrate and the trench structure 31 formed in the metal table 3.

[0057] When the manufacturing accuracy of the semiconductor integrated device S is low, it is desirable that characteristics such as the reflection coefficient of the transmission line 12 do not change much even if the design parameters change somewhat. Also, when the manufacturing accuracy of the semiconductor integrated device S is high, the design parameters may be determined tightly with a predetermined value as the target for characteristics such as the reflection coefficient of the transmission line 12.

Industrial Applicability

[0058] The semiconductor integrated device and its manufacturing method of the present disclosure can be applied in optical communication transmission rates expected to be 100 to 200 Gbaud in the future and in system evaluations of optical communication where measurement accuracy exceeding the operating speed of the system is required.

Explanation of Signs

[0059] S: Semiconductor integrated device 1: Semiconductor integrated chip 1T: Upper surface of the substrate 1B: Lower surface of the substrate 2: Coaxial line 3: Metal table 11: Semiconductor circuit 12: Transmission line 13: Ground plane 14: Ground removal surface 15: Ground plane 21: Pin 22: Fixed part 31: Trench structure

Claims

1. A semiconductor integrated chip in which a semiconductor circuit region on which a semiconductor circuit is mounted, a transmission line region in which a pattern of a transmission line is formed, and a coaxial line region to which a coaxial line is connected are arranged on one surface of a substrate in the order of the semiconductor circuit region, the transmission line region, and the coaxial line region, A metal table on which the semiconductor integrated chip is mounted and which contacts the other surface of the substrate, A semiconductor integrated device comprising: The metal table forms a trench structure as an air layer on one surface that contacts the other surface of the substrate and at a position facing the pattern of the transmission line, The other surface of the substrate has the ground plane removed at a position facing the pattern of the transmission line, The thickness of the substrate is 1 / 2 or less of the signal line width of the transmission line, The depth of the trench structure is substantially equal to or greater than the thickness of the substrate A semiconductor integrated device characterized by the above.

2. The width of the trench structure is larger than the removal width of the ground plane on the other surface of the substrate The semiconductor integrated device according to claim 1, characterized by the above.

3. Removal of the ground plane on the other surface of the substrate and formation of the trench structure are performed in an extension of the transmission line region in which the pattern of the transmission line is formed in the coaxial line region to which the coaxial line is connected, The removal width of the ground plane on the other surface of the substrate and the width of the trench structure are larger than the transmission line region in which the pattern of the transmission line is formed in the coaxial line region to which the coaxial line is connected The semiconductor integrated device according to claim 1 or 2, characterized by the above.

4. The transmission line is a microstrip line in which a ground plane is not formed on one surface of the substrate, or a coplanar line in which a ground plane is formed on one surface of the substrate The semiconductor integrated device according to claim 1 or 2, characterized by the above.

5. In manufacturing the semiconductor integrated device according to claim 1 or 2, A pin fixing step of fixing the pin of the coaxial line to the metal table, A chip mounting step of mounting the semiconductor integrated chip on the metal table, A position adjustment step of adjusting the position of the semiconductor integrated chip with respect to the metal table so that the position of the pattern of the transmission line is aligned with the position of the pin of the coaxial line and so that the entire removal width of the ground plane on the other surface of the substrate is included in a part of the width of the trench structure, A conduction fixing step of conductively fixing the pins of the coaxial line to the pattern of the transmission line; A method of manufacturing a semiconductor integrated device, comprising the steps in this order.

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