Semiconductor Module

Abstract

To desirably prevent stress concentrations in a semiconductor module.SOLUTION: A semiconductor module includes a semiconductor chip having a semiconductor substrate and a metal electrode provided above the semiconductor substrate, a protective film provided above the metal electrode, a plating layer provided at least partially at the same height as the protective film above the metal electrode, a solder layer provided above the plating layer, and a lead frame provided above the solder layer, and the plating layer is provided in a range that does not contact the protective film.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present invention relates to a semiconductor module. [Background technology]

[0002] Semiconductor modules equipped with semiconductor chips such as IGBTs (Insulated Gate Bipolar Transistors) have been known for some time. In such semiconductor modules, wiring members such as lead frames and semiconductor chips are joined via solder, which is a joining material (see, for example, Patent Documents 1 to 3). Patent Document 1: Japanese Patent Application Laid-Open No. 2006-245182 Patent Document 2: International Publication No. 2019-244492 Patent Document 3: JP 2019-186510 A Summary of the Invention [Problem to be solved by the invention]

[0003] It is preferable to prevent stress concentration in a semiconductor module. [Means for solving the problem]

[0004] In order to solve the above problem, one aspect of the present invention provides a semiconductor module. The semiconductor module may include a semiconductor chip. The semiconductor chip may have a semiconductor substrate and a metal electrode provided above the semiconductor substrate. The semiconductor module may include a protective film. The protective film may be provided above the metal electrode. The semiconductor module may include a plating layer. The plating layer may be provided above the metal electrode, at least a portion of which is at the same height as the protective film. The semiconductor module may include a solder layer. The solder layer may be provided above the plating layer. The semiconductor module may include a lead frame. The lead frame may be provided above the solder layer. The plating layer may be provided in an area that does not contact the protective film.

[0005] The solder layer may be provided in an area that does not contact the protective film. At least a portion of the solder layer may be provided at the same height as the protective film. The protective film may be provided at a position lower than the lead frame in the height direction.

[0006] The semiconductor chip may include a temperature sensing diode. The temperature sensing diode may be provided above a semiconductor substrate. The semiconductor chip may include a sense wiring. The sense wiring may be connected to the temperature sensing diode. A protective film may cover the temperature sensing diode and the sense wiring. The protective film covering the temperature sensing diode or the sense wiring may be separated from the solder layer and the plating layer.

[0007] The lead frame may include a chip connection portion for connection to the semiconductor chip. The chip connection portion does not need to overlap the temperature sensing diode and the sense wiring in a top view.

[0008] The chip connection portion may be above the protective film and cover the protective film. The semiconductor module may have a space between the chip connection portion and the protective film. The semiconductor module may have a space above the protective film between the solder layer and the protective film. The chip connection portion may have a plurality of protrusions that protrude toward the solder layer.

[0009] The semiconductor chip may have a metal gate runner. The metal gate runner may be provided above the semiconductor substrate. A protective film covering the metal gate runner may be separated from the solder layer and the plating layer.

[0010] The semiconductor module may be filled between the plating layer and the protective film with a filler material having a lower elastic modulus than the protective film.The semiconductor module may be filled between the plating layer and the protective film with a filler material having a smaller difference in linear expansion coefficient between the plating layer or the solder layer than the protective film.The semiconductor module may be filled between the plating layer and the protective film with a filler material having higher adhesion to the metal electrode than the protective film.

[0011] The semiconductor module may include a sealing resin. The sealing resin may seal the semiconductor chip and the lead frame. The filling material may be a material different from the sealing resin.

[0012] A solder layer may be provided between the plating layer and the protective film, and the solder layer may cover corners of the plating layer that are in contact with the solder layer.

[0013] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions. [Brief explanation of the drawings]

[0014] [Figure 1] 1 is a diagram illustrating an example of a semiconductor module 100 according to an embodiment of the present invention. [Figure 2] 1 is a diagram showing an example of the arrangement of gate runners 48, well regions, and pad regions of a semiconductor chip 40 as viewed from above. [Figure 3] 10 is a diagram showing an example of the arrangement of a protective film 150 of a semiconductor chip 40 when viewed from above. FIG. [Figure 4] 1 is a diagram showing an example of the arrangement of semiconductor chips 40 and chip connection portions 62 in a top view of a semiconductor module 100 according to a comparative example. [Figure 5] 5 is a diagram showing an example of the semiconductor module 100 at the aa cross section of FIG. 4. FIG. [Figure 6] 1 is a diagram showing an example of the arrangement of a semiconductor chip 40 and a chip connection portion 62 in a top view of a semiconductor module 100 according to an embodiment. [Figure 7] 7 is a diagram showing an example of the semiconductor module 100 at the bb cross section of FIG. 6. FIG. [Figure 8] 7 is a diagram showing an example of the semiconductor module 100 in the cc cross section of FIG. 6. FIG. [Figure 9] 7 is a diagram showing another example of the semiconductor module 100 in the cross section bb of FIG. 6. FIG. [Figure 10]7 is a diagram showing another example of the semiconductor module 100 in the cross section bb of FIG. 6. FIG. [Figure 11] 7 is a diagram showing another example of the semiconductor module 100 in the cross section bb of FIG. 6. FIG. [Figure 12] 10 is a diagram showing another example of the arrangement of the semiconductor chip 40 and the chip connection portion 62 in the top view of the semiconductor module 100 according to the embodiment. [Figure 13] 10 is a diagram showing another example of the arrangement of the semiconductor chip 40 and the chip connection portion 62 in the top view of the semiconductor module 100 according to the embodiment. [Figure 14] 14 is a diagram showing an example of the semiconductor module 100 in cross section dd of FIG. 13. FIG. [Figure 15] 10 is a diagram showing another example of the arrangement of the semiconductor chip 40 and the chip connection portion 62 in the top view of the semiconductor module 100 according to the embodiment. [Figure 16] 16 is a diagram showing an example of the semiconductor module 100 in the ee cross section of FIG. 15. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0015] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention. In this specification and drawings, elements having substantially the same function and configuration are designated by the same reference numerals to avoid redundant description, and elements not directly related to the present invention are not shown. Furthermore, in a single drawing, elements having the same function and configuration may be designated by the same reference numeral, and the reference numerals may be omitted for other elements.

[0016] In this specification, one side in a direction parallel to the depth direction of a semiconductor chip is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor module is mounted.

[0017] In this specification, technical matters may be described using orthogonal coordinate axes, i.e., the X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. The +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is referred to without specifying positive or negative, it means a direction parallel to the +Z-axis and the -Z-axis. In this specification, the orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, the axis perpendicular to the top and bottom surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. In this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0018] In this specification, when we say "same" or "equal," it may include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0019] FIG. 1 is a diagram illustrating an example of a semiconductor module 100 according to an embodiment of the present invention. The semiconductor module 100 may function as a power conversion device such as an inverter. The semiconductor module 100 includes one or more insulating substrates 21. A predetermined circuit pattern 26 is provided on one surface of the insulating substrate 21, and a cooling unit 20 is provided on the other surface of the insulating substrate 21. The circuit pattern 26 may be formed by directly bonding a copper plate, an aluminum plate, or a plate made of these materials to the insulating substrate 21 made of silicon nitride ceramic, aluminum nitride ceramic, or the like, or by bonding the copper plate, an aluminum plate, or a plate made of these materials, via a brazing layer.

[0020] One or more semiconductor chips 40 are mounted on the circuit pattern 26. In the example of FIG. 1, one semiconductor chip 40 is mounted. A solder layer 30 bonds the semiconductor chip 40 to the circuit pattern 26. The solder layer 30 may be made of the same material as a solder layer 32, which will be described later. The semiconductor chip 40 is protected by a resin package, such as a resin case 10 that surrounds the insulating substrate 21 and a sealing resin 12 that is filled in the resin case 10. It is also possible to protect the semiconductor chip 40 and the like by transfer molding using the sealing resin 12 without providing the resin case 10.

[0021] The semiconductor chip 40 may include an IGBT, a diode such as an FWD (Free Wheel Diode), an RC (Reverse Conducting)-IGBT which is a combination of these, a MOS transistor, and the like.

[0022] The semiconductor chip 40 in this example is a vertical chip with metal electrodes (e.g., an emitter electrode and a collector electrode) formed on its upper and lower surfaces. The semiconductor chip 40 is connected to the circuit pattern 26 by the metal electrodes formed on its lower surface, and is connected to a wiring member (a lead frame 60 in this example) by the metal electrodes formed on its upper surface. Note that the semiconductor chip 40 is not limited to a vertical chip. The semiconductor chip 40 may have metal electrodes on its upper surface that are connected to the circuit pattern 26 by wires or the like.

[0023] In this example, a plating layer 36 is provided above the metal electrodes of the semiconductor chip 40. The metal electrodes are connected to the wiring member via the plating layer 36. One example of the plating layer 36 is Ni plating. By providing the plating layer 36, the wettability between the metal electrodes of the semiconductor chip 40 and the solder layer, which is the bonding member, can be improved, thereby enhancing the bonding of the wiring member. The plating layer 36 may be provided over the entire top surface of the metal electrodes, or the plating layer 36 may be provided over most of the top surface of the metal electrodes.

[0024] The resin case 10 is provided to surround a space 94 that houses the semiconductor chip 40. The insulating substrate 21 is provided below the resin case 10. The space 94 may be an area above the insulating substrate 21 and surrounded by the resin case 10.

[0025] In this example, the resin case 10 is molded from a resin such as a thermosetting resin that can be formed by injection molding or an ultraviolet-curing resin that can be formed by UV molding. The resin may include one or more polymer materials selected from, for example, polyphenylene sulfide (PPS) resin, polybutylene terephthalate (PBT) resin, polyamide (PA) resin, acrylonitrile butadiene styrene (ABS) resin, and acrylic resin.

[0026] The cooling unit 20 contains a refrigerant such as water inside. The cooling unit 20 cools the semiconductor chip 40 via the insulating substrate 21 or the like. A heat sink may be provided between the cooling unit 20 and the insulating substrate 21. The cooling unit 20 may cool the semiconductor chip 40 via the heat sink.

[0027] The top surface of the semiconductor chip 40 is connected to a wiring member via a plating layer 36 and a solder layer 32, which is a bonding member. The wiring member in this example is a lead frame 60. The lead frame 60 is a member formed of a metal material such as copper or aluminum. At least a portion of the surface of the lead frame 60 may be plated with nickel or the like. At least a portion of the surface of the lead frame 60 may be coated with resin or the like. The lead frame 60 may have a plate-like portion. A plate-like shape refers to a shape in which the areas of two opposing main surfaces are larger than the areas of the other surfaces. At least the portion of the lead frame 60 that connects to the semiconductor chip 40 may be plate-shaped. The lead frame 60 may be formed by bending a single metal plate.

[0028] The lead frame 60 electrically connects the semiconductor chip 40 and the circuit pattern 26. A main current may flow through the lead frame 60. Here, the main current is the largest current flowing through the semiconductor chip 40. The lead frame 60 in this example includes a chip connection portion 62, a bridge portion 64, a circuit pattern connection portion 66, and a foot portion 68. The chip connection portion 62 is a portion that connects to the top surface of the semiconductor chip 40. The circuit pattern connection portion 66 is a portion that connects to the top surface of the circuit pattern 26. The chip connection portion 62 and the circuit pattern connection portion 66 may be plate-shaped portions that are approximately parallel to the XY plane. Therefore, the chip connection portion 62 and the circuit pattern connection portion 66 may be plate-shaped portions that are approximately parallel to the top surface of the semiconductor chip 40. Note that "approximately parallel" refers to a state in which the angle is, for example, 10 degrees or less.

[0029] The foot portion 68 is a portion extending in the Z-axis direction. The bridge portion 64 connects the chip connection portion 62 and the circuit pattern connection portion 66 via the foot portion 68. The bridge portion 64 is provided away from conductive members such as the circuit pattern 26. In this example, the bridge portion 64 is provided above the circuit pattern 26, etc., and is provided from the chip connection portion 62 to the circuit pattern connection portion 66 so as to straddle the circuit pattern 26, etc.

[0030] In this example, the sealing resin 12 is provided inside the resin case 10. The sealing resin 12 seals the semiconductor chip 40 and the lead frame 60 serving as a wiring member. In other words, the sealing resin 12 covers the entire semiconductor chip 40 and the lead frame 60 so that the semiconductor chip 40 and the lead frame 60 are not exposed. The sealing resin 12 can protect the semiconductor chip 40 and the lead frame 60.

[0031] The solder layer 32 is formed between the upper surface of the semiconductor chip 40 and the lower surface of the chip connection portion 62 of the lead frame 60, and mechanically and electrically connects the semiconductor chip 40 and the chip connection portion 62. In this example, lead-free solder is used for the solder layer 32. The lead-free solder mainly contains at least one of the following alloys: a tin-silver-copper alloy, a tin-zinc-bismuth alloy, a tin-copper alloy, and a tin-silver-indium-bismuth alloy. The solder layer 32 may also have a fillet on its side surface. The solder layer 32 may also be provided only between the upper surface of the semiconductor chip 40 and the lower surface of the chip connection portion 62 of the lead frame 60.

[0032] 2 is a diagram showing an example of the arrangement of gate runners 48, well regions, and pad regions of a semiconductor chip 40 in a top view. The semiconductor chip 40 has a semiconductor substrate 110. The semiconductor substrate 110 is a substrate formed of a semiconductor material such as silicon or a compound semiconductor. The semiconductor substrate 110 has edges 102 in a top view. The semiconductor substrate 110 of this example has two pairs of edges 102 facing each other in a top view. Figure 2 1 shows a pair of end edges 102-1 and 102-2 facing each other. Figure 2 , the direction parallel to the end sides 102-1 and 102-2 is the X-axis direction, and the direction perpendicular to the end sides 102-1 and 102-2 is the Y-axis direction.

[0033] The semiconductor substrate 110 is provided with an active portion 120. In this example, the semiconductor substrate 110 is provided with active portions 120-1 and 120-2. The active portion 120 is a region through which a main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 110 when the semiconductor chip 40 is controlled to be in the on state. Therefore, the active portion 120 may be a region inside the well region in FIG. 1. The active portion 120 may be provided with a transistor portion including a transistor element such as an IGBT. The active portion 120 may be provided with a diode portion including a diode element such as an FWD. The active portion 120 may be a region in which at least one of a transistor portion and a diode portion is provided. The active portion 120 may be a region overlapping with the top surface main electrode in a top view. The top surface main electrode may be the electrode with the largest area in a top view among the electrodes provided above the top surface of the semiconductor substrate 110. The upper main electrode may be electrically connected to, for example, the emitter region or the source region of the transistor section, or to the anode region of the diode section. In the example of Figure 2, the metal electrode 52 is the upper main electrode.

[0034] A P-type well region is provided in the semiconductor substrate 110. The well region is a P-type region with a higher concentration than the base region of the transistor section or the anode region of the diode section. The base region is provided opposite the gate electrode, and is a P-type region in which a channel is formed in the portion opposite the gate electrode when a predetermined gate voltage is applied to the gate electrode. The semiconductor chip 40 has a first well region 111 and a second well region 112. The first well region 111 and the second well region 112 are provided to sandwich the active section 120 in a top view. The first well region 111 and the second well region 112 are provided to sandwich the active section 120 in a predetermined direction (the Y-axis direction in FIG. 2). "Two well regions sandwich the active section 120" means that any line connecting the two well regions passes through the active section 120 in a top view.

[0035] The first well region 111 may be provided near the edge 102-1. That is, the distance between the first well region 111 and the edge 102-1 is smaller than the distance between the first well region 111 and the edge 102-2. The second well region 112 may be provided near the edge 102-2. That is, the distance between the second well region 112 and the edge 102-2 is smaller than the distance between the second well region 112 and the edge 102-1.

[0036] In this example, the first well region 111 is provided between the active portion 120 and the edge 102-1 in the Y-axis direction. The active portion 120 is not provided between the first well region 111 and the edge 102-1. In other words, the first well region 111 is provided between the end of the active portion 120 in the Y-axis direction and the edge 102-1.

[0037] In this example, the second well region 112 is provided between the active portion 120 and the edge 102-2 in the Y-axis direction. The active portion 120 is not provided between the second well region 112 and the edge 102-2. In other words, the second well region 112 is provided between the end of the active portion 120 in the Y-axis direction and the edge 102-2.

[0038] The first well region 111 and the second well region 112 may be provided in a range in the X-axis direction that includes a center position Xc between the end sides 102-1 and 102-2. The first well region 111 may be sandwiched between the active portions 120 in the X-axis direction. The second well region 112 may be sandwiched between the active portions 120 in the X-axis direction. The second well region 112 may be provided in a wider range in the X-axis direction than the first well region 111.

[0039] The semiconductor chip 40 may have a peripheral well region 113 that is provided to surround the active portion 120 in a top view. The peripheral well region 113 may be provided parallel to each edge of the semiconductor substrate 110. In this example, the peripheral well region 113 is an annular region that surrounds the active portion 120 in a top view. The width of the peripheral well region 113 may be constant in a direction perpendicular to each edge.

[0040] In this example, the first well region 111 and the second well region 112 protrude further toward the center of the active portion 120 than the peripheral well region 113. In another example, at least one of the first well region 111 and the second well region 112 may be provided between the peripheral well region 113 and the edge 102 of the semiconductor substrate 110. In this case, the first well region 111 and the second well region 112 protrude from the peripheral well region 113 toward the edge 102.

[0041] The semiconductor chip 40 may have divided well regions 114 that divide the active portion 120 in a top view. The active portion 120 may be divided into active portions 120-1 and 120-2 by well regions including the divided well regions 114. The divided well regions 114 have a longitudinal direction in a predetermined well longitudinal direction. The divided well regions 114 extend in the well longitudinal direction and cross the active portion 120. The well longitudinal direction of the divided well regions 114 is the Y-axis direction.

[0042] The divided well region 114 may be provided between the first well region 111 and the second well region 112. One longitudinal end of the divided well region 114 may be connected to the first well region 111, and the other longitudinal end may be connected to the second well region 112. The divided well region 114 may be provided in a region overlapping with the center of the active portion 120.

[0043] The divided well region 114 may have a wide portion 115 whose width in a direction perpendicular to the longitudinal direction of the well (in this example, the X-axis direction) in a top view is wider than other portions. The wide portion 115 is also provided between the first well region 111 and the second well region 112. The wide portion 115 may be provided in a region overlapping with the center of the active portion 120. The wide portion 115 may be provided in a region including the center of the divided well region 114 in the longitudinal direction of the well.

[0044] In divided well region 114, a portion that is narrower in width in a direction perpendicular to the well longitudinal direction (the X-axis direction in this example) than wide portion 115 in top view is referred to as narrow portion 116. Divided well region 114 has narrow portion 116-1 provided on the first well region 111 side and narrow portion 116-2 provided on the second well region 112 side. Ends of wide portion 115 in the well longitudinal direction are connected to narrow portion 116-1 and narrow portion 116-2, respectively.

[0045] The semiconductor chip 40 of this example has control electrodes such as a gate pad 50, a current detection pad 172, an anode pad 174, and a cathode pad 176. The gate pad 50 is provided above the first well region 111. The current detection pad 172, the anode pad 174, and the cathode pad 176 are provided above the second well region 112.

[0046] The temperature sensing diode 178 is a PN junction diode made of a semiconductor material such as polysilicon. The temperature sensing diode 178 is provided above the wide portion 115. In other words, at least a portion of the temperature sensing diode 178 overlaps with at least a portion of the wide portion 115. In this example, more than half of the temperature sensing diode 178 overlaps with the wide portion 115 when viewed from above. The entire temperature sensing diode 178 may overlap with the wide portion 115.

[0047] The metal electrode 52 and each control electrode are electrodes containing a metal such as aluminum. An interlayer insulating film is provided between the metal electrode 52 and each control electrode and the semiconductor substrate 110. The metal electrode 52 and each control electrode are connected to the semiconductor substrate 110 via contact holes provided in the interlayer insulating film. The interlayer insulating film and contact holes are omitted from FIG. 2.

[0048] The metal electrode 52 is provided above the active portion 120. The metal electrode 52 is connected to the active portion 120 via the contact hole described above. A wiring member is connected to the upper surface of the metal electrode 52, and a predetermined emitter voltage is applied to the metal electrode 52. The metal electrode 52 and each control electrode are provided separately from each other when viewed from above. A wire or the like is connected to the upper surface of each control electrode. The metal electrode 52 may be provided for each of the active portion 120-1 and the active portion 120-2. The metal electrode 52 is also connected to the well region (see FIG. 5).

[0049] A predetermined gate voltage is applied to the gate pad 50. The gate voltage applied to the gate pad 50 is supplied to the transistor portion of the active portion 120 by a gate runner 48 (described later) or the like. The gate pad 50 is provided above the first well region 111. That is, at least a portion of the gate pad 50 overlaps with at least a portion of the first well region 111. In this example, more than half of the gate pad 50 in top view overlaps with the first well region 111. The entire gate pad 50 may overlap with the first well region 111. In this example, the gate pad 50 may be provided near an edge 102-1 of the semiconductor chip 40. That is, the gate pad 50 is provided between the metal electrode 52 and the edge 102-1 of the semiconductor chip 40, and the metal electrode 52 is not provided between the gate pad 50 and the edge 102-1. Furthermore, the gate pad 50 may be provided in a region including the center position Xc of the edge 102-1 of the semiconductor chip 40 in the X-axis direction.

[0050] The current detection pad 172 is connected to a current detection unit (not shown) and detects the current flowing through the current detection unit. The anode pad 174 is connected to the anode region of the temperature sensing diode 178 via a sense wiring (see FIG. 5). The cathode pad 176 is connected to the cathode region of the temperature sensing diode 178 via a sense wiring (see FIG. 5). The sense wiring may be provided above the wide portion 115 and the narrow portion 116-1.

[0051] The current detection pad 172, the anode pad 174, and the cathode pad 176 are provided above the second well region 112. For each control electrode of the current detection pad 172, the anode pad 174, and the cathode pad 176, at least a portion of the control electrode overlaps with at least a portion of the second well region 112. In the present example, more than half of the current detection pad 172, the anode pad 174, and the cathode pad 176 overlap with the second well region 112 when viewed from above. The current detection pad 172, the anode pad 174, and the cathode pad 176 may entirely overlap with the second well region 112. In the present example, the control electrodes of the current detection pad 172, the anode pad 174, and the cathode pad 176 may be provided near the edge 102-2 of the semiconductor chip 40. That is, the control electrodes of the current detection pad 172, the anode pad 174, and the cathode pad 176 are provided between the metal electrode 52 and the edge 102-2 of the semiconductor chip 40, and no metal electrode 52 is provided between each control electrode and the edge 102-2. Furthermore, each control electrode may be provided in a region including the center position Xc in the X-axis direction of the edge 102-2 of the semiconductor chip 40. In this example, the gate pad 50 and the control electrodes of the current detection pad 172, the anode pad 174, and the cathode pad 176 may be provided on opposing edge edges 102-1 and 102-2 of the semiconductor chip 40, respectively. Furthermore, they may be provided facing each other with the divided well region 114 interposed therebetween.

[0052] 2, the gate runner 48 is indicated by a dashed line. In this example, the gate runner 48 is a wiring formed of polysilicon to which impurities are added. The gate runner 48 may be formed of a conductive material such as metal. The gate runner 48 supplies a gate voltage applied to the gate pad 50 to a transistor portion provided in the active portion 120. The gate runner 48 may be provided above a well region.

[0053] The semiconductor chip 40 may have a gate runner 48-3 provided to surround the active portion 120 in a top view. The gate runner 48-3 may be provided above the peripheral well region 113. The gate runner 48-3 may be connected to a metal gate runner, which will be described later.

[0054] The semiconductor chip 40 may have a gate runner 48-1 that surrounds at least a portion of the first well region 111 in a top view. The gate runner 48-1 may be provided along the edges of the first well region 111 in a top view. The gate runner 48-1 may have portions that are parallel to each edge of the first well region 111.

[0055] The semiconductor chip 40 may have a gate runner 48-2 that surrounds at least a portion of the second well region 112 in a top view. The gate runner 48-2 may be provided along the edges of the second well region 112 in a top view. The gate runner 48-2 may have portions that are parallel to each edge of the second well region 112.

[0056] The semiconductor chip 40 may have a gate runner 48-4 provided above the narrow portion 116 in a top view. The semiconductor chip 40 may have a gate runner 48-5 surrounding at least a portion of the wide portion 115 in a top view. The gate runner 48-5 may be provided along the edge of the wide portion 115 in a top view. The gate runner 48-5 may have portions parallel to each edge of the wide portion 115. The gate runner 48-4 and the gate runner 48-5 may divide the active portion 120 in a top view.

[0057] The semiconductor chip 40 may include an edge termination structure between the peripheral well region 113 and the edge of the semiconductor substrate 110. The edge termination structure relieves electric field concentration on the upper surface side of the semiconductor substrate 110. The edge termination structure may include, for example, a guard ring annularly arranged around the active region 120, a field plate, a resurf, or a combination of these structures. The edge termination structure is omitted in this specification.

[0058] FIG. 3 is a diagram showing an example of the arrangement of the protective film 150 of the semiconductor chip 40 as viewed from above. In FIG. 3, the area where the protective film 150 is arranged is indicated by diagonal hatching. The protective film 150 may be provided above the metal electrodes 52 and above the semiconductor substrate 110. The protective film 150 may be in contact with the upper surface of the metal electrodes 52. By providing the protective film 150, it is possible to protect the upper surface of the semiconductor chip 40. The protective film 150 is, for example, a polyimide film.

[0059] The semiconductor chip 40 may have a protective film 150-1 that covers the first well region 111. The protective film 150-1 may expose a part of the upper surface of the gate pad 50. This allows a wire or the like to be connected to the upper surface of the gate pad 50.

[0060] The semiconductor chip 40 may have a protective film 150-2 that covers the second well region 112. The protective film 150-2 may expose portions of the upper surfaces of the current detection pad 172, the anode pad 174, and the cathode pad 176. This allows wires and the like to be connected to the upper surfaces of the current detection pad 172, the anode pad 174, and the cathode pad 176.

[0061] The semiconductor chip 40 may have a protective film 150-3 that covers the peripheral well region 113. The protective film 150-3 may cover the entire peripheral well region 113. The semiconductor chip 40 may have a protective film 150-4 and a protective film 150-7 that cover the divided well region 114. The divided well region 114 may be entirely covered by the protective film 150-4 and the protective film 150-7. In this example, the protective film 150-4 covers the entire wide portion 115, and the protective film 150-7 covers the entire narrow portion 116.

[0062] The protective film 150 exposes a part of the upper surface of the metal electrode 52. This allows wires or the like to be easily connected to the upper surface of the metal electrode 52.

[0063] The semiconductor chip 40 may have a protective film 150-5 and a protective film 150-6 that divide the upper surface of the semiconductor substrate 110. The protective film 150-5 and the protective film 150-6 may be provided across the upper surface of the semiconductor substrate 110 in the X-axis direction.

[0064] 4 is a diagram showing an example of the arrangement of the semiconductor chip 40 and the chip connection portion 62 in a top view of a semiconductor module 100 according to a comparative example. Fig. 4 shows an example of the arrangement of the chip connection portion 62 of the lead frame 60 in the semiconductor chip 40. In Fig. 4, the protective film 150 overlapping the chip connection portion 62 is shown by a dotted line. Also in Fig. 4, the temperature sensing diode 178 overlapping the chip connection portion 62 is shown by a dashed line.

[0065] In this example, the chip connection portion 62 is provided so as to overlap the protective films 150-4 and 150-7 in top view. Therefore, the chip connection portion 62 overlaps the temperature sensing diode 178 and the sensing wiring (not shown in FIG. 4) in top view.

[0066] 5 is a diagram showing an example of the semiconductor module 100 in the aa cross section of FIG. 4. The aa cross section is a cross section on the XZ plane. In this cross section, the semiconductor module 100 includes a solder layer 32, a plating layer 36, an interlayer insulating film 38, a connection portion 44, a gate runner 48-4, a metal electrode 52, a chip connection portion 62 of a lead frame 60, a semiconductor substrate 110, and a protective film 150-7. In this cross section, the underside of the semiconductor substrate 110 is omitted.

[0067] A trench portion 42 is provided in the upper surface 11 of the semiconductor substrate 110. The trench portion 42 may be a gate trench portion. That is, a conductive portion in the trench portion 42 may be electrically connected to the control electrode of the gate pad 50. The trench portion 42 may have an insulating film.

[0068] In this cross section, an interlayer insulating film 38 is provided between the metal electrode 52 and the semiconductor substrate 110. The interlayer insulating film 38 also has a contact hole 45. The metal electrode 52 is connected to a connection portion 44 via the contact hole 45.

[0069] The connection portion 44 may be formed of the same material as the gate runner 48. In other words, the connection portion 44 may be a wiring formed of polysilicon to which an impurity is added. By providing the connection portion 44, the well region (in this example, the narrow portion 116-2 of the divided well region 114) and the metal electrode 52 can be electrically connected.

[0070] The metal electrode 52 is provided above the semiconductor substrate 110. In this example, the metal electrode 52 is provided on the upper surface of the interlayer insulating film .

[0071] In this cross section, the semiconductor module 100 includes sense wiring 180. The sense wiring 180-1 connects the anode region of the temperature sense diode 178 to the anode pad 174. The sense wiring 180-2 connects the cathode region of the temperature sense diode 178 to the cathode pad 176.

[0072] The sense wiring 180 is provided above the semiconductor substrate 110. In this example, the sense wiring 180 is provided on the upper surface of the interlayer insulating film 38. At least a portion of the sense wiring 180 may be provided at the same height as the metal electrode 52.

[0073] Furthermore, although the sense wiring 180 is illustrated in this cross section, the temperature sense diode 178 may also be provided at the same height as the sense wiring 180. In other words, the temperature sense diode 178 may be provided above the semiconductor substrate 110. The temperature sense diode 178 may be provided on the upper surface of the interlayer insulating film 38. At least a portion of the temperature sense diode 178 may be provided at the same height as the metal electrode 52.

[0074] In this cross section, the protective film 150-7 is provided above the metal electrode 52. The protective film 150-7 is provided above the sense wiring 180. In this example, the protective film 150-7 covers the sense wiring 180. In another cross section, the protective film 150-4 may be provided above the temperature sensing diode 178. The protective film 150-4 may cover the temperature sensing diode 178. In summary, the protective film 150 may cover the temperature sensing diode 178 and the sense wiring 180. The thickness T1 of the protective film 150 may be 1 μm or more and 20 μm or less.

[0075] The plating layer 36 is provided above the metal electrode 52. In this example, the plating layer 36 is provided on the upper surface of the metal electrode 52. At least a portion of the plating layer 36 may be provided at the same height as the protective film 150.

[0076] The solder layer 32 is provided above the plating layer 36. In this example, the solder layer 32 is provided between the chip connection portion 62 of the lead frame 60 and the plating layer 36. Also, in FIG. 5, the solder layer 32 is provided above the protective film 150-7. In this example, the solder layer 32 is provided between the chip connection portion 62 of the lead frame 60 and the protective film 150-7. The chip connection portion 62 of the lead frame 60 is provided above the solder layer 32. At least a portion of the solder layer 32 may be provided at the same height as the protective film 150. Also, the protective film 150 is provided at a position lower than the lead frame 60 in the height direction (Z-axis direction). In this example, the protective film 150 is provided below the chip connection portion 62 of the lead frame 60.

[0077] In this example, there is a point where the solder layer 32, the plating layer 36, and the protective film 150-7 meet. This point is referred to as the triple point G1. If the triple point G1 exists, repeated application of stress due to heat will cause stress concentration at the triple point G1. Therefore, it is preferable to not provide the triple point G1 in the semiconductor module 100 in order to prevent stress concentration.

[0078] Fig. 6 is a diagram showing an example of the arrangement of the semiconductor chip 40 and the chip connection portion 62 in a top view of the semiconductor module 100 according to the embodiment. Fig. 6 shows an example of the arrangement of the chip connection portion 62 of the lead frame 60 in the semiconductor chip 40. In Fig. 6, the chip connection portion 62 provided in the active portion 120-1 is referred to as chip connection portion 62-1, and the chip connection portion 62 provided in the active portion 120-2 is referred to as chip connection portion 62-2.

[0079] FIG. 7 is a diagram showing an example of the semiconductor module 100 at the bb cross section of FIG. 6. The bb cross section is a cross section on the XZ plane. In this cross section, the semiconductor module 100 includes a solder layer 32, a plating layer 36, an interlayer insulating film 38, a connection portion 44, a gate runner 48-4, a metal electrode 52, a chip connection portion 62 of a lead frame 60, a semiconductor substrate 110, and a protective film 150-7. In this cross section, the underside of the semiconductor substrate 110 is omitted. In this cross section, the configurations of the solder layer 32, the plating layer 36, and the chip connection portion 62 of the lead frame 60 differ from those in the cross section of FIG. 5. Other configurations in FIG. 7 may be the same as those in FIG. 5.

[0080] In this example, the plating layer 36 is provided in an area that does not contact the protective film 150. In this cross section, the plating layer 36 does not contact the protective film 150-7. The plating layer 36 and the protective film 150-7 are separated from each other. In other words, the semiconductor module 100 has a space 96 between the plating layer 36 and the protective film 150-7. Because the plating layer 36 is separated from the protective film 150, a triple point does not exist. Therefore, stress concentration due to the triple point can be prevented. The shortest distance D1 between the plating layer 36 and the protective film 150 may be 10 μm or more and 300 μm or less. The space 96 may be filled with the sealing resin 12 described above. In this example, the sealing resin 12 is omitted.

[0081] Furthermore, in this example, the solder layer 32 is provided in an area that does not contact the protective film 150. In this cross section, the solder layer 32 does not contact the protective film 150-7. The solder layer 32 and the protective film 150-7 are separated from each other. In other words, the semiconductor module 100 has a space 96 between the solder layer 32 and the protective film. Because the solder layer 32 is separated from the protective film 150, a triple point does not exist. Therefore, stress concentration due to the triple point can be prevented.

[0082] In this example, the protective film 150 covering the temperature sense diode 178 or the sense wiring 180 is separated from the solder layer 32 and the plating layer 36. In this cross section, the protective film 150-7 covering the sense wiring 180 is separated from the solder layer 32 and the plating layer 36. In another cross section (not shown), the protective film 150-4 covering the temperature sense diode 178 may be separated from the solder layer 32 and the plating layer 36. In this way, because the protective film 150 covering the temperature sense diode 178 or the sense wiring 180 is separated from the solder layer 32 and the plating layer 36, no triple point exists near the temperature sense diode 178 and the sense wiring 180. Therefore, stress concentration near the temperature sense diode 178 and the sense wiring 180 can be prevented.

[0083] 6, the chip connection portion 62 is provided so as not to overlap the protective film 150-4 and the protective film 150-7 in top view. That is, the chip connection portion 62 can be provided so as not to overlap the temperature sensing diode 178 and the sense wiring 180 in top view. By providing the chip connection portion 62 so as not to overlap the temperature sensing diode 178 and the sense wiring 180 in top view, it is not necessary to provide the solder layer 32 between the protective film 150 and the chip connection portion 62, and the solder layer 32 can be provided in an area that does not contact the protective film 150. Note that the bridge portion 64, the foot portion 68, etc. of the lead frame 60 may overlap the temperature sensing diode 178 and the sense wiring 180 in top view.

[0084] 6, the chip connection portion 62 is divided into a chip connection portion 62-1 and a chip connection portion 62-2. Dividing the chip connection portion 62 makes it easier to fill the sealing resin 12 near the gate runner 48-4, and makes it easier to ensure insulation between the gate runner 48-4 and the sense wiring 180.

[0085] 8 is a diagram showing an example of the semiconductor module 100 in the cc cross section of FIG. 6. The cc cross section is a cross section on the XZ plane. In this cross section, the semiconductor module 100 includes the plating layer 36, the interlayer insulating film 38, the connection portion 44, the metal gate runner 47, the gate runner 48- 3 , metal electrodes 52, chip connection portions 62 of lead frames 60, semiconductor substrate 110, and protective film 150-3. In this cross section, the underside of the semiconductor substrate 110 is omitted. In this example, explanations of common reference numerals to those in FIG. 7 will be omitted.

[0086] The metal gate runner 47 is provided above the semiconductor substrate 110. In this example, the metal gate runner 47 is provided on the upper surface of the interlayer insulating film 38. The metal gate runner 47 is electrically connected to the gate runner 48-3 through a contact hole 45 provided in the interlayer insulating film 38. The metal gate runner 47 is electrically connected to a gate pad 50, and a gate voltage may be applied to the metal gate runner 47. The metal gate runner 47 may be provided above the peripheral well region 113.

[0087] The protective film 150-3 covering the metal gate runner 47 is separated from the plating layer 36. The protective film 150-3 covering the metal gate runner 47 is also separated from the solder layer 32 (not shown in FIG. 8). By separating the protective film 150-3 covering the metal gate runner 47 from the plating layer 36 and the solder layer 32, no triple point exists near the metal gate runner 47. Therefore, stress concentration near the metal gate runner 47 can be prevented.

[0088] Fig. 9 is a diagram showing another example of the semiconductor module 100 in the bb cross section of Fig. 6. The bb cross section of Fig. 9 differs from the bb cross section of Fig. 7 in that a filler material 160 is provided between the plating layer 36 and the protective film 150. Other configurations in Fig. 9 may be the same as those in Fig. 7.

[0089] In this example, a filling material 160 is provided between the plating layer 36 and the protective film 150. The filling material 160 is filled between the plating layer 36 and the protective film 150. The filling material 160 may also be provided between the solder layer 32 and the protective film 150. The filling material 160 may be provided below the chip connection portion 62 of the lead frame 60. This configuration also makes it possible to prevent the occurrence of triple points.

[0090] The filler material 160 is preferably made of a material closer to the plating layer 36 and the solder layer 32 than the protective film 150. For example, the filler material 160 may have a lower modulus of elasticity than the protective film 150. By making the modulus of elasticity of the filler material 160 smaller than that of the protective film 150, stress concentration is less likely to occur. In this case, the filler material 160 is, for example, a silicone resin. More preferably, the filler material is a silicone gel.

[0091] Furthermore, the linear expansion coefficient of the filling material 160 may be smaller than that of the protective film 150 and the plating layer 36. The linear expansion coefficient of the filling material 160 may be smaller than that of the protective film 150 and the solder layer 32. The linear expansion coefficient is a coefficient that indicates the rate at which an object expands in length due to an increase in temperature. By reducing the difference between the linear expansion coefficient of the filling material 160 and that of the plating layer 36 or the solder layer 32 compared to that of the protective film 150, stress concentration is less likely to occur. In this case, the filling material 160 is, for example, a silicone resin or epoxy resin with an adjusted amount of inorganic filler added.

[0092] The filler material 160 may have higher adhesion to the metal electrode 52 than the protective film 150. Increasing the adhesion between the filler material 160 and the metal electrode 52 can prevent the protective film 150 from peeling off from the metal electrode 52. In this case, the filler material 160 is, for example, a silicone resin or an epoxy resin with an adjusted composition.

[0093] The filling material 160 may be a material different from the sealing resin 12. For example, the sealing resin 12 is preferably a material whose linear expansion coefficient is small compared to that of the semiconductor chip 40. On the other hand, the filling material 160 is preferably a material whose linear expansion coefficient is small compared to that of the plating layer 36 or the solder layer 32. Therefore, the filling material 160 may be a material whose linear expansion coefficient is larger than that of the sealing resin 12.

[0094] The sealing resin 12 contains a large amount of inorganic filler to reduce the thermal expansion coefficient, which tends to increase the elastic modulus of the sealing resin 12. Therefore, it is preferable that the filler material 160 has a smaller elastic modulus than the sealing resin 12.

[0095] Furthermore, since the sealing resin 12 contains a large amount of inorganic filler, it tends to have poor adhesion to the metal electrodes 52. Therefore, it is preferable that the filling material 160 has higher adhesion to the metal electrodes 52 than the sealing resin 12.

[0096] The sealing resin 12 is, for example, an epoxy resin to which 50% by volume or more and 95% by volume or less of an inorganic filler is added. Note that the filling material 160 may be a material different from the sealing resin 12.

[0097] Fig. 10 is a diagram showing another example of the semiconductor module 100 in the bb cross section of Fig. 6. The bb cross section of Fig. 10 differs from the bb cross section of Fig. 7 in that a solder layer 32 is provided between the plating layer 36 and the protective film 150. Other configurations in Fig. 10 may be the same as those in Fig. 7.

[0098] In this example, the solder layer 32 is provided between the plating layer 36 and the protective film 150-7. The side surfaces of the plating layer 36 are covered with the solder layer 32. In this example, the solder layer 32 covers the corners 37 of the plating layer 36 that are in contact with the solder layer 32. The corners 37 of the plating layer 36 are the portions where the top surface and side surfaces of the plating layer 36 intersect. Even with this configuration, it is possible to prevent the occurrence of triple points and stress concentration. Note that in this example, the solder layer 32 is separated from the protective film 150, but the solder layer 32 may be in contact with the protective film 150. Even when the solder layer 32 and the protective film 150 are in contact with each other, it is possible to prevent the occurrence of triple points.

[0099] Fig. 11 is a diagram showing another example of the semiconductor module 100 in the bb cross section of Fig. 6. The bb cross section of Fig. 11 differs from the bb cross section of Fig. 10 in the configuration of the solder layer 32. Other configurations in Fig. 11 may be the same as those in Fig. 10.

[0100] In this example, similar to FIG. 10, the solder layer 32 is provided between the plating layer 36 and the protective film 150-7. In this example, unlike FIG. 10, part of the side surface of the plating layer 36 is exposed. In other words, the entire plating layer 36 is not covered with the solder layer 32. In this example, the solder layer 32 also covers the corners 37 of the plating layer 36 that are in contact with the solder layer 32. This configuration also prevents the occurrence of triple points and stress concentration.

[0101] 12 is a diagram showing another example of the arrangement of the semiconductor chip 40 and the chip connection portion 62 in a top view of the semiconductor module 100 according to the embodiment. In FIG. 12, the configuration of the chip connection portion 62 is different from that in FIG. 6. Other configurations in FIG. 12 may be the same as those in FIG. 6.

[0102] In this example, each chip connection portion 62 has a recess 184. The recess 184 may be provided along the shape of the protective film 150. By having the recess 184 in the chip connection portion 62, the protective film 150 and the solder layer 32 can be separated, and the occurrence of triple points can be prevented.

[0103] 13 is a diagram showing another example of the arrangement of the semiconductor chip 40 and the chip connection portion 62 in the top view of the semiconductor module 100 according to the embodiment. Fig. 13 shows another example of the arrangement of the chip connection portion 62 of the lead frame 60 in the semiconductor chip 40. The arrangement of the semiconductor chip 40 and the chip connection portion 62 in the top view of Fig. 13 may be the same as the arrangement of the semiconductor chip 40 and the chip connection portion 62 in the top view of Fig. 4.

[0104] FIG. 14 is a diagram showing an example of the semiconductor module 100 in the cross section dd of FIG. 13. The cross section dd is a cross section on the XZ plane. In this cross section, the semiconductor module 100 includes a solder layer 32, a plating layer 36, an interlayer insulating film 38, a connection portion 44, a gate runner 48-4, a metal electrode 52, a chip connection portion 62 of a lead frame 60, a semiconductor substrate 110, and a protective film 150-7. In this cross section, the underside of the semiconductor substrate 110 is omitted. In this cross section, the configuration of the chip connection portion 62 of the lead frame 60 differs from the cross section of FIG. 7. Other configurations in FIG. 14 may be the same as those in FIG. 7.

[0105] In this cross section, the plating layer 36 is not in contact with the protective film 150-7. The plating layer 36 and the protective film 150-7 are separated from each other. That is, the semiconductor module 100 has a space 96 between the plating layer 36 and the protective film 150-7. Because the plating layer 36 is separated from the protective film 150, a triple point does not exist. Therefore, stress concentration due to the triple point can be prevented. The shortest distance D1 between the plating layer 36 and the protective film 150 may be 10 μm or more and 300 μm or less.

[0106] Furthermore, in this example, the chip connection portion 62 of the lead frame 60 is provided above the protective film 150-7. The chip connection portion 62 is above the protective film 150-7 and covers the protective film 150-7. Furthermore, the semiconductor module 100 has a space 96 between the chip connection portion 62 and the protective film 150-7. In this example, no solder layer 32 is provided between the chip connection portion 62 and the protective film 150-7. Even with this configuration, the plating layer 36 and the protective film 150 can be separated, and stress concentration due to triple points can be prevented.

[0107] 13, unlike in FIG. 6, the chip connection portion 62 is not divided. By not dividing the chip connection portion 62, current imbalance between the active portion 120-1 and the active portion 120-2 is less likely to occur. Furthermore, the area of the chip connection portion 62 can be increased, which can suppress heat generation due to the current flowing through the lead frame 60.

[0108] 15 is a diagram showing another example of the arrangement of the semiconductor chip 40 and the chip connection portion 62 in a top view of the semiconductor module 100 according to the embodiment. FIG. 15 shows another example of the arrangement of the chip connection portion 62 of the lead frame 60 in the semiconductor chip 40. FIG. 15 differs from FIG. 13 in that the chip connection portion 62 has a protrusion 63. Other configurations in FIG. 15 may be the same as those in FIG. 13. In FIG. 15, the arrangement of the protrusion 63 is indicated by a dotted line.

[0109] The chip connection portion 62 may have multiple protrusions 63. In this example, the chip connection portion 62 has four protrusions 63. The protrusions 63 may protrude toward the solder layer 32. In this example, the protrusions 63 protrude in the −Z-axis direction. It is preferable that the entire protrusions 63 are provided above the emitter electrode 52.

[0110] FIG. 16 is a diagram showing an example of the semiconductor module 100 in the ee cross section of FIG. 15. The ee cross section is a cross section on the XZ plane. In this cross section, the semiconductor module 100 includes a solder layer 32, a plating layer 36, an interlayer insulating film 38, a connection portion 44, a gate runner 48-4, a metal electrode 52, a chip connection portion 62 of a lead frame 60, a semiconductor substrate 110, and a protective film 150-7. In this cross section, the underside of the semiconductor substrate 110 is omitted. In this cross section, the configurations of the solder layer 32 and the chip connection portion 62 of the lead frame 60 differ from those in the cross section of FIG. 14. Other configurations in FIG. 16 may be the same as those in FIG. 14.

[0111] 14, in this example, the chip connection portion 62 of the lead frame 60 is provided above the protective film 150-7. The chip connection portion 62 is above the protective film 150-7 and covers the protective film 150-7. The semiconductor module 100 also has a space 96 between the chip connection portion 62 and the protective film 150-7.

[0112] In this example, the chip connection portion 62 has a plurality of protrusions 63 that protrude toward the solder layer 32. This makes it possible to increase the distance between the protective film 150-7 and the portion of the chip connection portion 62 above the protective film 150-7. This makes it possible to easily ensure the space 96.

[0113] 16, the solder layer 32 is provided between the chip connection portion 62 and the protective film 150-7. The semiconductor module 100 has a space 96 above the protective film 150-7 between the solder layer 32 and the protective film 150-7. The protrusions 63 cause the solder layer 32 to flow above the protective film 150-7, but in this example, the wide space 96 prevents the occurrence of triple junctions and stress concentration due to the triple junctions.

[0114] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention. [Explanation of symbols]

[0115] 10 Resin case, 11 Top surface, 12 Sealing resin, 20 Cooling portion, 21 Insulating substrate, 26 Circuit pattern, 30 Solder layer, 32 Solder layer, 36 Plating layer, 37 Corner portion, 38 Interlayer insulating film, 40 Semiconductor chip, 42 Trench portion, 44 Connection portion, 45 Contact hole, 47 Metal gate runner, 48 Gate runner, 50 Gate pad, 52 Metal electrode, 60 Lead frame, 62 Chip connection portion, 63 Protrusion portion, 64 Bridge portion, 66 Circuit Pattern connection portion, 68··foot portion, 94··space, 96··space, 100··semiconductor module, 102··edge, 110··semiconductor substrate, 111··first well region, 112··second well region, 113··peripheral well region, 114··divided well region, 115··wide portion, 116··narrow portion, 120··active portion, 150··protective film, 160··filling material, 172··current detection pad, 174··anode pad, 176··cathode pad, 178··temperature sensing diode, 180··sense wiring, 184··recess

Claims

1. a semiconductor chip having a semiconductor substrate and a metal electrode provided above the semiconductor substrate; a protective film provided above the metal electrode; a plating layer provided above the metal electrode, at least a portion of which is at the same height as the protective film; a solder layer provided above the plating layer; a lead frame provided above the solder layer; Equipped with the plating layer is provided in an area that does not contact the protective film, a filler material having a modulus of elasticity smaller than that of the protective film is filled between the plating layer and the protective film; The filling material covers the protective film. Semiconductor module.

2. The solder layer is provided in an area that does not contact the protective film. The semiconductor module according to claim 1 .

3. At least a portion of the solder layer is provided at the same height as the protective film.

3. The semiconductor module according to claim 1.

4. The protective film is provided at a position lower than the lead frame in the height direction. The semiconductor module according to claim 1 .

5. The semiconductor chip comprises: a temperature sensing diode provided above the semiconductor substrate; a sense wiring connected to the temperature sense diode; and the protective film covers the temperature sensing diode and the sensing wiring, The protective film covering the temperature sensing diode or the sensing wiring is separated from the solder layer and the plating layer. The semiconductor module according to claim 1 .

6. the lead frame includes a chip connection portion that is connected to the semiconductor chip, The chip connection portion does not overlap the temperature sensing diode and the sensing wiring when viewed from above. The semiconductor module according to claim 5 .

7. the semiconductor chip further includes a metal gate runner disposed above the semiconductor substrate; The protective film covering the metal gate runner is separated from the solder layer and the plating layer. The semiconductor module according to claim 1 .

8. The filler material has a smaller difference in linear expansion coefficient between the plating layer or the solder layer and the protective film. The semiconductor module according to claim 1 .

9. The filling material has higher adhesion to the metal electrode than the protective film. The semiconductor module according to claim 1 .

10. further comprising a sealing resin that seals the semiconductor chip and the lead frame; The filling material is a material different from the sealing resin. The semiconductor module according to claim 1 .

11. The filling material has a linear expansion coefficient greater than that of the sealing resin. The semiconductor module according to claim 10.

Images