Loop device

Abstract

The present invention prevents the occurrence of cracks in a via or the like for electrical connection with a rear surface or the like disposed around a semiconductor chip, the cracks being caused by thermal stress due to Joule heat from the semiconductor chip.　A plurality of heat radiation vias 15 are provided in an area of a substrate 11 having a semiconductor chip 20A mounted on a surface thereof in a face-up state, the area corresponding to a semiconductor chip mounting portion. A surface of the substrate 11 other than an opening for a wiring 40A and openings 12B for the heat radiation vias 15 is covered with an insulating layer 12 made of an insulating resin having low thermal conductivity. The rear surface of the semiconductor chip 20A adheres to the semiconductor chip mounting portion of the substrate 11 by means of an adhesion layer 50 made of a resin having high thermal conductivity and is connected through the adhesion layer 50 to the openings 12B for the plurality of heat radiation vias 15 provided in the semiconductor chip mounting portion of the substrate 11 and filled with a resin having high thermal conductivity.

Description

[Technical Field]

[0001] The present technology relates to an interposer, a circuit device, a method for manufacturing an interposer, and a method for manufacturing a circuit device. [Background technology]

[0002] Conventionally, SiP (System in Package) modules have been developed as a technology for various electrical products such as mobile phones, digital cameras, tuner products, etc., which makes it possible to realize large-scale systems in a single package. This SiP technology makes it possible to realize large memory capacity and multi-function integration by stacking multiple ICs or packages, thereby realizing miniaturization, weight reduction, and high functionality in various electrical products.

[0003] Furthermore, face-up structures are becoming more common for SiP modules, as they allow for low-cost manufacturing using existing manufacturing equipment. Furthermore, interposers are also known, which use vias that penetrate the front and back surfaces of a circuit board to establish electrical continuity between semiconductor chips such as LSIs on the front side and the ground on the back side, and are being utilized as a high-integration technology.

[0004] In recent years, there has been a demand for further miniaturization of SiP structures, which has led to a demand for the development of effective heat dissipation means necessary for high-density packaging. Under these circumstances, for example, for small, high-density packaged SiPs, proposals have been made to use heat dissipation via (thermal via) structures in interposers (see, for example, Patent Documents 1 and 2).

[0005] The devices described in these patent documents are configured to dissipate heat (Joule heat) from the LSI chip to the outside by directly connecting the back surface of the LSI chip to a via formed of metal (metal protrusion or thermal via) (Patent Document 1) or by connecting the back surface of the LSI chip to a via through a conductive metal (such as an island or adhesive) (Patent Document 2) in order to improve the heat dissipation properties of the circuit board and prevent a decrease in reliability due to heat generated by the circuit elements.

[0006] In addition, it has been proposed to increase the mounting efficiency of the metal parts (e.g., thermal vias) that serve as heat dissipation means by installing heat dissipation means that occupy a large area, thereby increasing the heat dissipation efficiency (see, for example, Patent Document 3).

[0007] Furthermore, a structure has been proposed in which, for the purpose of alleviating thermal stress, a concave portion made of a metal such as copper is provided on the outside of the semiconductor chip mounting portion, and this concave portion is filled with a buffer material made of a thermosetting resin or the like that has a lower Young's modulus than the metal that makes up the concave portion (see Patent Document 4). [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-324330 [Patent Document 2] Japanese Patent Application Laid-Open No. 2006-339596 [Patent Document 3] Japanese Patent Application Laid-Open No. 2007-096083 [Patent Document 4] Japanese Patent Application Laid-Open No. 2006-310783 Summary of the Invention [Problem to be solved by the invention]

[0009] In the devices described in Patent Documents 1 and 2, for example, a metal heat dissipation via is disposed in a portion of the underside of the conductive layer connected to the end of the signal line around the LSI chip. However, when heat generated by Joule heat from the LSI chip is conducted to the heat dissipation via, the thermal expansion of the heat dissipation via may cause cracks to form in the heat dissipation via, resulting in problems such as a loss of electrical connection reliability.

[0010] Furthermore, in the technology described in Patent Document 3, connection wiring such as signal lines between the LSI element and the wiring layer is performed near heat dissipation vias arranged around the semiconductor element. Therefore, in the heat dissipation vias through which Joule heat from the LSI element is thermally conducted, there is a risk that this Joule heat will thermally expand and cause cracks, and there is also a risk that the Joule heat conducted in the signal lines will cause thermal stress, which may lead to various problems.

[0011] Furthermore, in the device described in Patent Document 4, the formation of the concave portion effectively reduces the mounting area on the circuit board, which also causes a problem of a decrease in mounting density.

[0012] The purpose of this technology is to prevent cracks from occurring in heat dissipation vias (thermal vias) and vias that establish electrical connection with the backside, which are located around semiconductor elements such as LSI chips, due to thermal stress caused by Joule heat from the elements. [Means for solving the problem]

[0013] The interposer according to the present technology comprises a wiring board formed of insulating resin, wiring vias provided for electrical connection between both surfaces of the wiring board, a plurality of heat dissipation vias provided within the chip mounting area of the wiring board where a semiconductor chip is mounted, and an insulating layer that covers the openings of the wiring vias and the surface of the wiring board other than the openings of the heat dissipation vias with insulating resin having low thermal conductivity.

[0014] In another aspect of the interposer according to the present technology, the heat dissipation vias each have a circular opening with the same diameter and are arranged in a grid pattern at equal intervals.

[0015] In another aspect of the interposer according to the present technology, the insulating resin with low thermal conductivity is a solder resist, and the resin with high thermal conductivity is an Ag paste.

[0016] The circuit device according to the present technology includes a wiring board formed of insulating resin, wiring vias provided for electrical connection between both surfaces of the wiring board, a plurality of heat dissipation vias provided within a chip mounting area of the wiring board on which a semiconductor chip is mounted, and an insulating layer covering the surface of the wiring board with insulating resin having low thermal conductivity except for openings of the wiring vias and openings of the heat dissipation vias. The back surface of the semiconductor chip is formed of a resin with high thermal conductivity so that it is adhesively fixed to the chip mounting portion, and an adhesive layer that thermally connects the semiconductor chip to the heat dissipation vias.

[0017] In another aspect of the circuit device according to the present technology, the heat dissipation vias each have a circular opening shape with the same diameter and are arranged in a grid pattern at equal intervals.

[0018] In another aspect of the circuit device according to the present technology, the insulating resin with low thermal conductivity is a solder resist, and the resin with high thermal conductivity is an Ag paste.

[0019] The method for manufacturing an interposer according to the present technology includes the steps of forming wiring vias for electrical connection between both surfaces of a wiring substrate formed of insulating resin and a plurality of heat dissipation vias having openings in a chip mounting area where the semiconductor chip is mounted, and covering the surface of the wiring substrate other than the openings of the wiring vias and the openings of the heat dissipation vias with insulating resin having low thermal conductivity to form an insulating layer. and forming a conductive layer.

[0020] In another aspect of the method for manufacturing an interposer according to the present technology, in the step of forming the heat dissipation vias, the heat dissipation vias are each formed to have a circular opening shape with the same diameter, and are formed in a grid pattern at equal intervals.

[0021] Another aspect of the method for manufacturing an interposer according to the present technology is that in the step of forming the insulating layer, the insulating layer is formed using solder resist as an insulating resin with low thermal conductivity, and in the step of forming the adhesive layer, the resin with high thermal conductivity is formed using Ag paste.

[0022] A method for manufacturing a circuit device according to the present technology includes the steps of: forming wiring vias for electrical connection between both surfaces of a wiring board formed from an insulating resin, and a plurality of heat dissipation vias having openings within the chip mounting area where the semiconductor chip is mounted; covering the surface of the wiring board other than the openings of the wiring vias and the heat dissipation vias with an insulating resin having low thermal conductivity to form an insulating layer; adhesively fixing the back surface of the semiconductor chip to the chip mounting area with a resin having high thermal conductivity, and forming an adhesive layer for thermally connecting the semiconductor chip and the heat dissipation vias; and adhesively fixing the semiconductor chip face-up to the adhesive layer.

[0023] In another aspect of the method for manufacturing a circuit device according to the present technology, in the step of forming the heat dissipation vias, the heat dissipation vias are formed to have circular openings with the same diameter and are formed in a grid pattern at equal intervals.

[0024] In another aspect of the method for manufacturing a circuit device according to the present technology, in the step of forming the insulating layer, the insulating layer is formed using solder resist as an insulating resin with low thermal conductivity, and in the step of forming the adhesive layer, the resin with high thermal conductivity is formed using Ag paste.

[0025] Another method for manufacturing a circuit device according to the present technology includes the steps of: forming, in a wiring board formed of insulating resin, wiring vias for electrical connection between both surfaces of the wiring board, and a plurality of heat dissipation vias having openings within the area of the chip mounting portion on which the semiconductor chip is mounted; covering the surface of the wiring board other than the openings of the wiring vias and the openings of the heat dissipation vias with an insulating resin having low thermal conductivity to form an insulating layer; applying a resin having high thermal conductivity to the back surface of the semiconductor chip; and adhesively fixing the semiconductor chip coated with the resin having high thermal conductivity face-up to the chip mounting portion on the wiring board side to form an adhesive layer, thereby thermally connecting the semiconductor chip and the heat dissipation vias.

[0026] In another aspect of the manufacturing method for a circuit device according to the present technology, in the step of forming the heat dissipation vias, the heat dissipation vias are each formed to have circular openings with the same diameter and are formed in a grid pattern at equal intervals.

[0027] In another aspect of the manufacturing method of the circuit device according to the present technology, in the step of forming the insulating layer, the insulating layer is formed using solder resist as an insulating resin with low thermal conductivity, and in the step of forming the adhesive layer, the resin with high thermal conductivity is formed using Ag paste. [Brief explanation of the drawings]

[0028] [Figure 1] 1 is a cross-sectional view showing a structure of a circuit device including an interposer according to a first embodiment of the present technology. [Figure 2] 2 is a cross-sectional view taken along the line AA in the circuit device according to the first embodiment of the present technology. [Figure 3] 1 is an enlarged cross-sectional view showing a structure in the vicinity of a wiring via according to a first embodiment of the present technology. [Figure 4] 3 is an enlarged cross-sectional view showing a structure in the vicinity of a heat dissipation via according to a first embodiment of the present technology. FIG. [Figure 5]10A and 10B are explanatory diagrams showing other aspects of heat dissipation vias according to the first embodiment of the present technology, in which (A) shows a combination of insulating layers with different inner diameters of openings, (B) shows an aspect in which the openings are not arranged in a lattice pattern, and (C) shows an aspect in which the openings are square in shape. [Figure 6] 10 is a graph showing a correlation between the opening diameter ratio between the inner diameter of the opening and the outer diameter of the heat dissipation via and the stress of the heat dissipation via according to the first embodiment of the present technology. [Figure 7] 1A shows a main part of a circuit device according to a first embodiment of the present technology, and FIGS. 1B and 1C show modified examples thereof. [Figure 8] 10(A) to 10(G) are process diagrams showing the first half of a manufacturing process for a circuit device including an interposer according to a second embodiment of the present technology. [Figure 9] 10(H) to 10(K) are process diagrams showing the latter half of the manufacturing process of a circuit device including an interposer according to a second embodiment of the present technology. DETAILED DESCRIPTION OF THE INVENTION

[0029] The interposer of this technology has a highly thermally conductive resin disposed over the entire underside of the chip, and multiple heat dissipation vias connected to the underside of this highly thermally conductive resin, thereby dispersing and avoiding the Joule heat from the semiconductor chip from concentrating locally in the heat dissipation vias, and preventing cracks from occurring in the heat dissipation vias due to the concentration of thermal stress associated with Joule heat generated from the semiconductor element.

[0030] Hereinafter, modes for carrying out the present technology (hereinafter referred to as "embodiments") will be described with reference to the drawings. The embodiments will be described in the following order. 1. Configuration example of a circuit device including an interposer according to the first embodiment 2. Interposer according to the second embodiment and Example of a manufacturing method for a circuit device 3. No. 1 Experimental example regarding stress of heat dissipation vias in a circuit device including an interposer according to the embodiment

[0031] <1. Configuration Example of a Circuit Device Including an Interposer According to the First Embodiment> An example of the configuration of a circuit device 1 including an interposer 10 according to a first embodiment of the present technology will be described with reference to FIGS. 1 to 4. FIG. The circuit device 1 of this embodiment is The 1 0, a semiconductor chip 20 mounted on the interposer 10, a molded resin part 30 that seals the semiconductor chip 20 (20A, 20B) from above with resin, wiring 40 (40A, 40B), an adhesive layer 50 with high thermal conductivity [W / m·K], and the like.

[0032] [Interposer configuration] The interposer 10 comprises a wiring substrate 11 (hereinafter abbreviated as "substrate 11") formed of insulating resin or the like, insulating layers 12 and 13 formed on both the upper and lower surfaces of the substrate 11, a via 14 (hereinafter referred to as "wiring via 14") that establishes electrical connection between the upper and lower surfaces of the substrate 11, a heat dissipation via 15, a wiring terminal 16, and a ground terminal 17.

[0033] The substrate 11 is formed from a core material in which a wafer made of silicon resin, epoxy resin, or the like is sliced to a predetermined thickness to form a thin plate, and a conductive film layer such as copper foil is formed on both the top and bottom surfaces of the wafer. The substrate 11 is provided with insulating layers 12 and 13, wiring vias 14, heat dissipation vias 15, and conductive layers such as terminals, electrodes, and lands for wiring in various patterns (hereinafter, these of" The substrate 11 is provided with an insulating layer 12 and a filling material 13 (described later). Department 19, a chip mounting section (hereinafter referred to as "chip mounting section (MA)") is provided on which a semiconductor chip 20 is mounted.

[0034] The insulating layers 12 and 13 are made of solder resist formed to a required thickness and in a predetermined pattern on both the top and bottom surfaces of the substrate 11. As shown in Fig. 2, the insulating layers 12 and 13 are provided with openings 12A and 12B, which are circular windows, at locations corresponding to wiring vias 14 for connection to wiring 40 and heat dissipation vias 15, respectively.

[0035] The above-mentioned solder resist is made of a material with a low thermal conductivity [W / m·K] compared to adhesives such as Ag paste, which has a high thermal conductivity [W / m·K], that constitute the adhesive layer 50 described below and the filling portion 19 in the opening 12B provided in the insulating layer 12. Therefore, by providing the adhesive layer 50 and the filling portion 19, it is possible to prevent heat (Joule heat) from the semiconductor chip 20 from propagating to the insulating layer 12 and building up, which would cause cracks and the like to occur in various places on the substrate 11.

[0036] The wiring via 14 is formed by embedding a highly electrically conductive metal in the wiring via hole 14A to make an electrical connection with the wiring terminal 16 made of copper foil or the like formed in a predetermined pattern on the back side of the substrate 11.

[0037] 3, a conductive layer (hereinafter referred to as "pattern wiring 18") such as terminals, lands, and electrodes formed in a predetermined pattern using copper foil or the like is provided on the upper surface of substrate 11, which is the upper surface of wiring via 14, in order to establish electrical conduction with semiconductor chip 20. Furthermore, directly above via hole 14A for wiring via 14 on pattern wiring 18, the aforementioned opening 12A is formed by removing surrounding insulating layer 12 to open a window.

[0038] The tip of wiring 40 (such as a signal line) formed of Au wire (gold wire) or the like drawn out from the semiconductor chip 20 is connected with solder or the like to the pattern wiring 18 for electrical continuity. Note that, as will be described in detail later, a part of the molded resin part 30 (referred to as a "filled resin part 30'") enters and fills the opening 12A of the insulating layer 12 during resin molding.

[0039] The heat dissipation vias 15 are intended to prevent heat (Joule heat) generated from the semiconductor chip 20 from building up and causing cracks in the wiring vias 14. In particular, by providing the semiconductor chip 20 of the present disclosure with a face-up structure, for example, in this embodiment, the entire lower surface (rear surface) of the semiconductor chip 20, on which no pads (electrodes) for connection to the outside are provided, is utilized, and heat is dissipated by heat conduction from there to the ground terminals 17 on the lower surface of the substrate 11. Note that, as shown in FIG. 7(C) described later, a configuration in which a portion of the lower surface of the semiconductor chip 20 is adhered to an adhesive layer 50 may also be used.

[0040] The heat dissipation vias 15 are formed by, for example, electroless plating using a metal material with high thermal conductivity (e.g., Cu) so as to function as a heat conduction path (hereinafter referred to as a "thermal path (TR)") that transfers heat from the semiconductor chip 20 to the ground terminal 17. In the case of this embodiment, as shown in FIG. Regarding heat dissipation via 15, It is configured with a large number of perfect circular elements of the same radius arranged at equal intervals in a grid-like arrangement pattern.

[0041] 4, the aforementioned opening 12B communicating with the via hole 15A for the heat dissipation via 15 is formed in the portion of the insulating layer 12 on the top surface of the substrate 11 corresponding to the formation position of the heat dissipation via 15. This opening 12B is filled with Ag paste or the like, which is the same material as that of the adhesive layer 50 and has high thermal conductivity, to form a filling portion 19. With this configuration, a thermal path (TR) is formed from the semiconductor chip 20 from the adhesive layer 50 through the filling portion 19 with high thermal conductivity in this opening 12B and the heat dissipation via 15 to the ground terminal 17, thereby providing an efficient heat dissipation effect.

[0042] As described above, the same adhesive material as that used for the adhesive layer 50 can be used for the filling portion 19, and if this same adhesive is used, the adhesive layer 50 and the filling portion 19 can be manufactured simultaneously. This reduces the number of steps, thereby reducing the manufacturing cost of the circuit device 1.

[0043] Furthermore, the requirements for the filling portion 19 are not only the high thermal conductivity mentioned above, but also the following: 1) The linear expansion coefficient does not differ significantly from that of the material used for the insulating layer 12 (solder resist in this embodiment). 2) Because the lower surface is physically integrated with the upper surface of the heat dissipation via 15, the Young's modulus E [N / m 2 ] is low, It is desirable to meet each of the above requirements.

[0044] Furthermore, the openings 12B opened in the insulating layer 12 may be configured so that the outer diameters of the openings 12B vary as shown in Fig. 5(A), or so that the openings 12B of the same diameter are arranged in various arrangements other than a lattice as shown in Fig. 5(B), or so that the outer shape of the openings 12B is square as shown in Fig. 5(C). In short, any configuration that can achieve the highest thermal conductivity efficiency is sufficient, and the configuration is not limited to that disclosed herein.

[0045] 6, the outer diameter ratio of the opening 12B to the heat dissipation via 15 will be described in detail later, is set so that the outer diameter of the opening 12B is within or approximately three times the outer diameter of the heat dissipation via 15. The reason for keeping the outer diameter within or approximately three times this is to alleviate stress caused by heat, and because there is a risk of stress increase due to the difference in the linear expansion coefficient between the adhesive 50', which is the resin filled in the opening 12B, and the insulating layer 12 of the solder resist, and it is desirable to reduce this as much as possible.

[0046] The wiring terminals 16 are formed in a predetermined pattern from a conductive metal film such as copper foil on the back surface of the substrate 11. When heat (Joule heat) transmitted from the semiconductor chip 20 side via wiring 40 made of Au wire or the like is thermally conducted to the connection terminals 16 formed in a predetermined pattern from a conductive metal film such as copper foil via the wiring vias 14 having good electrical conductivity, heat dissipation from these connection terminals 16 is also expected.

[0047] The ground terminal 17 occupies a larger area than the wiring terminal 16, and therefore has a correspondingly greater heat dissipation effect. In this embodiment, in order to effectively utilize this large heat dissipation effect to effectively dissipate heat generated from the semiconductor chip 20, the installation area of the ground terminal 17 is provided on the underside of the substrate 11 at a position corresponding to the chip mounting area (MA) on the upper surface of the substrate 11.

[0048] With this configuration, the thermal path (TR) is kept to a minimum length, and heat is dissipated directly and efficiently to the outside of the substrate 11. That is, in this embodiment, as described above, a thermal path (TR) is formed that propagates heat from the back surface of the semiconductor chip 20 to the ground terminal 17, via the adhesive layer 50, the adhesive 50', and the heat dissipation via 15.

[0049] [Interposer top configuration] On the interposer 10 configured as above, as described above, the semiconductor chip 20, the molded resin part 30 in which the semiconductor chip 20 (20A, 20B) is sealed with a thermosetting resin or the like to protect the semiconductor chip 20 (20A, 20B) from above, the wiring 40 (40A, 40B) using Au wires or the like, and the adhesive layer 50 described above with a high thermal conductivity [W / m·K] are mounted. Road covering It constitutes position 1.

[0050] Next, we will explain the semiconductor chip 20 mounted on the interposer 10, the molded resin part 30 that resin-seals the semiconductor chip 20 (20A, 20B) from above, the wiring 40 (40A, 40B), and the adhesive layer 50 with high thermal conductivity (W / m·K).

[0051] The semiconductor chip 20 (20A, 20B) is mounted on the substrate 11 with the front surface (upper surface) on which the wiring pads (electrodes) are located facing up, that is, attached to the substrate 11 in a face-up manner. The semiconductor chip 20 used is a type that does not have wiring pads (electrodes) on the back surface (lower surface).

[0052] For this reason, in this embodiment, when mounting the semiconductor chip 20 on the substrate 11, the semiconductor chip 20 is mounted in a "sticky" state using a highly thermally conductive adhesive on the entire back surface (lower surface) of the semiconductor chip 20. By mounting the semiconductor chip 20 in this manner and using an adhesive with high thermal conductivity, the heat (Joule heat, etc.) generated by the semiconductor chip 20 can be efficiently guided (dissipated) from the entire back surface of the semiconductor chip 20 to the substrate 11 side.

[0053] The wiring 40 (40A, 40B) electrically connects and provides conduction between the electrodes (pads) of the semiconductor chip 20 and the top surfaces of the wiring vias 14 using a highly conductive wire (e.g., Au wire) and a wire bonder.

[0054] As described above, the adhesive layer 50 is formed over the entire back surface (lower surface) of the semiconductor chip 20 mounted in a face-up manner, and is made of a material with high thermal conductivity, so it can effectively conduct heat from the semiconductor chip 20. This forms a thermal path (TR) that guides heat to the ground terminal 17 via the filled portion 19 and the heat dissipation via 15 that are in direct physical contact with the back surface of the adhesive layer 50.

[0055] As for the installation mode of the adhesive layer 50, in addition to the adhesive mode as shown in this embodiment in Figure 7(A), it may also be configured so that the adhesive layer 50 extends onto the outer surface of the semiconductor chip 20 as shown in Figure 7(B), or so that it is formed only on the central side where heat is likely to concentrate rather than on the entire back surface (lower surface) of the semiconductor chip 20 as shown in Figure 7(C).

[0056] [Actions and Effects of the First Embodiment] In the circuit device 1 according to the present embodiment configured as described above, in order to efficiently and effectively dissipate heat by focusing on the large area of the back surface (bottom surface) of the semiconductor chip 20, an adhesive layer 50 made of a material with good thermal conductivity is formed on the entire back surface (bottom surface) of the semiconductor chip 20 mounted in a face-up state. Moreover, a thermal path (TR) (see FIG. 4) is formed that connects the back surface of the semiconductor chip 20 to the ground terminal 17 in the shortest possible manner so that heat (Joule heat) from the semiconductor chip 20 is guided to the ground terminal 17 having a wide area shape via the adhesive layer 50, the filling portion 19, and the heat dissipation via 15.

[0057] Therefore, heat from the semiconductor chip 20 is efficiently and effectively dissipated to the ground terminal 17, which effectively prevents the thermal stress caused by the heat generated by the semiconductor chip 20 from acting on the wiring vias 14 and causing cracks, etc. This can improve quality such as connection reliability, especially for semiconductor chips that generate a lot of heat.

[0058] Furthermore, by forming such thermal paths (TR) directly under the semiconductor chip 20, an effective heat dissipation effect can be obtained, so there is no need to form heat dissipation vias all the way to the periphery of the mounting area of the semiconductor chip 20. Therefore, the peripheral area of the semiconductor chip 20 can be effectively used, semiconductor chips and connection wiring can be installed at high density, and the circuit device can also be made smaller.

[0059] Furthermore, according to this embodiment, the semiconductor chip 20 mounted face-up on the upper surface of the interposer 10 forms a thermal path (TR) between the rear (lower) surface of the semiconductor chip 20 and the plurality of heat dissipation vias 15 via the adhesive layer 50, which is a resin with high thermal conductivity, and is connected in a thermally conductive state. Therefore, Joule heat generated from the semiconductor chip 20 is dispersed without being concentrated in a single heat dissipation via 15. This makes it possible to prevent cracks from occurring due to stress concentration in the heat dissipation vias 15.

[0060] Furthermore, in the insulating layer 12 on the top surface of the substrate 11, a plurality of openings 12B for heat dissipation vias 15 are opened in the chip mounting area (MA), and filled sections 19 filled with a highly thermally conductive resin are provided in multiple locations. Therefore, these filled sections 19 and the insulating layer 12 with low thermal conductivity surrounding these filled sections 19 act as buffers for thermal stress, thereby mitigating the concentration of thermal stress around the heat dissipation vias 15 and eliminating the need to install heat dissipation vias around the semiconductor chip 20. Therefore, the area for installing wiring vias around the semiconductor chip can be made larger by the amount of the heat dissipation via installation area that is not required, which ultimately leads to an increase in the packaging density of the semiconductor chips.

[0061] In addition, the circuit device 1 of this embodiment has a stacked structure of an interposer 10 and a semiconductor chip 20 above it, but it is also possible to configure a similar circuit device stacked below the interposer, for example, via an appropriate metal plate or the like.

[0062] <2. Method for manufacturing an interposer and a circuit device according to the second embodiment example > Next, a method for manufacturing an interposer 10′ and a circuit device 1′ according to a second embodiment of the present disclosure will be described with reference to Figures 8 and 9. Note that the interposer 10′ and circuit device 1′ manufactured in this embodiment differ from the interposer 10 and circuit device 1 of the first embodiment in that the upper ends of the heat dissipation vias 15 protrude somewhat above the upper surface of the substrate 11, and the connection terminals 16 and ground terminals 17 are recessed inward from the lower surface of the insulating layer 13.

[0063] The method for manufacturing the interposer 10 and the circuit device 1 of this embodiment is composed of a first step S1 to an eleventh step S11.

[0064] In the first step S1, as shown in FIG. 8(A), a core material is formed from a wafer or the like, which is composed of a substrate 11 formed of an insulating material such as silicon or epoxy resin, and an upper metal layer 11A and a lower metal layer 11B made of copper foil formed on the upper and lower surfaces of the substrate 11.

[0065] The second step S2 is as shown in (B) of the same figure. 1) Using techniques such as photolithography, a photosensitive resin called photoresist is applied to both sides of the core material (application process). 2) After that, the resist is exposed to light using a mask formed in a predetermined wiring pattern (exposure step). 3) In order to visualize the latent image formed by exposure, the film is developed with a developer (development step), thereby visualizing the desired photoresist pattern. 4) The entire surface of the substrate 11 including the transferred resist pattern (exposed or unexposed area) is immersed in an etching solution. As a result, in the case of a positive type resist, for example, the copper foil portion other than the resist pattern is melted and removed (resist removal process). By melting and removing the copper foil portion other than the resist portion applied to the pattern area corresponding to the exposed area with the etching solution, only the copper foil portion of the pattern area can be formed. As a result, the copper foil portions of the specified pattern area are formed as the upper surface metal layer 11A and the lower surface metal layer 11B. 5) In this way, the vias for forming the wiring vias 14 and the heat dissipation vias 15 are formed at predetermined locations. Ho 3 and a hole 11D (denoted by reference numeral 15A in FIG. 4). A ) is formed.

[0066] 8(C), in the third step S3, holes 11C and 11D of substrate 11 are plated (for example, by electroless plating) with a metal such as copper that has high electrical and thermal conductivity, to connect them to metal layers 11A and 11B on the top and bottom surfaces of the substrate. The metal plated into hole 11C becomes wiring via 14, and the metal plated into hole 11D becomes heat dissipation via 15.

[0067] In the fourth step S4, as shown in (D) of the figure, conductive layers (wiring vias 14, wiring terminals 16, pattern wiring 18) that will be connected to the upper and lower metal layers 11A and 11B are formed by predetermined patterning, and part of the heat dissipation means (heat dissipation vias 15 and ground terminals 17). In this embodiment, the conductive layers and heat dissipation means are formed through processes such as applying photoresist, exposing the resist using a mask with a predetermined pattern, developing the resist with a developer, and removing the resist, as in the second step S2.

[0068] That is, on the upper surface of the substrate 11, a conductive layer (pattern wiring 18) is formed integrally with the wiring via 14 formed in the hole 11C, and a metallic protrusion 15B (hereinafter referred to as a "heat dissipation protrusion 15B") (which is a heat dissipation means) is formed integrally with the heat dissipation via 15 formed in the hole 11D. On the other hand, on the lower surface of the substrate 11, a wiring terminal 16 which is a conductive layer and is integral with the wiring via 14, and a ground terminal 17 which is a conductive layer and is integral with the heat dissipation via 15 are formed.

[0069] 8(E), in the fifth step S5, solder resist SR, which is an insulating resin with low thermal conductivity, is applied to a predetermined thickness so as to cover the conductive layers on the upper and lower surfaces, namely, pattern wiring 18, wiring terminals 16, and ground terminals 17, and the heat dissipation protrusions 15B, which are heat dissipation means on the upper surface. Unnecessary portions of this solder resist SR will be removed later to form the insulating layers 12 and 13 on the upper and lower surfaces of the substrate 11.

[0070] In the sixth step S6, as shown in (F) of the same figure, the solder resist SR is exposed to light using a mask with a predetermined pattern, the solder resist SR is developed with a developer, and unnecessary parts of the solder resist are removed, and the necessary parts of the solder resist corresponding to the predetermined pattern are left behind, thereby forming insulating layers 12 and 13.

[0071] In this sixth step S6, a portion of the solder resist SR on the upper surface of the substrate 11 corresponding to the upper surface of the wiring via 14 is removed by a predetermined diameter to form a circular opening 12A, and multiple portions corresponding to the upper surface of the heat dissipation via 15 are removed by a predetermined diameter to form an opening 12B.

[0072] Similarly, in this sixth step S6, a portion of the solder resist SR on the underside of the substrate 11 corresponding to the underside of the wiring via 14 is removed by a predetermined diameter to form a circular opening 13A, and a portion of the solder resist SR corresponding to the underside of the heat dissipation via 15 is removed by a predetermined diameter to form an opening 13B.

[0073] As shown in FIG. 3, the opening 12A is a space into which the wiring 40A (40) is inserted by a wire bonder during wire bonding, in order to serve as a connection portion for the tip portion of the wiring 40A (40) that connects to the semiconductor chip 20.

[0074] 4, the opening 12B is intended to release heat from the semiconductor chip 20 and relieve thermal stress. Therefore, the opening 12B constitutes a part of the heat path that conducts heat from the semiconductor chip 20 to the ground terminal 17. In other words, a filling material with good thermal conductivity is formed using the same material at the same time as the adhesive layer 50 is formed in a later process. Department It is the space for forming 19.

[0075] As described above, if the opening 12B has an opening dimension that is excessively large compared to the outer diameter of the heat dissipation via 15, the filling material formed by filling the opening 12B may become too large. Department The difference in linear expansion coefficient between the highly thermally conductive resin 19 (Ag paste in this embodiment) and the low thermally conductive resin (solder resist) that will become the insulating layer 12 may lead to an increase in stress.

[0076] To avoid this, the opening 12B is formed to be three times the outer diameter of the heat dissipation via 15. Similarly, as shown in Fig. 5, the shape of the opening 12B is formed to be circular (for example, a perfect circle), but this is not particularly limited and it may be polygonal (for example, a square).However, in order to avoid or mitigate the occurrence of local stress concentration, a circular shape is preferable as it causes little local shape change.

[0077] On the other hand, in the present embodiment, the open spaces 13A and 13B on the underside of the substrate 11 have no particular use, but when stacking a large number of circuit devices as in the present embodiment, they can be used for electrical connection with the next circuit device (multilayer wiring) and for forming a thermal path for heat dissipation.

[0078] In the seventh step S7, as shown in FIG. 8(G), a suitable resin having high thermal conductivity is used as a filler material to fill the space of the opening 12B formed for stress relaxation, and the resin is filled into the opening 12B. Department As already explained in the first embodiment, it is preferable that the filling material satisfies the following requirements. 1) As mentioned above, it has high thermal conductivity. 2) The linear expansion coefficient does not differ significantly from that of the material used for the insulating layer 12 (solder resist in this embodiment). 3) Because the lower surface is physically integrated with the upper surface of the heat dissipation via 15, the Young's modulus E [N / m 2 ] is low.

[0079] Such a filling DepartmentAs the material for 19, for example, a thermally conductive paste such as silver paste similar to that used in the first embodiment, or a thermally conductive film such as a conductive die attach film (CDAF), can be used. Furthermore, by using the same highly thermally conductive material in this step as that used for adhesive layer 50 in the next step, it becomes possible to simultaneously perform this step (7th step S7) and the next step (8th step S8). This also makes it possible to reduce costs by reducing the number of steps.

[0080] In the eighth step S8, as shown in FIG. 9(H), each filling on the upper surface of the substrate 11 is Department 19, a suitable adhesive with high thermal conductivity is applied to a predetermined area to form an adhesive layer 50. In this case, the adhesive is applied to each filling Department 19 each filling Department This adhesive is also applied to the upper surface of the substrate 11 between the layers 19, that is, to the insulating layer 12 formed of a solder resist.

[0081] In the ninth step S9, as shown in FIG. 9(I), the semiconductor chip 20 is mounted and fixed face-up on the adhesive layer 50 so as to cover the adhesive layer 50 formed in the eighth step S8.

[0082] In this embodiment, the back surface (lower surface) of the semiconductor chip 20 is entirely covered by the respective filling layers. Department An adhesive is applied to the portion of the upper surface of the substrate 11 including 19 that corresponds to the entirety of a predetermined area, which is the chip mounting portion (MA), to form an adhesive layer 50. The entire back surface (lower surface) of the semiconductor chip 20 is adhered and fixed onto this adhesive layer 50 in a sticky state.

[0083] In addition, in this technology, the semiconductor chip 20 is attached to the insulating layer 12 and the filling layer 13 via the adhesive layer 50. DepartmentThe adhesive interface of the semiconductor chip 20 when fixed to the semiconductor chip 20 is not particularly limited to the entire surface of the semiconductor chip 20. In other words, in addition to the adhesive form of the first embodiment shown in Fig. 7(A), it may be configured to be formed on the outer surface of the semiconductor chip 20 as well, as shown in Fig. 7(B), or configured to be formed only on the central part where heat tends to concentrate, rather than on the entire back surface (lower surface) of the semiconductor chip 20, as shown in Fig. 7(C).

[0084] Furthermore, in this embodiment, adhesive is first applied to a predetermined area (chip mounting area (MA)) on the top surface of substrate 11 (8th step S8), and then semiconductor chip 20 is mounted in this area (9th step S9). However, the process order may be such that adhesive is first applied to the back surface (lower surface) of semiconductor chip 20 and then adhered to the top surface of substrate 11.

[0085] In the tenth step S10, as shown in (J) of Figure 9, wiring 40 is provided by wire bonding using a wire bonder or the like using an Au wire or the like between the pad (electrode) of the semiconductor chip 20 and the pattern wiring (conductive layer) 18 above the wiring via 14.

[0086] 9(K), in an eleventh step S11, a molded resin portion 30 is formed by resin molding using a thermosetting resin or the like so as to cover the semiconductor chip 20. During this resin molding, part of the resin seeps into the opening 12A above the pattern wiring 18, filling it with resin to form a filled resin portion 30', thereby protecting the pattern wiring portion 18 as well as the semiconductor chip 20 and insulating layer 12 from the outside. In this way, the interposer 10 and the circuit device 1 are completed.

[0087] [Effects of the second embodiment] Therefore, according to this embodiment, as described above, by using the same highly thermally conductive material as that used for the adhesive layer 50 as the filling material for filling the space in the opening 12B, it becomes possible to perform the seventh step S7 and the eighth step S8 simultaneously, which also makes it possible to reduce costs by reducing the number of steps.

[0088] Furthermore, according to the manufacturing method of this embodiment, the interposer 10 has a relatively simple structure compared to conventional interposers, and therefore can be manufactured at low cost.

[0089] <3. 1 Experiment on stress of heat dissipation via in circuit device with interposer according to the embodiment example > Next, 1 An example of an experiment conducted on the relationship between the ratio of the inner diameter of the opening of the insulating layer to the outer diameter of the heat dissipation via in a circuit device having an interposer according to the embodiment (hereinafter referred to as the "opening diameter ratio") and the ratio (hereinafter referred to as the "via stress ratio") of the stress generated in the heat dissipation via (hereinafter referred to as the "via stress") will be described using Figure 6.

[0090] It should be noted that FIG. 6 is a diagram of the first embodiment. In a positive manner In a circuit device equipped with such an interposer , opening diameter ratio and , beer This shows a graph of the function that correlates force with .

[0091] As a result of investigating the relationship between the aperture diameter ratio and via stress obtained in this experimental example, data was obtained that shows the correlation between the two. From this data showing the correlation, a graph such as that shown in Figure 6 was drawn. Note that here, the horizontal axis shows the aperture diameter ratio and the vertical axis shows the via stress ratio. Furthermore, regarding the via stress ratio, the stress generated in the heat dissipation via when the aperture diameter ratio is 1 is set to 1. Time is the standard.

[0092] As can be seen from the graph in Figure 6, which shows the results of this experiment, When the aperture diameter ratio was 1 or less, there was little data, making it difficult to obtain a clear correlation, but it appeared that the via stress ratio tended to decrease slightly. It was found that when the aperture diameter ratio was between 1 and around 2.5, the via stress ratio decreased linearly with a gentle slope (θ). Furthermore, it was found that the via stress ratio is at its minimum when the aperture diameter ratio is around 2.5. In other words, it was found that when the aperture diameter ratio exceeds around 2.5, the via stress ratio shows a positive correlation, increasing linearly with a fairly large slope (θ', where θ' ≒ 2θ).

[0093] From the above experimental results, it is judged that an opening diameter ratio of up to about 3 is appropriate because the rate of increase of the via stress ratio relative to the opening diameter ratio becomes large when the opening diameter ratio exceeds at least about 3. That is, as already explained with reference to FIG. 5, if the opening dimension is excessively large compared to the outer diameter dimension of the heat dissipation via 15, the filling material formed by filling this opening 12B becomes too large. Department The conclusion was reached that it is preferable to form the opening diameter ratio within three times the outer diameter of the heat dissipation via 15, because stress increases due to the difference in linear expansion coefficient between the highly thermally conductive resin 19 (Ag paste in this embodiment) and the low-thermal-conductivity resin (solder resist) that becomes the insulating layer 12. Also, it is not preferable for the opening diameter ratio to be less than 1, as this reduces the heat dissipation efficiency.

[0094] Based on the above findings obtained from the results of this experiment, in the first embodiment in which the present technology was implemented based on this, an opening 12B with a circular shape and opening diameter ratio was applied to the interposer 10, but the configuration of the opening of the present technology is not particularly limited to that of the opening 12B of the first embodiment.

[0095] Finally, the above-described embodiments are merely examples of the present disclosure, and the present disclosure is not limited to the above-described embodiments. Therefore, even if the embodiments are different from those described above, various modifications can be made depending on the design, etc., as long as they do not deviate from the technical concept of the present disclosure. Furthermore, the effects described in this specification are merely examples and are not intended to be limiting. Furthermore, other effects may also be present.

[0096] The drawings in the above-described embodiments are schematic, and the dimensional ratios of the various parts do not necessarily correspond to the actual ones. Furthermore, the drawings may include parts with different dimensional relationships and ratios.

[0097] The present technology can also be configured as follows. (1) a wiring substrate formed of insulating resin; a wiring via provided for electrical connection between both surfaces of the wiring board; a plurality of heat dissipation vias provided in a chip mounting area of the wiring board where a semiconductor chip is mounted; an insulating layer that covers the surface of the wiring board except for the openings of the wiring vias and the openings of the heat dissipation vias with an insulating resin having low thermal conductivity; An interposer having: (2) The heat dissipation vias each have a circular opening of the same diameter and are arranged in a grid pattern at equal intervals. The interposer according to (1) above. (3) the insulating resin having low thermal conductivity is a solder resist, The resin with high thermal conductivity is Ag paste. The interposer according to (1) or (2) above. (4) a wiring substrate formed of insulating resin; a wiring via provided for electrical connection between both surfaces of the wiring board; a plurality of heat dissipation vias provided in a chip mounting area of the wiring board on which a semiconductor chip is mounted; an insulating layer that covers the surface of the wiring board except for the openings of the wiring vias and the openings of the heat dissipation vias with an insulating resin having low thermal conductivity; an adhesive layer formed of a resin with high thermal conductivity so that the back surface of the semiconductor chip is adhesively fixed to the chip mounting portion, and which thermally connects the semiconductor chip to the heat dissipation vias; A circuit device having the (5) The heat dissipation vias each have a circular opening shape with the same diameter and are arranged in a grid pattern at equal intervals. The circuit device according to (4) above. (6) the insulating resin having low thermal conductivity is a solder resist, The resin with high thermal conductivity is Ag paste. The circuit device according to (4) or (5). (7) a step of forming, in a wiring board formed of an insulating resin, wiring vias for electrical connection between both surfaces of the wiring board and a plurality of heat dissipation vias having openings within a chip mounting area where the semiconductor chip is mounted; a step of covering the surface of the wiring board except for the openings of the wiring vias and the openings of the heat dissipation vias with an insulating resin having low thermal conductivity to form an insulating layer; Equipped with A method for manufacturing an interposer. (8) In the heat dissipation via forming step, the heat dissipation vias are formed to have circular openings with the same diameter and are formed in a lattice pattern at equal intervals. A method for manufacturing the interposer described in (7) above. (9) In the step of forming the insulating layer, the insulating layer is formed using a solder resist as an insulating resin having low thermal conductivity, and In the step of forming the adhesive layer, the resin with high thermal conductivity is formed using Ag paste. A method for manufacturing an interposer according to (7) or (8) above. (10) a step of forming, in a wiring board formed of an insulating resin, wiring vias for electrical connection between both surfaces of the wiring board and a plurality of heat dissipation vias having openings within a chip mounting area where the semiconductor chip is mounted; a step of covering the surface of the wiring board except for the openings of the wiring vias and the openings of the heat dissipation vias with an insulating resin having low thermal conductivity to form an insulating layer; a step of forming an adhesive layer for adhesively fixing the back surface of the semiconductor chip to the chip mounting portion with a resin having high thermal conductivity and thermally connecting the semiconductor chip and the heat dissipation vias; and adhesively fixing the semiconductor chip face-up to the adhesive layer. A method for manufacturing a circuit device. (11) In the step of forming the heat dissipation vias, the heat dissipation vias are formed to have circular openings with the same diameter and are formed in a lattice pattern at equal intervals. A method for manufacturing the circuit device according to (10) above. (12) In the step of forming the insulating layer, the insulating layer is formed using a solder resist as an insulating resin having low thermal conductivity, and In the step of forming the adhesive layer, the resin with high thermal conductivity is formed using Ag paste. A method for manufacturing the circuit device according to (10) or (11) above. (13) a step of forming, in a wiring board formed of an insulating resin, wiring vias for electrical connection between both surfaces of the wiring board and a plurality of heat dissipation vias having openings within a chip mounting area where the semiconductor chip is mounted; a step of covering the surface of the wiring board except for the openings of the wiring vias and the openings of the heat dissipation vias with an insulating resin having low thermal conductivity to form an insulating layer; a step of applying a resin having high thermal conductivity to the back surface of the semiconductor chip; a step of adhesively fixing the semiconductor chip coated with the highly thermally conductive resin face-up to a chip mounting portion of the wiring substrate to form an adhesive layer, thereby thermally connecting the semiconductor chip and the heat dissipation vias; Equipped with A method for manufacturing a circuit device. (14) In the step of forming the heat dissipation vias, the heat dissipation vias are formed to have circular openings with the same diameter and are formed in a lattice pattern at equal intervals. A method for manufacturing the circuit device according to (13) above. (15) In the step of forming the insulating layer, the insulating layer is formed using a solder resist as an insulating resin having low thermal conductivity, and In the step of forming the adhesive layer, the resin with high thermal conductivity is formed using Ag paste. A method for manufacturing the circuit device according to (13) or (14). [Explanation of symbols]

[0098] 1 circuit device 10 Interposer 11. Circuit board (wiring board) 11A Top metal layer 11B Bottom metal layer 11C hole (wiring via hole) 11D hole (heat dissipation via hole) 12,13 Insulating layer 12A (for wiring via) opening 12B (heat dissipation via) opening 13A (wiring terminal) opening 13B (Ground terminal) opening 14 Wiring vias 14A (wiring via) via hole 15 Heat dissipation vias 15A (heat dissipation via) via hole 15B Heat dissipation protrusion (heat dissipation via protrusion) 16 Wiring terminal (conductive layer) 17 Ground terminal (conductive layer) 18 Pattern wiring (conductive layer) 19 Filling part (Ag paste) 20 Semiconductor chips 30 Molded resin part 30´ Filled resin part 40 Wiring (Au wire) 50 adhesive layer (Ag paste) 50´ Adhesive MA chip mounting area SR solder resist TR Heat Path (Heat Conduction Path)

Claims

1. A wiring board, a semiconductor chip mounted on the upper surface side of the wiring substrate; a wiring via provided outside a region of a chip mounting portion of the wiring board on which the semiconductor chip is mounted, for electrical connection between both surfaces of the wiring board; a plurality of heat dissipation vias provided in the chip mounting area of the wiring substrate; an insulating layer covering portions of both surfaces of the wiring substrate other than the areas where the wiring vias and the heat dissipation vias are formed; a conductive layer formed in the same layer as the insulating layer covering the lower surface of the wiring board, the conductive layer electrically connecting the plurality of heat dissipation vias to each other; an adhesive layer that mounts the semiconductor chip on the insulating layer that covers the upper surface of the wiring substrate; a filling portion formed for each of the heat dissipation vias in the same layer as the insulating layer covering the upper surface of the wiring board, the filling portion being made of a material having a lower modulus of longitudinal elasticity than the material of the heat dissipation vias, and provided in contact with each of the heat dissipation vias and the adhesive layer; A circuit device having the following:

2. The heat dissipation vias each have a circular opening shape with the same diameter and are arranged in a grid pattern at equal intervals. The circuit device according to claim 1 .

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