3D mask simulation based on feature images

Abstract

A layout geometry of a lithography mask is received. The layout geometry is divided into a plurality of feature images, e.g., selected from a library. The library includes predefined feature images and their corresponding pre-calculated mask 3D (M3D) filters. The M3D filter for a feature image represents the electromagnetic scattering effect of that feature image for a given source illumination. A mask function contribution from each of the plurality of feature images is calculated by convolving the feature image with its M3D filter. The mask function contributions are combined to determine a mask function for the lithography mask illuminated by the source illumination.

Description

[Technical Field]

[0001] Related Applications This application claims priority under 35 U.S.C. §119(e) to U.S. Provisional Patent Application No. 63 / 079,067, "Three-Dimensional Mask Simulations Based on Feature Images," filed September 16, 2020, and U.S. Patent Application No. 17 / 463,075, "Three-Dimensional Mask Simulations Based on Feature Images," filed August 31, 2021. All subject matter above is incorporated herein by reference in its entirety.

[0002] The present disclosure relates to three-dimensional mask simulation, including, for example, full-chip or large-scale computational lithography applications. [Background technology]

[0003] One step in the manufacturing of semiconductor wafers involves lithography. In a typical lithography process, a light source generates light that is collected and directed by collection / illumination optics to illuminate a lithography mask. Projection optics relays the pattern produced by the illuminated mask onto the wafer, exposing the resist on the wafer according to the illumination pattern. The patterned resist is then used in processes to create structures on the wafer.

[0004] Various techniques are directed to improving the lithography process, including the design of lithography masks. In computational lithography, a lithography mask design is used as input to a three-dimensional mask model, which is used to calculate a mask function that describes the electromagnetic scattering properties of the mask illuminated by a light source. The mask function can then be used as input to an optical imaging model (e.g., the Abbe imaging model or the Hopkins imaging model) to predict the printed pattern in the resist. It is important that the three-dimensional mask model is both accurate and fast. Summary of the Invention

[0005] In one embodiment, a layout geometry of a lithography mask is received. The layout geometry is divided into a plurality of feature images, e.g., selected from a library. The library includes predefined feature images and their corresponding pre-calculated mask 3D (M3D) filters. The M3D filter for a feature image represents the electromagnetic scattering effect of that feature image for a given source illumination. A mask function contribution from each of the plurality of feature images is calculated by convolving the feature image with the M3D filter. The mask function contributions are combined to determine a mask function for the lithography mask illuminated by the source illumination.

[0006] Other aspects include components, devices, systems, enhancements, methods, processes, applications, computer-readable media, and other technologies related to any of the above.

[0007] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of embodiments of the present disclosure. The drawings are used to provide an understanding and understanding of embodiments of the present disclosure and do not limit the scope of the present disclosure to these specific embodiments. Furthermore, the drawings are not necessarily drawn to scale. [Brief explanation of the drawings]

[0008] [Figure 1A] FIG. 1 illustrates an extreme ultraviolet (EUV) lithography process suitable for use with embodiments of the present disclosure. [Figure 1B] 10 is a flowchart for calculating scattering from a mask. [Figure 2] FIG. 1 illustrates partitioning of a mask layout geometry into multiple feature images. [Figure 3] FIG. 1 shows feature images in a library. [Figure 4A] 10 is a flowchart for computing an M3D filter for a feature image. [Figure 4B] FIG. 1 illustrates an example M3D filter calculation. [Figure 5] 1 is a flowchart for developing a library of feature images. [Figure 6] FIG. 10 shows results comparing the approach described herein with other approaches. [Figure 7] 1 is a flowchart of various processes used during the design and manufacture of integrated circuits according to some embodiments of the present disclosure. [Figure 8] 1 is a diagram of an example computer system in which embodiments of the present disclosure can function. DETAILED DESCRIPTION OF THE INVENTION

[0009] Aspects of the present disclosure relate to three-dimensional mask simulation based on feature images. The illumination pattern that exposes resist on a wafer depends, among other things, on the geometric layout of the lithography mask and the source illumination. Simulation of the lithography process relies on accurate prediction of the electromagnetic field generated by the source illumination incident on the lithography mask. This electromagnetic field can be predicted using a rigorous three-dimensional simulation of Maxwell's equations, which account for diffraction and scattering effects. However, such simulations are computationally intensive and have long execution times. As a result, it is often prohibitively expensive to perform a rigorous three-dimensional simulation for a mask area covering an entire chip.

[0010] Aspects of the present disclosure relate to calculating electromagnetic field diffraction and scattering properties, represented by mask functions (MFs), by using feature images (also known as feature vectors) and a set of corresponding filters (called mask 3D or M3D filters). The feature images represent basic geometric shapes that may be present in the mask, and the corresponding M3D filters represent scattering effects resulting from the feature images. The M3D filters can be determined based on rigorous electromagnetic simulations of the scattering effects of the feature images given a source illumination.

[0011] In one approach, feature images are selected from a library of predefined feature images and their corresponding pre-computed Mask 3D (M3D) filters. The feature images in the library are: 0 Edge Feature Image: Bulk Area (No Edges) 1 edge feature image: multiple edges with different orientations Two-edge feature image: a combination of two edges with different orientations and spatial relationships to each other 3+ Edge Feature Image: A combination of three or more edges (e.g., polygon shapes). Including, but not limited to:

[0012] Advantages of the present disclosure include, but are not limited to, the following: The present invention is more suitable for use with both machine learning (ML) and non-ML frameworks, and may be more suitable for graphics processing units (GPUs) as well. Compared to fully rigorous simulations, the approach is more computationally efficient for model generation, training, and calibration, and run time is also reduced while still producing accurate results for the mask function. The resulting mask function can be efficiently used in both Hopkins and Abbe imaging models, which can be the next step in lithography simulation.

[0013] 1A illustrates an EUV lithography process suitable for use with embodiments of the present disclosure. In this system, a light source 102 generates EUV light that is collected and directed by collection / illumination optics 104 to illuminate a mask 110. Projection optics 116 relays the pattern generated by the illuminated mask onto a wafer 118, exposing resist on the wafer according to the illumination pattern. The exposed resist is then developed to produce patterned resist on the wafer, which is used to create structures on the wafer, for example, through deposition, doping, etching, or other processes.

[0014] In FIG. 1A, the light is in the EUV wavelength range, approximately 13.5 nm or in the 13.3-13.7 nm range. At these wavelengths, components are typically reflective rather than transmissive. Mask 110 is a reflective mask, and optics 104, 116 are also reflective and off-axis. This is merely an example. At other wavelengths, including deep ultraviolet (DUV), other types of lithography systems may also be used, including using transmissive masks and / or optics, and using positive or negative resists.

[0015] 1B is a flowchart for calculating scattering from a mask 110. Diffraction and scattering from the mask 110 are represented by a mask function (MF) 190. The process of FIG. 1B uses a mask description 115 and a library 120 to calculate the mask function 190 for the mask. The library includes predefined feature images 125 and corresponding filters 127 that will be called mask 3D (M3D) filters because they represent, for a given source illumination, the contribution to the overall mask function from that type of feature image. The M3D filters 127 include the effect of the source illumination.

[0016] As shown in Figure 1B, the layout geometry of the mask is received 130 and divided into multiple feature images 140. The mask function (MF) contribution from each feature image is calculated by convolving 150 the feature image 125 with its corresponding M3D filter 127. The aggregate mask function for the mask and given source illumination is determined by combining (e.g., summing) 160 the MF contributions from the individual feature images.

[0017] FIG. 2 illustrates the partitioning of a mask layout geometry into multiple feature images. Figure 2 shows two shapes 210 and 220 from the layout geometry and the partitioning of shape 210 into multiple feature images. Shape 210 is partitioned into the following feature images: one area image, six edge images, six corner images, and two edge-to-edge (E2E) images. Shape 210 can be partitioned into feature images based on rules that identify different features present in the mask layout. In this example, the interior area of polygon shape 210 and its contribution to the mask function is represented by the Area 1 feature image, which defines which areas of the mask are opaque versus transmissive or reflective. The edge feature images (Edge 1 through Edge 6) account for the diffraction and scattering of electromagnetic waves at the edges.

[0018] The remaining feature images are based on combinations of two edges where there is an interaction between the two edges. The corner feature images (Corner 1 through Corner 6) describe the interaction at the corners beyond just the individual contributions of the two edges. Note that in Figure 2, the corners include both inner and outer corners. The edge-to-edge (E2E) feature images describe the interaction between parallel edges. E2E 1 describes the interaction between edges 1 and 3. E2E 2 describes the interaction between edge 2 and the left edge of shape 220.

[0019] Each of the feature images is an image. For example, the area image can be a polygon of shape 210. Each of the edge images can be a filtered version of the associated edge. In some cases, a rasterization filter is applied to generate the feature images.

[0020] The segmentation of the layout geometry uses predefined feature images 125 from a library 120. The feature images in the library can be selected based on an understanding of scattering and what types of geometric features contribute to scattering.

[0021] Figure 3 shows some examples of feature images in the library. The feature images in Figure 3 are classified according to the number of edges in the feature image. The feature images in the top row have 0 edges, the feature images in the next row have 1 edge, then 2 edges, and then 3+ edges. These are just examples and are not exhaustive.

[0022] In the top example, the area feature image determines which areas of the mask are opaque versus transmissive or reflective. Actual instances of the area feature image can have different shapes, sizes, and locations depending on the geometric layout of the shape with respect to the mask. The M3D filter corresponding to the area feature image represents the scattering generated by each point within an area that assumes infinite area, i.e., the contribution to the mask function from each point within the bulk area of the geometric layout ignores any edge effects. Thus, convolution of the M3D filter with an instance of the area feature image (e.g., Area 1 in Figure 2) results in the MF contribution from the bulk area of that shape within the mask.

[0023] In the second column, edge feature images are another important class of feature images—because diffraction or scattering of electromagnetic waves occurs at edges. Figure 3 shows one edge feature image, but the library can have many types of edge images. For masks with only Manhattan geometry, the library contains four edge feature images corresponding to the four possible orientations of the edge within the Manhattan geometry. Some masks can also allow edges at multiples of 45 degrees or even at arbitrary angles. The M3D filter corresponding to the edge feature image represents the scattering produced by each point along the edge, assuming an infinitely long edge.

[0024] The third column shows another important class of feature images, which are combinations of two edges. When two edges are close enough, there will be an interaction between the two edges. Some examples are shown in Figure 3. In the first two examples, the two edges are parallel. This is commonly referred to as edge-to-edge (labeled E2E in Figure 2). Figure 3 shows two different polarities, depending on whether the area between the two edges is filled with mask material or not. In addition to the two different polarities, the library can also contain edge-to-edge feature images with different separations between the edges and where the edges are oriented at different angles (horizontally, vertically, multiples of 45 degrees, etc.).

[0025] In the last two examples in the third column, the two edges are perpendicular to each other. These are corner feature images: inner corner and outer corner depending on the polarity. The library can contain corners oriented at different angles. Other two edge feature images are possible. For example, the two edges can be at different angles to each other. The two edges can be separated but not parallel to each other. Therefore, the two edges will slowly converge or diverge. Corners at angles other than 90 degrees are also possible.

[0026] The bottom row shows feature images with three or more edges. The first two examples are bipolar tips. The library can contain versions of different widths and different angular orientations. The next two examples are bipolar holes or vias. The different versions can have different widths, heights, and angular orientations. The last example shows a curved edge.

[0027] Each feature image has a corresponding filter that is used to generate the MF contribution from the feature image. That is, the scattering effect of the feature image is captured by the M3D filter. In one approach, rigorous simulations are performed on the feature images, and the rigorous results are used to determine the M3D filter.

[0028] The M3D filter can be calculated by starting with low-order effects. The effect of the area image (0th-order feature image) depends only on the transmission or reflection of the area in question. In an exact simulation, the mask structure for this feature image is a constant-valued plane. The M3D filter is a constant equal to the transmission or reflection calculated from the exact simulation.

[0029] Next, consider the edge feature image. The edges in the layout geometry are divided into an area feature image plus an edge feature image. A rigorous simulation of edge scattering is then modeled by the MF contribution from the area feature image plus the MF contribution from the edge feature image. Since the MF contribution from the area feature image has already been determined, the mask function contribution from the edge feature image and the corresponding M3D filter can then be determined.

[0030] After all single-edge feature images have been considered, consider a feature image consisting of two edges. Figure 4A shows a flowchart for computing M3D filters for feature images progressing from low-order feature images to high-order feature images. Figure 4B shows an example M3D filter computation for the two-edge-gap feature image shown in Figure 3.

[0031] In the example of FIG. 4B , the M3D filters for the 0-edge and 1-edge feature images have already been calculated, and the process moves to a more complex feature image: the 2-edge feature image 405. A gap feature image with a particular spacing Δ is next considered 410. The mask structure for the gap feature image is determined to be two edges separated by spacing Δ 420. A rigorous 3D simulation can be performed 430 on this mask structure, resulting in a mask function for this mask structure.

[0032] The geometric layout for this mask structure is divided into low-order feature images: area feature image of interest + two edge feature images + gap feature image 440. This is shown pictorially in the top row of Figure 4B. The aggregate mask function calculated by rigorous electromagnetic simulation is equal to the sum of the MF contributions from each feature image.

number

number

[0033] The approach described above can be repeated for gap feature images with different spacings Δ, for example, in 1 nm increments. The approach can also be repeated for different orientations and polarities. The approach can also be repeated for other two-edge and more complex feature images.

[0034] Equation 1 can be calculated and solved in the spatial domain using direct convolution. However, Equation 1 can also be processed in the spatial frequency domain. The quantities are transformed into the spatial frequency domain and convolution becomes the product. The equivalent equation is then

number

[0035] In some cases, the feature images included in the library depend on the layout geometry of the mask. FIG. 5 is a flowchart for developing a library of feature images. The library 120 can begin with a base set of common feature images, which are then supplemented based on which feature images are present in the layout geometry of the lithography mask. In FIG. 5, a mask layout is received 510. The layout geometry is compared 520 with feature images already in the library. If the library is inadequate, for example, if a feature appears in the mask but has no corresponding feature image in the library, the library can be supplemented with additional feature images 530. M3D filters for these feature images can be calculated as described above.

[0036] In addition to performing the calculations in either the spatial domain (Equation 1 above) or the spatial frequency domain (Equation 2 above), the calculations can also be performed in parallel or sequentially. In a fully parallel approach, all feature images are convolved in parallel with the corresponding M3D filters. The results are then summed.

[0037] Various embodiments of the approach described herein may also have the following features and benefits: The approach allows for easy implementation for graphics processing units (GPUs), as well as for both machine learning (ML) and non-ML frameworks. As shown above, model formation is based on convolution between feature images and M3D filters, which is compatible with popular ML frameworks (e.g., TensorFlow) and GPUs. Thus, the model can be directly implemented within these frameworks to take advantage of capabilities (e.g., optimization engines, hardware acceleration, etc.) offered by these ML frameworks for lithography applications (e.g., lithography model calibration / fine-tuning, mask layout optimization, illumination source optimization, etc.).

[0038] The approach can also be data-efficient for model creation, training, and calibration. Traditional ML-based M3D models rely on machines to generate feature images and filters by learning from data, and the learning is highly empirical and generally requires large amounts of data to avoid overfitting and ensure predictive stability. Traditional models are computationally expensive and time-consuming to generate the required amount of data. In the approach described herein, feature images and M3D filters are generated based on physical insights that are more stable and require significantly less data.

[0039] This approach can improve runtime. Feature image generation involves rasterizing a mask polygon into a grayscale image. Traditionally, mask polygons are rasterized into a thin mask transmission function, which is computationally inefficient because a sinc (or sinc-like) rasterization function must be used for the thin mask transmission function calculation to ensure a uniform frequency response within the passband. In the approach described herein, a special rasterization function can be designed that is more compact than a sinc (or sinc-like) function and therefore more computationally efficient. This new rasterization function does not need to have a uniform frequency response in the passband. The M3D filter is modified (step 470 in FIG. 4A ) to restore the required frequency response upon convolution between the feature image and the modified M3D filter.

[0040] This approach can be computationally efficient for both Hopkins and Abbe imaging models. While only one MF is required in a Hopkins imaging simulation, multiple MFs (one per incident electromagnetic field angle) are required in an Abbe imaging simulation, which significantly increases runtime when a conventional Abbe-based approach is used because the MFs are calculated multiple times. In the approach described herein, the feature image can be independent of the incident electromagnetic field angle and therefore only needs to be calculated once. Although multiple sets of M3D filters and convolutions (one per incident electromagnetic field angle) are used, the filters can be pre-computed and the convolutions can be performed efficiently using FFT methods.

[0041] These increases in computational efficiency and runtime can make it feasible to simulate the entire mask layout of a chip within a reasonable period of time.

[0042] Figure 6 shows the results of comparing the approach described above with other approaches. These experiments simulate EUV masks with different types of patterns on the mask. Figure 6 shows the root-mean-square of the CD (critical dimension) error in the optical image predicted using this approach versus three other approaches. In Figure 6, the cross-hatched bars are the approach described herein, and the white bars are the other approaches. The left group of four bars is at a defocus of -60 nm, the middle group is at a defocus of -20 nm, and the right group is at a defocus of +20 nm. In all cases, the approach described herein has a lower root-mean-square (RMS) error.

[0043] FIG. 7 shows an example set of processes 700 used during the design, verification, and fabrication of manufactured products, such as integrated circuits, to transform and verify design data and instructions representing the integrated circuit. Each of these processes can be structured and enabled as multiple modules or operations. The term "EDA (Electronic Design Automation)" refers to the term "electronic design automation." These processes begin with the creation of a product idea 710 with information provided by a designer, which is transformed to create a manufactured product using a set of EDA processes 712. Once the design is finished, the design is taped out 734, which is when the artwork (e.g., geometric pattern) for the integrated circuit is sent to a fabrication facility that produces a set of masks, which are then used to fabricate the integrated circuit. After tape-out, semiconductor die are fabricated 736, and packaging and assembly processes 738 are performed to produce the finished integrated circuit 740.

[0044] Specifications for circuits or electronic structures can range from low-level transistor material layouts to high-level description languages. Higher levels of abstraction can be used to design circuits and systems using hardware description languages ("HDLs") such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL, or OpenVera. HDL descriptions can be converted into logic-level register transfer level ("RTL") descriptions, gate-level descriptions, layout-level descriptions, or mask-level descriptions. Each lower level of abstraction adds more useful detail to the design description, for example, more details about the modules that contain the description. Lower levels of abstraction can be computer-generated, derived from design libraries, or created by another design automation process. An example of a specification language at a lower level of abstraction for specifying more detailed descriptions is SPICE, which is used for detailed descriptions of circuits with many analog components. The description at each level of abstraction is validated for use by the corresponding tool (e.g., formal verification tool) at that layer. The design process can use the sequence shown in Figure 7. The process described can be enabled by an EDA product (or tool).

[0045] During system design 714, the functionality of the integrated circuit to be manufactured is specified. The design can be optimized for desired characteristics such as power consumption, performance, area (physical and / or lines of code), and reduced cost. Partitioning of the design into different types of modules or components can occur at this stage.

[0046] During logic design and functional verification 716, modules or components in a circuit are specified in one or more description languages, and the specifications are checked for functional accuracy. For example, the components of the circuit can be verified to produce outputs that match the requirements of the specification of the circuit or system being designed. Functional verification can use simulators and other programs such as testbench generators, static HDL checkers, and formal verifiers. In some embodiments, specialized systems of components called "emulators" or "prototyping systems" are used to accelerate functional verification.

[0047] During synthesis and design for test 718, the HDL code is converted into a netlist. In some embodiments, the netlist can be a graph structure, with edges in the graph structure representing components of the circuit and nodes in the graph structure representing how the components are connected. The HDL code and netlist together are a hierarchical artifact that can be used by an EDA product to verify that the integrated circuit, once manufactured, will perform according to the specified design. The netlist can be optimized for the target semiconductor manufacturing technology. Furthermore, the completed integrated circuit can be tested to verify that the integrated circuit meets the requirements of the specification.

[0048] During netlist verification 720, the netlist is checked for adherence to timing constraints and correspondence with the HDL code. During design planning 722, an overall floorplan for the integrated circuit is constructed and analyzed for timing and top-level routing.

[0049] During layout and physical implementation 724, physical placement (positioning of circuit components such as transistors or capacitors) and routing (connection of circuit components by multiple conductors) can occur, and cell selection from a library can be performed to enable a particular logic function. As used herein, the term "cell" can designate a set of transistors, other components, and interconnects that provide a Boolean logic function (e.g., AND, OR, NOT, XOR) or a memory function (e.g., a flip-flop or latch). As used herein, a circuit "block" can refer to two or more cells. Both cells and circuit blocks can be referred to as modules or components and are enabled both as physical structures and in simulations. Parameters such as size are specified for the selected cell (based on a "standard cell") and made accessible in a database for use by the EDA product.

[0050] During analysis and extraction 726, circuit functionality is verified at the layout level, which allows for fine-tuning of the layout design. During physical verification 728, the layout design is checked to ensure that manufacturing constraints, such as DRC constraints, electrical constraints, and lithography constraints, are correct and that circuit functionality matches HDL design specifications. During resolution enhancement 730, the geometry of the layout is transformed to improve how the circuit design will be manufactured.

[0051] During tape-out, data is prepared for use in the production of lithography masks (after lithography enhancements are applied, if appropriate). During mask data preparation 732, the "tape-out" data is used to produce lithography masks that are used to produce finished integrated circuits.

[0052] The storage subsystem of a computer system (such as computer system 800 of FIG. 8) can be used to store programs and data structures used by some or all of the EDA products described herein and products used for the development of cells for libraries and for physical and logical designs that use the libraries.

[0053] 8 illustrates an example computer system 800 machine within which a set of instructions may be executed to cause the machine to perform any one or more of the methods discussed herein. In alternative implementations, the machine may be connected (e.g., networked) to other machines within a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine within a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine within a cloud computing infrastructure or environment.

[0054] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), mobile phone, web appliance, server, network router, switch or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Further, although a single machine is shown, the term "machine" shall also be considered to include any collection of machines that individually or jointly execute a set of instructions (or multiple sets) to perform any one or more of the methods discussed herein.

[0055] The example computer system 800 includes a processing device 802, a main memory 804 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM), static memory 806 (e.g., flash memory, static random access memory (SRAM), etc.)), and a data storage device 818 that communicate with each other via a bus 830.

[0056] Processing device 802 represents one or more processors, such as a microprocessor, a central processing unit, or the like. More specifically, processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets or combinations of instruction sets. Processing device 802 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. Processing device 802 may be configured to execute instructions 826 to perform the operations and steps described herein.

[0057] Computer system 800 may further include a network interface device 808 that communicates over a network 820. Computer system 800 may also include a video display unit 810 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 812 (e.g., a keyboard), a cursor control device 814 (e.g., a mouse), a graphics processing unit 822, a signal generation device 816 (e.g., a speaker), a graphics processing unit 822, a video processing unit 828, and an audio processing unit 832.

[0058] Data storage device 818 may include a machine-readable storage medium 824 (also known as a non-transitory computer-readable medium) on which is stored one or more sets of instructions 826 or software embodying any one or more of the methods or functions described herein. The instructions 826 may also reside, completely or at least partially, within main memory 804 and / or within processing device 802 during execution of the instructions by computer system 800, main memory 804, and processing device 802, which also constitute machine-readable storage media.

[0059] In some implementations, instructions 826 include instructions that implement functions corresponding to the present disclosure. While machine-readable storage medium 824 is shown to be a single medium in example implementations, the term "machine-readable storage medium" should be considered to include a single medium or multiple media (e.g., a centralized or distributed database and / or associated caches and servers) that store one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for execution by a machine, causing the machine and processing device 802 to perform any one or more of the methods of the present disclosure. The term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0060] Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm may be a sequence of operations leading to a desired result. Operations are those requiring physical manipulation of physical quantities. Such quantities may take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. Such signals may be referred to as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0061] It should be noted, however, that all of these and similar terms are associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise, as will be apparent from this disclosure, it will be recognized that throughout the description, certain terms refer to the acts and processes of a computer system or similar electronic computing device that manipulate and convert data represented as physical (electronic) quantities in the computer system's registers and memory into other data also represented as physical quantities in the computer system's memory or registers or other such information storage devices.

[0062] The present disclosure also relates to apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purposes, or it may comprise a computer selectively activated or reconfigured by a computer program stored within the computer. Such computer programs may be stored on a computer-readable storage medium, such as any type of disk, including, but not limited to, floppy disks, optical disks, CD-ROMs, and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0063] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various other systems can be used with programs in accordance with the teachings herein, or it may prove convenient to construct a more specialized apparatus to carry out the methods. Further, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the present disclosure as described herein.

[0064] The present disclosure may be provided as a computer program product or software that may include a machine-readable medium having instructions stored thereon, which instructions may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). For example, machine-readable (e.g., computer-readable) media includes machine (e.g., computer) readable storage media such as read-only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, etc.

[0065] In the above disclosure, implementations of the present disclosure have been described with reference to specific example implementations thereof. It will be apparent that various modifications can be made to the implementations without departing from the broader spirit and scope of the implementations of the present disclosure as set forth in the appended claims. Where the present disclosure refers to several elements in the singular, more than one element may be shown in the figures, and similar elements will be labeled with similar numerals. The present disclosure and drawings are thereby to be considered in an illustrative sense, and not in a restrictive sense.

Claims

1. Receiving a layout geometry of a lithography mask, the layout geometry including a plurality of polygons; dividing the layout geometry into a plurality of feature images, the feature images being images representing geometric features present in the layout geometry of the lithography mask, and dividing the layout geometry into a plurality of feature images includes rasterizing the mask polygons using a low-pass rasterization function having a non-uniform response within a frequency passband; calculating, by a processor, a mask function (MF) contribution from each of the plurality of feature images by convolving the feature image with a corresponding mask 3D (M3D) filter, the M3D filter corresponding to a feature image representing electromagnetic scattering effects of the geometric feature represented by the feature image, the M3D filter including the effect of an equalization filter that compensates for the non-uniform response; and Combining the calculated MF contributions to determine a mask function for the lithography mask. A method comprising:

2. The method of claim 1 , further comprising determining the M3D filter by a rigorous electromagnetic simulation of the scattering effect of a mask structure based on the geometric features illuminated by a source illumination.

3. The method of claim 1 , wherein the plurality of feature images are selected from a library comprising predefined feature images and corresponding precomputed M3D filters for the predefined feature images.

4. The library of predefined feature images includes feature images of different orders of complexity, and the method comprises: The method of claim 3 , further comprising pre-computing the M3D filter at an order dependent on the complexity of the feature image.

5. Determining the M3D filter for a high order complexity feature image comprises: determining a mask structure corresponding to the high-order feature image; segmenting the mask structure into the high-level feature image and one or more low-level feature images; performing a rigorous electromagnetic simulation to predict a mask function for said mask structure; calculating the MF contribution from each of the plurality of low-level feature images by convolving the respective low-level feature image with the corresponding M3D filter of the low-level feature image; and determining the M3D filter for the high-level feature image based on combining the MF contributions from the high-level feature image with the MF contributions of the low-level feature image, thereby resulting in the predicted mask function for the mask structure corresponding to the high-level feature image. The method of claim 4, comprising:

6. 5. The method of claim 4, further comprising determining the predefined feature image in the library, wherein based on the predefined geometric features, the feature image resides within the layout geometry of the lithography mask.

7. 7. The method of claim 6, wherein the library of predefined feature images comprises a common base of feature images supplemented by higher order feature images present within the layout geometry of the lithographic mask.

8. The method of claim 1 , further comprising applying the mask function as an input to an Abbe imaging model or a Hopkins imaging model.

9. a computer-readable storage medium storing instructions and a library including pre-defined feature images and corresponding pre-computed mask 3D (M3D) filters, the pre-defined feature images being images representing geometric features present in a lithography mask layout geometry; a processor, coupled to the computer-readable storage medium, for executing instructions that, when executed, cause the processor to: dividing a layout geometry of a lithography mask into a plurality of feature images selected from the library, the layout geometry of the mask comprising a plurality of polygons, and dividing the layout geometry into a plurality of feature images comprises rasterizing the mask polygons using a low-pass rasterization function having a non-uniform response within a frequency passband; calculating a mask function (MF) contribution from each of the plurality of feature images by convolving the feature image with a corresponding M3D filter from the library, the M3D filter including the effect of an equalization filter that compensates for the non-uniform response; The system combines the calculated MF contributions to determine a mask function for the lithography mask.

10. The system of claim 9 , wherein the library of predefined feature images includes an area image, one or more single-edge images, and a plurality of multi-edge images.

11. The system of claim 10 , wherein the library of predefined feature images includes a plurality of feature images, each of which consists of two parallel edges.

12. The system of claim 10 , wherein the library of predefined feature images includes a plurality of feature images, each of which consists of two perpendicular edges forming a corner.

13. The system of claim 10 , wherein the library of predefined feature images includes a plurality of feature images, each of which consists of a single edge oriented at an angle that is not a multiple of 45 degrees.

14. The system of claim 10 , wherein the library of predefined feature images includes a plurality of feature images, each of the feature images consisting of a curved edge.

15. A non-transitory computer-readable medium having stored thereon instructions that, when executed by a processor, cause the processor to: dividing a layout geometry of a lithography mask into a plurality of feature images, the feature images being images representative of geometric features present in the layout geometry of the lithography mask, the layout geometry of the mask including a plurality of polygons, and dividing the layout geometry into feature images includes rasterizing the mask polygons using a low-pass rasterization function having a non-uniform response within a frequency passband; calculating a mask function (MF) contribution from each of the plurality of feature images using a mask 3D (M3D) filter for the feature images, the M3D filter including the effect of an equalization filter that compensates for the non-uniform response; A non-transitory computer-readable medium that combines the calculated MF contributions to determine a mask function for the lithography mask.

16. The non-transitory computer-readable medium of claim 15 , wherein the M3D filter is based on rigorous electromagnetic simulation.

17. The non-transitory computer-readable medium of claim 15 , wherein the layout geometry comprises a layout geometry for an entire chip.

18. 16. The non-transitory computer-readable medium of claim 15, wherein the source illumination of the lithography mask is extreme ultraviolet (EUV) or deep ultraviolet (DUV) illumination.

19. The method of claim 1, wherein rasterizing the mask polygon produces a grayscale feature image.

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