Semiconductor manufacturing jig and method for manufacturing semiconductor manufacturing jig

Abstract

A semiconductor manufacturing jig using materials with different physical properties and a method for manufacturing the semiconductor manufacturing jig are provided. [Solution] The semiconductor manufacturing jig according to the present disclosure is a semiconductor manufacturing jig 1 for use in a semiconductor manufacturing apparatus. The semiconductor manufacturing jig 1 includes a first layer 11 having a first resistivity and a second layer 12 laminated with the first layer 11 and having a second resistivity different from the first resistivity. The second resistivity is greater than the first resistivity, or the second resistivity is less than the first resistivity.

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor manufacturing tool and a method for manufacturing the semiconductor manufacturing tool. [Background technology]

[0002] In a plasma etching apparatus for etching semiconductor wafers, an etcher ring is used as a semiconductor manufacturing jig for holding the wafer to be etched (Patent Document 1). Such an etcher ring is formed, for example, from CVD-SiC (Silicon Carbide) formed by CVD (Chemical Vapor Deposition).

[0003] When making an etcher ring with CVD-SiC, it is common to use a material with uniform physical properties. Even if the etcher ring has a structure with two or more layers of SiC stacked together to achieve a predetermined thickness, the material is made with uniform physical properties. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2020-1947 Summary of the Invention [Problem to be solved by the invention]

[0005] However, there was a problem in that simply making semiconductor manufacturing jigs using materials with uniform physical properties, as with conventional semiconductor manufacturing jigs, did not make it possible to provide a variety of semiconductor manufacturing jigs that were suited to the applications of semiconductor manufacturing equipment.

[0006] The present disclosure has been made to solve the above-mentioned problems, and its purpose is to provide a semiconductor manufacturing jig that uses materials with different physical properties, and a method for manufacturing the semiconductor manufacturing jig. [Means for solving the problem]

[0007] A semiconductor manufacturing jig according to an aspect of the present disclosure is a semiconductor manufacturing jig for use in a semiconductor manufacturing apparatus, the semiconductor manufacturing jig including: a first layer made of SiC having a first resistivity; and a second layer made of SiC having a second resistivity different from the first resistivity, the second layer being deposited directly on the first layer by the same CVD deposition apparatus as that for the first layer. The semiconductor manufacturing jig has a first main surface and a second main surface opposite to the first main surface, and when viewed from above from the first main surface, the first layer is disposed on an inner portion and the second layer is disposed on an outer portion. .

[0008] A method for manufacturing a semiconductor manufacturing jig according to another aspect of the present disclosure is a method for manufacturing a semiconductor manufacturing jig for use in semiconductor manufacturing equipment, the method including the steps of: depositing a first layer made of SiC having a first resistivity around a substrate using a CVD deposition apparatus; depositing a second layer made of SiC having a second resistivity different from the first resistivity directly on the first layer using the same CVD deposition apparatus as for the first layer; processing the stacked first and second layers into a predetermined shape; and removing the substrate. a step of processing the stacked first and second layers so that the semiconductor manufacturing jig has a first main surface and a second main surface opposite to the first main surface, and the first layer is disposed on an inner portion and the second layer is disposed on an outer portion when viewed in plan from the first main surface; Includes: [Effects of the Invention]

[0009] The semiconductor manufacturing jig according to the present disclosure comprises a first layer having a first resistivity and a second layer stacked on the first layer and having a second resistivity different from the first resistivity, thereby making it possible to provide a variety of semiconductor manufacturing jigs to suit the applications of semiconductor manufacturing equipment. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a plan view of a semiconductor manufacturing jig according to a first embodiment. [Figure 2] 1 is a cross-sectional view of a jig for semiconductor manufacturing according to a first embodiment. [Figure 3] 1 is a schematic diagram of a CVD film-forming apparatus for manufacturing a jig for semiconductor manufacturing according to the first embodiment. [Figure 4] 2 is a cross-sectional view of a substrate used in manufacturing the semiconductor manufacturing tool according to the first embodiment. FIG. [Figure 5]1 is a cross-sectional view of a laminate in which a first layer and a second layer are laminated around a base material in the first embodiment. [Figure 6] 3 is a cross-sectional view of the stack showing a portion of a semiconductor manufacturing jig obtained by processing the stack of the first embodiment with a processing device. FIG. [Figure 7] 3 is a flowchart showing a manufacturing process of the semiconductor manufacturing jig according to the first embodiment. [Figure 8] FIG. 10 is a cross-sectional view of a jig for semiconductor manufacturing in accordance with a second embodiment. [Figure 9] 10 is a cross-sectional view of a stack showing a portion of a semiconductor manufacturing jig obtained by processing the stack of the second embodiment with a processing device. FIG. [Figure 10] FIG. 10 is a plan view of a semiconductor manufacturing jig according to a modified example. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. While multiple embodiments will be described below, it is anticipated from the beginning that the configurations described in each embodiment will be appropriately combined. Note that identical or corresponding parts in the drawings will be designated by the same reference numerals, and their description will not be repeated.

[0012] [Embodiment 1] (Configuration of semiconductor manufacturing jigs) This disclosure describes a semiconductor manufacturing jig used in a semiconductor manufacturing apparatus. In particular, this description describes a semiconductor manufacturing jig, such as an etcher ring, used in a semiconductor manufacturing apparatus that uses plasma (for example, a plasma etching apparatus). Note that the semiconductor manufacturing jig according to this disclosure is not limited to an etcher ring. FIG. 1 is a plan view of a semiconductor manufacturing jig 1 in a first embodiment. FIG. 2 is a cross-sectional view of the semiconductor manufacturing jig 1 in the first embodiment. FIG. 2 shows a cross section taken along the center line of the ring-shaped semiconductor manufacturing jig 1 shown in FIG. 1.

[0013] The semiconductor manufacturing jig 1 is an etcher ring used inside a plasma etching apparatus. The semiconductor manufacturing jig 1 is an annular member formed by laminating a first layer 11 and a second layer 12 having a different resistivity from the first layer 11. The first layer 11 is made of silicon carbide (SiC) having a first resistivity. The second layer 12 is made of SiC having a second resistivity different from the first resistivity. For example, the first resistivity is set to a value within a range of 1 Ωcm to 25 Ωcm used in typical etcher rings, and the second resistivity is set to a value greater than the first resistivity, such as 50 Ωcm or greater or 100 Ωcm or greater. Conversely, the second resistivity is set to a value within a range of 1 Ωcm to 25 Ωcm used in typical etcher rings, and the first resistivity is set to a value less than 1 Ωcm, which is smaller than the second resistivity.

[0014] The second resistivity may differ from the first resistivity by at least a value that exceeds manufacturing variations. Alternatively, the second resistivity may differ from the first resistivity by at least an order of magnitude. Furthermore, the second resistivity may have a value that exceeds the specification range of the first resistivity. Furthermore, the magnitude relationship between the first resistivity and the second resistivity is not limited to first resistivity<second resistivity, and may be first resistivity>second resistivity.

[0015] In semiconductor manufacturing jig 1, second layer 12 is stacked below first layer 11. Because semiconductor manufacturing jig 1 is annular, a circular space 13 is formed on the inner periphery, and a portion where first layer 11 and second layer 12 are stacked is formed outside of that. Semiconductor manufacturing jig 1 also has a portion where only second layer 12 is formed on the outer side. Semiconductor manufacturing jig 1 has an upper surface (first main surface) that holds wafer 2 and a lower surface (second main surface) opposite the upper surface. When viewed from above in a plan view as shown in FIG. 1, semiconductor manufacturing jig 1 is configured such that first layer 11 with a first resistivity is arranged on the inner periphery (inside) and second layer 12 with a second resistivity is arranged on the outer periphery (outside).

[0016] In the semiconductor manufacturing jig 1, a holder 14 for holding a wafer 2 to be etched is provided on the inner circumferential portion of the top surface of the first layer 11, as shown in Fig. 2. The wafer 2 has a disk shape. The holder 14 is thinner than the other portions of the semiconductor manufacturing jig 1, and a step is formed between the holder 14 and the other portions.

[0017] Generally, semiconductor manufacturing jigs, such as etcher rings, require uniform resistivity across the top surface. However, in the semiconductor manufacturing jig 1 according to the present embodiment, a first layer 11 with a first resistivity is disposed on the inner periphery and a second layer 12 with a second resistivity is disposed on the outer periphery, thereby varying the resistivity across the top surface. By varying the resistivity across the top surface, the density of the plasma etcher generated within the plasma etching apparatus can be partially changed. For example, when the first resistivity < the second resistivity relationship is satisfied, the semiconductor manufacturing jig 1 can increase the density of the plasma etcher on the inner periphery because the second layer 12 on the outer periphery has a higher resistivity. By using the semiconductor manufacturing jig 1 with varying resistivity across the top surface in a plasma etching apparatus, the processing state of the wafer 2 can be modified compared to when a conventional semiconductor manufacturing jig is used.

[0018] (Semiconductor manufacturing jig manufacturing equipment) FIG. 3 is a schematic diagram of a CVD film forming apparatus for manufacturing semiconductor manufacturing jig 1 according to the first embodiment.

[0019] The CVD film forming apparatus 4 includes a chamber 41 , a high frequency power supply 42 , a vacuum pump 43 , a source gas container 44 , a first valve 451 , a second valve 452 , and a control device 49 .

[0020] The control device 49 includes a CPU (Central Processing Unit) 491, memory (ROM (Read Only Memory) and RAM (Random Access Memory)) 492, an input / output buffer (not shown), etc. The CPU 491 loads a program stored in the ROM into the RAM, etc., and executes it. The program stored in the ROM includes a control procedure to be executed by the control device 49, parameters for depositing films with different resistivities, etc. The control device 49 controls various devices in the CVD film formation apparatus 4 in accordance with such a program.

[0021] The control device 49 controls various devices within the chamber 41, such as the high frequency power supply 42, the vacuum pump 43, the first valve 451, and the second valve 452.

[0022] A film formation table 46, a heater 47, and a shower head 48 are provided inside the chamber 41. The heater 47 is provided inside the shower head 48. A substrate 5 of the semiconductor manufacturing jig 1 on which a film is to be formed is held above the film formation table 46. The substrate 5 is made of, for example, graphite. The substrate 5 is held so that a film is formed all around it. Note that the substrate 5 may be made of a material other than graphite.

[0023] The first valve 451 is provided in the gas path between the vacuum pump 43 and the chamber 41. The second valve 452 is provided in the gas path between the source gas container 44 and the chamber 41.

[0024] When forming a film on the substrate 5 in the CVD film forming apparatus 4, the control device 49 controls the second valve 452 to be closed, the first valve 451 to be open, and the vacuum pump 43 to be operated, thereby creating a vacuum state inside the chamber 41.

[0025] Thereafter, the control device 49 controls the second valve 452 to be opened while the first valve 451 is closed to maintain the inside of the chamber 41 in a vacuum state. As a result, the source gas is supplied from the source gas container 44 into the chamber 41. When the source gas is being supplied into the chamber 41, the control device 49 controls the high-frequency power supply 42 to supply high-frequency power to the electrode of the shower head 48. As a result, the source gas is converted into plasma in the chamber 41 and released from the shower head 48.

[0026] When a film is formed on a substrate 5 in the CVD film forming apparatus 4, the control device 49 supplies power to the heater 47 and controls the heater to heat. As a result, a film of a substance contained in the source gas is formed on the film forming target, such as the substrate 5, while the film forming target is heated. The resistivity of the film to be formed can be changed by adjusting parameters such as the flow rate of the source gas, the high-frequency power, and the amount of heating by the heater. The resistivity of the film to be formed can also be adjusted by adjusting the amount of impurities added as dopants (including zero).

[0027] In such a CVD film-forming apparatus 4, a film of SiC is formed around the substrate 5, thereby forming a film for manufacturing a semiconductor manufacturing jig 1 as shown in FIGS.

[0028] The manufacturing equipment for the semiconductor manufacturing jig 1 includes not only the CVD film forming equipment 4 but also a processing equipment (not shown) for processing the semiconductor manufacturing jig 1, such as cutting.

[0029] (Method of manufacturing semiconductor manufacturing jig 1) 4 to 6, which will be described below, show an example of simultaneously manufacturing two semiconductor manufacturing jigs 1. In Fig. 4 to Fig. 6, in order to clarify the manufacturing range of each semiconductor manufacturing jig 1, the boundary between the manufacturing ranges of the two semiconductor manufacturing jigs 1 is indicated by a dashed dotted line 70.

[0030] 4 is a cross-sectional view of a substrate 5 used in manufacturing the semiconductor manufacturing jig 1 in the first embodiment. The substrate 5 is a ring-shaped member in which a first portion 51 on the outer periphery is thinner than a second portion 52 on the inner periphery. Because the substrate 5 is ring-shaped, a circular space 53 is formed on the inner periphery. The shapes of the first portion 51 and the second portion 52 of the substrate 5 are determined to be the cross-sectional shape of the interface between the stacked first and second layers.

[0031] FIG. 5 is a cross-sectional view of a laminate 6 in which a first layer 61 and a second layer 62 are laminated around a substrate 5 in the first embodiment.

[0032] 5, a first layer 61 is first formed around the substrate 5 in the CVD film-forming apparatus 4. The first layer 61 is a layer that will become the first layer 11 of the semiconductor manufacturing jig 1. The first layer 61 is a layer of SiC having a first resistivity.

[0033] Thereafter, in the CVD film forming apparatus 4, a second layer 62 is formed around the first layer 61. The second layer 62 is a layer that will become the second layer 12 of the semiconductor manufacturing jig 1. The second layer 62 is a SiC layer with a second resistivity. Because the base material 5 of the laminate 6 is ring-shaped, a circular space 63 is formed on the inner periphery after the first layer 61 and the second layer 62 are laminated.

[0034] 5, the base material 5 has a shape in which the thickness of the first portion 51 on the outer periphery side is thinner than the thickness of the second portion 52 on the inner periphery side. Accordingly, the shape of the first layer 61 of the laminate 6 has a step between the outer periphery side region and the inner periphery side region, following the shape of the base material 5. Furthermore, the shape of the second layer 62 of the laminate 6 has a step between the outer periphery side region and the inner periphery side region, following the shape of the first layer 61.

[0035] After the stack 6 shown in FIG. 5 is formed in the CVD film forming apparatus 4, the stack 6 can be processed in a processing apparatus to obtain the semiconductor manufacturing jig 1 having the shape shown in FIGS. 1 and 2.

[0036] 6 is a cross-sectional view of the laminate 6 showing a portion of the semiconductor manufacturing jig 1 obtained by processing the laminate 6 of the embodiment 1 using a processing device. As shown in FIG. 6, two semiconductor manufacturing jigs 1 can be obtained from the laminate 6.

[0037] 6, the processing portion for obtaining the semiconductor manufacturing jig 1 will be described below, taking the semiconductor manufacturing jig 1 shown at the bottom of the figure as a representative example. In the processing device, the laminate 6 is processed as follows, thereby obtaining the semiconductor manufacturing jig 1 having the configuration shown in FIG.

[0038] When obtaining the semiconductor manufacturing jig 1 shown in the lower part of the figure from the laminate 6, first, in a processing device, the lower surface of the laminate 6 is cut to the position of the dashed line 71 to be flattened, and then the upper surface of the laminate 6 is cut to the position of the dashed line 72 to be flattened. As a result, both end surfaces of the laminate 6 in the stacking direction are flattened.

[0039] Next, in the processing device, the outer periphery of the laminate 6 is cut to a position such as dashed line 73 to expose the first portion 51 of the base material 5, and the inner periphery of the laminate 6 is cut to a position such as dashed line 74 to expose the second portion 52 of the base material 5.

[0040] In processing to expose first portion 51 of substrate 5, the position of the center of the circle of substrate 5 is used as a reference position, and the outer periphery side of laminate 6 is cut to a position that is the same as the position of the predetermined outer periphery dimension of semiconductor manufacturing jig 1 as indicated by dashed line 73. In processing to expose second portion 52 of substrate 5, the position of the center of the circle of ring-shaped substrate 5 is used as a reference position, and the inner periphery side of laminate 6 is cut to a position that is the same as the position of the predetermined inner periphery dimension of semiconductor manufacturing jig 1 as indicated by dashed line 74.

[0041] In the processing to expose the first portion 51 of the base material 5, it is sufficient to cut the laminate 6 until at least the outer peripheral end and inner peripheral end of the base material 5 are exposed, and cutting to the position indicated by the dashed line 73 in Figure 6 and cutting to the position indicated by the dashed line 74 in Figure 6 may be performed after removing the base material 5.

[0042] Next, a chemical treatment is performed to remove base material 5. As a result, stack 6 is separated into a first member for fabricating semiconductor manufacturing jig 1 shown above dashed-dotted line 70 in Fig. 6 and a second member for fabricating semiconductor manufacturing jig 1 shown below dashed-dotted line 70 in Fig. 6.

[0043] In the following, a processing method for producing semiconductor manufacturing jig 1 will be described with respect to the members for producing semiconductor manufacturing jig 1 shown in the lower part of FIG.

[0044] 6 is held in a processing section of a processing device with the side of second layer 62, which has been planarized as described above, facing downward. The processing device then cuts the top surface of semiconductor manufacturing jig 1 until second layer 62 is exposed.

[0045] Specifically, the upper surface of the second member is cut using the position of the lower end of the substrate 5 as a reference position so that the cross-sectional shape of the semiconductor manufacturing jig 1 becomes the cross-sectional shape shown in Fig. 2. The processing device cuts the second member, for example, up to the position of dashed line 75 in Fig. 6, and then further cuts the second member up to the position of dashed line 76. The positions at which the upper surface of the second member is cut can be estimated in advance based on the elapsed time from the start to the end of deposition of the first layer 61 (11) and the second layer 62 (12), and the deposition rates of the first layer 61 and the second layer 62.

[0046] Furthermore, the lower surface of the second member is cut using the position of the lower end of the substrate 5 as a reference position so that the cross-sectional shape of the semiconductor manufacturing jig 1 becomes the cross-sectional shape shown in Fig. 2. For example, the second member is cut to the position of dashed line 77 in Fig. 6. The position at which the lower surface of the second member is cut can be estimated in advance based on the elapsed time from the start to the end of deposition of the first layer 61 (11) and the second layer 62 (12), and the deposition rates of the first layer 61 and the second layer 62.

[0047] As a result, the semiconductor manufacturing jig 1 has a configuration in which a portion where the first layer 11 and the second layer 12 are stacked is formed outside the space portion 13, as shown in Figure 2, and a portion where only the second layer 12 is formed further outside.

[0048] The first member can be processed in the same manner as the second member described above to obtain semiconductor manufacturing jig 1 having the configuration shown in FIG.

[0049] In embodiment 1, as described above, a stack 6 as shown in FIG. 5 is formed in a CVD film forming apparatus 4, and then the stack 6 is processed in a processing apparatus as shown in FIG. 6, thereby obtaining a semiconductor manufacturing jig 1 having a configuration as shown in FIGS. 1 and 2 from the stack 6.

[0050] (Semiconductor manufacturing jig manufacturing process) Fig. 7 is a flowchart showing the manufacturing process of semiconductor manufacturing jig 1 according to embodiment 1. The flow of manufacturing processes for realizing the manufacturing method of semiconductor manufacturing jig 1 described above with reference to Figs. 4 to 6 will be summarized using Fig. 7.

[0051] The manufacturing process shown in FIG. 7 will be explained mainly to summarize the manufacturing method of the semiconductor manufacturing jig 1 described above and to clarify the flow of the manufacturing process.

[0052] In step S1, a first layer 61 of SiC having a first resistivity is formed around the substrate 5 in the CVD film formation apparatus 4. Specifically, in step S1, as described above, the first layer 61 is formed around the substrate 5 so as to have the cross-sectional shape shown in FIG.

[0053] In step S2, a second layer 62 of SiC having a second resistivity is formed around the first layer 61 in the CVD film formation apparatus 4. Specifically, in step S2, as described above, the second layer 62 is formed around the first layer 61 so as to have the cross-sectional shape shown in FIG. 5. By performing steps S1 and S2, a stacked body 6 as shown in FIG. 5 is formed.

[0054] In the process of step S3, the processing device processes the upper surface side of the laminate 6 into a flat surface, and also processes the lower surface side of the laminate 6 into a flat surface. In the process of step S3, as described above, the upper surface side of the laminate 6 shown in FIG. 6 is flattened to the position of the dashed line 72, and the lower surface side is flattened to the position of the dashed line 71.

[0055] In step S4, the processing device exposes the inner and outer circumferential sides of the substrate 5. Specifically, in step S4, as described above, the inner circumferential side of the laminate 6 is cut up to the position of the predetermined broken line 74, with the center position of the circle of the substrate 5 shown in Fig. 6 as the reference position. Furthermore, in step S4, as described above, the outer circumferential side of the laminate 6 is cut up to the position of the predetermined broken line 73, with the center position of the circle of the substrate 5 shown in Fig. 6 as the reference position.

[0056] In step S5, the processing device removes the base material 5. Specifically, in step S5, the base material 5 exposed in step S4 is removed by chemical treatment. This results in the first member and the second member as described above.

[0057] In step S6, the processing device cuts the first member or the second member so that its cross-sectional shape matches the cross-sectional shape of the semiconductor manufacturing jig 1 shown in Fig. 2. In other words, the processing device processes the first member or the second member into the configuration of the semiconductor manufacturing jig 1 in which a portion where the first layer 11 and the second layer 12 are stacked is formed outside the space portion 13, and a portion where only the second layer 12 is formed further outside, as shown in Fig. 2.

[0058] Specifically, in the process of step S6, as described above, the position of the bottom end of base material 5 shown in Fig. 6 is used as a reference position, and the portion that will become the top surface of semiconductor manufacturing jig 1 is cut down to the position of dashed line 75. Also, in the process of step S6, as described above, the position of the bottom end of base material 5 shown in Fig. 6 is used as a reference position, and the portion that will become the bottom surface of semiconductor manufacturing jig 1 is cut down to the position of dashed line 76.

[0059] By carrying out the manufacturing process as described above, the semiconductor manufacturing jig 1 having the configuration shown in FIGS. 1 and 2 can be obtained.

[0060] In the semiconductor manufacturing jig 1 of the first embodiment, the first layer 11 and the second layer 12 are made of the same material, SiC. However, the present invention is not limited to this, and the first layer 11 and the second layer 12 may be made of different materials. For example, the second layer 12 may be made of a silicon material other than SiC.

[0061] Furthermore, semiconductor manufacturing jig 1 is not limited to having two layers of SiC stacked, but may have three or more layers of SiC stacked. For example, semiconductor manufacturing jig 1 may have a structure in which three or more layers of SiC are stacked in order to increase the thickness of semiconductor manufacturing jig 1. When three or more layers of SiC are stacked, the resistivity of the third layer may be the same as or different from the first resistivity of first layer 11 or the second resistivity of second layer 12.

[0062] As described above, semiconductor manufacturing jig 1 according to the first embodiment includes first layer 11 having a first resistivity and second layer 12 laminated with first layer 11 and having a second resistivity different from the first resistivity, and can be configured to suit the application of semiconductor manufacturing jig 1. Furthermore, when viewed in plan from the top, semiconductor manufacturing jig 1 has first layer 11 disposed on the inner circumferential portion and second layer 12 disposed on the outer circumferential portion, which allows the density of the plasma etcher to be changed within the plane of the top surface.

[0063] [Embodiment 2] Next, semiconductor manufacturing jig 1a according to embodiment 2 will be described with reference to Figures 8 to 9. Note that the method for manufacturing semiconductor manufacturing jig 1a according to embodiment 2 is basically the same as the method for manufacturing semiconductor manufacturing jig 1 shown in embodiment 1 and described with reference to Figures 3 to 7, and therefore detailed description thereof will not be repeated.

[0064] (Configuration of semiconductor manufacturing jigs) FIG. 8 is a cross-sectional view of the entire semiconductor manufacturing jig 1a according to the second embodiment. The cross section of the semiconductor manufacturing jig 1a shown in FIG. 8 is taken along the center line of the ring shape. In the semiconductor manufacturing jig 1a, a second layer 12a having a different resistivity from the first layer 11a is formed below the first layer 11a. The first layer 11a is made of SiC having a first resistivity, similar to the first layer 11 described above. The second layer 12a is made of SiC having a second resistivity, similar to the second layer 12 described above.

[0065] Since semiconductor manufacturing jig 1a has an annular shape, a circular space 13 is formed on the inner periphery, and a holding portion 14 for holding wafer 2 is provided outside of this. Holding portion 14 is formed by a portion where first layer 11a and second layer 12a are stacked. Semiconductor manufacturing jig 1a also has a portion where first layer 11a and second layer 12a are stacked further outside holding portion 14. Semiconductor manufacturing jig 1a has an upper surface (first main surface) that holds wafer 2, and a lower surface (second main surface) that faces the upper surface. Semiconductor manufacturing jig 1a is configured so that first layer 11a is arranged on the upper surface, and second layer 12a is arranged on the lower surface.

[0066] The wafer 2 is fixed by a chuck device provided in the plasma etching apparatus. Meanwhile, the semiconductor manufacturing jig 1a is placed around the chuck device. Therefore, when the wafer 2 and the semiconductor manufacturing jig 1a are cooled in the plasma etching apparatus, the cooling efficiency of the wafer 2 that is in close contact with the chuck device is high, while the cooling efficiency of the semiconductor manufacturing jig 1a that is simply placed on the device is low. Therefore, in the semiconductor manufacturing jig 1a, it is conceivable to increase the thermal conductivity of the lower surface side that contacts the device and improve the cooling efficiency by making the second resistivity of the second layer 12a on the lower surface smaller than the first resistivity of the first layer 11a on the upper surface.

[0067] (Method of manufacturing semiconductor manufacturing jigs) 9 is a cross-sectional view of the stack of semiconductor manufacturing jigs 1a obtained by processing the stack of the embodiment 2 using a processing device. As shown in FIG. 9, two semiconductor manufacturing jigs 1a can be obtained from the stack of semiconductor manufacturing jigs 6.

[0068] The manufacturing method of the semiconductor manufacturing jig 1a of embodiment 2 is the same as the method described in embodiment 1 using Figures 4 and 5, up to the method of forming the laminate 6 in which the first layer 61 and the second layer 62 are stacked around the base material 5.

[0069] In the following, the processing portion for obtaining semiconductor manufacturing jig 1a will be described, taking as a representative example semiconductor manufacturing jig 1a shown at the bottom of Fig. 9, out of the areas for obtaining two semiconductor manufacturing jigs 1a shown in Fig. 9. In the processing device, stack 6 is processed as follows, thereby obtaining semiconductor manufacturing jig 1a having the structure shown in Fig. 8.

[0070] When obtaining the semiconductor manufacturing jig 1a shown in the lower part of the drawing from the laminate 6, the processing device first performs a process of cutting and planarizing the lower surface of the laminate 6, for example, to the position of the broken line 71a, and then a process of cutting and planarizing the upper surface of the laminate 6, for example, to the position of the broken line 72a. As a result, both end surfaces of the laminate 6 in the stacking direction are planarized.

[0071] Next, in the processing device, the outer periphery of the laminate 6 is cut to a position such as dashed line 73a to expose the first portion 51 of the base material 5, and the inner periphery of the laminate 6 is cut to a position such as dashed line 74a to expose the second portion 52 of the base material 5.

[0072] In processing to expose first portion 51 of substrate 5, the center position of the circle of substrate 5 is used as a reference position, and the outer periphery side of laminate 6 is cut to a position that is the same as the position of the predetermined outer periphery dimension of semiconductor manufacturing jig 1a as indicated by dashed line 73a. In processing to expose second portion 52 of substrate 5, the center position of the circle of ring-shaped substrate 5 is used as a reference position, and the inner periphery side of laminate 6 is cut to a position that is the same as the position of the predetermined inner periphery dimension of semiconductor manufacturing jig 1a as indicated by dashed line 74a.

[0073] In the processing to expose the first portion 51 of the base material 5, it is sufficient to cut the laminate 6 until at least the outer peripheral end and the inner peripheral end of the base material 5 are exposed, and cutting to the position indicated by the dashed line 73a in Figure 9 and cutting to the position indicated by the dashed line 74a in Figure 9 may be performed after removing the base material 5.

[0074] Next, a chemical treatment is performed to remove base material 5. As a result, stack 6 is separated into a first member for producing semiconductor manufacturing jig 1a shown above dashed-dotted line 70 in FIG. 9 and a second member for producing semiconductor manufacturing jig 1a shown below dashed-dotted line 70 in FIG. 9.

[0075] In the following, a processing method for producing semiconductor manufacturing jig 1a will be described with respect to the members for producing semiconductor manufacturing jig 1a shown in the lower part of FIG.

[0076] 8 is held in a processing section of a processing device with the side of second layer 62, which has been planarized as described above, facing downward. The processing device then cuts the top surface of semiconductor manufacturing jig 1a until second layer 62 is exposed.

[0077] Specifically, the upper surface of the second member is cut using the position of the lower end of the substrate 5 as a reference position so that the cross-sectional shape of the semiconductor manufacturing jig 1a becomes the cross-sectional shape shown in Fig. 8. The processing device cuts the second member, for example, to the position of dashed line 75a in Fig. 9, and then further cuts the second member to the position of dashed line 76a. Note that the positions at which the upper surface of the second member is cut can be estimated in advance based on the elapsed time from the start to the end of deposition of the first layer 61 (11a) and the second layer 62 (12a), and the deposition rates of the first layer 61 and the second layer 62.

[0078] Furthermore, the lower surface of the second member is cut using the position of the lower end of the substrate 5 as a reference position so that the cross-sectional shape of the semiconductor manufacturing jig 1a becomes the cross-sectional shape shown in Fig. 8. For example, the second member is cut to the position of dashed line 77a in Fig. 9. The position at which the lower surface of the second member is cut can be estimated in advance based on the elapsed time from the start to the end of deposition of the first layer 61 (11a) and the second layer 62 (12a) and the deposition rates of the first layer 61 and the second layer 62.

[0079] As a result, semiconductor manufacturing jig 1a has a configuration in which first layer 11a is formed on the upper surface and second layer 12a is formed on the lower surface, as shown in FIG.

[0080] The first member can be processed in the same manner as the second member described above to obtain a semiconductor manufacturing jig 1a having a configuration as shown in FIG.

[0081] In the second embodiment, as described above, a stack 6 as shown in FIG. 5 is formed in the CVD film forming apparatus 4, and then the stack 6 is processed in the processing apparatus as shown in FIG. 9, thereby obtaining a semiconductor manufacturing jig 1a having the configuration as shown in FIG. 8 from the stack 6.

[0082] [Variations] The semiconductor manufacturing jig 1 according to the first embodiment has been described as having a configuration in which the resistivity varies radially on the upper surface, as shown in FIG. 1 . Specifically, the semiconductor manufacturing jig 1 shown in FIG. 1 has a first layer 11 with a first resistivity on the inner circumferential side and a second layer 12 with a second resistivity on the outer circumferential side. The semiconductor manufacturing jig 1a according to the second embodiment has been described as having a configuration in which the resistivity varies thicknesswise, as shown in FIG. 8 . Specifically, the semiconductor manufacturing jig 1a shown in FIG. 8 has a first layer 11a with a first resistivity on the upper surface and a second layer 12a with a second resistivity on the lower surface. However, the semiconductor manufacturing jig according to the present disclosure is not limited to a configuration in which the resistivity varies radially or thicknesswise. The semiconductor manufacturing jig according to the present disclosure may have any portion with a different resistivity.

[0083] For example, the semiconductor manufacturing jig may have a configuration in which the resistivity varies circumferentially on its top surface. FIG. 10 is a plan view of a semiconductor manufacturing jig 1b according to a modification. When viewed from the top as shown in FIG. 10, semiconductor manufacturing jig 1b has a different resistivity in each of its quarters. Specifically, semiconductor manufacturing jig 1b has a first region made of layer 11c having a first resistivity, a second region made of layer 12c having a second resistivity, a third region made of layer 11d having a first resistivity, and a fourth region made of layer 12d having a second resistivity. While semiconductor manufacturing jig 1b has two regions divided into layers with different resistivities, the regions may be divided into three or more layers with different resistivities. Although semiconductor manufacturing jig 1b has a top surface divided into equal quarters, the top surface need not be divided evenly.

[0084] In the method for manufacturing semiconductor manufacturing jig 1b, regions with different resistivities can be formed by repeating the steps of forming a SiC film using a CVD film forming device and processing the film multiple times.

[0085] [Aspect] (Item 1) The semiconductor manufacturing jig according to the present disclosure comprises: A semiconductor manufacturing jig used in a semiconductor manufacturing device, a first layer having a first resistivity; The second layer is laminated on the first layer and has a second resistivity different from the first resistivity.

[0086] (Item 2) The semiconductor manufacturing jig according to item 1, The second resistivity is greater than the first resistivity.

[0087] (Item 3) The semiconductor manufacturing jig according to item 1 or 2, The semiconductor manufacturing jig has a first main surface and a second main surface opposite to the first main surface, When viewed from above from the first main surface, the first layer is disposed on the inner portion, and the second layer is disposed on the outer portion.

[0088] (Item 4) The semiconductor manufacturing jig according to any one of items 1 to 3, The semiconductor manufacturing jig has a first main surface and a second main surface opposite to the first main surface, A first layer is disposed on the first major surface and a second layer is disposed on the second major surface.

[0089] (Item 5) The semiconductor manufacturing jig according to any one of items 1 to 4, The first and second layers are made of SiC.

[0090] (Item 6) The semiconductor manufacturing jig according to any one of items 1 to 5, The semiconductor manufacturing equipment is a plasma etching equipment.

[0091] (Item 7) The semiconductor manufacturing jig according to any one of items 1 to 6, The semiconductor manufacturing tool is an etcher ring.

[0092] (Item 8) A method for manufacturing a semiconductor manufacturing jig according to the present disclosure includes: A method for manufacturing a semiconductor manufacturing jig used in semiconductor manufacturing equipment, comprising: depositing a first layer having a first resistivity around a substrate; laminating a second layer having a second resistivity different from the first resistivity on the first layer; a step of processing the laminated first layer and second layer into a predetermined shape; and removing the substrate.

[0093] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present disclosure is defined by the claims, not by the description of the above embodiments, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0094] 1, 1a, 1b semiconductor manufacturing jig, 2 wafer, 4 CVD film formation apparatus, 5 substrate, 6 laminate, 11, 11a, 61 first layer, 12, 12a, 62 second layer, 13, 53, 63 space portion, 14 holding portion, 41 chamber, 42 high frequency power supply, 43 vacuum pump, 44 source gas container, 46 film formation table, 47 heater, 48 shower head, 49 control device.

Claims

1. A semiconductor manufacturing jig used in a semiconductor manufacturing device, a first layer made of SiC having a first resistivity; a second layer formed directly on the first layer by the same CVD deposition apparatus as that for the first layer, the second layer being made of SiC and having a second resistivity different from the first resistivity; the semiconductor manufacturing jig has a first main surface and a second main surface opposite to the first main surface, The semiconductor manufacturing jig, when viewed in plan from the first main surface, has the first layer disposed on an inner portion and the second layer disposed on an outer portion.

2. The semiconductor manufacturing tool of claim 1 , wherein the second resistivity is greater than the first resistivity.

3. 3. The semiconductor manufacturing jig according to claim 1, wherein the first layer and the second layer are made of SiC.

4. 3. The semiconductor manufacturing jig according to claim 1, wherein the semiconductor manufacturing equipment is a plasma etching equipment.

5. 3. The semiconductor manufacturing jig according to claim 1, wherein the semiconductor manufacturing jig is an etcher ring.

6. A method for manufacturing a semiconductor manufacturing jig used in semiconductor manufacturing equipment, comprising: forming a first layer made of SiC having a first resistivity around a substrate using a CVD film forming apparatus; depositing a second layer made of SiC having a second resistivity different from the first resistivity directly on the first layer in the same CVD deposition apparatus as that for the first layer; a step of processing the laminated first layer and second layer into a predetermined shape; removing the substrate; the semiconductor manufacturing jig has a first main surface and a second main surface opposite the first main surface, and a step of processing the stacked first layer and second layer so that, when viewed in a plane from the first main surface, the first layer is positioned on an inner portion and the second layer is positioned on an outer portion.

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