Voltage waveform generator for plasma-assisted processing equipment.

Abstract

A voltage waveform generator for a plasma-assisted processing apparatus comprises a common node, a voltage supply circuit operable to switch between at least two voltage levels at a first switch node, a first inductor connected between the first switch node and the common node, and a control unit configured to operate the voltage supply circuit.

Description

[Technical Field]

[0001] The present invention relates to a voltage waveform generator for a plasma-assisted processing apparatus and to a method for generating a voltage waveform for use in plasma-assisted processing, particularly for generating a voltage bias across a sheath of a plasma in contact with a substrate being processed. The voltage bias is advantageously used to control ion energy in plasma-assisted etching, plasma-assisted layer deposition, or reactive ion etching (REI). [Background technology]

[0002] In plasma-assisted etching and plasma-assisted layer deposition, radio frequency (RF) generators are used to generate bias voltages to control ion energy. Accurate control of the bias voltage and the resulting ion energy distribution (IED) is important for improved process control. This bias voltage is typically generated using linear amplifiers with limited efficiency (broadband), switch-mode amplifiers with limited versatility (narrowband), or dedicated pulse-generating amplifiers. Amplifiers typically only indirectly control the output voltage waveform (e.g., by controlling output power or relying on calibration), which results in limited performance (the generated waveform does not approximate the desired output voltage waveform), less than desirable ion energy distribution, and limited repeatability (wafer-to-wafer and system-to-system variations).

[0003] U.S. Patent Application Publication No. 2018 / 0032100 describes a waveform generator for a plasma-assisted processing apparatus in which multiple bridge legs, each with its own floating DC power supply, are cascaded to provide a switched voltage waveform at an output node, the voltage waveform including a voltage gradient obtained by driving semiconductor switches according to a current control method such that the output voltage is proportional to a drive signal applied to the semiconductor switches.

[0004] No. 9,208,992 describes a plasma-assisted processing apparatus that includes a switch-mode power supply for generating a periodic voltage function at an irradiated surface of a substrate to be processed, the periodic voltage function producing a desired ion energy intensity distribution to perform etching of the substrate or plasma-assisted deposition on the substrate.

[0005] The above-mentioned switched-mode power supply can generate a waveform of a specific shape by a DC current to compensate for the ionic current (see FIG. 14 of U.S. Pat. No. 9,208,992). To do so, the switched-mode power supply comprises two switch components coupled in a half-bridge and controlled based on a drive signal generated by a controller as shown in FIG. 3 of U.S. Pat. No. 9,208,992.

[0006] Current trends in plasma-assisted processes are towards higher commutation voltage levels, larger reactor sizes and higher capacities.

[0007] The inherent plasma reactor capacitance and the stray inductance of the interconnection between the reactor and the bias voltage generator form an LC circuit with inherent resonant characteristics. Due to the resonance within the system, a slow switching speed (limited dV / dt on the switch node) or a damping resistor (or snubber) is essential to suppress the excitation of the resonance, which causes undesired ringing of the sheath voltage. This voltage ringing has a negative effect on the desired IED. However, a slow switching speed increases the discharge period, effectively reducing the process / discharge ratio and thereby increasing the time to process the substrate. A too long discharge time can also negatively affect sheath formation or sheath preservation. Furthermore, a damping resistor (or snubber) introduces additional undesirable losses. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] U.S. Patent Application Publication No. 2018 / 0032100 [Patent Document 2] U.S. Patent No. 9,208,992 Summary of the Invention [Problem to be solved by the invention]

[0009] The object of the present invention is to overcome the above-mentioned drawbacks, and in particular those relating to voltage ringing. It is an object of the present invention to provide a voltage waveform generator for use in plasma-assisted processing, and an associated method for generating voltage waveforms that make it possible to achieve at least equal and possibly higher efficiencies. An object is to provide such a generator and a method that makes it possible to increase process throughput while preventing or limiting efficiency losses.

[0010] It is an object of the present invention to provide a plasma-assisted processing apparatus and related methods that allow for improved process control. In particular, an object is to provide an apparatus and method that allows for more accurate arrival at an ideal or desired voltage waveform and / or faster convergence to such an ideal voltage waveform. [Means for solving the problem]

[0011] According to a first aspect of the present disclosure, there is provided a voltage waveform generator as set forth in the accompanying claims. The voltage waveform generator described herein for a plasma-assisted processing apparatus comprises a common node, a voltage supply circuit operable to switch at least two voltage levels at a first switch node, a first (physical) inductor connected between the first switch node and the common node, and a control unit configured to operate the voltage supply circuit. The inductance of the first inductor advantageously increases the stray inductance of the electrical connection to the plasma-assisted processing apparatus, thereby reducing the resonant frequency of the LC circuit formed by the load capacitance and stray inductance and increasing the load impedance. This improves control of the current (and voltage) applied to the load. This also reduces voltage oscillations in the LC circuit during voltage switching to generate a desired voltage waveform at the switch node, allowing for improved control of the desired voltage waveform.

[0012] Advantageously, the voltage waveform generator comprises a voltage clamp circuit connected to the common node and a voltage clamp node. The voltage clamp circuit is operable to clamp the voltage of the common node to the voltage of the voltage clamp node, which may be a voltage node of the voltage supply circuit. Advantageously, the control unit is configured to determine a switching time for switching between at least two voltage levels at the switch node so as to achieve a voltage at the common node equal to the voltage at the voltage clamp node at the moment when the current through the first inductor (and therefore the energy stored in the inductor) is substantially zero. By doing so, voltage oscillations and / or voltage overshoots can be reduced or suppressed before activating the voltage clamp, further improving control of the desired voltage waveform.

[0013] According to a second aspect of the present disclosure there is provided an apparatus for plasma assisted processing as set out in the accompanying claims.

[0014] According to a third aspect of the present disclosure, there is provided a method of generating a voltage waveform as set out in the accompanying claims.

[0015] Advantageously, the voltage waveform generators described herein and the devices described herein are configured to carry out the methods described herein.

[0016] Aspects of the present disclosure are set forth in the following numbered clauses: 1. A voltage waveform generator for a plasma-assisted processing device, comprising: a first switch node and a common node; a voltage supply circuit coupled to the first switch node and operable to switch at least two voltage levels at the first switch node; a first inductor connected between the first switch node and a common node; a control unit configured to operate the voltage supply circuit to obtain a predetermined voltage waveform at the common node. 2. The voltage waveform generator of clause 1, wherein the control unit is configured to operate the voltage supply circuit to obtain a first current pulse of a first sign through the first inductor and then a second current pulse of an opposite sign. 3. A voltage waveform generator as described in clause 1 or 2, wherein the control unit is configured to operate the voltage supply circuit so as to obtain a switching voltage signal at the switch node, thereby causing a current pulse to flow through the first inductor, thereby obtaining a predetermined waveform at the common node. 4. The voltage waveform generator of clause 3, wherein the switching voltage signal includes a sequence of voltage levels, the sequence including a first voltage level having a first magnitude, followed by a second voltage level having a second magnitude less than the first magnitude, followed by a third voltage level having a third magnitude greater than the second magnitude, the third magnitude being equal to or different from the first magnitude. 5. A voltage waveform generator as described in any one of clauses 1 to 4, wherein the predetermined waveform is a voltage pulse. 6. A voltage waveform generator as described in any one of clauses 1 to 5, wherein the voltage supply circuit comprises a neutral point clamped converter operable to switch at least three voltage levels at the first switch node. 7. A voltage waveform generator as described in any one of clauses 1 to 6, comprising a current source coupled to the common node and configured to draw a DC current from the common node. 8. The voltage waveform generator of clause 7, wherein the current sources are continuously connected to the common node and configured to continuously draw DC current. 9. A voltage waveform generator as claimed in any one of clauses 1 to 8, comprising a voltage clamp circuit coupled to the common node and operable to clamp the voltage of the common node to a predetermined level. 10. The voltage waveform generator of clause 9, wherein the voltage clamp circuit is coupled to a voltage node of the voltage supply circuit, the voltage node being configured to provide one of at least two voltage levels as the predetermined level. 11. The voltage waveform generator of clause 9 or 10, wherein the voltage clamp circuit comprises a passive clamp branch comprising one or more diodes. 12. A voltage waveform generator as described in any one of clauses 9 to 11, wherein the voltage clamp circuit comprises an active clamp branch. 13. The voltage waveform generator of clauses 11 and 12, wherein the active clamp branch and the passive clamp branch are connected in parallel. 14. A voltage waveform generator according to any one of clauses 9 to 13, comprising an electrical damping element. 15. A voltage waveform generator as described in any one of clauses 9 to 14, wherein the control unit is configured to determine switching times for applying at least two voltage levels at the switch node so as to achieve a voltage at the common node equal to a predetermined level at the moment when the current through the first inductor is substantially zero. 16. A voltage waveform generator as claimed in any one of clauses 1 to 15, comprising output terminals connected to a plasma reactor, the common node being connected to the output terminals through a DC current blocking capacitor. 17. An apparatus for plasma-assisted processing of a substrate, comprising: means for generating a plasma; a processing platform for supporting the substrate; a voltage waveform generator according to any one of clauses 1 to 16; An apparatus in which the common node is electrically connected to the processing platform. 18. A method of generating a voltage waveform for a substrate undergoing plasma-assisted processing, comprising: 1. A method comprising: applying a switching voltage to a switch node, the switch node connected to a common node through an inductor, the common node electrically coupled to a substrate, the switching voltage causing a first current to flow through the inductor, the first current flowing through the inductor defining ramp-up and ramp-down voltage pulses of a voltage waveform. 19. The step of applying a switching voltage comprises: applying a first voltage level having a first magnitude for a first period to increase a first current; and applying a second voltage level having a second magnitude less than the first magnitude during a second period following the first period, thereby reducing the first current. 20. The method of clause 19, further comprising clamping the voltage at the common node to a third voltage level having a third magnitude while the absolute value of the first current is substantially zero during a third period following the second period. 21. The method of clause 20, wherein the third magnitude is greater than or equal to the first magnitude. 22. The method of clause 20 or 21, wherein the absolute value of the first current is substantially zero and the voltage at the common node is substantially equal to the third voltage level at the end of the second period. 23. The method of any one of clauses 19 to 22, further comprising applying a fourth voltage level having a fourth magnitude during a fourth period following the second period and optionally the third period, thereby increasing the absolute value of the first current. 24. The method of any one of clauses 19 to 23, further comprising applying a fifth voltage level having a fifth magnitude greater than the second magnitude during a fifth period, optionally a third period, optionally a fourth period, following the second period, to reduce the absolute value of the first current. 25. The method of any one of clauses 18 to 24, comprising applying a second current to the common node during at least a third period and the first period of the subsequent cycle. 26. The method of clause 25, wherein the second current is applied throughout the first through third periods. 27. A method according to any one of clauses 18 to 26 implemented in a control unit of a voltage waveform generator according to any one of clauses 1 to 16 or in an apparatus according to clause 17.

[0017] Aspects of the present invention will now be described in more detail with reference to the accompanying drawings, in which like reference numerals refer to like features, and in which: [Brief explanation of the drawings]

[0018] [Figure 1] FIG. 1 illustrates an example of a voltage waveform generator used in a bias generator for an ICP (inductively coupled plasma) reactor according to an embodiment of the present invention. [Figure 2] FIG. 1 illustrates a simplified plasma reactor model and a voltage waveform generator according to the present invention coupled thereto. [Figure 3] FIG. 1 is a block diagram of components of a voltage waveform generator in accordance with the present invention. [Figure 4A] FIG. 1 shows the combined plasma voltage and sheath voltage during the machining and discharge cycle, i.e. the voltage at the irradiated substrate surface. [Figure 4B] FIG. 2 shows the voltage at the substrate stage during the machining and discharge cycle, i.e. the voltage supplied by the bias generator according to the invention. [Figure 4C] FIG. 10 illustrates the voltage generated in the bias voltage generator and biased through a DC blocking capacitor during the machining and discharge cycles. [Figure 5A] FIG. 10 is a diagram showing sheath current and ion current during machining and discharge cycles. [Figure 5B] FIG. 10 shows the substrate stage current during the machining and discharge cycle. [Figure 5C] 10A and 10B show the current supplied by the bias generator according to the present invention during machining and discharge periods. [Figure 6] FIG. 2 is a circuit diagram of a bias voltage generator according to the present invention. [Figure 7] FIG. 7 is a circuit diagram of a neutral-point clamped (NPC) electrical converter used as a DC power supply in the pulse generation circuit of the bias voltage generator of FIG. 6. [Figure 8] FIG. 4D shows details of the voltage waveform of FIG. 4C during a discharge period. [Figure 9] FIG. 10 shows details of the current supplied by the pulse generation circuit during a discharge period. [Figure 10] FIG. 1 illustrates the current path in the bias voltage generator during the ramp-up period of a voltage discharge pulse that increases the current through the inductor coil of the pulse generation circuit. [Figure 11] FIG. 10 illustrates the current path in the bias voltage generator during the freewheel period of the voltage discharge pulse following the ramp-up, reducing the current through the inductor coil of the pulse generation circuit. [Figure 12] FIG. 12 shows alternative current paths in the bias voltage generator during the same freewheeling period as FIG. 11. [Figure 13] FIG. 10 illustrates the current path in the bias voltage generator during the voltage clamp period of the voltage discharge pulse, during which no current flows through the inductor coil of the pulse generation circuit. [Figure 14] FIG. 10 illustrates the current path in the bias voltage generator during the ramp-down period of a voltage discharge pulse that increases the reverse current through the inductor coil of the pulse generation circuit. [Figure 15]FIG. 10 illustrates the current path in the bias voltage generator during a freewheel period following a ramp down that reduces the reverse current flowing through the inductor coil of the pulse generation circuit. [Figure 16] FIG. 1 is a circuit diagram of a power supply for a current source of a bias voltage generator described herein, implemented as a "rainstick" DC / DC converter. [Figure 17] FIG. 10 illustrates the voltage at the switch node of a current source versus the voltage at the common node of a bias voltage generator as described herein, where the current source is switched, resulting in a switched voltage at the switch node and minimizing volt-seconds across the inductor of the current source. [Figure 18] 18 shows the current ripple on the current flowing through the inductor of the current source associated with the voltage waveform of FIG. 17. DETAILED DESCRIPTION OF THE INVENTION

[0019] FIG. 1 illustrates one common use of a bias voltage waveform generator (BVG) 10 in an inductively coupled plasma (ICP) system 100, where the BVG 10 controls the substrate stage voltage and thereby the substrate 101 (typically a wafer) voltage. In a plasma reactor 102, a plasma 103 is generated by introducing a plasma-forming gas 104 into a dielectric tube 108 surrounded by an induction coil 107. This configuration forms a plasma torch that directs the plasma 103 toward a platform 105 (substrate stage) on which the substrate 101 is placed. Optionally, a precursor 109 can be introduced into the plasma reactor 102. As known in the art, a radio frequency (RF) voltage is applied to the induction coil 107 through an RF power supply 120 and matching network 121. The RF power supply 120 and the BVG 10 can be controlled through a system host controller 130. Plasma processes suitable for the present invention are so-called low-pressure or reduced-pressure plasmas, i.e., they operate at pressures much lower than atmospheric pressure, e.g., between 1 mTorr and 10 Torr. To this end, the plasma reactor 102 is advantageously gas-tight, and the desired pressure within the plasma reactor 102 is obtained by a vacuum pump 106 .

[0020] The BVG 10 can also be used in other configurations, such as a capacitively coupled plasma (CCP) reactor, or in a configuration where control signals are directly interconnected between the source generator (RF power supply) and the BVG (without going through a system host controller). Different sources can be used to generate the plasma (e.g., capacitively coupled plasma, electron cyclotron resonance, magnetron, DC voltage, etc.).

[0021] FIG. 2 depicts an electrical model of the plasma reactor 102, showing the loads imposed by the reactor, plasma, sheath, and substrate as seen by the BVG 10. The sheath is a boundary layer with a higher density of positive ions and therefore an overall excess positive charge that forms on the irradiated surface of the substrate due to the plasma. The excess positive charge generally balances out with an opposite negative charge on the irradiated surface of the substrate that the positive charge contacts. Vpl represents the plasma potential in the sheath above the substrate, and I i represents the ion current in the sheath. sh represents the voltage across the sheath, which is the sheath capacitance C sh and the sheath capacitance current i sh represents the limited ion mobility in the sheath during the process cycle, while the diode D p represents the high electron mobility in the sheath during the discharge period. sub represents the voltage across the substrate 101. The lumped capacitance C sub represents the capacitance of the dielectric substrate. par is the lumped inductance representing the stray inductance of the BVG output power interconnect and return. C t is the capacitance of the substrate stage (e.g., due to an electrostatic (dielectric) chuck holder on / in the substrate stage), as well as the associated voltage v t and current i t is a lumped capacitance that represents the capacitance from the substrate stage power interconnect with ground 14 having a capacitance from the substrate table to the dark shield, i.e., the metal shield adjacent to the platform 105 that prevents the plasma from propagating beyond the platform, e.g., to the pump 106.

[0022] The DC (bias) voltage across the sheath ideally results in a narrow IED, and the level of the DC voltage controls the level of the (average) ion energy. Positively charged ions collected on the plasma-irradiated surface cause charge accumulation on the dielectric substrate and / or dielectric substrate stage (e.g., electrostatic chuck holder). Due to charge accumulation, a decreasing (ever-decreasing) voltage must be applied by the BVG to maintain a constant sheath voltage, which is not feasible in practical implementations. To prevent damage to the substrate and / or substrate stage, the charge accumulation, and therefore the potential across the substrate and / or substrate stage, must be limited. This compensation can be achieved by periodic discharge of the substrate and / or substrate stage during the discharge interval between successive (plasma) process cycles.

[0023] Referring to FIG. 4A, the process cycle period T C is the plasma processing period T process Including the plasma processing period T process The discharge period T D precedes (or plasma processing period T process The discharge period T D (The plasma processing period T process During this time, the sheath voltage v sh and / or the process voltage on the illuminated surface of the substrate, V process =v sh +V pl is advantageously controlled (directly or indirectly) and kept constant. process Typical values of range between 0V and -1000V. Successive plasma processing periods T process Discharge period T D During the discharge period T, a positive voltage pulse is applied to the substrate stage to remove any charge that may have accumulated on the illuminated substrate surface. D is advantageously as small as possible, typically around 200-500 ns, and the voltage pulses occurring during this period are advantageously characterized by short rise and fall times and, in some cases, minimal oscillations of the voltage peaks.

[0024] The voltage shapes described above can be obtained by generating a voltage waveform at the substrate stage by the BVG 10, as shown in Figure 4B. Considering the equivalent electrical scheme of Figure 2, T process A voltage gradient must be generated by the BVG during this time.

[0025] Referring to Figures 5A to 5C, the process currents corresponding to the voltage waveforms of Figures 4A to 4B are shown. D The voltage pulse of sh is accompanied by the plasma current I i is the total cycle period T C remains substantially constant during T process Between sh= 0. In the substrate, T D Very high current peaks during sub occurs, while ideally T process Between sub =-I i i sub To generate D During this time, a much higher current pulse i load must occur, while T process The current i that must be generated during load is generally between about 0 A and 4 A, and the method in Figure 2

[0026]

number

[0027] ) one order of magnitude smaller.

[0028] Voltage waveform generator circuit To obtain the desired voltage waveforms described above, in accordance with the present invention, a BVG 10 is provided, as shown schematically in Figure 3. The BVG 10 comprises a pulse generating circuit 11 and a current source 16 coupled to a common node 13. The common node 13 is connected to an optional physical DC blocking capacitor C block 1. The output of the BVG 10 is coupled to the output node 12 of the BVG 10 via the

[0029] The pulse generating circuit 11 generates a discharge period T D The voltage pulse is applied to the common node 13 and connected to a DC blocking capacitor C block to output node 12 via . An optional voltage clamp circuit 15 may be coupled to common node 13 to reduce voltage oscillations and / or overshoot at the upper plateau of the voltage pulse, as further described below. A current source 16 is connected to common node 13 for at least the processing period T process A current i flows through the common node 13 during CS , while the pulse generating circuit 11 is advantageously configured to provide T process Therefore, Tprocess Between load =i CS holds true. i CS It is convenient to note that is generally negative (current source 16 sinks current).

[0030] According to one embodiment, the current source 16 is C It operates continuously for a period of time and connects to the common node 13. CS In this case, the discharge period T D Between load =i CS +i pulse However, as is clear from the graphs 5A to 5C, i CS (between 0.5A and 4A, preferably between 1A and 2A) is T D Between pulse (peak amplitude of at least 30 A, advantageously at least 40 A) and therefore has a negligible effect on the generation of the voltage pulse.

[0031] Referring to Figure 4C, the DC blocking capacitor C block DC bias voltage v Cblock is the voltage at the common node, v CN Allows you to set a bias on

[0032] A circuit diagram of various parts of the BVG 10 is shown in FIG. 6. The pulse generation circuit 11 advantageously comprises or consists of a neutral-point clamped (NPC) bridge circuit with an active switch 112 connected to a (DC) power supply having at least two (DC) voltage nodes A-G, where G denotes electrical ground GND. The power supply is advantageously provided as a "rainstick" converter 110, possibly combined with a (separate) DC / DC converter as shown in FIG. 7, to form at least two voltage nodes A-G (seven voltage nodes in the example of FIG. 7, thus six DC bus voltages A-B, B-C, C-D, D-E, E-F, and F-G). By way of example, each DC bus voltage A-B or F-G, etc., can provide a DC voltage between 100V and 400V, advantageously between 200V and 400V. Advantageously, the DC bus voltages A-B, B-C, etc. can be controlled by adjusting the operation of the active switches of converter 110.

[0033] The voltage nodes A-G are connected to a switch node 111 through an operable switch 112 of the NPC bridge, which is operably coupled to the control unit 17. The switch 112 is advantageously a semiconductor switch, for example implemented as a field effect transistor (FET), and advantageously includes an internal anti-parallel diode (not shown). The switch node 111 is connected to a physical inductor (e.g., coil) L pulse is connected to the common node 13 via the inductor L pulse is advantageously the current i drawn from the pulse generating circuit 11 pulse Precise control of i pulse When controlling the substrate stage, the parasitic inductance of the electrical coupling (L in Figure 2) par In fact, L pulse If there is no current i pulse is mainly the parasitic inductance L par and the parasitic inductance L par is unknown, so i pulseis difficult to estimate accurately. Advantageously, L par L pulse It is relatively small compared to L pulse Providing a voltage across the switch node 111 lowers the LC resonant frequency and increases the load impedance of the equivalent LC circuit seen by the switch node 111. When a voltage is applied to the switch node 111, the current increases more slowly, making it easier to calculate the timing of the voltage pulse applied to the switch node 111 to generate a clean discharge pulse.

[0034] The voltage clamp circuit 15 forms a switchable connection between the common node 13 and a DC voltage node, in particular a voltage node of a DC power supply, such as voltage node A of the power supply 110. For this purpose, the first branch 151 comprises an active switch or a series arrangement of active switches, e.g., active semiconductor switches 153, to form an actively switchable connection between the common node 13 and voltage node A. The switches 153 can be operated via the control unit 17. The voltage clamp circuit comprises a second branch 152 in parallel with the first branch 151, which can comprise a passive switch, such as a diode or a series of diodes 155, such that the moment the active switch 153 is turned on is not critical. The voltage clamp circuit 15 can comprise an electrical damping element, such as a resistor 154, which is advantageously connected in series with the switch 153 to the first branch 151, or alternatively to the second branch 152, or to both branches 151 and 152. Resistor 154 allows for reducing / damping voltage oscillations caused by voltage mismatches when voltage clamp circuit 15 is activated.

[0035] current source circuit According to another aspect, which may be provided in combination with or independently of other aspects described herein, the current source 16 comprises a power supply having at least two voltage levels (nodes) X, Y switchably connected to a switch node 161 through a switch 162, which may be an active semiconductor switch such as a FET, and which may be operatively coupled to the control unit 17. The switch node 161 advantageously has a physical inductor (e.g., coil) L CS 162. The current source 16 is advantageously arranged as a buck converter, the duty ratio of the switch 162 making it possible to regulate the DC voltage at the switch node 161 of the current source. Advantageously, a DC bus midpoint GND between the voltage nodes X and Y is connected to the common node 13 via CS is provided. GND CS The voltage level of the inductor L CS In one example, the (average) DC voltage at switch node 161 when the duty cycle of switch 162 is set to 0.5 (50%). In this case, the potentials of X and Y are advantageously set to GND. CS is symmetric with respect to

[0036] Referring to FIG. 16, the power supply of current source 16 is a multiple DC bus voltage X to GND. Cs , GND Cs Multiple voltage nodes X, Y, Z, and GND to realize ~Y, Y~Z, etc. CS The voltage of the DC bus can advantageously be adjusted by suitable switching of the switches of the DC / DC converter 160 and can be set to a suitable value by a voltage difference between successive nodes advantageously between 100V and 400V. CSserves as the DC bus midpoint in the buck converter of current source 16 and is inserted between node X and node Y. Advantageously, "rainstick" DC / DC converter 160 and the "rainstick" converter of power supply 110 are connected to a shared power supply, in particular converter / power supplies 160 and 110 share a DC bus, for example DC buses E-F shared between the two converters.

[0037] Voltage waveform (pulse) generation Next, the discharge period T D The operation of the pulse generating circuit 11 for generating a voltage pulse during T D A voltage pulse v occurs at the common node 13 during CN The enlarged waveform of is shown by the solid line in Figure 8. pulse The corresponding current i flows through pulse is shown in Figure 9.

[0038] The voltage pulse begins at instant t1 with a ramp-up period T 12 and at instant t1, switch 112 is operated, for example by control unit 17, to connect a high voltage level, for example the voltage level at node A, to switch node 111. This corresponds to the voltage v at switch node 111 in FIG. SN In this case, all switches 112 between switch node 111 and node A are closed, and current flows through the pulse generation circuit, as shown by the gray arrows in Figure 10. The high voltage causes L pulse Current i passing through pulse increases. i pulse The gradient of L pulse The inductance is determined by the inductance of L. Smaller inductance values generally result in faster current and voltage ramp-up, but typically result in higher peak currents, making the switching timing discussed above more critical and increasing sensitivity to signal oscillations if the switch timing is slightly off. pulseThe larger the inductance value of L, the smaller the ramp slope. pulse The optimum inductance value is between 0.5 μH and 10 μH, preferably between 1 μH and 5 μH.

[0039] At instant t2, switch 112 is opened to a non-conducting state and all switches 112 remain in a non-conducting state. This corresponds to a ramp-up period T 12 ends and the freewheeling period T 23 The instant t2 can be selected as the instant when the voltage at the common node 13 reaches approximately the voltage level at the switch node 111 (e.g., the voltage level at node A). pulse The current i pulse must be continuous, a current path is formed from electrical ground at node G through the internal anti-parallel diode of switch 112 located between node G and switch node 111, as shown by the gray arrow in Figure 11. The voltage v at switch node 111 SN falls to the voltage level of node G, while the voltage v at the common node 13 CN is the inductor L pulse continues to rise somewhat due to the current in the inductor L pulse The current at voltage v is still flowing, releasing its energy into the load capacitance and still charging this capacitance while ramping down. CN can eventually reach the level of node A. Therefore, the inductor L pulse The current i pulse is reduced, and finally the freewheeling period T 23 becomes zero at the instant t3, which indicates that

[0040] Alternatively, the freewheel period T 23 It is possible to connect the switch node 111 to the intermediate voltage levels B to F during i pulseThe falling slope of changes, thus affecting the slope of the rising edge of the voltage, and therefore the appropriate voltage level can be selected based on the desired waveform. The current path for the exemplary case where switch node 111 is connected to voltage node F is shown in Figure 12. In this case, switch 112a is actively closed to form a current path through node F.

[0041] At the instant t3, the voltage at the common node 13 advantageously rises to the clamping period T 34 During the time t3, the voltage level at the common node 13 is clamped to the maximum level of the common node 13, for example the level of node A. A voltage clamp circuit 15 is advantageously used for this purpose. The switch 153 may be an active semiconductor switch, for example a FET, and is operated into a conducting state by the control unit 17. The voltage level at the common node 13 is therefore clamped to the voltage of node A. Any voltage mismatch between the common node 13 and the voltage node A when the switch 153 is turned on is advantageously suppressed by the resistor 154. At the time t3, the inductor L pulse The current i pulse is zero and T 34 Since all switches 112 are maintained in a non-conducting state for the entire clamp period T 34 Between pulse remains zero. The clamp period T 34 The length of the voltage pulse is advantageously determined by the desired length T D are selected based on

[0042] The diode 155 in the clamp branch 152 is connected to the voltage v CN rises too fast, for example, too quickly, specifically, the inductor L pulse If the voltage v reaches the level of node A before the current through CN It is convenient to note that this allows clamping of the signal level . This may be done when mismatches in switch timing occur.

[0043] Clamp period T 34Possible current paths through BVG in are represented by gray arrows in Figure 13. When the voltage level at common node 13 eventually reaches the level of node A on the other side of voltage clamp circuit 15, diode 155 may begin to conduct. At this point, switch 153 can be switched to a non-conducting state.

[0044] Alternatively, T 34 This means that the switch 153 can be maintained in a conducting state for the duration of the discharge period T D This is particularly appropriate when switch 153 also operates during the clamp interval. Switch 153 then prevents the current drawn by current source 16 from discharging the load capacitance during the clamp interval and causing the voltage at common node 13 to drop below A. Thus, switch 153 directs the current drawn by current source 16, enabling the voltage at common node 13 to remain clamped to the voltage at voltage node A.

[0045] Alternatively, the clamp period T 34 In such a case, the voltage clamp circuit 15 does not need to be provided.

[0046] Advantageously, a clamping diode (not shown) is provided between the common node 13 and the voltage node G, making it possible to limit the magnitude of voltage spikes, as can be seen in Figure 4C. Such voltage spikes are induced when the switch 153 of the clamping circuit 15 is turned off (opened), interrupting the current of the current source 16. The diode between 13 and G clamps this voltage spike.

[0047] At instant t4, the voltage pulse begins to ramp down. This corresponds to the clamp period T 34 ends, and the ramp-down period T 45 To achieve the ramp down, the inductor L pulse The current i pulseis made negative. For this purpose, the switch node 111 is connected to a voltage node of the DC power supply 110 having a potential lower than the (instantaneous) potential of the common node 13. In the present exemplary embodiment, since the common node is fixed at voltage level A due to the voltage clamp circuit 15, it is sufficient to select one of the levels B to G. The selected level will of course affect the slope of the ramp down, and therefore a suitable level can be selected based on the desired waveform.

[0048] As an example, the current path through BVG 10 during the ramp-down period is shown in FIG. 14 when switch node 111 is connected to voltage node C by operating switches 112b and 112c to a conducting state. 45 The voltage between CN and v SN is shown in Figure 8, and the inductor L pulse The current i pulse is shown in Figure 9.

[0049] Ramp-down period T 45 After the freewheel period T 56 continues, the discharge period (and therefore the operation of the pulse generating circuit 11) ends, and a new machining period T process Before the start of L pulse The current i pulse is returned to zero. For this purpose, at t5, switches 112b and 112c are switched back to the non-conducting state, and all switches 112 remain in the non-conducting state (or any other suitable voltage level can be selected). pulse must remain continuous, so the inductor L pulseconducts current between switch node 111 and voltage node A. Switch 112 may include an internal antiparallel diode, in which case the internal antiparallel diode conducts this current. Alternatively, an external diode may be provided antiparallel to switch 112. Still alternatively, other solutions that mimic the behavior of such antiparallel diodes may be used, for example, switch 112 may be a GaN normally-off junction-gate field-effect transistor (JFET) switch, which allows third-quadrant operation, i.e., behavior similar to a diode in the reverse conduction state. T 56 The resulting current path during this time is represented by the grey arrow in Figure 15. The internal diode of switch 112 allows the current i pulse becomes zero (see Figure 9), the machine automatically becomes non-conductive. This means that the discharge cycle ends and a new machining cycle T process Indicates that has started.

[0050] The instants t1 to t6 and the voltage levels A to G applied to the switch node 111 are advantageously pulse In other words, referring to FIG. 8, the curve v CN and curve v SN The resulting area between D This will cause the inductor L pulse Current i at pulse It is possible to maintain a steady state / operation in which the average value of i does not fluctuate. CS T D When continuously flowed over a D (and T C ) across i pulse The mean value of i CS is related to, and therefore I i It is convenient to note that the period T 12 ~T 56 Additional voltage switching states (v SN period) and add v CNIt is convenient to note that the desired voltage waveform for

[0051] Process period T process During this time, the pulse generating circuit 11 remains inoperative and the inductor L pulse current i pulse Therefore, L pulse The voltage across T is zero and the voltage level at switch node 111 is process The voltage level of the common node 13 in the

[0052] current generation Next, the operation of the current source 16 will be described. i Load capacitance C due to sub To compensate for the charging of C sub (and therefore C t For this purpose, as shown in FIGS. 4B-4C, a current is taken from the process period T process A voltage gradient must be obtained at the common node 13 (and therefore at the output node 12) during the period. A current source 16 supplies an appropriate DC current i CS The current source 16 is advantageously connected continuously to the common node 13 to provide a full repetition period T C Between T process and T D During both CS continuously because this eliminates distortions that occur when enabling / disabling or connecting / disconnecting the current source 16 and eliminates system complexity in terms of steps that need to be taken to implement connecting / disconnecting devices / circuits.

[0053] 17-18, one advantage of allowing switch node 161 of current source 16 to switch between different voltage levels (at nodes X-Y) is that the C or one process period T process across i CSThis is because the current ripple at the switch node 161 can be minimized. CS As can be seen in Figure 17, when the inductor L CS 17, the shaded area indicates the voltage v at the common node 13. CN and v CS This shows that the difference between the voltages of i and i completely compensates each other over one period. CS This also means that the average value of i does not fluctuate and a steady state can be achieved. CS Measure the average value of i CS This can be achieved by adapting the duty cycle of switch 162 (which can be done by a current control loop implemented in control unit 17) so that the average value of v is equal to a predetermined value. Alternatively, or additionally, the potentials of nodes X and Y can be adjusted appropriately. Figure 17 shows the relationship between the voltage v at switch node 161 and the voltage v at node X. CS is switched between node X and node Y at instant t7.

[0054] The current ripple is v CS and v CN v so that all individual volt-second areas between the curves of CS v CN Alternatively or additionally, i CS The voltage levels of X and Y can be adapted to minimize the current ripple in v. This advantageously reduces the current ripple while maintaining steady state, i.e., the zero net volt-second region, or in other words, v CS The average of v CN It is executed for a time equal to the average of i CS Reducing the current ripple above advantageously reduces the ripple in the sheath voltage.

[0055] In another aspect, the control unit 17 is configured to synchronize the switching of the switch 162 of the current source 16 and the switch 112 of the pulse generation circuit 11, advantageously in both frequency and phase. This can be achieved by implementing the same clock for operating the switches 162 and 112 in the control unit 17. This allows synchronizing the voltage switch of the switch node 161 of the current source and the voltage switch of the switch node 111 of the pulse generation circuit. Thus, over a given period, the inductor L CS The volt-seconds of the rectifier can be very easily reduced to zero, eliminating any possible mismatch due to asynchronous clocks. By doing so, the smaller inductor coil L CS can be used, resulting in a more compact circuit. CS Advantageously, the current ripple occurring on the L CS The inductance of the switch 162 is between 500 μH and 1 mH. Advantageously, the switching frequency of the switch 162 is between 1 kHz and 10 MHz, in particular between 10 kHz and 1 MHz.

[0056] The current source 16 includes three or more switchable voltage levels, i CS In this way, the voltage at the switch node 161 of the current source can be reduced by a factor of 1 / 2. CN However, this can increase the footprint of the current source circuit, and a two-voltage level circuit (buck converter) can be considered the best compromise between performance and footprint.

[0057] The pulse generation circuit 11 and possibly the voltage clamp circuit 15 and / or the current source 16 may be operated through an open loop by the control unit 17. Alternatively, it may be advantageous to implement a closed loop control in the control unit 17 for operating any one of the pulse generation circuit 11, the voltage clamp circuit 15, and the current source 16. To this end, the BVG 10 may be equipped with a measurement device configured to measure one or a combination of the following: a voltage waveform (voltage envelope), which may be measured at the common node 13 and / or the output node 12; the voltage level of the common node 13 and / or the output node 12 at the beginning of the discharge period (instant t1); the voltage level of the common node 13 and / or the output node 12 at the end of the discharge period (instant t6), - Inductor L pulse The current i pulse , - (inductor L Cs current i generated by current source 16 CS , - the current through the clamping circuit 15, - one or more voltage levels of the DC bus of the power source 11 and / or 160, and - the process voltage in the plasma chamber 102 (e.g., v t ). Any one of the above measurements may be used in a feedback control loop implemented in control unit 17 to control the operation of the pulse generation circuitry and / or voltage clamp circuitry during the discharge period. Additionally or alternatively, these measurements may also be used to control the operation of current source 16 during either or both of the process and discharge periods. [Explanation of symbols]

[0058] 10 Bias voltage waveform generator 11 Pulse generating circuit 12 Output Nodes 13 Common Node 14 Earth 15 Voltage clamp circuit 16 Current source 17 Control Unit 100 Inductively Coupled Plasma (ICP) Equipment 101 Substrate 102 Plasma Reactor 103 Plasma 104 Plasma-forming gases 105 Platform 106 Vacuum Pump 107 Induction Coil 108 Dielectric Tube 109 Precursors 110 Power supply 111 Switch Node 112 Switch 120 RF power supply 121 Matching Network 130 System Host Controller 151 First Branch 152 Second Branch 153 Active Switch 154 Resistor 155 Diode 160 DC / DC Converter 161 Switch Nodes 162 Switch A voltage node C block DC Blocking Capacitor C sub load capacity G voltage node i CS DC current i pulse current i sh Current Pulse i sub Current Peak L CS inductor L pulse inductor L par Parasitic inductance TC Process Repetition Period T D discharge period T process Plasma Processing Cycle v sh Sheath Voltage v CN voltage pulse v SN Voltage

Claims

1. A voltage waveform generator (10) for a plasma-assisted processing device (100), comprising: a first switch node (111) and a common node (13); a voltage supply circuit (11) connected to the first switch node (111) and operable to switch at least two voltage levels at the first switch node (111); A first inductor (L) connected between the first switch node (111) and the common node (13) ｐｕｌｓｅ )and, A predetermined voltage waveform (v ＣＮ a control unit (17) configured to operate the voltage supply circuit to obtain 1. A voltage waveform generator comprising: a voltage clamp circuit (15) coupled to the common node (13); and a voltage clamp node, the voltage clamp circuit configured to provide a switchable connection between the common node (13) and the voltage clamp node operable to clamp the voltage of the common node to the voltage of the voltage clamp node.

2. The control unit (17) controls the first inductor (L ｐｕｌｓｅ 2. The voltage waveform generator of claim 1, configured to operate the voltage supply circuit (11) to obtain a first current pulse of a first sign through a first input terminal (11) and then a second current pulse of an opposite sign.

3. The control unit (17) generates a switching voltage signal (v ＳＮ ), thereby obtaining the first inductor (L ｐｕｌｓｅ ) into a current pulse (i ｐｕｌｓｅ ) flows, thereby generating the predetermined waveform (v ＣＮ 2. The voltage waveform generator of claim 1, configured to operate the voltage supply circuit (11) so as to obtain a

4. The switching voltage signal (v ＳＮ 4. The voltage waveform generator of claim 3, wherein the first voltage level includes a first magnitude, followed by a second voltage level having a second magnitude that is less than the first magnitude, followed by a third voltage level having a third magnitude that is greater than the second magnitude, and wherein the third magnitude is equal to or different from the first magnitude.

5. 5. The voltage waveform generator of claim 1, wherein the predetermined waveform is a voltage pulse.

6. 6. The voltage waveform generator of claim 5, further comprising a measuring device configured to measure a current through the clamp circuit, wherein the control unit is implemented with a feedback control loop configured to control operation of the voltage supply circuit to generate the voltage pulses, and the control unit is configured to use the current measured by the measuring device in the feedback control loop.

7. 5. The voltage waveform generator of claim 1, wherein the voltage supply circuit (11) comprises a neutral-point clamped converter operable to switch at least three voltage levels at the first switch node (111).

8. A DC current (i ＣＳ 5. The voltage waveform generator of claim 1, further comprising a current source (16) configured to draw a

9. 5. The voltage waveform generator of claim 1, wherein the voltage clamp node is a voltage node (A) of the voltage supply circuit (11), the voltage node being configured to provide one of the at least two voltage levels.

10. 5. The voltage waveform generator of claim 1, wherein the voltage at the voltage clamp node is at a predetermined level.

11. 5. The voltage waveform generator of claim 1, wherein the voltage clamp circuit comprises one or more of a passive clamp branch (152) comprising one or more diodes (155), an active clamp branch (151), and an electrical damping element (154).

12. 12. The voltage waveform generator of claim 11, comprising the active clamp branch (151) and the passive clamp branch (152), wherein the active clamp branch (151) and the passive clamp branch (152) are connected in parallel.

13. The control unit (17) controls the first inductor (L ｐｕｌｓｅ ) current (i ｐｕｌｓｅ ) is essentially zero (t ３ 11. The voltage waveform generator of claim 10, configured to determine switching times for applying at least two voltage levels at the switch node (111) to achieve a voltage at the common node (13) equal to the predetermined level.

14. 5. The voltage waveform generator of claim 1, wherein the common node (13) is connected to a voltage node (G) of the voltage supply circuit (11) via a diode, the voltage node being configured to provide one of the at least two voltage levels, the one of the at least two voltage levels being electrical ground.

15. An apparatus (100) for plasma-assisted processing of a substrate (101), comprising: means (102, 107) for generating a plasma (103); a processing platform (105) for supporting said substrate (101); 5. An apparatus comprising the voltage waveform generator (10) of any one of claims 1 to 4, wherein the common node (13) is electrically connected to the processing platform (105).

16. The voltage waveform (v ＣＮ ) a method for generating A switching voltage (v ＳＮ ), wherein the switch node is connected to an inductor (L ｐｕｌｓｅ ) to a common node (13), the common node (13) being electrically coupled to the substrate, and the switching voltage causing a first current (i ｐｕｌｓｅ ) flows through the inductor, and the first current (i ｐｕｌｓｅ ) is the voltage waveform (v ＣＮ and determining a ramp-up and ramp-down of the voltage pulse of The switching voltage (v ＳＮ ) is The first period (T １２ ) a first voltage level having a first magnitude for a period of time, and the first current (i ｐｕｌｓｅ ) and The second period (T ２３ ) a second voltage level having a second magnitude less than the first magnitude, and applying the first current (i ｐｕｌｓｅ ) and The second period (T ２３ ) followed by the third period (T ３４ ) in the first current (i ｐｕｌｓｅ ) is substantially zero, the voltage (v ＣＮ and clamping the first input voltage to a third voltage level having a third magnitude.

17. The second period (T ２３ ) and optionally the third period (T ３４ ) followed by the fourth period (T ４５ a fourth voltage level having a fourth magnitude is applied for a period of time during which the first current (i ｐｕｌｓｅ 17. The method of claim 16, further comprising the step of increasing the absolute value of

18. The second period, and possibly the third period (T ３４ ), and optionally the fourth period (T ４５ ) followed by the fifth period (T ５６ ), applying a fifth voltage level having a fifth magnitude greater than the second magnitude, and applying the first current (i ｐｕｌｓｅ 18. The method of claim 16 or 17, further comprising the step of reducing the absolute value of

19. At least during successive cycles of applying the switching voltage, a DC current (i ＣＳ 18. The method of claim 16 or 17, comprising the step of applying a voltage to said common node (13).

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