Data generation device and program

Abstract

A data generation device (1) generates table data for determining a destination for data that is to be transferred between a plurality of computation circuits (41) which sequentially execute a plurality of processes on process data. The data generation device comprises: a first acquisition unit (1F) that acquires a first correspondence table consisting of data IDs identifying the process data, and flow IDs identifying a flow specifying the order of processing and the computation circuit to be used for processing the process data; a second acquisition unit (1G) that acquires a second correspondence table consisting of the flow IDs and flow information in which the content of the flow identified by the flow ID is specified by the order of the destinations; and a generation unit (1H) that uses the flow ID to associate the data ID in the acquired first correspondence table with the flow information in the acquired second correspondence table, and generates table data in which the data IDs are associated with the flow information.

Description

[Technical Field]

[0001] The present invention relates to a data generating device and a program. [Background technology]

[0002] Devices such as smartphones, PCs, and servers are composed of electronic computers. For example, these computers consist of a general-purpose processor that reads programs and executes calculations, and communication lines such as buses that connect the storage device and the general-purpose processor. There is a continuous demand for improved performance from these computers, including higher speed, higher throughput, smaller size, lower power consumption, more flexible processing, and improved user convenience. To meet these demands, computing units with various features have emerged. Examples include GPUs, which offer high-speed video and AI processing; ASICs, which can process specific functions at ultra-high speeds but whose processing content cannot be changed; and FPGAs, which are fast but whose processing content can be changed after manufacturing.

[0003] In recent years, configurations have emerged that aim to improve the overall performance of a computer by using computing units with various characteristics as accelerators (Non-Patent Document 1). Such configurations consist of a control unit such as a general-purpose processor, a memory unit, multiple computing units such as FPGAs, and communication lines such as buses that connect them. In such configurations, a specific process may be executed by a computing unit that is good at that process. In this way, the overall performance of the computer is improved by allocating that process to a computing unit that is good at that process. [Prior art documents] [Non-patent literature]

[0004] [Non-Patent Document 1] R. Takano and T. Kudoh, "Flow-centric computing leveraged by photonic circuit switching for the post-moore era," 2016 Tenth IEEE / ACM International Symposium on Networks-on-Chip (NOCS), 2016, pp. 1-3, doi: 10.1109 / NOCS.2016.7579339. Summary of the Invention [Problem to be solved by the invention]

[0005] In the above configuration, it is necessary to prepare table data for determining the destination of data to be transferred between a plurality of arithmetic circuits, but this point is not disclosed in the above Non-Patent Document 1.

[0006] An object of the present invention is to preferably generate table data for determining the destination of data to be transferred between a plurality of arithmetic circuits. [Means for solving the problem]

[0007] To solve the above problems, a data generation device of the present invention generates table data for determining destinations of data transferred between multiple arithmetic circuits that sequentially execute multiple processes on processing data, and includes: a first acquisition unit that acquires a first correspondence table between a data ID that identifies the processing data and a flow ID that identifies a flow that specifies which arithmetic circuit processes the processing data and in what order; a second acquisition unit that acquires a second correspondence table between the flow ID and flow information that specifies the content of the flow identified by the flow ID based on the destination order; and a generation unit that associates the data IDs in the acquired first correspondence table with the flow information in the acquired second correspondence table via the flow IDs, and generates the table data in which the data IDs and the flow information are associated. Furthermore, a program according to the present invention causes a computer to function as each of the above units. The program may be stored in a non-transitory computer-readable storage medium. [Effects of the Invention]

[0008] According to the present invention, table data for determining the destination of data transferred between a plurality of arithmetic circuits can be suitably generated. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a block diagram showing the configuration of a computer according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a flowchart of the operation of the electronic computer of FIG. [Figure 3] FIG. 3 is a diagram illustrating an example of the configuration of a transmission circuit. [Figure 4] FIG. 4 is a block diagram showing the configuration of a computer according to a modified example of the first embodiment. [Figure 5] FIG. 5 is a flowchart of the operation of the electronic computer according to the second embodiment. [Figure 6] FIG. 6 is a diagram illustrating an example of the configuration of an arithmetic circuit according to the second embodiment. [Figure 7]FIG. 7 is a diagram illustrating an example of the configuration of another arithmetic circuit according to the second embodiment. [Figure 8] FIG. 8 is a flowchart of the operation of the electronic computer according to the third embodiment. [Figure 9] FIG. 9 is a diagram illustrating an example of the configuration of an arithmetic circuit according to the third embodiment. [Figure 10] FIG. 10 is a diagram illustrating the data structure of ID-added data according to the fourth embodiment. [Figure 11] FIG. 11 illustrates an example of the configuration of an ID conversion table according to the fifth embodiment. [Figure 12] FIG. 12 illustrates an example of the configuration of an ID conversion table according to the fifth embodiment. [Figure 13] FIG. 13 is a flowchart of the operation of the electronic computer according to the fifth embodiment. [Figure 14] FIG. 14 is a diagram illustrating an example of the configuration of an arithmetic circuit according to the fifth embodiment. [Figure 15] FIG. 15 is a diagram illustrating a configuration example of an arithmetic circuit according to the sixth embodiment. [Figure 16] FIG. 16 is a block diagram showing the configuration of a computer according to the seventh embodiment. [Figure 17] FIG. 17 is a block diagram showing the configuration of a computer according to the eighth embodiment. [Figure 18] FIG. 18 is a diagram illustrating the data structure of ID-added data according to the eighth embodiment. [Figure 19] FIG. 19 illustrates an example of the configuration of a process setting table according to the eighth embodiment. [Figure 20] FIG. 20 is a flowchart of the processing performed by the arithmetic circuit according to the eighth embodiment. [Figure 21] Fig. 21 is a configuration diagram of a data generating device according to the eighth embodiment. [Figure 22] Fig. 22 is a configuration diagram of a data generating device according to the eighth embodiment. [Figure 23] FIG. 23 is a diagram showing how a process setting table is generated in the eighth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings, but the present invention is not limited to the following embodiments.

[0011] [First embodiment] The first embodiment of the present invention enables direct data transmission and reception between a plurality of processing elements, thereby reducing the number of times a control unit transfers data and improving the throughput of the entire computer.

[0012] (Configuration of the electronic computer 10) As shown in FIG. 1, the electronic computer 10 according to the first embodiment includes a control unit 20, a memory unit 30 including a main memory 31 (main memory) and an auxiliary memory unit 32 of the control unit 20, a plurality of calculation units 40, and a communication line 50 such as a bus to which these are connected.

[0013] The control unit 20 reads out a program stored in an auxiliary storage device 32 such as a hard disk or a solid state drive (SSD) into a main storage device 31 such as a random access memory (RAM) and executes the program. The control unit 20 is, for example, made up of a processor that performs predetermined processing by executing the program, for example, a general-purpose processor such as a central processing unit (CPU). As will be described later, the control unit 20 executes a program that causes at least some of the multiple calculation units 40 to perform processing.

[0014] Each calculation unit 40 is made up of a one-chip integrated circuit such as an FPGA (Field-Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), etc. Each calculation unit 40 includes a calculation circuit 41 and a transmission circuit 42.

[0015] The arithmetic circuits 41 are configured to execute predetermined processes. The type of process executed by each arithmetic circuit 41 is different. An arithmetic circuit ID "#1" to "#N" is set for each arithmetic circuit 41 to uniquely identify it. Hereinafter, when distinguishing between the arithmetic circuits 41 by arithmetic circuit ID, the arithmetic circuits 41 may be referred to as arithmetic circuits 41-1 to 41-N, respectively. For example, an arithmetic circuit 41 assigned "#1" may also be referred to as arithmetic circuit 41-1. An arithmetic circuit 41 assigned "#2" may also be referred to as arithmetic circuit 41-2. An arithmetic circuit 41 assigned "#N" may also be referred to as arithmetic circuit 41-N. The arithmetic units 40 having the arithmetic circuits 41-1 to 41-N, respectively, may also be referred to as arithmetic units 40-1 to 40-N, respectively.

[0016] The transmission circuit 42 transmits data transmitted from the control unit 20, the main memory device 31, or another calculation unit 40 via the communication line 50 to the calculation circuit 41. The transmission circuit 42 also transmits data output by the calculation circuit 41 of the same calculation unit 40 to the control unit 20, the main memory device 31, or another calculation unit 40 via the communication line 50. The transmission circuits 42 of the calculation units 40-1 to 40-N are also referred to as transmission circuits 42-1 to 42-N, respectively.

[0017] (Example of operation of the electronic calculator 10) An example of the operation of the electronic calculator 10 will be described with reference to FIGS. 1 and 2. Here, as an example, it is assumed that the electronic calculator 10 executes a process A and a process B using the calculation result of the process A. The process A is executed by an arithmetic circuit 41-1. The process B is executed by an arithmetic circuit 41-2. Examples of the processes A and B include image processing. An example of the process A is a binarization process for an image, and an example of the process B is an edge detection process for a binarized image. It is also assumed that the main memory device 31 of the storage unit 30 stores processing data to be processed in the processes A and B, which is supplied from the outside via, for example, a network.

[0018] 2 begins when the control unit 20 reads into the main memory 31 a program that specifies the execution of processes A and B, which is stored in the auxiliary memory 32, and starts executing the program. Thereafter, the control unit 20 performs the following operations by executing the program.

[0019] In the operation of Figure 2, first, the control unit 20 treats the processing data stored in the memory unit 30 as the data body, and assigns the calculation circuit ID of each calculation circuit 41 that executes processing A and processing B, respectively, to this data body (step S11 in Figures 1 and 2).

[0020] The arithmetic circuit ID may be written in the program or may be stored in the auxiliary storage device 32 in association with the program. The control unit 20 assigns the arithmetic circuit IDs "#1" and "#2" of the arithmetic units 40-1 that execute processes A and B, respectively, to the processing data as the data body in the order of processing, starting from the beginning. Hereinafter, the entire data consisting of the data body and the arithmetic circuit ID assigned to the data body will also be referred to as ID-attached data. The arithmetic circuit ID functions as the destination of the data body, that is, an address. Note that the arithmetic circuit ID also identifies the arithmetic unit 40 that includes the arithmetic circuit 41 and the transmission circuit 42 connected to the arithmetic circuit 41.

[0021] The control unit 20 transfers the ID-attached data to the arithmetic circuit 41-1, whose leading "#1" is the arithmetic circuit ID (step S12). The ID-attached data is transmitted via the communication line 50 and the transmission circuit 42-1 (see also the dashed-dotted arrow A1 in FIG. 1). As will be explained below, the transfer of the ID-attached data triggers the execution of process A by the arithmetic circuit 41-1 and process B by the arithmetic circuit 41-2. In this way, the control unit 20, which operates by executing a program, controls the arithmetic circuits 41-1 and 41-2 to sequentially execute process A and process B.

[0022] The transmission circuit 42-1 that transmits the ID-attached data deletes the leading arithmetic circuit ID "#1" from the ID-attached data (step S13). The arithmetic circuit 41-1 executes processing A on the data body of the ID-attached data from which "#1" has been deleted (step S14). The format of the arithmetic circuit ID, etc., is predetermined, and each arithmetic circuit 41, including the arithmetic circuit 41-1, is configured to be able to recognize the presence or absence of an arithmetic circuit ID and the beginning and end of the data body. The arithmetic circuit 41-1 generates new ID-attached data with the arithmetic result obtained by processing A (also referred to as processed data after processing A, processing result of processing A, etc.) as the new data body. This ID-attached data is data with "#2" added to the data body.

[0023] The arithmetic circuit 41-1 transfers the generated ID-attached data to the arithmetic circuit 41-2, which uses "#2" as the arithmetic circuit ID, with the "#2" at the beginning of the data as the destination (step S15). The ID-attached data is transmitted via the transmission circuit 42-1, the communication line 50, and the transmission circuit 42-2 (see also the dashed-dotted arrow A2 in FIG. 1). In this transfer process, the transmission circuit 42-1, which has received the ID-attached data from the arithmetic circuit 41-1, may notify the control unit 20 of the receipt of the data. In this case, the timing of the transfer of the ID-attached data may be controlled by the control unit 20, which has received the notification. For example, the control unit 20 instructs the transmission circuit 42-1 to transfer the ID-attached data at a predetermined timing.

[0024] The transmission circuit 42-2 that transmits the ID-assigned data deletes the leading arithmetic circuit ID "#2" from the ID-assigned data (step S16). As a result, no arithmetic circuit ID is assigned to the data body. The arithmetic circuit 41-2 executes processing B on the data body (step S17). The calculation result of this processing B is the processed data after the current series of processes, i.e., the final processing result, and is transmitted from the arithmetic circuit 41-2 to the transmission circuit 42-2 as a new data body. Here, the transmission circuit 42 of each arithmetic unit 40 is configured to transmit the data body from the arithmetic circuit 41 as the final processing result to the main memory device 31 of the storage unit 30 when the data body from the arithmetic circuit 41 does not have an arithmetic circuit ID assigned to it. Therefore, the transmission circuit 42-2 transmits the data body from the arithmetic circuit 41-2 (i.e., the final processing result) to the main memory device 31 via the communication line 50 (step S18; also see the dashed-dotted arrow A3 in FIG. 1). Note that when the transmission circuit 42-2 receives the data body, it may notify the control unit 20 of this fact. When the control unit 20 receives the notification from the transmission circuit 42-2, the control unit 20 can recognize that process B has ended, in other words, that a series of processes to be executed by the arithmetic circuit 41 specified by the program have ended. The control unit 20 may perform interrupt processing when it receives the notification, thereby controlling the transfer of the processing result data received by the transmission circuit 42-2 to the main memory device 31.

[0025] (Detailed configuration and operation of transmission circuit 42) 3, the transmission circuit 42 includes an ID storage block 42A, a transmission / reception block 42B, an ID determination block 42C, and an ID deletion block 42D. The transmission circuit 42 receives as input not only the ID-attached data and the data body that is the final processing result, but also various other data output to the communication line 50.

[0026] The ID storage block 42A stores the arithmetic circuit ID of the arithmetic circuit 41 in the same arithmetic unit 40. For example, the ID storage block 42A of the arithmetic unit 40-1 stores the arithmetic circuit ID "#1" of the arithmetic circuit 41-1.

[0027] The transmission / reception block 42B sends various data input to the transmission circuit 42 to the ID determination block 42C in accordance with the implemented protocol.

[0028] The ID determination block 42C extracts the arithmetic circuit ID at the beginning of the data from the transmission / reception block 42B. The ID determination block 42C determines whether the extracted arithmetic circuit ID matches the arithmetic circuit ID stored in the ID storage block 42A. If the arithmetic circuit ID cannot be extracted or the comparison results in a mismatch, the data sent to that arithmetic unit 40 is not intended for processing by the arithmetic circuit 41 of that arithmetic unit 40. In this case, the ID determination block 42C discards the input data without supplying it to the ID deletion block 42D at the next stage. On the other hand, if the two IDs match, the data sent to that arithmetic unit 40 is ID-attached data and is intended for processing by the arithmetic circuit 41 of that arithmetic unit 40. In this case, the ID determination block 42C sends the ID-attached data to the ID deletion block 42D at the next stage. If the arithmetic circuit ID at the beginning of the ID-attached data is "#1," the ID-attached data is sent to the arithmetic circuit 41-1 only by the transmission circuit 42-1 of the arithmetic unit 40-1, as described below. In this way, the ID-attached data is sent to the arithmetic circuit 41 identified by the arithmetic circuit ID at the beginning of the data.

[0029] The ID deletion block 42D deletes, from the ID determination block 42C, the arithmetic circuit ID that is integrated with the arithmetic circuit ID stored in the ID storage block 42A, and sends the data with the deleted ID to the arithmetic circuit 41.

[0030] When the transmission / reception block 42B receives ID-attached data or the final processing result, which is the data body without an arithmetic circuit ID, from the arithmetic circuit 41, it outputs the received data to the communication line 50. The ID-attached data is transmitted by each transmission circuit 42 to the arithmetic circuit 41 with the leading arithmetic circuit ID. The final processing result is transmitted to the main memory device 31 of the storage unit 30. The transmission / reception block 42B transmits, for example, the processing result data to which the address of the main memory device 31 has been assigned.

[0031] In this embodiment, an example is shown in which only processes A and B are executed by a program, i.e., an example is shown in which arithmetic circuits 41-1 and 41-2 are connected and sequentially execute the processing flows of processes A and B. However, the number of processes is not limited to two and may be any number. The arithmetic circuits used may also be determined depending on the number and type of processes. For example, arithmetic circuit 41-1, arithmetic circuit 41-2, and arithmetic circuit 41-3 that executes process N may be connected, and processes A, B, and N may be sequentially executed by these circuits. Multiple arithmetic circuits of the same or different types may be "connected," and the multiple connected arithmetic circuits 41 may sequentially execute multiple processes specified by a program. By "connecting" multiple arithmetic circuits of the same or different types and sequentially executing multiple processes specified by a program, it is possible to execute various processes specified by a program with almost no load on the control unit 20.

[0032] (Effects and Modifications) In this embodiment, a unique arithmetic circuit ID is assigned to each arithmetic circuit 41, and when multiple processes of a program are performed sequentially by the multiple arithmetic circuits 41, processing data (data body) is transmitted and received between the arithmetic circuits 41 based on the arithmetic circuit ID. Therefore, data (data body) after processing by a certain arithmetic circuit 41 is not written to the storage unit 30, particularly the main memory device 31, and is not transferred from the main memory device 31 to the arithmetic circuit 41-2. In addition, no bottleneck occurs in data transfer by the control unit 20. This improves the throughput of the electronic computer 10. Furthermore, effects such as lower power consumption, reduced latency, lighter programs, improved computer stability, and improved usability can be obtained.

[0033] In this embodiment, the control unit 20 assigns an arithmetic circuit ID to the processing data (data body), but a dedicated module for this assignment may be provided. The arithmetic circuit ID may be defined and assigned in the program as described above, or may be created and assigned by a compiler.

[0034] Any communication protocol may be used by the control unit 20, the storage unit 30, the calculation unit 40 (particularly the transmission circuit 42), and the communication line 50, and TCP / IP using IPv4 and / or IPv6 addresses as calculation circuit IDs, or a network layer service chaining protocol may be used. The control unit 20, the storage unit 30, the calculation unit 40 (particularly the transmission circuit 42), and the communication line 50 may be connected by the Ethernet standard, CXL (Compute Express Link), Gen-Z, or the like. The transmission circuit 42 may be provided separately outside the calculation unit 40, such as an FPGA. In this case, the transmission circuit 42 may utilize a processor bus or a PCIe bridge function, or the like. The transmission circuit 42 may be a router, or the like.

[0035] The arithmetic circuit 41 may be configured with a processor such as a CPU. In this case, a storage unit (not shown) may be provided inside or outside the transmission circuit 42, and a subprogram for causing the arithmetic circuit 41 to operate as each of the above-mentioned blocks may be stored in this storage unit. The arithmetic circuit 41 and the storage unit may be connected to a communication line 50, and the subprogram may be supplied to the arithmetic circuit 41 via the communication line 50. The program may be supplied to the arithmetic circuit 41 via the communication line 50. As another example, the arithmetic circuit 41 may be a GPU or the like. In this case, a set of a processor that controls the operation of the GPU and a storage unit that stores a program executed by the processor may be provided inside or outside the transmission circuit 42. The processor and the storage unit may be connected to the communication line 50, and the program may be supplied to the processor via the communication line 50.

[0036] In this embodiment, the arithmetic circuit IDs are designated "#1" to "#N" for the sake of convenience, but IP addresses, MAC addresses, etc. may also be used as the arithmetic circuit IDs.

[0037] The transmission circuit 42 may be provided to each module of the electronic computer 10. For example, as shown in FIG. 4, the control unit 20 and the memory unit 30 may be connected to a communication line 50 via the transmission circuit 42. In this case, the ID memory block 42A of the transmission circuit 42 connected to the control unit 20 stores the address of the control unit 20 instead of the arithmetic circuit ID. The ID memory block 42A of the transmission circuit 42 connected to the memory unit 30 (each of the main memory device 31 and the auxiliary memory device 32) stores the address of the main memory device 31 or the auxiliary memory device 32 instead of the arithmetic circuit ID.

[0038] [Second embodiment] In this embodiment, a process ID that identifies each process is set for each processing unit of a program, and the process data is assigned the process ID of the process to be executed by the arithmetic circuit having that arithmetic circuit ID, along with the arithmetic circuit ID.

[0039] This embodiment will be described below with reference to FIGS. 5 to 7. Note that descriptions that overlap with those of the first embodiment will be omitted as appropriate. This also applies to the third embodiment and thereafter, and descriptions of an embodiment that overlap with those of the previous embodiments will be omitted as appropriate. The electronic computer according to the second embodiment has a device configuration similar to the electronic computer 10 of FIG. 1. However, here, the arithmetic circuit 41-1 can execute processes A, B, and C, and the arithmetic circuit 41-2 can execute process D. Hereinafter, the electronic computer according to the second embodiment will also be referred to as electronic computer 110. It is assumed that processes A to D have process IDs set to "#A" to "#D", respectively.

[0040] (Example of operation of the electronic computer 110) An example in which the electronic computer 110 executes processing A, C, and D on processing data to be processed will be described below with reference to FIGS. 1 and 5. In the processing of FIG. 5, the control unit 20 assigns, to the processing data (data body) in accordance with a program, the processing circuit ID of the processing circuit 41 that will perform the processing and the processing ID of the processing to be executed by the processing circuit 41 (step S21). Here, the processing circuit ID "#1", processing IDs "#A" and "#C", processing circuit ID "#2", and processing ID "#D" are assigned in this order from the beginning. The assigned IDs are arranged in processing order from the beginning, with the processing circuit ID of the processing circuit 41 and one or more processing IDs to be executed by that processing circuit 41 forming a pair. The multiple processing IDs in each pair are also arranged in processing order from the beginning. The data body and the IDs assigned to the data body are collectively referred to as ID-assigned data, as described above (the same applies hereinafter to data to which other IDs are assigned). The format of the processing ID is defined, and the arithmetic circuit 41 and the like can recognize the location of the processing ID in the ID-attached data.

[0041] After step S21, the same processing as steps S12 and S13 in Fig. 2 described above is performed. That is, the ID-attached data is transferred to the arithmetic circuit 41-1, which uses the leading "#1" of the ID-attached data as the arithmetic circuit ID, and at that time, the "#1" is deleted in the transmission circuit 42-1.

[0042] Thereafter, the arithmetic circuit 41-1 executes process A indicated by the first process ID "#A" on the data body and deletes "#A" (step S24A). Thereafter, the arithmetic circuit 41-1 regards the processing result of process A as a new data body, executes process C indicated by the currently first process ID "#C" on this data body, and deletes "#C" (step S24B). As a result, the processed data after process C is obtained as the data body.

[0043] Thereafter, the processed data after process C becomes the data body, and the ID-assigned data in which "#2" and "#D" remain is subjected to the same processes as steps S15 and S16 in Fig. 2 described above. That is, the ID-assigned data is transferred to the arithmetic circuit 41-2, and the leading arithmetic circuit ID is deleted by the transmission circuit 42-2. As a result of deleting the arithmetic circuit ID, the ID-assigned data input to the arithmetic circuit 41-2 has the processing ID "#D" at its beginning in addition to the data body.

[0044] Thereafter, the arithmetic circuit 41-2 executes the process D on the processed data and deletes "#D" (step S27). Thereafter, the same process as step S18 in Fig. 2 described above is executed, and the data body after the process D is sent to the main memory device 31 as the final processing result.

[0045] (Detailed configuration and operation of arithmetic circuit 41-1) 6, the arithmetic circuit 41-1 includes a process ID table 41A-1, a distribution block 41B-1, and process execution blocks 41C-1 to 41E-1 that respectively execute processes A to C. The arithmetic circuit 41-1 further includes ID deletion blocks 41F-1 to 41H-1 that delete the process ID after each of processes A to C is completed, and an end determination block 41I-1.

[0046] In the processing ID table 41A-1, a processing ID is associated with specific information that identifies the processing execution block that executes the processing identified by that processing ID. For example, processing ID "#A" is associated with processing execution block 41C-1 that executes processing A. ID-assigned data input from transmission circuit 42-1 to arithmetic circuit 41-1 is first input to allocation block 41B-1. Allocation block 41B-1 references processing ID table 41A-1 using the first processing ID of the ID-assigned data as a key to obtain specific information corresponding to the processing ID used as a key. Allocation block 41B-1 inputs the ID-assigned data to the processing execution block identified by the obtained specific information among processing execution blocks 41C-1 to 41E-1.

[0047] The processing execution block 41C-1 executes processing A on the data body of the input ID-attached data, and generates new ID-attached data whose data body is the processing result of processing A. The processing execution block 41C-1 inputs the generated ID-attached data to the subsequent ID deletion block 41F-1. The ID deletion block 41F-1 deletes the first processing ID ("#A") from the ID-attached data, and outputs the deleted ID-attached data to the termination determination block 41I-1.

[0048] Similarly, the process execution block 41D-1 executes process B on the data body of the input ID-attached data. The ID deletion block 41G-1 deletes the first process ID ("#B") from the ID-attached data and outputs the ID-attached data after deletion to the termination determination block 41I-1.

[0049] Similarly, the process execution block 41E-1 executes process C on the data body of the input ID-attached data. The ID deletion block 41H-1 deletes the first process ID ("#C") from the ID-attached data and outputs the ID-attached data after deletion to the end determination block 41I-1.

[0050] In addition, if the executed process is the final process in the program, the data sent to the termination judgment block 41I-1 may not be data with an ID, but rather the data itself (final processing result) without a process ID or the like.

[0051] The termination judgment block 41I-1 judges whether the received data (ID-attached data or final processing result) contains any of the processing IDs in the processing ID table 41A-1. If it does, processing continues, and the received data (ID-attached data) is input again to the distribution block 41B-1. On the other hand, if there is no match, the received data (ID-attached data or final processing result) is output to the transmission circuit 42.

[0052] As described above, when processes A, C, and D are executed, in the arithmetic circuit 41-1, process execution block 41C-1 executes process A and ID deletion block 41F-1 deletes process ID "#A" from the ID-added process data. Furthermore, process execution block 41E-1 executes process C and ID deletion block 41H-1 deletes process ID "#C" from the ID-added process data.

[0053] (Detailed configuration and operation of arithmetic circuit 41-2) 7, the arithmetic circuit 41-2 includes a process ID table 41A-2, a distribution block 41B-2, and a process execution block 41C-2 that executes process D. The arithmetic circuit 41-2 further includes an ID deletion block 41D-2 that deletes the process ID after process D, and an end determination block 41I-2. In the process ID table 41A-2, the process ID "#D" of process D is associated with specific information that identifies the process execution block 41C-2 that executes process D. The other configurations are the same as those of the arithmetic circuit 41-1, so detailed explanations will be omitted. When the ID-added data has "#D" as the process ID, process D will be executed by the arithmetic circuit 41-2.

[0054] (Effects and Modifications) In this embodiment, it is possible to implement a plurality of processes in one arithmetic circuit 41, which has the advantage of increasing the efficiency of circuit utilization in devices such as FPGAs.

[0055] In this embodiment, #A to #D are used as the process IDs. The process ID is not limited to this, and may be, for example, an IP address, a MAC address, or a simple numerical value. Furthermore, the process ID may be configured to indicate the location of the part that executes the process, like a memory pointer.

[0056] [Third embodiment] In this embodiment, parallel processing in the arithmetic circuit 41 is enabled by inserting a parallel tag, which specifies that the processing is to be executed in parallel, in addition to the processing ID.

[0057] This embodiment will be described below with reference to Figures 8 and 9. The electronic computer according to the third embodiment has a device configuration similar to that of the electronic computer 110. However, the arithmetic circuit 41-1 is capable of executing processes A and B in parallel. Hereinafter, the electronic computer according to the third embodiment will also be referred to as electronic computer 210.

[0058] (Example of operation of the electronic computer 210) 1 and 8, an example will be described in which the electronic computer 210 executes processes A and B in parallel on the processing data to be processed, and then executes processes C and D sequentially. In the processing shown in FIG. 8, the control unit 20 assigns, to the processing data (the data body) in accordance with the program, the arithmetic circuit ID of the arithmetic circuit 41 that will perform the processing and the processing ID of the process to be executed by the arithmetic circuit 41 (step S31). Here, the arithmetic circuit ID "#1", the processing IDs "#A" to "#C", the arithmetic circuit ID "#2", and the processing ID "#D" are assigned in this order from the beginning. However, since processes A and B are executed in parallel in this case, the control unit 20 inserts a parallel tag "+" indicating parallel execution between "#A" and "#B" that identify processes A and B, respectively. The "+" indicates that the two processes identified by the process IDs before and after it are executed in parallel.

[0059] After step S31, the same processes as steps S12 and S13 in FIGS. 2 and 5 described above are performed. Then, the arithmetic circuit 41-1 determines whether a tag "+" is present immediately after the first process ID "#A." If there is no "+," the process A identified by "#A" is executed. However, since there is a "+" in this case, parallel execution of processes A and B identified by the process IDs "#A" and "#B" before and after the "+" is performed on the data body of the ID-associated data (step S34A). Furthermore, "#A," "+," and "#B" are deleted (step S34A). Then, the result of this processing is used as the new data body, and based on the ID-associated data from which "#A," "+," and "#B" have been deleted, the same processes as step S24C in FIG. 5 are performed, and the same processes as steps S15, S16, S27, and S18 in FIGS. 2 and 5 are performed. The above determination is also performed in step S24C. Through the above processes, processes C and D are executed.

[0060] (Detailed configuration and operation of arithmetic circuit 41-1) As shown in FIG. 9, the arithmetic circuit 41-1 includes a parallel processing determination block 41J-1 in addition to the configuration of the arithmetic circuit 41-1 of the second embodiment (see FIG. 6). A flag indicating parallel processing can be supplied from the allocation block 41B-1 to the parallel processing determination block 41J-1. The allocation block 41B-1 determines whether a tag "+" is present immediately after the first process ID of the ID-assigned data, and if the "+" is present, supplies the flag to the parallel processing determination block 41J-1. The allocation block 41B-1 also references the process ID table 41A-1 to obtain specific information corresponding to the process IDs before and after the "+" in the ID-assigned data. The specific information obtained here identifies the process execution blocks 41C-1 and 41D-1. In this case, the allocation block 41B-1 inputs the data bodies to the process execution blocks 41C-1 and 41D-1, thereby executing processes A and B in parallel. Depending on the processing content, the distribution block 41B-1 may divide the data body and input them to the processing execution blocks 41C-1 and 41D-1 respectively, or may input the data body as is to the processing execution blocks 41C-1 and 41D-1.

[0061] In the above parallel execution, the execution times may differ between process A and process B. When the above flag is supplied, the parallel processing determination block 41J-1 holds the processing results until both processes A and B being executed in parallel are completed, and when both processes A and B are completed, it outputs the parallel processing results of processes A and B to the termination determination block 41I-1.

[0062] (Effects and Modifications) By adopting the above configuration, it becomes possible to perform parallel processing using hardware such as FPGA, and it becomes possible to reduce the latency of the entire processing.

[0063] Parallel processing is not limited to the parallel execution of consecutive processes such as processes A and B. For example, if processes A and C can be executed in parallel, they may be arranged from the beginning as "#A", "+", "#C", "#B", etc. Furthermore, three or more processes may be executed in parallel. For example, by inserting multiple tags such as "#A", "+", "#B", "+", and "#C", three or more processes can be executed in parallel. Furthermore, parallel execution may be expressed by a number such as "+2" that indicates the number of process IDs to be executed in parallel. With "+2", the processes of the two process IDs following the number will be executed in parallel.

[0064] [Fourth embodiment] In addition to or instead of the parallel tag of the third embodiment, a branch tag indicating a branch of processing may be employed. For example, when processing A to processing D are executed, processing B is executed if the result of processing A is X, and processing C is executed if the result of processing A is Y. In this case, as shown in FIG. 10, the data body is prefixed with "#1", "#A", "!", "X", "#B", "Y", "#C", "#2", and "#D". The "!" after "#A" indicates a branch of processing A. The following "X", together with the following "#B", specify that processing B should be executed if the result of processing A corresponds to "X". The following "Y", together with the following "#C", specify that processing C should be executed if the result of processing A corresponds to "Y". The arithmetic circuit 41-1, to which the ID-added data from which "#1" has been deleted by the transmission circuit 42-1, executes processing A according to "#A" and deletes "#A". The arithmetic circuit 41-1 then follows the "!" to read up to "X", "#B", "Y", and "#C", and if the processing result of process A is the result corresponding to X, it executes process B. If the processing result is Y, the arithmetic circuit 41-1 executes process C.

[0065] The configuration of the arithmetic circuit 41-1 may be the same as that shown in FIG. 6. For example, after processing A, the termination determination block 41I-1 inputs the ID-attached data, to which "!", "X," "#B," "Y," "#C," "#2," and "#D" are added, as the processing result of processing A to the sorting block 41B-1. The sorting block 41B-1 reads the leading "!", "X," "#B," "Y," and "#C" of the input ID-attached data and determines whether the data body, which is the processing result of processing A, corresponds to X or Y. If the processing result is X, the sorting block 41B-1 refers to the processing ID table and inputs the ID-attached data to the processing execution block 41D-1 corresponding to "#B." At this time, the sorting block 41B-1 deletes "!", "X," "Y," and "#C" from the ID-attached data.

[0066] If the processing result is Y, the allocation block 41B-1 refers to the processing ID table and inputs the data with the ID to the processing execution block 41E-1 corresponding to "#C." At this time, the allocation block 41B-1 deletes "!", "X," "#B," and "Y" from the data with ID. Note that if the processing result does not correspond to both "X" and "Y," it may be determined that an abnormality has occurred and the entire series of processing by the program may be terminated.

[0067] As described above, in this embodiment, branch processing can be executed in the arithmetic circuit 41 by inserting a branch tag. Branching may be performed across multiple arithmetic circuits 41. The tag to be inserted is not limited to a branch tag, and various tags may be used. For example, a tag that executes loop processing may be prepared.

[0068] [Fifth embodiment] In this embodiment, instead of a processing ID and various tags, a data ID (an ID determined depending on the processing performed on the data body, etc.) that identifies the data body is assigned to the data body. Each arithmetic circuit 41 executes processing based on the data ID. In the above, a processing ID, etc. is assigned to the data body, but as the number of processes increases, the amount of data with IDs increases, which causes a decrease in the throughput of the electronic computer. In this embodiment, an individual data ID is assigned to the processing data that is the data body, and the processing required for each data ID is stored in a table in the arithmetic circuit 41, thereby reducing the amount of data assigned to the processing data.

[0069] The following description of this embodiment focuses on the handling of data IDs. The electronic computer according to the fifth embodiment has a device configuration similar to that of the electronic computer 10 shown in FIG. 1. However, here, the arithmetic circuit 41-1 can execute processes A, B, and C, and the arithmetic circuit 41-2 can execute process D. Hereinafter, the electronic computer according to the fifth embodiment will also be referred to as electronic computer 410. It is assumed that processes A to D are assigned process IDs "#A" to "#D," respectively. It is also assumed that data IDs are assigned "data #X" to "data #Z." Each arithmetic circuit 41 stores an ID correspondence table showing the correspondence between data IDs and process IDs. For example, the arithmetic circuit 41-1 has the ID conversion table shown in FIG. 11. The arithmetic circuit 41-2 has the ID conversion table shown in FIG. 12. In each ID conversion table, a data ID is associated with the process ID of a process that can be executed by the arithmetic circuit 41 that includes the ID conversion table. The format of the data ID is fixed, and the arithmetic circuit 41 and the like can recognize the location of the data ID in the ID-attached data.

[0070] (Example of operation of the electronic calculator 410) An example of the operation of the electronic calculator 410 will be described with reference to Fig. 1 and Fig. 13. Here, it is assumed that processes A to C are executed in the arithmetic circuit 41-1, and process D is executed in the arithmetic circuit 41-2. In the process of Fig. 13, the control unit 20 assigns, to the processing data that is the data body, the arithmetic circuit ID of the arithmetic circuit 41 that will perform the processing, and a data ID that can identify the processing to be executed by the arithmetic circuit 41, in accordance with the program (step S41). Here, it is assumed that the arithmetic circuit ID "#1", the arithmetic circuit ID "#2", and "data #X" as a data ID are assigned in this order from the beginning.

[0071] After step S41, the same processing as steps S12 and S13 in Fig. 2 is performed. That is, the ID-attached data is transferred to the arithmetic circuit 41-1, which uses the leading "#1" of the ID-attached data as the arithmetic circuit ID, and at that time, the "#1" is deleted in the transmission circuit 42-1.

[0072] Thereafter, the arithmetic circuit 41-1 refers to the ID conversion table shown in Fig. 11 using the data ID of the ID-added data as a key to acquire the process ID associated with the data ID (step S44). In this case, since the data ID is "data #X", the corresponding "#A" to "#C" are acquired. The arithmetic circuit 41-1 sequentially executes process A, process B, and process C identified by the acquired process ID.

[0073] Thereafter, the processed data after process C becomes the data body, and the ID-associated data in which "#2" and "data #X" remain is subjected to the same processes as steps S15 and S16 in FIG. 2 described above. That is, the ID-associated data is transferred to the arithmetic circuit 41-2, and the leading arithmetic circuit ID "#2" is deleted by the transmission circuit 42-2. As a result of deleting the arithmetic circuit ID, the ID-associated data input to the arithmetic circuit 41-2 has "data #X" at its beginning in addition to the data body.

[0074] Thereafter, the arithmetic circuit 41-2 refers to the ID conversion table shown in FIG. 12 using the data ID of the ID-added data as a key, and acquires the processing ID associated with this data ID (step S47). In this case, since the data ID is "data #X", the corresponding "#D" is acquired. The arithmetic circuit 41-1 executes processing D identified by the acquired processing ID. Thereafter, processing similar to step S18 in FIG. 2 described above is executed, and the data body after processing D is sent to the main memory device 31 as the final processing result. At this time, the data ID may or may not be deleted.

[0075] (Detailed configuration and operation of arithmetic circuit 41-1) As shown in FIG. 14, the arithmetic circuit 41-1 includes an ID conversion table 41M-1 and an ID conversion block 41N-1 shown in FIG. 11 in addition to the blocks shown in FIG. 6. This configuration is similar to that of the other arithmetic circuits 41. ID-assigned data supplied from the transmission circuit 42-1 is input to the ID conversion block 41N-1. The ID conversion block 41N-1 references the ID conversion table 41M-1 and obtains a processing ID corresponding to the data ID of the ID-assigned data. The ID conversion block 41N-1 assigns the obtained processing ID to the ID-assigned data in processing order (also defined by the ID conversion table 41M-1) from the beginning, and outputs the assigned ID-assigned data to the allocation block 41B-1. The allocation block 41B-1 performs the same operation as above, references the processing ID table 41A-1, and outputs the ID-assigned data to the processing execution block corresponding to the processing ID. This realizes the execution of processing A, etc.

[0076] The arithmetic circuit 41 may include an ID conversion table and an ID conversion block in addition to the blocks shown in Fig. 8 etc. In such a case, the information associated with the data ID in the ID conversion table may include information for performing parallel processing, branching, etc. in addition to the processing ID.

[0077] (Effects and Modifications) With the above configuration, by storing the processing content in a table, it is not necessary to assign a processing ID or the like that specifies the processing content to the ID-attached data, and the amount of data with the ID can be reduced, thereby preventing a decrease in throughput.

[0078] The data ID may be prepared individually for each arithmetic circuit 41. The ID conversion table may be configured so that the processing to be executed by each arithmetic circuit 41 can be identified using the data ID as a key. For example, the ID conversion table may store addresses of processing execution blocks in the form of pointers, or may store information in a form that allows routing to the destination of processing within the arithmetic circuit 41 in the form of next hops.

[0079] The data ID may be, for example, explicitly written in the program in advance by the user and stored in the storage unit.

[0080] [Sixth embodiment] In this embodiment, processing requests or program tasks from multiple users are processed. The electronic computer according to this embodiment is also referred to as electronic computer 510. The device configuration of electronic computer 510 is the same as that shown in FIG. 1. For example, user A requests the execution of processes A to D, and user B requests the execution of processes C and D. The user processing execution requests, along with processing data, are input to electronic computer 510 via a network or the like. As above, processes A to C are executed by arithmetic circuit 41-1, and process D is executed by arithmetic circuit 41-2. The ID-attached data requested by user A includes data #X as the data ID, and the ID-attached data requested by user B includes data #Y as the data ID. Furthermore, data #X is prepared for user A, and data #Y is prepared for user B. In other words, the users are identified by the data ID.

[0081] As shown in FIG. 15, the arithmetic circuit 41-1 of this embodiment has a configuration similar to that of FIG. 14, but includes an arbitration / allocation block 41P-1 instead of the allocation block 41B-1 of FIG. 14. Processing requests from multiple users may overlap. In other words, processing requests may conflict. Therefore, the arbitration / allocation block 41P-1 arbitrates the processing requests and prioritizes execution of one of the conflicting processing requests or waits for execution. The ID conversion tables shown in FIGS. 11 and 12 are used. When ID-attached data from user A and ID-attached data from user B are input simultaneously, the arbitration / allocation block 41P-1 compares the data IDs of the ID-attached data and determines the priority of the data to be processed. Priorities are set for each data ID, and the arbitration / allocation block 41P-1 determines the priority based on this setting. The arbitration / allocation block 41P-1 outputs the ID-attached data to the processing execution block in descending order of priority.

[0082] (Effects and Modifications) With the above configuration, multiple users or program tasks can be executed simultaneously on one computer.

[0083] In the ID conversion table, priority information such as processing priority may be associated with each data ID. In this case, the arbitration / distribution block 41P-1 may acquire the priority information by referring to the ID conversion table, and perform arbitration processing based on the acquired priority information.

[0084] [Seventh embodiment] 16, an electronic computer 610 according to this embodiment is basically the same as the configuration in FIG. 1, but each calculation unit 40 includes a calculation circuit 41 and a transmission circuit 42, as well as a transmission circuit 43 connected to the calculation circuit 41 and a communication line 60 connected to an external network. When the transmission circuits 43 are distinguished by the calculation circuit ID of the calculation circuit 41 to which they are connected, the transmission circuits 43 are also referred to as transmission circuits 43-1 to 43-N.

[0085] In this embodiment, the arithmetic circuit ID included in the ID-added data transmitted from communication line 50 to arithmetic unit 40 and the arithmetic circuit ID included in the ID-added data transmitted from communication line 60 to arithmetic unit 40 are different even though they identify the same arithmetic circuit 41. For example, for arithmetic circuit 41-1, "#1a" is set as the arithmetic circuit ID on the communication line 50 side, and "#1b" is set as the arithmetic circuit ID on the communication line 60 side. Similarly, for arithmetic circuit 41-2, "#2a" is set as the arithmetic circuit ID on the communication line 50 side, and "#2b" is set as the arithmetic circuit ID on the communication line 60 side. In this way, it is possible to determine from the arithmetic circuit ID whether the ID-added data was transmitted via communication line 50 or communication line 60.

[0086] In this embodiment, the transmission circuits 42 and 43 do not delete the arithmetic circuit ID included in the ID-associated data. For example, the arithmetic circuit 41 separates and stores the leading arithmetic circuit ID from the ID-associated data received from the transmission circuit 42 or 43. Thereafter, the arithmetic circuit 41 executes processing on the data body of the ID-associated data in the same manner as described above, and when returning new ID-associated data or the final processing result obtained as a result of the processing to the transmission circuit 42 or 43, the arithmetic circuit 41 determines the return destination according to the arithmetic circuit ID it holds. For example, if the held arithmetic circuit ID is #1a, it returns the ID-associated data or the final processing result to the transmission circuit 42, and if the arithmetic circuit ID is #1b, it returns the ID-associated data or the final processing result to the transmission circuit 43.

[0087] As described above, by assigning a different arithmetic circuit ID to each transmission path of ID-attached data, it becomes possible to clarify from which path the data has been sent.

[0088] [Eighth embodiment] 17, the electronic computer 710 according to this embodiment includes a control unit 20, a storage unit 30, a calculation unit 40, and a processing setting table T1. The processing setting table T1 is stored in a storage unit accessible by the calculation circuit 41 or the transmission circuit 42. The processing setting table T1 may be stored in each calculation unit 40, or may be stored in the storage unit 30. An example of the configuration of the processing setting table T1 will be described later.

[0089] FIG. 18 shows ID-assigned data handled by the electronic computer 710. ID-assigned data includes a data body, and a data ID, prefix length, and sequence number attached to the beginning of the data body. The data ID identifies the data body (i.e., the processing data to be processed). The data ID is also called a data address. The prefix length indicates the data length of the data ID. The prefix length identifies the data ID in the ID-assigned data. The sequence number indicates the current stage in the processing flow (the number of times the processing has been executed). The arithmetic circuit 41 increments this sequence number each time it executes a process. The flow identifies which arithmetic circuit (here, the arithmetic circuit is a concept that includes not only the arithmetic circuit 41 but also virtual arithmetic units such as processing execution blocks identified by the processing ID, which will be described later; the same applies hereinafter to arithmetic circuits not assigned reference numerals in this embodiment) will process the processing data and in what order. The flow ID identifies the flow.

[0090] The processing setting table T1 is table data for determining the destination of data transferred between multiple arithmetic circuits that sequentially execute multiple processes on processing data, and as shown in FIG. 19, data IDs, flow IDs, and flow information are associated with one another. The flow information is composed of multiple resource addresses (destinations of the data) that identify arithmetic circuits (including processing execution blocks as described above) that correspond to the arithmetic circuit IDs and processing IDs. The resource addresses correspond to the processing order, and here, the content of the flow is indicated by being arranged in processing order. The sorting order of the resource addresses corresponds to the sequence number. For example, the third resource address identifies the arithmetic circuit that executes the third process (arithmetic circuit 41; if arithmetic circuit 41 is capable of executing multiple processes, the arithmetic circuit and the processing execution block therein), and corresponds to sequence number "3."

[0091] The ID-attached data and the first resource address may be generated by any method. The ID-attached data transferred between arithmetic circuits is transferred together with the resource address. If the information included in the resource address that identifies at least the arithmetic circuit 41 is information that identifies the arithmetic circuit 41 connected to this transmission circuit 42, the transmission circuit 42 transmits the resource address and ID-attached data to that arithmetic circuit 41. If the information does not identify the arithmetic circuit 41 connected to this transmission circuit 42, the resource address and ID-attached data are discarded. As a result, the arithmetic circuit 41 receives the resource address and ID-attached data that specify itself.

[0092] When the arithmetic circuit 41 (which may be an arithmetic circuit without a code) receives a resource address and ID-associated data from the communication line 50 via the transmission circuit 42, it performs the processing shown in FIG. 20. When the arithmetic circuit 41 receives the ID-associated data (step S91), it processes the data body using the processing specified by the resource address transmitted together with the ID-associated data (e.g., processing in the processing execution block 41C-1 specified by the resource address), and increments the sequence number included in the ID-associated data (step S92). Thereafter, the arithmetic circuit 41 updates the data body to the processed data. The arithmetic circuit 41 refers to the processing setting table using the data ID included in the ID-associated data as a key, and identifies a flow ID corresponding to the data ID (step S93). The arithmetic circuit 41 identifies a resource address corresponding to the sequence number included in the ID-associated data from among the resource addresses included in the flow information corresponding to the identified flow ID in the processing setting table (step S94). Thereafter, the arithmetic circuit 41 sends the ID-attached data together with the resource address to the specified resource address, more specifically, to the address of the arithmetic circuit specified by the resource address (step S95).

[0093] Data IDs, flow IDs, and resource addresses are all generated with a 128-bit length, the same as IPv6. Each ID and address consists of a prefix and a suffix, the length of which is determined by the type of ID or address. Each ID and address is managed by a designated address management device, which handles address allocation and other tasks.

[0094] The data ID is assigned to the device (such as a surveillance camera or temperature sensor) that generates the processing data and is assigned to the generated data. For example, the data ID and prefix length are obtained from an address management device, and each time processing data is generated, the address is incremented within the prefix range and the address is assigned to the new data. The device that generates the processing data places the data ID and prefix length at the beginning of the data it generates (i.e., the data body or processing data) and transmits it to the electronic computer 710.

[0095] When the prefix is full, a request from a user occurs, data is changed, or the processing flow is changed, a new data address and prefix length are issued from the address management device.

[0096] The resource address is determined based on, for example, the location information (DC name, flow name, rack number, unit number) of the electronic computer 710. The resource address may include an address with a prefix length of 8 that identifies the computer cluster to which the electronic computer 710 belongs, and an address with a prefix length of 16 from a suffix that identifies each computer in the cluster. The resource address further includes an address with a prefix length of 32 from a suffix of the arithmetic circuit 41 in the electronic computer 710, and an address with a prefix length of 64 from a suffix of a virtual arithmetic unit (such as the above-mentioned processing execution block) configured in the arithmetic circuit 41. The resource address is determined based on the location and type of the resource each time a resource (arithmetic circuit) is added. When a resource is deleted, the address is released. Information identifying the resource is associated with the resource address and managed by the address management device. The resource information includes various information such as the cluster, computer, arithmetic unit, virtual arithmetic unit, processing content, and input / output regulations. In this way, the resource address includes affiliation information indicating the affiliation of the device that includes the arithmetic circuit and device information indicating the device that includes the arithmetic circuit, so by checking the resource address, it is possible to know the location of the arithmetic circuit, etc. The resource address as a whole is defined by IPv6, and the address of the arithmetic circuit 41 in the resource address may be defined by IPv4.

[0097] The flow address may include the address of the data to be processed in the flow. The user defines which resources to use and in what order to process the data, as well as the data to be processed in the processing flow. This definition is assigned a flow address and stored in the flow management device.

[0098] The processing setting table is generated by a data generating device 1 shown in FIG. 21. The data generating device 1 is composed of a server computer or the like. The data generating device 1 includes a processor 1A, a main memory 1B, and a non-volatile storage unit 1C. The data generating device 1 is communicably connected to an electronic computer 710 via a network NW. The processor 1A executes a program stored in the storage unit 1C to operate as a first acquisition unit 1F, a second acquisition unit 1G, and a generation unit 1H shown in FIG. 22.

[0099] The first acquisition unit 1F acquires a first correspondence table (FIG. 23) which is data indicating the correspondence between data IDs and flow IDs. The second acquisition unit 1G acquires a second correspondence table which is data indicating the correspondence between flow IDs and flow information. The first and second correspondence tables (FIG. 23) may be stored in and acquired from the storage unit 1C, or may be acquired via a network NW from outside the data generation device 1 (for example, from an address management device that manages the above two correspondence tables by any method). As shown in FIG. 23, the generation unit 1H associates the data IDs in the acquired first correspondence table with the flow information in the acquired second correspondence table via the flow IDs, and generates a process setting table (FIG. 19) in which the data IDs and flow information are associated with each other. The generation unit 1H supplies the generated process setting table to the electronic computer 710 for storage. The flow ID may be omitted from the process setting table. In this case, instead of steps S93 and S94, the calculation circuit 41 refers to the processing setting table using the data ID contained in the ID-attached data as a key, and identifies the resource address corresponding to the sequence number contained in the ID-attached data from among the resource addresses contained in the flow information corresponding to the data ID.

[0100] As shown in Figure 23, different data IDs may be associated with a common flow ID. More specifically, if the data specified by the data ID is different data, such as image data, for which the processing to be executed is the same but the content is different, the data IDs may be different but the processing flow may be the same. In the processing setting table described above, data IDs and flow information are associated via flow IDs, so different data IDs can be associated with the same flow information, thereby reducing the size of the table data.

[0101] If the data ID of the ID-added data is not entered in the processing setting table, the calculation circuit 41 may make an inquiry to the data generating device 1 to obtain a flow ID or the like and enter it in the processing setting table. If the data ID of the ID-added data is not entered in the processing setting table, the calculation circuit 41 may notify the control unit 20 to that effect, and the control unit 20 may make the above-mentioned inquiry, etc.

[0102] In this embodiment, the use of resource addresses makes it possible to clearly represent the location information of each arithmetic circuit, making it possible to find the most optimal placement of arithmetic circuits when executing continuous processing. Furthermore, by monitoring only the data addresses processed by each processing part, the data processing order, processing process, and data flow can be traced (data traceability), enabling high security, easy troubleshooting, visualization, and more. Furthermore, by using an address management mechanism equivalent to IPv6, it is possible to reduce the processing load of the part that handles the transfer of data flowing over the network, making it possible to process large volumes of data with low latency.

[0103] [Variations, etc.] The multiple arithmetic circuits that perform multiple processes on the processing data as described above may be integrated circuits such as FPGAs, virtual circuits within the integrated circuits, or processors such as CPUs. The arithmetic circuits may be connected to each other via a network other than a bus. The arithmetic circuits may also be connected to a router or the like. Note that the processing results of some of the arithmetic circuits may be temporarily stored in the storage unit 30 rather than being directly input to other arithmetic circuits.

[0104] [Configurations, modifications, etc., based on the above-described embodiments] (A)(1) The electronic computer may include, for example, a plurality of arithmetic circuits that sequentially execute a plurality of processes on processing data, and a control unit that executes a program and controls the plurality of arithmetic circuits to sequentially execute the plurality of processes. The plurality of processes includes branching processing and parallel processing. The arithmetic circuits include the arithmetic circuit 41 configured with an integrated circuit such as an FPGA, as described above, as well as processors such as a CPU and a GPU. The processor may be realized by a device that performs processing by executing a program. The arithmetic circuit may be realized by a virtual arithmetic unit such as a processing execution block 41C-1 that is part of the arithmetic circuit 41.

[0105] For example, each of the plurality of arithmetic circuits may be assigned an arithmetic circuit ID. The arithmetic circuit ID may be anything that identifies the arithmetic circuit. The arithmetic circuit ID may be realized by the resource address.

[0106] For example, the plurality of arithmetic circuits include a first arithmetic circuit that executes a first process among the plurality of processes, and a second arithmetic circuit that executes a second process that processes a processing result of the first process among the plurality of processes, and the first arithmetic circuit transmits the processing result of the first process to the arithmetic circuit ID of the second arithmetic circuit.

[0107] With the above configuration, when the processing result of the first processing is transmitted from the first arithmetic circuit to the second arithmetic circuit, no transfer by the control unit, for example, is required, and therefore an improvement in throughput is expected.

[0108] The multiple arithmetic circuits may each be housed in a separate housing, and the electronic computer may be realized as a system consisting of multiple housings.

[0109] (2) The electronic computer may further include a main memory device of the control unit, and the processing result of the first processing may be sent to the second arithmetic circuit without going through the main memory device. This eliminates the need to transfer the processing result to the main memory device, thereby further improving throughput.

[0110] (3) For example, the computer may further include a plurality of first transmission circuits connected to the plurality of arithmetic circuits, respectively, and a first communication line connecting the plurality of first transmission circuits and the control unit. The plurality of first transmission circuits may include a 1-1 transmission circuit connected to the first arithmetic circuit and a 1-2 transmission circuit connected to the second arithmetic circuit. The 1-1 transmission circuit may transmit the processing result of the first processing together with the arithmetic circuit ID of the second arithmetic circuit to the first communication line, and the 1-2 transmission circuit may receive the processing result of the first processing transmitted together with the arithmetic circuit ID of the second arithmetic circuit from the first communication line and transmit the received processing result to the second arithmetic circuit. When the arithmetic circuit is the above-mentioned processing execution block or the like, the transmission circuit may be considered to include the allocation block 41B-1, the completion determination block 41I-1, the transmission circuit 42-1, and the like of FIG. 6. This configuration facilitates the transfer of processing results.

[0111] (4) The plurality of arithmetic circuits may include a third arithmetic circuit that performs a third process that processes a processing result of the second process among the plurality of processes. The plurality of first transmission circuits may include a 1-3 transmission circuit connected to the third arithmetic circuit. The 1-2 transmission circuit may transmit the processing result of the second process together with the arithmetic circuit ID of the third arithmetic circuit to the first communication line. The 1-3 transmission circuit may receive the processing result of the second process transmitted together with the arithmetic circuit ID of the third arithmetic device from the first communication line and transmit the received processing result to the third arithmetic circuit. The processing result of the first process may be assigned the arithmetic circuit ID of the second arithmetic circuit and the arithmetic circuit ID of the third arithmetic circuit from the stage of transmission from the 1-1 transmission circuit to the first communication line. In this way, the processing results can be transferred sequentially by deleting the arithmetic circuit IDs.

[0112] (5) The electronic computer may further include a second transmission circuit connected to the second arithmetic circuit and a second communication line. The second arithmetic circuit may be assigned a first circuit ID that is the arithmetic circuit ID and a second circuit ID that is different from the first circuit ID. The second arithmetic circuit may be configured so that data to be processed in the second process is input from the first communication line via the first-to-second transmission circuit along with the first circuit ID, or so that data to be processed in the second process is input from the second communication line via the second transmission circuit along with the second circuit ID. The second arithmetic circuit may transmit data (processing results) obtained by performing the second process on the data to be processed to the first communication line via the first-to-second transmission circuit when the first circuit ID is input, and may transmit data (processing results) to the second communication line via the second transmission circuit when the second circuit ID is input. This allows the processing results to be correctly returned to the transmission line that is the source of the data to be processed.

[0113] (6) The second arithmetic circuit may be capable of executing a plurality of types of processing including the second processing, and the processing result may be provided with data that can identify the processing to be executed by the second arithmetic circuit, and the second arithmetic circuit may execute the processing identified based on the data attached to the processing result on the processing result. This allows the second arithmetic circuit to execute a plurality of processing operations while improving throughput.

[0114] (7) The second arithmetic circuit refers to a table based on the data to identify the processing to be performed, thereby reducing the amount of data transferred along with the processing results.

[0115] (8) The data may include data specifying branching of processing or parallel execution of multiple processing, thereby improving throughput for various processing.

[0116] (9) When a conflict occurs between a request for the first process on the first processing target data and a request for the second processing target data, the first arithmetic circuit may preferentially execute one of the first processes according to a predetermined priority order, thereby enabling appropriate processing to be performed for multiple processing requests.

[0117] (B)(1) A data generation device generates table data for determining the destination of processing data to be transferred between a plurality of arithmetic circuits that sequentially execute a plurality of processes on the processing data. The data generation device includes a first acquisition unit that acquires a first correspondence table between a data ID that identifies the processing data and a flow ID that identifies a flow that specifies which arithmetic circuits process the processing data and in what order, and a second acquisition unit that acquires a second correspondence table between the flow ID and flow information that specifies the contents of the flow identified by the flow ID by the destination order (more specifically, the destinations and their order). Furthermore, the data generation device associates the data IDs in the acquired first correspondence table with the flow information in the acquired second correspondence table via the flow IDs, and generates the table data in which the data IDs and the flow information are associated. This configuration makes it possible to suitably generate table data for determining the destination of data to be transferred between a plurality of arithmetic circuits. Furthermore, a program that causes a computer to operate as each of the above-mentioned units may be stored, for example, in a nonvolatile storage medium, more specifically, a computer-readable non-transitory storage medium.

[0118] (2) The generating unit may generate the table data in which the data ID, the flow ID, and the flow information are associated with each other. This allows a flow to be identified in the table data. The first correspondence table may include different data IDs associated with the same flow ID. This prevents the amount of table data from increasing due to the same flow information being associated with different data IDs.

[0119] (3) The destination may include affiliation information indicating the affiliation of a device including the arithmetic circuit and device information indicating the device including the arithmetic circuit. If the arithmetic circuit is a virtual arithmetic unit, the device information may be information specifying the arithmetic circuit in which the virtual arithmetic unit is provided. With this configuration, the location of the arithmetic circuit can be identified by looking at the destination.

[0120] (4) The generating unit may transmit the generated table data to an electronic computer including at least one of the plurality of arithmetic circuits.

[0121] (C) The electronic computer may include at least one of a plurality of arithmetic circuits that sequentially executes a plurality of processes on processing data to be processed. At least one of the plurality of arithmetic circuits may receive the processing data together with a data ID that identifies the processing data and a sequence number that indicates which of the plurality of processes has been executed. At least one of the arithmetic circuits may increment the sequence number when processing the processing data. At least one of the arithmetic circuits may also refer to the table data (see (B) above) in which the data ID and flow information are associated with each other, and obtain a destination corresponding to the incremented sequence number from among the destinations included in the flow information corresponding to the data ID. At least one of the arithmetic circuits may transfer its processing result to the arithmetic circuit of the obtained destination. The next destination is preferably identified by the sequence number.

[0122] [Scope of the present invention] The present invention is not limited to the above-described embodiments and modifications. For example, the present invention includes various modifications to the above-described embodiments and modifications that can be understood by a person skilled in the art within the scope of the technical concept of the present invention. The configurations listed in the above-described embodiments and modifications can be combined as appropriate within a range that does not cause contradictions. Furthermore, any of the above-described configurations can be deleted. [Explanation of symbols]

[0123] 1...data generation device, 10...electronic computer, 20...control unit, 30...memory unit, 31...main memory device, 32...auxiliary memory device, 40...arithmetic unit, 41...arithmetic circuit, 42...transmission circuit, 43...transmission circuit, 50...communication line, 60...communication line, 110...electronic computer, 210...electronic computer, 410...electronic computer, 510...electronic computer, 610...electronic computer, 710...electronic computer.

Claims

1. 1. A data generation device that generates table data for determining a destination of data to be transferred between a plurality of arithmetic circuits that sequentially execute a plurality of processes on processing data, comprising: a first acquisition unit that acquires a first correspondence table between a data ID that identifies the processing data and a flow ID that identifies a flow that specifies which arithmetic circuit processes the processing data and in what order; a second acquisition unit that acquires a second correspondence table between the flow ID and flow information that specifies the content of the flow identified by the flow ID based on the order of the destinations; a generation unit that associates the acquired data IDs of the first correspondence table with the acquired flow information of the second correspondence table via flow IDs, and generates the table data in which the data IDs and the flow information are associated with each other; A data generating device comprising:

2. the generation unit generates the table data in which the data ID, the flow ID, and the flow information are associated with each other. The data generating device according to claim 1 .

3. In the first correspondence table, different data IDs are associated with the same flow ID.

3. The data generating device according to claim 1 or 2.

4. The destination includes affiliation information indicating an affiliation of an apparatus including the arithmetic circuit, and apparatus information indicating an apparatus including the arithmetic circuit. The data generating device according to any one of claims 1 to 3.

5. a computer that generates table data for determining destinations of data to be transferred between a plurality of arithmetic circuits that sequentially execute a plurality of processes on processing data, a first acquisition step of acquiring a first correspondence table between a data ID for identifying the processing data and a flow ID for identifying a flow for specifying which arithmetic circuit processes the processing data and in what order; a second acquisition step of acquiring a second correspondence table between the flow ID and flow information that specifies the content of the flow identified by the flow ID based on the order of the destinations; a generating step of associating the acquired data IDs of the first correspondence table with the acquired flow information of the second correspondence table via flow IDs, and generating the table data in which the data IDs and the flow information are associated with each other; A program that executes the following.

Images