Ohmic contact formation in SiC-based electronic devices and electronic devices

Abstract

To provide a SiC-based electronic device and a method for manufacturing the SiC-based electronic device.SOLUTION: The method includes: implanting, on a top surface of a drift layer 52 made of SiC having a conductivity of N type on a substrate 53 of a wafer 100, dopant species of P type, thus forming an implanted region 59' that extends in the drift layer starting from the top surface and has a top surface coplanar with the top surface of the drift layer; and generating a laser beam 82 directed towards the implanted region 59' in order to generate heating of the implanted region 59' to a temperature between 1500°C and 2600°C so as to form a first carbon-rich electrical-contact region 59" at the implanted region 59'. The first carbon-rich electrical-contact region 59" forms an ohmic contact.SELECTED DRAWING: Figure 7D

Description

[Technical Field]

[0001] The present invention relates to SiC-based electronic devices and methods for fabricating SiC-based electronic devices, and more particularly to the formation of ohmic-type electrical contact regions in SiC-based electronic devices. [Background technology]

[0002] As is known, a wide band gap, especially a band gap energy value Eg higher than 1.1 eV, and a low on-state resistance (R ON ), high thermal conductivity values, high operating frequencies, and high saturation rates of charge carriers make semiconductor materials ideal for the manufacture of electronic components, such as diodes or transistors, especially for power applications. A material that possesses the above properties and that is being considered for use in the manufacture of electronic components is silicon carbide (SiC). In particular, silicon carbide, in its different polytypes (e.g., 3C-SiC, 4H-SiC, 6H-SiC), is more preferable than silicon as far as the aforementioned properties are concerned.

[0003] Compared to similar devices built on silicon substrates, electronic devices built on silicon carbide have many advantages, such as low output resistance in conduction, low leakage current, high operating temperature, and high operating frequency. In particular, SiC Schottky diodes have shown higher switching performance, making SiC electronic devices particularly desirable for high-frequency applications. Current applications impose requirements on the electrical properties and long-term reliability of the devices.

[0004] FIG. 1 shows a known type of merged PiN Schottky (MPS) device 1 in a cross-sectional side view in a (three-axis) Cartesian coordinate system of axes X, Y and Z.

[0005] The MPS device 1 comprises a substrate 3 made of N-type SiC, having a first dopant concentration, a surface 3a opposite a surface 3b, and having a thickness of about 350 μm; a drift layer (epitaxially grown) 2 made of N-type SiC, having a second dopant concentration lower than the first dopant concentration, extending on the surface 3a of the substrate 3, and having a thickness of between 5 and 15 μm; and an ohmic contact region 6 (e.g., made of nickel silicide) extending on the surface 3b of the substrate 3. anode metallization 8 extending over the upper surface 2 a of the drift layer 2; multi-junction barrier (JB) elements 9 in the drift layer 2 facing the upper surface 2 a of the drift layer 2 and including respective implanted regions 9′ of P type and ohmic contacts 9″ composed of a metal material; and end termination regions or guard rings 10 (optional), which are implanted regions of P type completely surrounding the JB elements 9.

[0006] A Schottky diode 12 is formed at the interface between the drift layer 2 and the anode metallization 8. In particular, a Schottky junction (semiconductor-metal) is formed by respective portions of the drift layer 2 in direct electrical contact with respective portions of the anode metallization 8.

[0007] The region of the MPS device 1 that includes the JB element 9 and the Schottky diode 12 (ie, the region contained within the guard ring 10 ) is the active area 4 of the MPS device 1 .

[0008] 2A and 2B, the steps for fabricating the MPS device 1 of FIG. 1 include a step (FIG. 2A) of masked implantation of a dopant species (e.g., boron or aluminum) having a second conductivity type (P). The implantation is illustrated by arrow 18 in FIG. 2A. For the implantation, a mask 11 is used, in particular a hard mask made of silicon oxide or TEOS. Thus, implanted region 9′ and end termination region 10 are formed. Then, as shown in FIG. 2B, the mask 11 is removed, and a thermal annealing step is performed for the diffusion and activation of the dopant species implanted in the step of FIG. 2A. The thermal annealing is performed, for example, at a temperature higher than 1600° C. (e.g., between 1700 and 1900° C., and in some cases even higher).

[0009] 3A-3C, a further step of forming ohmic contacts 9" is then performed. Referring to FIG. 3A, a deposition mask 13 composed of silicon oxide or TEOS is formed to cover the surface portion of drift layer 2 other than implanted regions 90' (and edge termination regions 10, if present). That is, mask 13 has through openings 13a in implanted regions 90' (and optionally at least part of edge termination regions 10). Referring to FIG. 3B, nickel deposition is then performed on mask 13 and in through openings 13a (metal layer 14 in FIG. 3B). The nickel thus deposited reaches and makes contact with implanted regions 9' and edge termination regions 10 via through openings 13a.

[0010] Referring to FIG. 3C, a subsequent thermal annealing at high temperature (between 900° C. and 1200° C.) for a time period of 1 to 120 minutes allows the formation of nickel silicide ohmic contacts 9″ by chemical reaction between the silicon of the drift layer 2 in the through openings 13 a and the deposited nickel. In fact, the deposited nickel reacts where it contacts the surface material of the drift layer 2 to form Ni2Si (i.e., ohmic contacts). Then, steps of removal of the metal extending on the mask 13 and removal of the mask 13 are performed.

[0011] The inventors have found that, where the nickel of metal layer 14 and mask 13 are in direct contact, a reaction, albeit limited, occurs, as illustrated in FIG. 4. FIG. 4 is a plan view in plane XY of a portion of the device of FIG. 3B, specifically the area demarcated by the dotted line and designated by reference numeral 15 in FIG. 3B. FIG. 4 relates to an intermediate fabrication step between the steps of FIGS. 3B and 3C, in which mask 13 is still present but nickel layer 14 has been removed. As can be seen in FIG. 4, irregular regions or islands 17 extend above mask 13, resulting from an undesired reaction between the nickel and the silicon of mask 13. The inventors have further found that similar irregular regions extend below mask 13, i.e., on surface 2a of drift layer 2. In FIG. 4, these irregular regions are designated by reference numeral 16 and are composed of a conductive material (including nickel). If the extension of the roughened region 16 in the plane XY, especially along X, is greater than the corresponding extension of the implanted region 9', it may create a short circuit that will result in breakdown of the device. In particular, if the undesired conductive region extends into an area dedicated to a Schottky contact, an ohmic or quasi-ohmic contact (a Schottky contact with a low barrier) will be formed on the N-type area (which is resistive from an electrical point of view), resulting in continuous current passage in both forward and reverse bias and loss of the diode properties.

[0012] Similar problems are encountered during ohmic contact formation on the body and source regions of SiC MOSFET devices.

[0013] FIG. 5 shows a MOSFET device 20 having a top surface 22a and a bottom surface 22b, and a semiconductor body 22 made of semiconductor material (which includes a substrate and, optionally, one or more epitaxial layers). The semiconductor body 22 has, for example, N-doping. A drain region 24, formed, for example, by implantation of N-type dopant species (N+ doping), extends to the bottom surface 22b. At the top surface 22a, a body region 25 (with P doping) surrounds the source region 28 (N+ doping). A gate structure 26, including a stack formed by a gate conductive layer 26a (e.g., polysilicon) and a gate dielectric layer 26b, extends over the top surface 22a, partially overlapping the source region 28. A respective insulating or dielectric layer 29 (e.g., made of silicon dioxide or TEOS) covers the gate structure 26.

[0014] An upper metal layer 30 is in electrical contact with source region 28 and body region 25 at respective surface portions 36 and 37, and therefore biases source region 28 and body region 25 to the same bias voltage during use.

[0015] An interface region (having P+ doping) 34 is formed in body region 25 facing upper surface 22a at surface portion 37 to improve electrical contact between upper metal layer 30 and body region 25. An interface ohmic contact layer 38, typically made of silicide, is formed in interface region 34 to form an ohmic contact between metal 30 and body region 25. Similarly, a further interface ohmic contact layer 39, also made of silicide, is formed in surface portion 36 to form an ohmic contact between metal 30 and source region 28.

[0016] 3A-3C, the formation of interfacial ohmic contact layers 38 and 39 involves the deposition of an intermediate metal layer, particularly nickel, using insulating layer 29 in a manner similar to that previously described for mask 13. This intermediate metal layer therefore extends over insulating layer 29 and over surface portions 36 and 37 in contact with intermediate region 34 and source region 28.

[0017] 3C, a subsequent thermal annealing at high temperature (between 900° C. and 1200° C. for a time period of 1 minute to 120 minutes) allows the formation of ohmic contacts consisting of nickel silicide by chemical reaction between the silicon of semiconductor body 22 and the deposited nickel in surface portions 36 and 37 (more particularly, in interface region 34 and source region 28). A step is then performed to remove the metal extending over insulating layer 29. The insulating layer 29, which will have a function in the final device, is not removed.

[0018] However, as previously mentioned, the inventors have found that where the nickel of metal layer 14 and insulating layer 29 are in direct contact (as illustrated in FIG. 4), there is reaction between the nickel 14 and insulating layer 29. As a result, irregular regions or islands extend onto insulating layer 29 and are due to undesired reaction between the nickel and the silicon of insulating layer 29. Because these islands are electrically conductive, they pose potential problems for the operation of device 20, particularly if their extensions create undesired short circuits or other types of undesired electrical connections. Isolation of polysilicon 26 through oxide 29 coverage is not uniform and is typically smallest at the highest point of polysilicon step 26. If reaction between the silicon of the oxide and the nickel occurs in this area, there is a high risk of forming a bridge between metal 30 and polysilicon 26, thereby creating a gate-to-source short circuit. Summary of the Invention [Problem to be solved by the invention]

[0019] SUMMARY OF THE INVENTION It is an object of the present invention to provide a SiC-based electronic device and a method for manufacturing the SiC-based electronic device that overcomes the drawbacks of the prior art. [Means for solving the problem]

[0020] According to the present invention, there is provided a SiC-based electronic device and a method for manufacturing the SiC-based electronic device, as defined in the claims.

[0021] For a better understanding of the invention, preferred embodiments thereof will now be described, purely by way of non-limiting example, with reference to the accompanying drawings, in which: [Brief explanation of the drawings]

[0022] [Figure 1] 1 is a cross-sectional view of an MPS device according to a known embodiment. [Figure 2A] 2A-2C are cross-sectional views illustrating intermediate steps for fabricating the MPS device of FIG. 1 according to the prior art. [Figure 2B] 2A-2C are cross-sectional views illustrating intermediate steps for fabricating the MPS device of FIG. 1 according to the prior art. [Figure 3A] 2C is a cross-sectional view illustrating steps for forming ohmic contacts in the MPS device of FIG. 1 after the steps of FIGS. 2A and 2B according to the prior art. [Figure 3B] 2C is a cross-sectional view illustrating steps for forming ohmic contacts in the MPS device of FIG. 1 after the steps of FIGS. 2A and 2B according to the prior art. [Figure 3C] 2C is a cross-sectional view illustrating steps for forming ohmic contacts in the MPS device of FIG. 1 after the steps of FIGS. 2A and 2B according to the prior art. [Figure 4] 3A-3B according to the prior art. FIG. [Figure 5] 1 is a cross-sectional view of a MOSFET device according to a known embodiment; [Figure 6] 1 is a cross-sectional view of an MPS device according to one embodiment of the present invention. [Figure 7A] 7A-7D are cross-sectional views illustrating certain steps for fabricating the MPS device of FIG. 6 in accordance with the present invention. [Figure 7B] 7A-7D are cross-sectional views illustrating certain steps for fabricating the MPS device of FIG. 6 in accordance with the present invention. [Figure 7C] 7A-7D are cross-sectional views illustrating certain steps for fabricating the MPS device of FIG. 6 in accordance with the present invention. [Figure 7D] 7A-7D are cross-sectional views illustrating certain steps for fabricating the MPS device of FIG. 6 in accordance with the present invention. [Figure 8] 7 is a graph illustrating the voltage-current polarity of the MPS device of FIG. 6; [Figure 9] 1 is a cross-sectional view of a MOSFET device according to one embodiment of the present invention. [Figure 10] 10A-10C are cross-sectional views illustrating certain steps in fabricating the MOSFET device of FIG. 9 in accordance with one embodiment of the present invention. [Figure 11] 10A-10C are cross-sectional views illustrating certain steps in fabricating the MOSFET device of FIG. 9 in accordance with further embodiments of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0023] The invention will be described with reference to two possible embodiments, specifically a merged PiN Schottky (MPS) device (FIGS. 6, 7A-7D) and a MOSFET device (FIGS. 9-11), but as will become apparent from the following description, the invention is generally applicable to any SiC-based electronic device.

[0024] FIG. 6 illustrates a side cross-sectional view of a merged PiN Schottky (MPS) device 50 according to one aspect of the present invention in a Cartesian coordinate system having X, Y, and Z axes (three-axis).

[0025] The MPS device 50 comprises a substrate 53 made of N-type SiC and having a thickness between 50 μm and 350 μm, more particularly between 160 μm and 200 μm, e.g., equal to 180 μm, and a surface 53 a opposite a surface 53 b, the substrate 53 having a first dopant concentration; a drift layer (epitaxially grown) 52 made of N-type SiC and having a thickness between 5 and 15 μm, extending on the surface 53 a of the substrate 53 and having a second dopant concentration lower than the first dopant concentration; an ohmic contact region or layer 56 (made of, for example, nickel silicide) extending on the surface 53 b of the substrate 53; anode metallization 58 extending over the upper surface 52 a of the drift layer 52 and made of, for example, Ti / AlSiCu or Ni / AlSiCu; a passivation layer 69 on the anode metallization 58 for protecting the anode metallization 58; multi-junction barrier (JB) elements 59 facing the upper surface 52 a of the drift layer 52 and each including a respective P-type implanted region 59′ and ohmic contact 59″; and end termination regions or guard rings 60 (optional), which are P-type implanted regions that completely surround the junction barrier elements 59.

[0026] One or more Schottky diodes 62 are formed at the interface between the drift layer 52 and the anode metallization 58, next to the implanted region 59'. In particular, a (semiconductor-metal) Schottky junction is formed by respective portions of the drift layer 52 in direct electrical contact with respective portions of the anode metallization 58.

[0027] The region of MOS device 50 containing JB element 59 and Schottky diode 62 (ie, the region contained within guard ring 60 ) is the active area 54 of MPS device 50 .

[0028] According to one aspect of the present invention, each ohmic contact 59″ is formed by one or more carbon-rich layers, including, for example, a graphite layer or a graphene multilayer. More specifically, each ohmic contact 59″ has, on the surface 52 a, a Si / C amorphous layer in which, due to phase separation between carbon and silicon atoms in the SiC substrate, carbon atoms are predominant (e.g., at least two times higher, particularly 2 to 100 times higher) compared to silicon atoms. Beneath this amorphous layer, each ohmic contact 59″ may provide a layer (e.g., a graphite layer) containing carbon clusters, which has a thickness greater than that of the amorphous layer. The formation of such ohmic contacts 59″ results from the thermal decomposition of silicon carbide as a result of the manufacturing process described below.

[0029] According to a further aspect of the invention, the ohmic contact 59" is self-aligned on the surface 52a with the implanted region 59" (i.e., in plan view in the plane XY, the ohmic contact 59" has the same shape and extent as the implanted region 59'). In this case, electrical contact between the anode metallization 58 and the implanted region 59' occurs exclusively via the ohmic contact 59".

[0030] Moreover, in accordance with a further aspect of the present invention, ohmic contact 59" does not extend along Z beyond surface 52a; i.e., upper surface 59a of ohmic contact 59" is flush with surface 52a (i.e., aligned along the X axis) and extends into ohmic contact 59' only a depth (along Z) of between one nanometer and several tens of nanometers (e.g., between 1 nm and 20 nm) measured from surface 52a.

[0031] Each ohmic contact 59" provides an electrical connection having a lower electrical resistance than the electrical resistance of the region in which it is received. In particular, each ohmic contact 59" has a lower electrical resistance than the electrical resistance of the respective region 59' in which it is received.

[0032] The steps for forming ohmic contacts 59' are described below with reference to the steps for fabricating MPS device 50 (FIGS. 7A-7D).

[0033] Referring to FIG. 7A, a wafer 100 is provided having a SiC substrate 53 (specifically 4H-SiC, although other polytypes such as, but not limited to, 2H-SiC, 3C-SiC, 6H-SiC, etc., may also be used).

[0034] The substrate 53 has a first conductivity type (in this example, N-type doping) and has a front surface 53a and a back surface 53b that are opposite each other along the Z axis. 19 〜1×10 22 atoms / cm 3 The dopant concentration is between 0.01 and 0.1.

[0035] The front of wafer 100 corresponds to front surface 53a, and the back of wafer 100 corresponds to back surface 53b. The resistivity of substrate 30 is, for example, between 2 mΩ·cm and 40 mΩ·cm. Formed on the front surface 53a of the substrate 53, for example by epitaxial growth, is a drift layer 52, which is made of silicon carbide having a first conductivity type (N) and a lower dopant concentration than that of the substrate 53, for example 1×10 14 ~5×10 16 atoms / cm 3 The drift layer 52 is composed of SiC, particularly 4H—SiC, although other SiC polytypes such as 2H, 6H, 3C, or 15R may also be used.

[0036] Drift layer 52 has a thickness defined between top side 52a and bottom side 52b (bottom side 52b is in direct contact with front surface 53a of substrate 53). 7B, a hard mask 70 is then formed on the upper side 52a of the drift layer 52, e.g., photoresist, or TEOS, or some other material designed for that purpose. The hard mask 70 has a thickness between 0.5 μm and 2 μm, or any thickness that will block the implants described below with reference to the same FIG. 7B. The hard mask 70 extends over the region of the wafer 100 where the active areas 54 of the MPS devices 50 will be formed in a later step.

[0037] In plan view in plane XY, hard mask 70 covers the region of upper side 52 a of drift layer 52 that will form Schottky cell (diode 62) and leaves exposed the region of upper side 52 a of drift layer 52 that will form implanted region 59′ as previously described with reference to FIG. 6.

[0038] An implantation step of a dopant species (for example boron or aluminum) is then carried out, which has the second conductivity type (in this case P type) and which uses a hard mask 70 (the implantation is indicated in the figure by arrows 72). During the step of Figure 7B, the guard ring 60 (if present) is also formed.

[0039] In one embodiment given by way of example, the implantation step of FIG. 18 atoms / cm 3 To form implanted region 59' having a dopant concentration higher than 1×10 12 atoms / cm 2 〜1×10 15 atoms / cm 2 The implantation includes implanting one or more dopant species having the second conductivity type at an implantation energy between 30 keV and 400 keV at a dose between 0.4 μm and 1 μm, thus forming an implanted region having a depth measured starting from surface 52 a of between 0.4 μm and 1 μm.

[0040] Then, referring to FIG. 7C, the mask 70 is removed, and, referring to FIG. 7D, a thermal treatment is performed on the surface 52a, designed to favor the development of implanted regions 59'.

[0041] To this end, a laser source 80 is used that is configured to generate a beam 82 for locally heating the surface 52a (in particular the implanted region 59') to a temperature of approximately 1500° C. to 2600° C. Given the maximum depth of the implanted region 59', a temperature of approximately 2000° C. at the level of the surface 52a is sufficient to ensure a temperature within the aforementioned range even at the maximum depth (e.g., 1 μm) reached by the implanted region 59'.

[0042] This temperature is such as to favor the generation of ohmic contacts (e.g., containing graphite and / or graphene, as described above) exclusively on the implanted regions 59', and not on the surfaces 52a where the implanted regions 59' are not provided. This effect is of a type known per se and is described, for example, in "Low-temperature, site selective graphitization of SiC via ion implantation and pulsed laser annealing" by Maxime G. Lemaitre, APPLIED PHYSICS LETTERS 100, 193105 (2012).

[0043] In one embodiment, conversion of a portion of implanted region 59' to an ohmic contact 59'' is accomplished by heating the entire wafer 100 by moving laser 80 accordingly.

[0044] In a further embodiment, conversion of the surface portion of implanted region 59' to ohmic contact 59" is achieved by heating the useful surface of wafer 100, where "useful surface" refers to the portion of the surface of drift layer 52 that includes implanted region 59' that is externally bounded by, for example, edge termination region 10. The useful surface may not correspond to the entire surface of wafer 100 (e.g., excluding some portions of wafer 100 laterally relative to active area 54 that are not of interest during use of MPS device 50 unless they are involved in charge transport).

[0045] In a further embodiment, a mask can be placed over surface 52a (either in contact with surface 52a or at a distance therefrom) having areas that are transparent to beam 82 (i.e., beam 82 passes through those areas) and areas that are opaque to beam 82 (i.e., beam 82 does not pass through those areas or passes through those areas in an attenuated manner so as not to significantly heat portions of wafer 100 extending thereunder). The transparent areas of the mask are aligned with implanted regions 59' to allow for the formation of ohmic contacts 59".

[0046] Optionally, and independently of the embodiment used, implanted region 59' (particularly, about 1×10 17 atoms / cm 3 〜1×10 20 atoms / cm 3 5. An ohmic contact 59" is formed simultaneously with each implanted region, in which the dopant is activated to obtain a concentration of the dopant species between 5.

[0047] Furthermore, because the ohmic contacts are formed exclusively on the implanted regions 59', there is self-alignment between the implanted regions 59' and the respective ohmic contacts 59'' even in the absence of a mask.

[0048] In the implanted region 59', a localized and surface temperature increase causes the formation of ohmic contacts 59", but no such effect is observed laterally of the implanted region 59'. The formation of ohmic contacts 59" is carried out at temperatures between 1200°C and 2600°C. According to the invention, these temperatures are reached in the surface portion (a few nanometers, e.g., 1-20 nm) of the implanted region 59'. For greater depths, the temperature drops to a value that no longer causes the formation of ohmic contacts 59", and is therefore self-limiting. Thus, the ohmic contacts 59" do not extend through the thickness of the respective implanted region, but are solely at its surface level.

[0049] The laser 80 is, for example, a UV excimer laser. Other types of lasers can also be used, among them lasers with wavelengths in the visible light range.

[0050] The construction and operating parameters of laser 80 optimized for the purposes of the present invention are as follows:

[0051] Wavelength: between 290 nm and 370 nm, in particular 310 nm; Pulse duration: between 100 ns and 300 ns, in particular 160 ns; Number of pulses: between 1 and 10, especially 2; Energy density: (2) 1.6 to 4 J / cm 2 Especially (3) 2.6 J / cm 2 (considered at the level of surface 52a); and Temperature: between 1400° C. and 2600° C., in particular 1800° C. (considered at the level of the surface 52a).

[0052] The area of the spot of the beam 82 at the level of the surface 52a is, for example, 0.7 to 1.5 cm 2 It is between.

[0053] One or more scans of the laser 80 are performed in the plane XY (e.g., multiple scans parallel to each other and to the axis X and / or to the axis Y) to cover the entire wafer 100 or a sub-area of the wafer 100 to be heated.

[0054] However, the inventors have found that the aforementioned parameters result in the desired electrical behavior for MPS device 50. Figure 8 illustrates experimental data in this regard, showing the change in conduction current as a function of the voltage applied between the anode and cathode of MPS device 50. Curve S1 relates to electrical measurements on the PiN diode before the laser treatment, while curve S2 relates to electrical measurements on the PiN diode after the laser treatment, and thus after ohmic contact formation. The trends of curves S1 and S2 confirm the predicted behavior.

[0055] Figure 9 illustrates a MOSFET device 90 according to one aspect of the present invention. Technical elements and features of MOSFET device 90 that are common to MOSFET device 20 of Figure 5 are indicated by the same reference numerals and therefore will not be described again.

[0056] Unlike MOSFET device 20, MOSFET device 90 includes an ohmic contact 91 at interface region 34 between metal 30 and body region 25. MOSFET device 90 also includes an additional ohmic contact 92 at surface portion 36 between metal 30 and source region 28.

[0057] According to one aspect of the present invention, both ohmic contact 91 and ohmic contact 92 are formed by one or more carbon-rich layers, including, for example, graphite layers or graphene multilayers. More specifically, each ohmic contact 91, 92 includes, on surface 52a, a Si / C amorphous layer in which carbon atoms predominate (e.g., at least two times higher, particularly 2 to 100 times higher) relative to silicon atoms due to phase separation between silicon and carbon atoms in the SiC substrate. Beneath this amorphous layer, each ohmic contact 91, 92 can include a layer containing carbon clusters (e.g., a graphite layer) having a thickness greater than that of the amorphous layer. The formation of such ohmic contact 59″ results from the thermal decomposition of silicon carbide as a result of the manufacturing process described below.

[0058] According to a further aspect of the invention, the ohmic contacts 91 and 92 are self-aligned on the surface 22a with the interface region 34 and the source region 28 (i.e., in a plan view in the plane XY, the ohmic contacts 91 and 92 have the same shape and extent as the interface region 34 and the source region 28, respectively).

[0059] The ohmic contacts 91 and 92 extend depthwise (along the Z axis) into the semiconductor body 22 to a depth of between one nanometer and several tens of nanometers (e.g., between 1 and 20 nm), measured starting from the surface 22a.

[0060] Each ohmic contact 91, 92 provides an electrical connection having a lower electrical resistance than the electrical resistance of the region in which it is contained. In particular, each ohmic contact 91, 92 has a lower electrical resistance than the electrical resistance of the respective region 34, 28 in which it is contained.

[0061] The steps for forming ohmic contacts 91 and 92 are described below with reference to FIG.

[0062] In particular, FIG. 10 shows a wafer 200 containing a MOSFET device 90 at an intermediate stage of fabrication, in which body region 25, interface region 34, source region 28, gate structure 26, and insulating layer 29 have been formed (in a manner known per se).

[0063] To form the ohmic contacts 91, 92, a heat treatment is generated on the surface 22a, configured to favor the generation of the respective ohmic contacts 91, 92, in the interface region 34 and in the source region 28. For that purpose, a laser source 95 is used, configured to generate a beam 96 that locally heats the surface 22a (in particular the interface region 34 and the source region 28) to a temperature of approximately 1200°C to 2600°C.

[0064] Temperatures within the aforementioned ranges are achieved by increasing the temperature of the interface region 34 and the source region 28. This is to favor the development of carbon-rich regions and graphite / graphene layers exclusively in the interface region 34 and source region 28, rather than in the undisturbed surface region 22a.

[0065] In one embodiment, the conversion of interface region 34 and source region 28 to their respective ohmic contacts is accomplished by heating the entire wafer 200 by moving laser 95 appropriately.

[0066] In a further embodiment, the conversion of the interface region 34 and the source region 28 to their respective ohmic contacts is accomplished by selectively heating the interface region 34 and the source region 28 by appropriately directing the beam 96 .

[0067] In a further embodiment, a mask (not shown) can be placed over wafer 200 that has areas that are transparent to beam 96 (i.e., beam 96 passes through the areas) and areas that are opaque to beam 96 (i.e., beam 96 does not pass through the areas or passes through the areas in an attenuated manner so as not to significantly heat the masked portions of wafer 200). The transparent areas of the mask are aligned with interface region 34 and source region 28 to allow for the formation of respective ohmic contacts and to protect portions of wafer 200 where ohmic contacts are not intended to be formed via laser 95.

[0068] The inventors have discovered that forming ohmic contact 92 in source region 28 (which has N+ doping) requires a different energy of beam 96 than the energy required to form ohmic contact 91 in interface region 34 (which has P+ doping).

[0069] Optimizing the ohmic properties of contact 92 in source region 28 (which has N+ doping) requires a different energy of beam 96 than the energy required to optimize the ohmic properties of contact 91 in interface region 34 (which has P+ doping). To that end, the operating parameters of laser 95 can be controlled to generate respective beams 96 in interface region 34 and in source region 28, with each beam set to generate a respective layer with optimal ohmic properties.

[0070] In any event, the inventors have discovered that even if beams of the same energy are applied, it is possible to form an ohmic contact 92 in the source region 28 (having N+ dopant) and an ohmic contact 91 in the interface region 34 (having P+ doping).

[0071] In summary, the geometry and operating parameters of laser 95, in source region 28 and interface region 34, optimized to achieve the objectives of the present invention are as follows:

[0072] Wavelength: between 290 nm and 370 nm, in particular 310 nm; Pulse duration: between 100 ns and 300 ns, in particular 160 ns; Number of pulses: between 1 and 10, especially 2; Energy density: (2) 1.6 and 4 J / cm 2 Especially (3) 2.6 J / cm 2 (considered at the level of surface 22a); Temperature: between 1400° C. and 2600° C., in particular 1800° C. (considered at the level of the surface 22a).

[0073] The area of the spot of the beam 82 at the level of the surface 22a is, for example, 0.7 to 1.5 cm 2 It is between.

[0074] One or more scans of the laser 95 are performed in the plane XY (e.g., multiple scans parallel to each other and to the axis X and / or to the axis Y) to cover the entire wafer 200 or a sub-region of the wafer 200 to be heated.

[0075] 11, a mask 97 can be placed over wafer 200, with windows 97a, 97b at (and vertically aligned with) interface region 34 and source region 28, respectively. The remainder 97c of mask 97 is completely opaque to beam 96, i.e., beam 96 does not pass through it, or if it does pass through, it does so in such a way that it does not cause heating that would cause damage or any other type of undesirable phenomenon to the underlying structure of wafer 200.

[0076] Window 97a in interface region 34 is provided with a filter 98 configured to modify the properties of beam 96, for example, if it is desired to modify some properties of the beam incident on interface region 34. Alternatively, filter 98 may not be provided. Window 97b in source region 28 does not have any filter, i.e., it is transparent to beam 96, which passes through window 97b substantially unchanged as far as its properties are concerned.

[0077] In the following embodiment of the invention, both windows 97a and 97b are unfiltered, and mask 97 functions to protect (via opaque portion 97c) areas that should not be heated by beam 96.

[0078] Specifically, in this embodiment, beam 96 is generated by controlling laser 95 in the following manner.

[0079] Wavelength: between 290 nm and 370 nm, in particular 160 nm; Pulse duration: between 100 ns and 300 ns, in particular 160 ns; Number of pulses: between 1 and 10, especially 2; Energy density: (2) 1.6 to 4 J / cm 2 Especially (3) 2.6 J / cm 2 (considered at the level of surface 22a); Temperature: between 1400° C. and 2600° C., in particular 1800° C. (considered at the level of the surface 22a).

[0080] The area of the spot of the beam 82 at the level of the surface 22a is, for example, 0.7 to 1.5 cm 2 It is between.

[0081] One or more scans of the laser 95 are performed in the plane XY (e.g., multiple scans parallel to each other and to the axis X and / or to the axis Y) to cover the entire wafer 200 or a sub-region of the wafer 200 to be heated.

[0082] The beam 96 so generated is directed towards the source region 28 (N+) through window 97b and towards the interface region 34 (P+) through window 97a.

[0083] According to a further embodiment, it will be apparent that window 97b may also be provided with a filter to generate beam 96 in an appropriate manner (i.e., with the filtered beam configured to generate an ohmic contact in source region 28).

[0084] Because the ohmic contacts are formed exclusively at the P and N implanted regions, there is self-alignment between the interface region 34 / source region 28 and the respective ohmic contacts 91 / 92.

[0085] The conversion of SiC into carbon-rich layers and / or graphite and / or graphene layers occurs based on the technical considerations already mentioned above with respect to the fabrication of MPS devices.

[0086] The laser 95 is, for example, a UV excimer laser. Other types of lasers can also be used, among them lasers with wavelengths in the visible light range.

[0087] The advantages of the present invention are apparent upon reviewing the characteristics of the present invention provided in accordance with this disclosure, particularly in that the present invention allows for the provision of ohmic contacts on P+ or N+ regions in a single process and without the deposition of a metal layer, thereby overcoming the drawbacks of the prior art discussed above.

[0088] While specific embodiments of the present invention have been described in detail above, it should be understood that the present invention is not limited to these specific embodiments, and various modifications, alterations, and substitutions can be made without departing from the scope of the present invention. In particular, as mentioned above, the present invention is not limited to the formation of ohmic contacts in MOS devices or MOSFETs, but is applicable to the formation of ohmic contacts in general vertical conduction electronic devices such as Schottky diodes, JBS devices, MOSFETs, IGBTs, JFETs, and DMOSs.

Claims

1. A method for manufacturing a SiC-based electronic device (50; 90), comprising: implanting P-type dopant species into a surface (52a; 22a) of a solid body (52, 22) of SiC having N-type conductivity to form an implanted region (59'; 34) starting from said surface (52a; 22a) and extending into said solid body and having an upper surface flush with said surface (52a; 22a); generating a first laser beam (82; 96) directed at the implanted region (59'; 34) to cause heating of the implanted region (59'; 34) to a temperature between 1500°C and 2600°C to form a first carbon-rich electrical contact region (59"; 91) in the implanted region (59'; 34); A way of embracing that.

2. 10. The method of claim 1, wherein forming the first carbon-rich electrical contact region (59"; 91) comprises forming one or more graphene and / or graphite layers in the implanted region (59'; 34).

3. said first laser beam (82; 96) having the following parameters: Wavelength: between 290 nm and 370 nm, in particular 310 nm; Pulse duration: between 100 ns and 300 ns, in particular 160 ns; Number of pulses: between 1 and 10, especially 2; Energy density: between 1.6 and 4 J / cm2, in particular 2.6 J / cm2; The method according to claim 1 or 2, wherein the method is generated based on

4. 4. The method of claim 1, wherein the first carbon-rich electrical contact region (59"; 91) forms a first ohmic contact having an upper surface coinciding with an upper surface of the implanted region (59'; 34).

5. 5. A method according to any one of claims 1 to 4, wherein said first carbon-rich electrical contact region (59"; 91) has a thickness between 1 nm and 20 nm.

6. 6. The method of claim 1, wherein the material of the solid body is one of 4H-SiC, 6H-SiC, 3C-SiC, and 15R-SiC.

7. 7. The method of any one of claims 1 to 6, wherein the electronic device (50; 90) is one of a combined PiN Schottky diode, a Schottky diode, a JBS diode, a MOSFET, an IGBT, a JFET, and a DMOS.

8. The electronic device (50) is a merged PiN Schottky diode (MPS), and the method comprises: forming the solid body by providing an N-type SiC substrate having opposed front and back sides and epitaxially growing a drift layer (52) of N-type SiC on the front side of the substrate; forming a first electrical terminal (58) in electrical contact with the implanted region (59') through the first carbon-rich electrical contact region (59") and in direct electrical contact with the drift layer (52) laterally of the implanted region (59') to form a junction barrier (JB) diode with the implanted region (59') and a Schottky diode with the drift layer (52); forming a second electrical terminal (57) on the backside of the substrate; 8. The method of any one of claims 1 to 7, comprising:

9. the electronic device (90) is a MOSFET, and the method comprises: forming a P-type first body region (25) on the front side (22a) of the solid body (22); forming the implanted region (34) within the first body region (25); forming a P-type second body region (25) on the front side (22a) of the solid body (22) and extending laterally relative to the first body region (25); forming an N-type source region (28) in the second body region (25); generating a second laser beam (96) directed toward the source region (28) to cause heating of the source region (28) to a temperature between 1500°C and 2600°C to form a second carbon-rich electrical contact region (92) in the source region (28); 9. The method of any one of claims 1 to 8, comprising:

10. The second laser beam (96) has the following parameters: Wavelength: between 290 nm and 370 nm, in particular 310 nm; Pulse duration: between 100 ns and 300 ns, in particular 160 ns; Number of pulses: between 1 and 10, especially 2; Energy density: between 1.6 and 4 J / cm2, in particular 2.6 J / cm2; The method of claim 9, wherein the method is generated based on

11. 11. The method of claim 9 or 10, wherein forming the second carbon-rich electrical contact region (92) comprises forming one or more graphene and / or graphite layers in the source region (28).

12. 12. The method of any one of claims 1 to 11, wherein the first carbon-rich electrical contact region (59"; 91) forms a first ohmic contact having an upper surface coinciding with an upper surface of the implanted region (59'; 34).

13. 10. The method of claim 9, wherein the second carbon-rich electrical contact region (92) has a thickness between 1 nm and 20 nm.

14. In an electronic device based on SiC (50; 90), a solid body made of SiC with N-type conductivity (52:22); an implanted region (59'; 34) extending over the front side (52a; 22a) of the solid body (52; 22) and containing a P-type dopant species and having an upper surface flush with the front side (52a; 22a) of the solid body; and a first carbon-rich electrical contact region (59"; 91) extending in said implanted region (59'; 34) and having an upper surface coplanar with said upper surface of said implanted region; A device having:

15. 15. The device of claim 14, wherein the first carbon-rich electrical contact region (59"; 91) comprises one or more graphene and / or graphite layers within the implanted region (59'; 34).

16. 16. The device of claim 15, wherein the first carbon-rich electrical contact region (59"; 91) forms an ohmic contact having an upper surface coinciding with an upper surface of the implanted region (59'; 34).

17. 17. The device of any one of claims 14 to 16, wherein the first carbon-rich electrical contact region (59") has a thickness between 1 nm and 20 nm.

18. 18. The apparatus of any one of claims 14 to 17, wherein the material of the solid body is any one of 4H-SiC, 6H-SiC, 3C-SiC, and 15R-SiC.

19. 19. The device of any one of claims 14 to 18, wherein the device is selected from the group consisting of a combined PiN Schottky diode, a Schottky diode, a JBS diode, a MOSFET, an IGBT, a JFET, and a DMOS.

20. the device is of the merged PiN Schottky (MPS) diode type, the solid body comprising an N-type SiC substrate having opposed front and back sides, and a drift layer (52) of N-type SiC on the front side of the substrate; and a first electrical terminal (58) in electrical contact with the implantation region (59') through a first region of the ohmic contact (59") to form a junction barrier (JB) with the implantation region (59') and a Schottky diode with the drift layer (52), and in direct electrical contact with the drift layer (52) laterally of the implantation region (59'); and a second electrical terminal (57) on the backside of the substrate; 17. The device of claim 16, comprising:

21. The electronic device (90) a P-type first body region (25) on the front side (22a) of the solid body (22) containing the implanted region (34); a second body region (25) of P type extending on the front side (22a) of the solid body (22) transversely to the first body region (25); an N-type source region (28) within the second body region (25); a second carbon-rich electrical contact region (92) within the source region (28); 20. The device of any one of claims 14 to 19, which is a MOSFET having

22. 22. The device of claim 21, wherein the second carbon-rich electrical contact region (92) comprises one or more graphene and / or graphite layers in the source region (28).

23. 23. The device of claim 21 or 22, wherein the second carbon-rich electrical contact region (92) forms an ohmic contact having an upper surface coincident with an upper surface of the surface region (28).

24. 24. The device of any one of claims 21 to 23, wherein the electrical contact region (92) has a thickness between 1 nm and 20 nm.

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