Method, semiconductor structure, and vacuum processing system

Abstract

The present disclosure relates to a method (100), semiconductor structure, and vacuum processing system for passivating a semiconductor structure comprising a semiconductor layer and an oxide layer on the semiconductor layer, the method (100) comprising the steps of providing the semiconductor structure in a vacuum chamber (310) (110), maintaining the semiconductor structure in the vacuum chamber (120) through a purification period having a duration of at least 25 seconds, while maintaining the temperature of the semiconductor structure within a purification temperature range ranging from 20°C to 800°C (131), and increasing the total pressure of the vacuum chamber to a maximum total pressure of 1×10 -3 and purifying (130) the oxide layer by maintaining (132) the oxide layer at or below 1000 mbar.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE This disclosure relates to semiconductor technology. In particular, this disclosure relates to passivating semiconductor structures and devices. [Background technology]

[0002] In conventional semiconductor devices, semiconductor surfaces are often passivated by growing an oxide layer on the surface. However, many methods for forming oxides result in oxide layers with significant defect densities. This inevitably results in the presence of defects in the passivated semiconductor surface, which degrades the performance of conventional semiconductor devices. Furthermore, conventional oxide formation methods can require relatively high processing temperatures, which can degrade the properties of the semiconductor substrate and / or structures formed thereon. In light of these challenges, it is desirable to develop new solutions for passivating semiconductor structures and devices. Summary of the Invention

[0003] This summary is provided to introduce some concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

[0004] According to a first aspect, there is provided a method for passivating a semiconductor structure comprising a semiconductor layer and an oxide layer on the semiconductor layer, the method comprising providing the semiconductor structure in a vacuum chamber and subjecting the semiconductor structure to a vacuum treatment for a duration (t) of at least 25 seconds (s). RP ), while maintaining the semiconductor structure in a vacuum chamber through a purification period (RP) having a temperature (T) of the semiconductor structure within a purification temperature range (ΔT) ranging from 20 degrees Celsius (°C) to 800°C, and maintaining a total pressure (p tot ) at maximum total pressure

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[0005] According to a second aspect, there is provided a semiconductor structure passivated using a method according to the first aspect.

[0006] It is specifically understood that a semiconductor structure according to the second aspect may be passivated using any method according to the first aspect, and correspondingly, any semiconductor structure according to the second aspect may be passivated using a method according to the first aspect.

[0007] According to a third aspect, there is provided a vacuum processing system, the vacuum processing system comprising a vacuum chamber, a pumping unit for evacuating the vacuum chamber, and a total pressure (p tot a pressure sensor for measuring a pressure difference between the semiconductor layer and the oxide layer on the semiconductor layer, a temperature-controlled sample holder for holding the sample within the vacuum chamber, and a control unit operatively coupled to the pumping unit, the pressure sensor, and the sample holder and configured to receive sample structure data relating to a structure of the sample to be processed by the vacuum processing system and sample position data indicative of a position of the sample to be processed. In response to receiving the sample structure data indicative of a sample having a semiconductor layer and an oxide layer on the semiconductor layer, and the sample position data indicative of the sample being disposed in the sample holder, the control unit is configured to operate the pumping unit, the pressure sensor, and the sample holder to perform a process for purifying the oxide layer in accordance with the process for purifying the oxide layer of the method according to the first aspect.

[0008] It is specifically understood that the vacuum processing system according to the third aspect may be specifically configured to carry out any of the methods according to the first aspect. [Brief explanation of the drawings]

[0009] The present disclosure will be better understood from the following detailed description read in light of the accompanying drawings.

[0010] [Figure 1] A method for passivating a semiconductor structure is presented. [Figure 2] 1 shows a semiconductor structure. [Figure 3] 1 shows a schematic diagram of a vacuum processing system.

[0011] Unless specifically stated to the contrary, any of the foregoing drawings may not be drawn to scale, and any element of the drawing may be drawn in incorrect proportion to other elements of the drawing, in order to emphasize certain structural aspects of the embodiments of the drawing. DETAILED DESCRIPTION OF THE INVENTION

[0012] FIG. 1 illustrates a method 100 for passivating a semiconductor structure comprising a semiconductor layer and an oxide layer on the semiconductor layer, according to an embodiment.

[0013] As used herein, "semiconductor" may refer to a material, such as silicon (Si), that has a conductivity intermediate between that of conductive materials, such as metals, and that of insulating materials, such as many plastics and glasses. Furthermore, a "semiconductor structure" may refer to a structure that may constitute, for example, all or only a portion of a complete and operational semiconductor device, such as a diode, photodiode, solar cell, photodetector, radiation detector, image sensor, light-emitting diode, laser diode, capacitor, transistor, or structural portion, layer, and / or other element of a microprocessor, microcontroller, memory chip, programmable logic device, radio frequency (RF) circuit, or integrated circuit, such as a three-dimensional integrated circuit, or memristor. When forming only a portion of such a component, element, or device, the term "structure" may be considered a structure or building block "for" such component, element, or device. Semiconductor structures generally may comprise non-semiconductor materials, such as conductors and / or insulators, in addition to semiconductor materials.

[0014] In this disclosure, "passivation" may refer to a process that reduces the sensitivity of a device structure to the surrounding environment during use. Passivation may include the formation of one or more protective outer layers, which may or may not be implemented as oxide layers. Additionally or alternatively, passivation may refer to surface passivation, a process that may make the surface of a semiconductor layer more inactive.

[0015] As used herein, a "layer" may refer to a generally sheet-like element disposed on a surface or body. Additionally or alternatively, a layer may refer to one of a series of superimposed, overlaid, or stacked generally sheet-like elements. In general, the extent of a layer may or may not be defined by boundaries between different materials or material compositions. However, a "semiconductor layer" may also refer to a layer formed of a semiconductor material, and an "oxide layer" may also refer to a layer formed of an oxide material.

[0016] In the embodiment of FIG. 1, the method 100 includes a process of providing a semiconductor structure 110 in a vacuum chamber.

[0017] As used herein, a "process" may refer to a series of one or more steps leading to an end result. As such, a process may be a single-step process or a multi-step process. Furthermore, a process may be divisible into multiple sub-processes, which may or may not share common steps. Here, a "step" may refer to the means employed to achieve a predetermined result.

[0018] Throughout this disclosure, "vacuum chamber" may refer to an enclosure configured to withstand evacuation by a vacuum pump. Additionally or alternatively, vacuum chamber may refer to an enclosure suitable for maintaining within said enclosure a low-pressure environment, i.e., a vacuum, resulting from such evacuation.

[0019] Furthermore, "providing" can also mean making available the element or item in question. It may include at least partially forming, producing, or manufacturing the element or component in question. Additionally or alternatively, providing may include making available an off-the-shelf or pre-produced or pre-manufactured element or component. For example, the process of providing a semiconductor structure may or may not include one or more steps employed to form the semiconductor structure.

[0020] 1, the process 110 for providing a semiconductor structure may include a chemical vapor deposition step 111 and / or a thermal oxidation step 112 to form at least a portion of an oxide layer. Generally, a chemical vapor deposition step may allow for the formation of a variety of different combinations of semiconductor and oxide layers, while a thermal oxidation step may result in an oxide layer with a lower defect density. In other embodiments, the process for providing a semiconductor structure may or may not include a chemical vapor deposition step and / or a thermal oxidation step to form at least a portion of the oxide layer of the semiconductor structure.

[0021] 1 embodiment may be performed as, for example, a low-pressure chemical vapor deposition (LPCVD) step or an atomic layer deposition (ALD) step. Generally, an LPCVD step may provide a higher oxide layer deposition rate, while an ALD step may provide a higher thickness uniformity for the oxide layer. In other embodiments, when a process for providing a semiconductor structure includes a chemical vapor deposition step, the chemical vapor deposition step may be performed as any suitable type of chemical vapor deposition step, for example, as an LPCVD step or an ALD step.

[0022] 1 embodiment may be performed as, for example, a dry oxidation step or a wet oxidation step. Generally, a dry oxidation step may produce an oxide layer with a low defect density, while a wet oxidation step may result in a high oxidation rate. In other embodiments, the process for providing a semiconductor structure includes a thermal oxidation step, which may be performed as any suitable type of thermal oxidation step, for example, a dry oxidation step or a wet oxidation step.

[0023] In the embodiment of FIG. 1 , the method 100 further includes refining the oxide layer 130 while holding the semiconductor structure in the vacuum chamber 120 for a refining period (RP) having a duration (tRP) of at least 30 seconds. Generally, a longer tRP can increase the overall change in the oxide layer, e.g., the overall change in crystallinity of the oxide layer, achieved by the method for passivating the semiconductor structure. In other embodiments, the RP can have any suitable tRP, such as at least 25 seconds, or at least 30 seconds, or at least 40 seconds, or at least 1 minute (min), or at least 2 minutes, or at least 5 minutes, or at least 8 minutes, or at least 10 minutes, or at least 12 minutes, or at least 15 minutes, or at least 18 minutes, or at least 20 minutes, or at least 30 minutes, or at least 45 minutes, or at least 60 minutes, such as a tRP of 25 seconds or 40 seconds, or a tRP of 1 minute, or 2 minutes, or 3 minutes.

[0024] In the embodiment of FIG. 1, the process 130 of purifying the oxide layer includes maintaining 131 the temperature (T) of the semiconductor structure throughout the RP within a purification temperature range (ΔT) ranging from 20° C. to 800° C. In the embodiment of FIG. 1, T may be maintained at, for example, about 350° C. In general, T s A high T may steepen the gradient of the oxide layer, e.g., its crystallinity, achievable by a method for passivating a semiconductor structure. sA lower ΔT may enable a method for passivating semiconductor structures in situations where tighter thermal budgets must be maintained. In other embodiments, the process of purifying the oxide layer may include maintaining the T of the semiconductor structure within any suitable ΔT throughout the RP, for example, ΔT s ranges from 50°C to 750°C, or from 80°C to 700°C, or from 100°C to 650°C, or from 130°C to 600°C, or from 160°C to 550°C, or from 180°C to 520°C, or from 200°C to 500°C, or from 220°C to 480°C, or from 240°C to 460°C, or from 260°C to 440°C, or from 280°C to 420°C, or from 300°C to 400°C, or from 320°C to 380°C.

[0025] As used herein, "crystallinity" may refer to the proportion of a crystalline phase in a material. Here, the crystallinity of an oxide layer may refer to a value determined based on X-ray diffraction measurement.

[0026] In the embodiment of FIG. 1, the process 130 of purifying the oxide layer is performed by increasing the total pressure (p tot ) across the RP, 1 × 10 -3 Maximum total pressure in mbar

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[0027] Generally, the T of the semiconductor structure should be maintained within a ΔT ranging from 20°C to 800°C, and a t of at least 25 seconds should be maintained. RP While the semiconductor structure is maintained in the vacuum chamber throughout the RP, tot 1×10 -3 mbar

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[0028] In the embodiment of FIG. 1, the process of purifying the oxide layer 130 may include a process 133 of supplying molecular oxygen (O) into the vacuum chamber 310 during RP. Generally, the process of supplying molecular oxygen into the vacuum chamber may facilitate purification of the oxide layer of the semiconductor structure, especially if the oxide layer is substoichiometric, i.e., oxygen-deficient. In other embodiments, the process of purifying the oxide layer may or may not include a process of supplying O into the vacuum chamber. In other embodiments, the process of purifying the oxide layer of the semiconductor structure may or may not include a process of supplying molecular oxygen into the vacuum chamber.

[0029] In the embodiment of FIG. 1, the process 133 of supplying molecular oxygen involves increasing the oxygen partial pressure (p O2 ) across the RP at 4 × 10 -9 Minimum oxygen partial pressure in mbar

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[0030] In general, the process of purifying an oxide layer may include supplying one or more gases other than O into the vacuum chamber during or throughout RP, in addition to or as an alternative to supplying O. For example, in some embodiments, the process of purifying an oxide layer may include supplying one or more of molecular hydrogen (H), hydrogen peroxide (H0), ammonia (NH), molecular nitrogen (N), nitrogen dioxide (NO), ethanol (CHOH), and a noble gas (e.g., helium (He) or argon (Ar)). In embodiments, the process of purifying an oxide layer may include supplying a gas other than O into the vacuum chamber during or throughout RP, and the process of purifying an oxide layer may include adjusting the partial pressure of the gas to a value greater than or equal to the value disclosed herein.

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[0031] In one embodiment, a method for passivating a semiconductor structure includes processes corresponding to processes 110, 120, 130, 131, 132, 133, and 134 of the method 100 of the embodiment of Figure 1. In other embodiments, a method for passivating a semiconductor structure may include processes corresponding to the forcing processes 110, 120, 130, 131, and 132 of the method 100 of the embodiment of Figure 1.

[0032] In general, the steps of a method of passivating a semiconductor structure performing processes corresponding to any of processes 110, 120, 130, 131, 132, 133, and 134 of the embodiment of method 100 of Figure 1 may be performed in any suitable order. In general, a method of passivating a semiconductor structure may include any number of additional processes or steps not disclosed herein in connection with the embodiment of method 100 of Figure 1.

[0033] The above primarily discusses process and parameter issues of methods for passivating semiconductor structures. In the following, more emphasis will be placed on the structural characteristics of semiconductor structures before and after they have been passivated using a method according to any of the methods disclosed herein. The above statements regarding implementations, definitions, details, and advantages related to process and parameter issues also apply mutatis mutandis to the semiconductor structures discussed below, and vice versa.

[0034] FIG. 2 illustrates a semiconductor structure 200 according to one embodiment.

[0035] The semiconductor structure 200 of the embodiment of FIG. 2 comprises a semiconductor layer 210 and an oxide layer 220 on the semiconductor layer 210 .

[0036] In the embodiment of FIG. 2 , semiconductor structure 200 may include capping layer 230 covering oxide layer 220 such that oxide layer 220 is spaced from the periphery of semiconductor structure 200. Alternatively, oxide layer 220 may extend along periphery 201 of semiconductor structure 200. In general, an oxide layer extending along the periphery of a semiconductor structure can sharpen the gradient of the oxide layer achievable by a method for passivating a semiconductor structure, e.g., sharpen the crystallinity, particularly if the method includes providing molecular oxygen in a vacuum chamber to purify the oxide layer. In other embodiments, the oxide layer may or may not extend along the periphery of the semiconductor structure.

[0037] Throughout this specification, "capping layer" may refer to any layer disposed over an oxide layer of a semiconductor structure such that the oxide layer is spaced from the periphery of the semiconductor structure.

[0038] Furthermore, the "periphery" of an object can refer to the outermost boundary of the object. In practice, such outermost boundary may be considered to extend from the outermost atoms of the object toward the center of the object a nanoscale distance, e.g., at most 20 nanometers (nm), or at most 10 nm, or at most 5 nm, or at most 2 nm.

[0039] Before being subjected to a process for purifying the oxide layer 220, the oxide layer 220 has a first crystallinity.

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[0040] After being subjected to a process for purifying the oxide layer 220, the oxide layer 220 has a second crystallinity.

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[0041] Oxide layer 220 of an embodiment has a thickness (t) measured following a process for purifying the oxide layer and perpendicular to the interface between semiconductor layer 210 and oxide layer 220. In the embodiment of Figure 2, t may be, for example, about 2 nm. In other embodiments, the oxide layer may have any suitable t measured following a process for purifying the oxide layer and perpendicular to the interface between the semiconductor layer and the oxide layer, such as a t of at least 1 nm, or at least 2 nm, or at least 5 nm, or at least 8 nm, or at least 10 nm, or at least 12 nm, or at least 15 nm, or at least 20 nm, or at least 25 nm, or at least 30 nm, or at least 40 nm, or at least 50 nm, or at least 60 nm, or at least 75 nm, or at least 100 nm.

[0042] The semiconductor layer 210 of the embodiment of Figure 2 may have a crystalline structure, for example, a single crystal structure. Generally, a semiconductor layer having a crystalline structure, for example, a polycrystalline or single crystal structure, allows for the formation of an epitaxial oxide on the semiconductor layer and can reduce the defect density between the semiconductor layer and the oxide layer after a process for refining the oxide layer. In other embodiments, the semiconductor layer may have any suitable type of microstructure, for example, a crystalline structure (e.g., a polycrystalline or single crystal structure), a semi-crystalline structure, or an amorphous structure.

[0043] Here, the "crystalline" structure of a material may refer to constituent elements, such as atomic nuclei, of said material forming at least one ordered two- or three-dimensional crystal lattice.

[0044] In the embodiment of Figure 2, semiconductor layer 210 has a first predominant constituent element, and oxide layer 220 is implemented as a layer of oxide of the first predominant constituent element. Such correspondence between the atomic constituent elements of the semiconductor layer and the oxide layer may generally facilitate refinement of the oxide layer, particularly if the semiconductor layer has a crystalline structure. In other embodiments, the oxide layer may or may not be implemented as a layer of oxide of the first predominant constituent element of the semiconductor layer.

[0045] Here, the "major constituent element" of a layer may refer to the repeating structural motif within the layer or the chemical element at the atomic nucleus of the lattice of the material.

[0046] The first major constituent element in the embodiment of Figure 2 may be Si. In other embodiments in which the oxide layer is implemented as an oxide of the first major constituent element of the semiconductor layer, the first major constituent element may be any suitable element, such as Si or germanium (Ge), or gallium (Ga), although the range of suitable elements is not necessarily limited to these examples.

[0047] The semiconductor layer 210 of the embodiment of Figure 2 may have a single predominant constituent element. Thus, the semiconductor layer 210 may have a monoatomic structure. In other embodiments, the semiconductor layer may or may not have a monoatomic structure. In some embodiments, the semiconductor layer may have a multi-atomic structure, for example, a diatomic structure or a triatomic structure.

[0048] 2 may be specifically implemented as a Si layer. In other embodiments, the semiconductor layer may or may not be implemented as a Si layer. In other embodiments, the semiconductor layer may be implemented as any suitable type of semiconductor layer. In some embodiments, the semiconductor layer may be, for example, a Group IV element semiconductor layer (e.g., a Si layer or a Ge layer), or a Group IV compound semiconductor layer (e.g., a silicon carbide (SiC) layer), or a Group V element semiconductor layer (e.g., a tellurium (Te) layer), or a IV-VI compound semiconductor layer (e.g., a lead telluride (PbTe) layer or a tin(IV) sulfide (SnS) layer), or a III-V compound semiconductor layer (e.g., a gallium nitride (GaN) layer or an indium phosphide (InP) layer), or a II-VI compound semiconductor layer (e.g., a cadmium selenide (CdSe) layer), or a I-VII compound semiconductor layer (e.g., a copper sulfide (CuS) layer), or an oxide semiconductor layer (e.g., a titanium dioxide (TiO) layer, a copper(I) oxide (CuO) layer, or a composite oxide layer of a semiconductor), or an alloy semiconductor layer (e.g., a silicon-germanium (Si 1-x Ge x ) layer, indium gallium arsenide (In x Ga 1-x As) layer, gallium indium arsenide antimonide phosphide (Ga 1-x In x As y Sb z P 1-y-z ), as an organic-inorganic hybrid perovskite structure semiconductor layer (e.g., a methylammonium halide (MALH) layer), or as a two-dimensional semiconductor layer (e.g., a graphene layer or a transition metal dichalcogenide (TMDC) layer).

[0049] In the embodiment of FIG. 2, the oxide layer 220 may be implemented as a silicon oxide (SiO x , where "0 < x ≦ 2") layer. In other embodiments, the semiconductor layer may or may not be implemented as such a SiO x layer. In other embodiments, the oxide layer may be implemented as any suitable type of oxide layer. In some embodiments, the oxide layer may be, for example, an electrically insulating oxide layer (e.g., aluminum oxide (Al2O3)) layer, or a semiconductor oxide layer (e.g., TiO2 layer, or Cu2O layer, or a semiconductor composite oxide layer), or an electrically conductive oxide layer (e.g., indium tin oxide (ITO) layer or aluminum-doped zinc oxide (AZO) layer).

[0050] In the embodiment of FIG. 2, the semiconductor structure 200 may be subjected to at least one of a wafer slicing step, a wafer wrapping step, an etching step, a polishing step, a cleaning step, a scribing step, and a dicing step before the process of providing the semiconductor structure in a vacuum chamber. Thus, the semiconductor layer 210 may include a surface 211 damaged by at least one of the wafer slicing step, the wafer wrapping step, the etching step, the polishing step, the cleaning step, the scribing step, and the dicing step. As a result, the surface 211 may be passivated after being damaged by at least one of the aforementioned steps by a method for passivating a semiconductor structure according to any method disclosed herein. In other embodiments, the surface of the semiconductor layer may or may not be passivated by a method for passivating a semiconductor structure according to any method disclosed herein after being damaged by at least one of the wafer slicing step, the wafer wrapping step, the etching step, the polishing step, the cleaning step, the scribing step, and the dicing step.

Example

[0051] Some examples are detailed below.

[0052] In a first example, silicon dioxide (SiO2) layers were grown by atomic layer deposition on unpatterned 4-inch Si sample wafers and corresponding reference wafers.

[0053] The sample wafer was then placed in a cylindrical stainless steel vacuum chamber of an ultra-high vacuum (UHV) system. In this system, the vacuum chamber was connected to a turbomolecular pump with a rotary backing pump, and the oxygen partial pressure (p O2 An all-metal gas regulator was connected to the vacuum chamber to regulate the amount of oxygen in the atmosphere, approximately 1 × 10 -9 A cold cathode pressure gauge suitable for measuring pressures above mbar was also provided.

[0054] Within the vacuum chamber, the sample wafers were mounted in cradles made of an austenitic nickel-chromium superalloy material without plates, bolts, or clams. Once mounted in the cradle, the wafer temperature could be controlled by a heating system comprising a heating element and a temperature regulator / power supply connected to a K-type thermocouple.

[0055] While the sample wafer is held in the vacuum chamber, the total pressure (p tot ) is approximately 5 × 10 -6 Maximum total pressure in mbar

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[0056] During the purification period, reflection high-energy electron diffraction (RHEED) measurements were performed to examine the morphology of the SiO2 layer. The RHEED measurements confirmed that the crystallinity of the SiO2 layer increased while the sample wafers were processed in the vacuum chamber.

[0057] After processing the sample wafers in a vacuum chamber, carrier lifetime measurements were performed on both the sample wafers and the reference wafers using a Semilab PV-2000A lifetime scanner tool. The results of the carrier lifetime measurements confirmed that processing the sample wafers in a vacuum chamber increased the average carrier time from 2.12 milliseconds (ms) to 2.90 ms.

[0058] In a second example, a 6 mm × 6 mm Si photodiode sample with alumina-coated black silicon (b-Si) surface texture was diced from a Si wafer after wafer-scale device processing. The dicing step introduced scratches into the sidewalls of the photodiode sample, exposing the sidewalls to the surroundings and forming a native oxide covering the sidewalls.

[0059] The photodiode sample was then placed in a temperature-controlled sample holder in the vacuum chamber of the UHV system. While the photodiode sample wafer was held in the vacuum chamber, the total pressure (p) in the vacuum chamber was maintained at 100 psi throughout the purification period (RP) with a duration of 30 min. tot ) is 2 × 10 -4 Maximum total pressure in mbar

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[0060] The leakage current of the photodiode samples before and after vacuum treatment was measured using an LCR precision measuring instrument under temperature control without irradiation. The leakage current measurement results showed that the vacuum treatment reduced the leakage current of the photodiode samples. This result may indicate that the vacuum treatment reduced the density of defect-induced gap levels near the sidewalls. This effect may also be caused by structural modification of the oxide layer on the sidewalls.

[0061] In the third example, a photodiode sample identical to the photodiode sample in the second example was prepared and placed in a temperature-controlled sample holder in the vacuum chamber of a UHV system. While the photodiode sample wafer was held in the vacuum chamber, it was heated for a duration of 30 minutes (t RP ) throughout the purification period (RP), the total pressure in the vacuum chamber (p tot ) is 1×10 -5 Maximum total pressure in mbar

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[0062] As in the second example, leakage current measurements were performed on the photodiode samples before and after vacuum treatment. The results of the leakage current measurements showed that the vacuum treatment reduced the leakage current in the photodiode samples. This result may indicate that the vacuum treatment reduced the density of defect-induced gap levels near the sidewalls. This effect may also be caused by structural modification of the oxide layer on the sidewalls.

[0063] It will be appreciated that the embodiments of the first and second aspects described above may be used in combination with each other, and some of the embodiments may be combined to form further embodiments of the first or second aspect.

[0064] The foregoing has primarily discussed process and parameter issues of methods for passivating semiconductor structures, as well as structural features of semiconductor structures before and after passivation using such methods. Below, more emphasis is placed on features of vacuum processing systems configured to implement methods according to any of the methods disclosed herein. The implementations, definitions, details, and advantages discussed above in relation to aspects of the methods and semiconductor structures also apply mutatis mutandis to the vacuum processing systems discussed below, and vice versa.

[0065] FIG. 3 shows a schematic diagram of a vacuum processing system 300 according to one embodiment.

[0066] In the embodiment of FIG. 3, a vacuum processing system 300 includes a vacuum chamber 310 .

[0067] In the embodiment of FIG. 3, the vacuum processing system 300 further comprises a pumping unit 320 for evacuating the vacuum chamber 310 .

[0068] Here, "pumping unit" can also refer to the equipment (e.g., vacuum pumps and electronics) and interconnecting elements (e.g., valves, sealing elements, and gas lines) necessary or useful for evacuating a vacuum chamber.

[0069] In the embodiment of FIG. 3, the vacuum processing system 300 controls the total pressure (p tot The apparatus further includes a pressure sensor (330) for measuring the pressure.

[0070] Here, "pressure sensor" may refer to any device for measuring the (static) pressure of a gas in a vacuum chamber. In general, it is considered standard practice for a person skilled in the art to select a commercially available pressure sensor of a suitable type for any given application. For example, in an oxygen-containing environment, a cold cathode manometer measures approximately 1×10 -9 It can generally be used to measure pressures above mbar.

[0071] In the embodiment of FIG. 3, the vacuum processing system 300 further comprises a temperature-controlled sample holder 340 for holding a sample 341 within the vacuum chamber 310 .

[0072] Here, "temperature-controlled sample holder" can also refer to a part of a vacuum processing system, when a vacuum processing system is used, that is specifically configured to hold, heat, and optionally cool a sample within the vacuum chamber. Such a sample holder may, for example, include electrical connections for making electrical measurements on the sample within the vacuum chamber, and / or an integrated quartz crystal balance for measuring the mass of the sample, and / or a sample heating element, which may, for example, be based on resistive heating, electron bombardment heating, and / or direct heating of the sample, and / or a sample cooling element, which may, for example, be utilized for cryogenic cooling. In general, the selection of a commercially available sample holder suitable for any given application is considered standard practice for those skilled in the art.

[0073] In the embodiment of Figure 3, vacuum processing system 300 further comprises a control unit 350 operatively coupled to pumping unit 320, pressure sensor 330, and sample holder 340. In Figure 3, such operative couplings are indicated schematically by dotted lines.

[0074] As used herein, a "control unit" may refer to a device (e.g., an electronic device) having at least one specified function related to determining and / or influencing an operating condition, state, or parameter associated with another device, unit, or element. A control unit may or may not form part of a multi-function control system.

[0075] Additionally, a control unit being "operably coupled" to a device, unit, or element may mean that the control unit has at least one specified function related to determining and / or influencing operating conditions, states, or parameters associated with said device, unit, or element.

[0076] The control unit 350 of the embodiment of FIG. 3 is configured to receive sample structure data 351 and sample position data 352 relating to the structure of the sample (341) to be processed by the vacuum processing system (300).

[0077] A control unit "configured" to perform a process may refer to the control unit's ability and suitability for such process. This may be achieved in various ways. For example, a control unit may comprise at least one processor and at least one memory coupled to the at least one processor, the memory storing program code instructions that, when executed on the at least one processor, cause the processor to perform the process in question.

[0078] Additionally or alternatively, the functionally described features of the control unit may be implemented, at least in part, by one or more hardware logic components. For example, without limitation, exemplary types of suitable hardware logic components include field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on a chip (SOCs), complex programmable logic devices (CPLDs), etc. The control unit may generally be operated according to any suitable principles and by any suitable circuits and / or signals known in the art.

[0079] Here, "sample structure data" may refer to any data relating to the structure of a sample to be processed by a vacuum processing system. In some embodiments, the sample structure data may include, for example, a partial or complete fabrication recipe for the sample. In some embodiments, the sample structure data may include recipe data used exclusively for a particular sample type.

[0080] Throughout this specification, "sample position data" may refer to any data that indicates the position of a sample to be processed by a vacuum processing system. In some embodiments, the sample structure data may include, for example, a start signal that indicates that processing of the sample may begin. Such a start signal may be transmitted, for example, in response to automatically sensing that a sample has been placed in the sample holder or in response to a user input.

[0081] 3 embodiment is further configured to perform a process for purifying an oxide layer according to the process for purifying an oxide layer of any method for passivating a semiconductor structure disclosed herein in response to receiving sample structure data 351 indicative of a sample 341 having a semiconductor layer and an oxide layer on the semiconductor layer, and sample position data 352 indicative of the sample being disposed in a sample holder 340. The control unit 350 performs the process by operating the pumping unit 320, the pressure sensor 330, and the sample holder 340. In other embodiments, the control unit may be configured to perform such a process for purifying an oxide layer in response to receiving sample structure data for a sample indicative of a sample having a semiconductor layer and an oxide layer on the semiconductor layer, and optionally also indicative of one or more structural features of a semiconductor structure disclosed herein, and sample position data indicative of the sample being disposed in a sample holder.

[0082] 3 includes a gas inlet 311 having a pressure regulator 312 operably coupled to a control unit 350. In other embodiments, the vacuum chamber may or may not include such a gas inlet with such a pressure regulator.

[0083] Here, a "pressure regulator" of a gas inlet may also refer to a control valve suitable or configured to set, e.g., reduce, the pressure of the gas supplied through the gas inlet to a desired value or within a desired pressure range.

[0084] 3, vacuum processing system 300 includes an oxygen line (313) for supplying O2 into vacuum chamber 310 via gas inlet 311. In other embodiments, the vacuum processing system may or may not include such an oxygen line.

[0085] The process for purifying an oxide layer in the embodiment of FIG. 3 may be according to any process for purifying an oxide layer disclosed herein, including a process for supplying molecular oxygen into a vacuum chamber. If the process for purifying an oxide layer includes a process for supplying molecular oxygen into a vacuum chamber, the control unit (350) may be configured to perform the process for purifying an oxide layer by operating the pumping unit 320, the pressure sensor 330, the sample holder 340, and the pressure regulator 312. In other embodiments, the process for purifying an oxide layer may or may not be according to a process for purifying an oxide layer disclosed herein, including a process for supplying molecular oxygen into a vacuum chamber. In embodiments where the process for purifying an oxide layer includes a process for supplying molecular oxygen into a vacuum chamber, the control unit may be configured to perform the process for purifying an oxide layer by operating the pumping unit, the pressure sensor, the sample holder, and the pressure regulator.

[0086] In general, the process of purifying an oxide layer performed by the control unit may include supplying one or more gases other than O into the vacuum chamber during or throughout RP, in addition to or as an alternative to supplying O. For example, in some embodiments, such a process of purifying an oxide layer may include supplying one or more of molecular hydrogen (H), hydrogen peroxide (H2O2), ammonia (NH3), molecular nitrogen (N2), nitrogen dioxide (NO2), ethanol (C2H5OH), and a noble gas (e.g., helium (He) or argon (Ar)). In embodiments in which the process of purifying an oxide layer performed by the control unit of a vacuum processing system includes supplying a gas other than O to the vacuum chamber during or throughout RP, the vacuum processing system may include any elements necessary to supply the gas (e.g., a gas inlet with a pressure regulator) and a gas line for supplying the gas into the vacuum chamber via the gas inlet. In such embodiments, the control unit may be configured to perform the process of purifying an oxide layer by operating the pumping unit, the pressure sensor, the sample holder, and the pressure regulator.

[0087] In the embodiment of FIG. 3 , the vacuum processing system 300 further includes a user interface unit 360 for transmitting sample structure data 351 and sample position data 352 to the control unit 350 in response to user input. In alternative embodiments, the vacuum processing system may or may not include a user interface unit for transmitting sample structure data and / or sample position data to the control unit in response to user input. The vacuum processing system may generally include any known means, devices, and / or procedures for providing sample structure data and / or sample position data to the control unit. For example, in some embodiments, the sample position data may be automatically transmitted to the control unit in response to detecting a sample in or set on the sample holder. Additionally or alternatively, in some embodiments, the sample structure data may be transmitted to the control unit in response to an automated analysis procedure being performed on a sample placed on the sample holder.

[0088] Here, a "user interface unit" may refer to a unit configured to provide a user interface for operating a vacuum processing system. In general, a user interface unit may include any elements and / or devices necessary or useful for providing such a user interface. A user interface unit may include, for example, an input device (e.g., a button, a switch, a pedal, a keyboard, a mouse, a trackball, or a lever) and / or a display device, which may generally be based on any known display technology. In some embodiments, a user interface unit may include a touch screen that can be used as both an input device and a display device. In some embodiments, a user interface unit may be implemented as software, for example, as a computer program.

[0089] It will also be appreciated that the above-described embodiments of the third aspect may be used in combination with each other. Some embodiments may be combined to form further embodiments.

[0090] It is obvious to those skilled in the art that with the advancement of technology, the basic idea of the present invention can be implemented in various ways. Therefore, the present invention and its embodiments are not limited to the examples described above, but instead may vary within the scope of the claims.

[0091] It will be understood that any benefits and advantages described herein may relate to one embodiment or to multiple embodiments, and embodiments are not limited to embodiments that solve any or all of the stated problems or that have any or all of the stated benefits and advantages.

[0092] In this specification, the term "comprising" is used to mean including the following feature or act without excluding the presence of one or more additional features or acts. It will be further understood that a reference to "an" or "an" item means one or more of those items. [Explanation of symbols]

[0093] RP purification period t RP Duration of the refining period T is the temperature of the semiconductor structure ΔT Purification temperature range p tot Total pressure in the vacuum chamber

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Claims

1. A method (100) for passivating a semiconductor structure (200) comprising a semiconductor layer (210) and an oxide layer (220) on the semiconductor layer (210), comprising: the semiconductor layer is implemented as a silicon layer, a germanium layer, a silicon carbide layer, or a II-VI compound semiconductor layer; a process (110) for providing said semiconductor structure in a vacuum chamber (310); A duration t of at least 25 seconds (s) ＲＰ maintaining (131) a temperature T of the semiconductor structure (200) within a purification temperature range ΔT ranging from 20 degrees Celsius (°C) to 480°C while holding (120) the semiconductor structure in a vacuum chamber through a purification period RP having a total pressure p ｔｏｔ Maximum total pressure [Equation 1] 1 x 10 －３ a process (130) for purifying the oxide layer by maintaining (132) the oxide layer at or below millibar (mbar); A method (100) comprising:

2. The duration t ＲＰ is at least 30 s, or at least 40 s, or at least 1 minute (min), or at least 2 min, or at least 5 min, or at least 8 min, or at least 10 min, or at least 12 min, or at least 15 min, or at least 18 min, or at least 20 min, or at least 30 min, or at least 45 min, or at least 60 min.

3. 3. The method (100) according to claim 1 or 2, wherein the purification temperature range ΔT ranges from 220°C to 480°C, or from 240°C to 460°C, or from 260°C to 440°C, or from 280°C to 420°C, or from 300°C to 400°C, or from 320°C to 380°C.

4. The maximum total pressure [Equation 2] But 5 x 10 －４ mbar, or 1 x 10 －４ mbar, or 5 x 10 －５ mbar, or 1 x 10 －５ mbar, or 5 x 10 －６ mbar, or 2 x 10 －６ The method (100) according to any one of claims 1 to 3, wherein the temperature is 1000 KPa (1000 KJ / s) or 1000 KPa (1000 KJ / s).

5. The process (130) of purifying the oxide layer comprises the step of: ２ The method (100) of any one of claims 1 to 4, comprising the step of providing (133) into the vacuum chamber (310).

6. The process (133) for supplying molecular oxygen is performed by adjusting the partial pressure p of oxygen in the vacuum chamber (310). Ｏ２ During the purification period RP, 4 × 10 －９ mbar, or 9 x 10 －９ mbar, or 4 x 10 －８ mbar, or 9 x 10 －８ mbar, or 4 x 10 －７ mbar, or 9 x 10 －７ Minimum oxygen partial pressure (mbar) [Equation 3] The method (100) of claim 5, comprising maintaining (134) above.

7. The method (100) according to any one of the preceding claims, wherein the process (110) for providing the semiconductor structure comprises a chemical vapor deposition step (111) for forming at least a part of the oxide layer (220).

8. The method (100) of any one of claims 1 to 7, wherein the oxide layer (220) extends along the periphery (201) of the semiconductor structure (200).

9. Prior to the process of purifying the oxide layer (130), the oxide layer (220) has a first crystallinity of up to 50% by mass (m %), or up to 40 m %, or up to 30 m %, or up to 20 m %, or up to 15 m %, or up to 10 m %, or up to 5 m %, or up to 2 m %, or up to 1 m %. [Equation 4] The method (100) according to any one of claims 1 to 8, comprising:

10. The method (100) of any one of claims 1 to 9, wherein the semiconductor layer (210) has a crystalline structure.

11. The method (100) according to any one of the preceding claims, wherein the semiconductor layer (210) comprises a first main constituent element and the oxide layer (220) is implemented as a layer of oxide of the first main constituent element.

12. 12. The method (100) of claim 11, wherein the first major constituent element is silicon Si.

13. 13. The method (100) of any one of claims 1 to 12, wherein the surface (211) of the semiconductor layer (210) is passivated after being damaged by at least one of a wafer slicing step, a wafer lapping step, an etching step, a polishing step, a cleaning step, a scribing step, and a dicing step.

14. The method (100) of any one of claims 1 to 13, wherein the semiconductor structure (200) forms an operational semiconductor device.

15. A vacuum processing system (300) comprising: a vacuum chamber (310); a pumping unit (320) for evacuating said vacuum chamber (310); The total pressure p in the vacuum chamber (310) ｔｏｔ a pressure sensor (330) for measuring a temperature-controlled sample holder (340) for holding a sample (341) within said vacuum chamber (310); a control unit (350) operatively coupled to the pumping unit (320), the pressure sensor (330), and the sample holder (340), configured to receive sample structure data (351) relating to the structure of a sample (341) to be processed by the vacuum processing system (300) and sample position data (352) indicating the position of the sample (341) to be processed; Equipped with 15. A vacuum processing system (300) configured to, in response to receiving sample structure data (351) indicative of a sample (341) having a semiconductor layer (210) implemented as a silicon layer, a germanium layer, a silicon carbide layer, or a II-VI compound semiconductor layer and an oxide layer (220) on the semiconductor layer (210), and sample position data (352) indicative of the sample (341) being disposed in the sample holder (340), operate the pumping unit (320), the pressure sensor (330), and the sample holder (340) to perform a process for purifying the oxide layer in accordance with the process (130) for purifying the oxide layer of any one of claims 1 to 14.

16. The vacuum chamber (310) includes a gas inlet (311) having a pressure regulator (312) operably coupled to the control unit (350), and the vacuum processing system (300) supplies molecular oxygen O 2 into the vacuum chamber (310) through the gas inlet (311). ２ and an oxygen line (313) for supplying oxygen to the vacuum processing system (300), wherein the process of purifying the oxide layer is in accordance with the process of purifying the oxide layer (220) of claim 5 or 6, and the control unit (350) is configured to operate the pumping unit (320), the pressure sensor (330), the sample holder (340), and the pressure regulator (312) to perform the process of purifying the oxide layer.

17. 17. The vacuum processing system (300) of claim 15 or 16, comprising a user interface unit (360) for transmitting sample structure data (351) and / or sample position data (352) to the control unit (350) in response to a user input.

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