Chip, chip manufacturing method, radio frequency power amplifier, and terminal

Abstract

The embodiments of the present application provide a chip, a chip manufacturing method, a radio frequency power amplifier, and a terminal, which relate to the field of semiconductor technology, and ensure that an epitaxial layer is in sufficient contact with a source conductive layer. The chip includes a first transistor and a second transistor, and the method includes forming an epitaxial layer (11) and a source conductive layer (21) stacked in sequence on a substrate (10) to form a first epitaxial layer (101) of the first transistor and a second epitaxial layer (102) of the second transistor, the epitaxial layer includes a first via, the source conductive layer includes a first source (211) of the first transistor and a second source (212) of the second transistor, and the first source (211) an edge of the second source (212) is flush with an edge of the first epitaxial layer (101) close to the first via, an edge of the second source (212) is flush with an edge of the second epitaxial layer (102) close to the first via, forming a first conductive layer (13) in the first via, the first conductive layer (13) contacting the first source (211) and the second source (212) and forming a second via, forming a second conductive layer (14) in the second via, the second conductive layer (14) contacting the first conductive layer (13) and being grounded.

Description

[Technical Field]

[0001] This application relates to the field of semiconductor technology, and in particular to chips, chip manufacturing methods, radio frequency power amplifiers, and terminals. [Background technology]

[0002] Radio frequency components based on compound semiconductor materials are widely used in base stations, radar, consumer electronics, and other products. Radio frequency components, such as transistors, typically include a source, a gate, and a drain. The source may be connected to ground via a conductive wire bond.

[0003] However, the conductive wire has parasitic inductance, and the source of the transistor is electrically connected to the conductive wire, which increases the parasitic inductance of the source and reduces the gain of the transistor.

[0004] Therefore, the source of a transistor is usually grounded directly through a back hole in the substrate instead of being grounded through a conductive wire bond. This can reduce parasitic parameters and improve the performance of the transistor. However, since the back hole in the substrate is usually designed directly under the source metal, a design that introduces a back hole in the substrate inevitably increases the width of the source metal. This increases the area of the transistor chip and increases the cost of the radio frequency component. Summary of the Invention

[0005] In order to solve the above-mentioned technical problems, this application provides a chip, a chip manufacturing method, a radio frequency power amplifier, and a terminal, for avoiding the case where the source conductive layer is inaccurately etched, resulting in the epitaxial layer being unable to make sufficient contact with the source conductive layer when the layout area of the chip is reduced.

[0006] According to a first aspect, the present application provides a chip manufacturing method, the chip including a first transistor and a second transistor, the chip manufacturing method including first forming an epitaxial layer and a source conductive layer stacked in order on a substrate to form a first epitaxial layer of the first transistor and a second epitaxial layer of the second transistor, the epitaxial layer including a first via, the source conductive layer including a first source of the first transistor and a second source of the second transistor, the first source being disposed on a side of the first epitaxial layer opposite the substrate, and the second source being disposed on a side of the second epitaxial layer opposite the substrate. an edge of the first source is flush with an edge of the first epitaxial layer close to the first via side, an edge of the second source is flush with an edge of the second epitaxial layer close to the first via side, then forming a first conductive layer, the first conductive layer being filled in the first via and separately contacting the first source and the second source, then forming a second via in the substrate, the second via at least partially overlapping the first via, and then forming a second conductive layer, the second conductive layer being located in the second via, the second conductive layer being in contact with the first conductive layer and being grounded.

[0007] In the solution of this application, an epitaxial layer is formed through a front-side lithography process. Specifically, lithography is performed on the semiconductor film along a direction from the source conductive layer to the semiconductor film. The lithography accuracy of the front-side lithography process can be less than 100 nm, which is much higher than that of the back-side lithography process. Therefore, when the semiconductor film is etched, inaccurate etching of the source conductive layer due to imperfections in the lithography process, which would result in over-etching of the first epitaxial layer and the second epitaxial layer, can be avoided. As a result, it is possible to ensure that the first epitaxial layer is in sufficient contact with the first source, and the second epitaxial layer is in sufficient contact with the second source. When the first transistor is connected, the first epitaxial layer can effectively transmit current to the first source, and the first source discharges current to ground through the first conductive layer and the second conductive layer. When the second transistor is connected, the second epitaxial layer can effectively transmit current to the second source, and the second source discharges the current to ground through the first conductive layer and the second conductive layer. Furthermore, compared with the related art, the transistor in this application does not require the length of the first epitaxial layer protruding from the first source and the length of the second epitaxial layer protruding from the second source. Therefore, the layout area of the first transistor, the second transistor, and ultimately the chip can be reduced.

[0008] In one possible implementation, the process of forming an epitaxial layer and a source conductive layer stacked in sequence on a substrate specifically includes first forming a semiconductor film and a source conductive layer in sequence on a substrate, and then providing a first via in the semiconductor film to obtain an epitaxial layer.

[0009] In this case, the edge of the first source is flush with the edge of the first epitaxial layer closer to the first via, and the edge of the second source is flush with the edge of the second epitaxial layer closer to the first via. Alternatively, for process reasons, there may be a tolerance between the first epitaxial layer and the first source, and there may be a tolerance between the second epitaxial layer and the second source. The surface of the first epitaxial layer opposite the substrate may be flush with the edge of the first source, and the surface of the second epitaxial layer opposite the substrate may be flush with the edge of the second source. However, the surface of the first epitaxial layer facing the substrate may protrude from the edge of the first source, and the surface of the second epitaxial layer facing the substrate may protrude from the edge of the second source.

[0010] In another possible implementation, the process of forming the epitaxial layer and the source conductive layer stacked in order on the substrate specifically includes first forming a semiconductor film on the substrate, then providing a first via in the semiconductor film to obtain the epitaxial layer, and then forming the source conductive layer on the opposite side of the epitaxial layer from the substrate. Since the first source and the second source are formed after the first epitaxial layer and the second epitaxial layer are formed, an etching material for etching the semiconductor film does not affect the patterns of the first source and the second source.

[0011] In this case, the edge of the first source is flush with the edge of the first epitaxial layer closer to the first via, and the edge of the second source is flush with the edge of the second epitaxial layer closer to the first via. Alternatively, a portion of the first source and a portion of the second source may extend further to the first via. Due to process reasons, there may be a tolerance between the actually formed first epitaxial layer and the first source, and there may also be a tolerance between the second epitaxial layer and the second source. The surface of the first epitaxial layer opposite the substrate may be flush with the edge of the first source, and the surface of the second epitaxial layer opposite the substrate may be flush with the edge of the second source. However, the surface of the first epitaxial layer facing the substrate may protrude from the edge of the first source, and the surface of the second epitaxial layer facing the substrate may protrude from the edge of the second source.

[0012] In some possible implementations, in the above-mentioned two implementations, the process of providing a first via in the semiconductor film to obtain an epitaxial layer specifically includes first forming a photoresist on the side of the semiconductor film opposite to the substrate, then exposing the photoresist and developing the photoresist to obtain a photoresist pattern, and then etching the semiconductor film along the direction from the epitaxial layer to the substrate to obtain a first epitaxial layer and a second epitaxial layer.

[0013] In some possible implementations, the semiconductor film can be etched through a front lithography process. The accuracy of the front lithography process is higher than that of the back lithography process, and the alignment accuracy of the front lithography process can be less than 100 nm. Therefore, when the semiconductor film is etched through the front lithography process, a case in which the first source and the second source are inaccurately etched due to imperfections in the lithography process, resulting in over-etching of the first epitaxial layer and the second epitaxial layer, is avoided, thereby ensuring that the first source is in sufficient contact with the first epitaxial layer and the second source is in sufficient contact with the second epitaxial layer.

[0014] In some possible implementations, commonly used chlorine-based gases have an etching effect on the materials of the first epitaxial layer and the second epitaxial layer and the materials of the first source and the second source, but in this application, the semiconductor film is etched through a front lithography process and the alignment precision is very high, so the chlorine-based gas does not contact the first source and the second source and therefore does not affect the source pattern. Based on this, in this application, the semiconductor film can be further etched by using a chlorine-based gas to obtain the first epitaxial layer and the second epitaxial layer.

[0015] In some possible implementations, the step of forming the second via in the substrate specifically includes etching the substrate along a direction from the substrate to the epitaxial layer to obtain the second via.

[0016] In some possible implementations, the first via and the second via are arranged opposite each other, and the edge of the first source facing the second source is flush with the edge of the first epitaxial layer facing the second epitaxial layer. In other words, the edge of the first source is flush with the edge of the first epitaxial layer closer to the first via, and the edge of the second source is flush with the edge of the second epitaxial layer closer to the first via, so that the second conductive layer contacts the first conductive layer. Also, the length of the first via is the same as the length of the second via along the direction from the first source to the second source. In this way, the second conductive layer formed can be in sufficient contact with the first conductive layer.

[0017] In some possible implementations, the first via and the second via are arranged opposite to each other so that the second conductive layer contacts the first conductive layer. In addition, the length of the first via is shorter than the length of the second via along the direction from the first source to the second source. In this way, the second conductive layer formed can be in sufficient contact with the first conductive layer. Furthermore, the length of the first via can be shortened while the length of the second via remains unchanged. This further reduces the layout area occupied by the first transistor and the second transistor.

[0018] In some possible implementations, the first via and the second via are not disposed opposite each other, but the second conductive layer still contacts the first conductive layer. In addition, along the direction from the first source to the second source, the length of the first via is shorter than the length of the second via. Thus, the length of the first via can be shortened while the length of the second via remains unchanged. This further reduces the layout area occupied by the first transistor and the second transistor.

[0019] In some possible implementations, the first via and the second via may or may not be arranged opposite each other, and the second conductive layer contacts the first conductive layer. Additionally, the orthogonal projection of the source conductive layer and the first via onto the substrate is within the range of the second via, and the total length from the edge of the first source opposite the second source to the edge of the second source opposite the first source along the direction from the first source to the second source is shorter than the length of the second via. Thus, the formed second conductive layer can be in sufficient contact with the first conductive layer. Also, a first gate is arranged on the opposite side of the epitaxial layer from the substrate, the first gate being located on the opposite side of the first source from the second source, and the second gate being located on the opposite side of the second source from the first source. The material of the second conductive layer can be a metal material, and the thermal conductivity of the metal material is higher than that of the material of the substrate. Therefore, when the first gate and the second gate generate heat, the heat on the first gate can be conducted to the second conductive layer through the first epitaxial layer, and the heat on the second gate can be conducted to the second conductive layer through the second epitaxial layer, thereby avoiding the performance of the transistor being affected by excessively high temperatures of the first gate and the second gate.

[0020] According to a second aspect, this application provides a chip. The chip can be manufactured by using the method according to the first aspect. The chip includes a substrate and a first transistor and a second transistor disposed on the substrate. The first transistor includes a first epitaxial layer and a first source, which are stacked in order on the substrate. The second transistor includes a second epitaxial layer and a second source, which are stacked in order on the substrate. A first via is provided between the first epitaxial layer and the second epitaxial layer. An edge of the first source is flush with an edge of the first epitaxial layer closer to the first via, and an edge of the second source is flush with an edge of the second epitaxial layer closer to the first via. The chip further includes a first conductive layer, which separately contacts the first source and the second source and is filled in the first via between the first epitaxial layer and the second epitaxial layer. The substrate includes a second via, and the chip further includes a second conductive layer, the second conductive layer filling the second via, the second conductive layer contacting the first conductive layer and being grounded.

[0021] In the solution of this application, a first epitaxial layer and a second epitaxial layer are formed through a front lithography process. Specifically, lithography is performed on the semiconductor film along a direction from the source conductive layer to the semiconductor film. The lithography accuracy of the front lithography process can be less than 100 nm, which is much higher than that of the back lithography process. Therefore, when the semiconductor film is etched, inaccurate etching of the source conductive layer due to imperfections in the lithography process, which would result in over-etching of the epitaxial layer, can be avoided, thereby ensuring that the epitaxial layer is sufficiently in contact with the first source and the second source, respectively. When the first transistor is connected, the first epitaxial layer can effectively transmit current to the first source, and the first source discharges current to ground through the first conductive layer and the second conductive layer. When the second transistor is connected, the second epitaxial layer can effectively transmit current to the second source, and the second source then discharges the current to ground through the first and second conductive layers. Furthermore, compared to the related art, the transistor in this application does not require the length L2 of the epitaxial layer protruding from the source. This reduces the layout area of the first and second transistors, and ultimately the chip.

[0022] In one possible implementation, an edge of the first source is flush with an edge of the first epitaxial layer near the first via, and an edge of the second source is flush with an edge of the second epitaxial layer near the first via. This structure can be implemented through the process of the first aspect. Specifically, the structure can be implemented by first forming a semiconductor film and a source conductive layer on a substrate, in that order, and then providing a first via in the semiconductor film to obtain the epitaxial layer. Alternatively, a semiconductor film can be first formed on a substrate, then providing a first via in the semiconductor film to obtain the epitaxial layer, and then forming a source conductive layer on the opposite side of the epitaxial layer from the substrate.

[0023] In another possible implementation, an edge of the first source facing the second source protrudes from an edge of the first epitaxial layer facing the second epitaxial layer, and an edge of the second source facing the first source protrudes from an edge of the second epitaxial layer facing the first epitaxial layer. In other words, a portion of the first source and a portion of the second source further extend to the first via. This structure can be implemented through the process of the first aspect. Specifically, a semiconductor film can be first formed on a substrate, and then a first via is provided in the semiconductor film to obtain the first epitaxial layer and the second epitaxial layer. Then, the first source is formed on the side of the first epitaxial layer opposite the substrate, and the second source is formed on the side of the second epitaxial layer opposite the substrate.

[0024] Also, for process reasons, there may be tolerances between the first epitaxial layer and the first source that are actually formed, and there may be tolerances between the second epitaxial layer and the second source. The surface of the first epitaxial layer opposite the substrate may be flush with the edge of the first source, and the surface of the second epitaxial layer opposite the substrate may be flush with the edge of the second source. However, the surface of the first epitaxial layer facing the substrate may protrude from the edge of the first source, and the surface of the second epitaxial layer facing the substrate may protrude from the edge of the second source.

[0025] In some possible implementations, the first via and the second via are arranged opposite each other, and the edge of the first source facing the second source is flush with the edge of the first epitaxial layer facing the second epitaxial layer. In other words, the edge of the first source is flush with the edge of the first epitaxial layer closer to the first via, and the edge of the second source is flush with the edge of the second epitaxial layer closer to the first via, so that the second conductive layer contacts the first conductive layer. Also, the length of the first via is the same as the length of the second via along the direction from the first source to the second source. In this way, the second conductive layer formed can be in sufficient contact with the first conductive layer.

[0026] In some possible implementations, the first via and the second via are arranged opposite to each other so that the second conductive layer contacts the first conductive layer. In addition, the length of the first via is shorter than the length of the second via along the direction from the first source to the second source. In this way, the second conductive layer formed can be in sufficient contact with the first conductive layer. Furthermore, the length of the first via can be shortened while the length of the second via remains unchanged. This further reduces the layout area occupied by the first transistor and the second transistor.

[0027] In some possible implementations, the first via and the second via are not disposed opposite each other, but the second conductive layer still contacts the first conductive layer. In addition, along the direction from the first source to the second source, the length of the first via is shorter than the length of the second via. Thus, the length of the first via can be shortened while the length of the second via remains unchanged. This further reduces the layout area occupied by the first transistor and the second transistor.

[0028] In some possible implementations, the first via and the second via may or may not be arranged opposite each other, and the second conductive layer contacts the first conductive layer. Additionally, the orthogonal projection of the source conductive layer and the first via onto the substrate is within the range of the second via, and the total length from the edge of the first source opposite the second source to the edge of the second source opposite the first source along the direction from the first source to the second source is shorter than the length of the second via. Thus, the formed second conductive layer can be in sufficient contact with the first conductive layer. Also, a first gate is arranged on the opposite side of the epitaxial layer from the substrate, the first gate being located on the opposite side of the first source from the second source, and the second gate being located on the opposite side of the second source from the first source. The material of the second conductive layer can be a metal material, and the thermal conductivity of the metal material is higher than that of the material of the substrate. Therefore, when the first gate and the second gate generate heat, the heat on the first gate can be carried away through the first epitaxial layer to the second conductive layer, and the heat on the second gate can be carried away through the second epitaxial layer to the second conductive layer, thereby avoiding the performance of the transistor being affected by excessively high temperatures of the first gate and the second gate.

[0029] According to a third aspect, the present application provides a radio frequency power amplifier, the radio frequency power amplifier including a radio frequency input terminal, a ground terminal, a voltage terminal, an output terminal, and a chip according to the second aspect, wherein a first gate of a first transistor and a second gate of a second transistor in the chip are coupled to the radio frequency input terminal, a first source of the first transistor and a second source of the second transistor are coupled to the ground terminal, and a first drain of the first transistor and a second drain of the second transistor are coupled to the operating voltage terminal and the output terminal, respectively.

[0030] An implementation of the third aspect corresponds to any of the implementations of the second aspect. For technical effects corresponding to the implementation of the third aspect, please refer to the technical effects corresponding to the second aspect and any one of the implementations of the second aspect. Details will not be described again here.

[0031] According to a fourth aspect, the application provides a terminal, the terminal comprising a transmitter, the radio frequency transmitter comprising a radio frequency power amplifier according to the third aspect.

[0032] An implementation of the fourth aspect corresponds to any of the implementations of the second aspect. For technical effects corresponding to the implementation of the fourth aspect, please refer to the technical effects corresponding to the second aspect and any one of the implementations of the second aspect. Details will not be described again here. [Brief explanation of the drawings]

[0033] [Figure 1] FIG. 2 is a block diagram of a terminal configuration according to an embodiment of the present application. [Figure 2] FIG. 1 is a circuit diagram of a power amplifier according to an embodiment of the present application. [Figure 3a] 1 is a diagram of a transistor structure according to the related art; [Figure 3b] FIG. 3b is a diagram of the structure when the source of the transistor of FIG. 3a is incorrectly etched. [Figure 4a] 1 is a diagram of another transistor structure according to the related art; [Figure 4b] 3b is a diagram of the structure of the transistor of FIG. 3a when an etching error occurs in the substrate and epitaxial layer. [Figure 5] FIG. 2 is a top view of a plurality of transistors according to an embodiment of the present application. [Figure 6] 1 is a schematic flow chart of a transistor fabrication according to one embodiment of the present application. [Figure 7a] 1 is a diagram of a transistor manufacturing process according to one embodiment of the present application. [Figure 7b] 1 is a diagram of a transistor manufacturing process according to one embodiment of the present application. [Figure 7c] 1 is a diagram of a transistor manufacturing process according to one embodiment of the present application. [Figure 7d] 1 is a diagram of a transistor manufacturing process according to one embodiment of the present application. [Figure 7e] 1 is a diagram of a transistor manufacturing process according to one embodiment of the present application. [Figure 7f] 1 is a diagram of a transistor manufacturing process according to one embodiment of the present application. [Figure 7g] 1 is a diagram of a transistor manufacturing process according to one embodiment of the present application. [Figure 7h] 1 is a diagram of a transistor manufacturing process according to one embodiment of the present application. [Figure 7i] 1 is a diagram of a transistor manufacturing process according to one embodiment of the present application. [Figure 7j] 1 is a diagram of a transistor manufacturing process according to one embodiment of the present application. [Figure 7k] 1 is a diagram of a transistor manufacturing process according to one embodiment of the present application. [Figure 7l] 1 is a diagram of a transistor manufacturing process according to one embodiment of the present application. [Figure 7m] 1 is a diagram of a transistor manufacturing process according to one embodiment of the present application. [Figure 7n] 1 is a diagram of a transistor manufacturing process according to one embodiment of the present application. [Figure 7o] 1 is a diagram of a transistor manufacturing process according to one embodiment of the present application. [Figure 8] 1 is a schematic flow chart of another transistor fabrication according to an embodiment of the present application. [Figure 9a] 1 is a diagram of a transistor manufacturing process according to one embodiment of the present application. [Figure 9b] 1 is a diagram of a transistor manufacturing process according to one embodiment of the present application. [Figure 9c] 1 is a diagram of a transistor manufacturing process according to one embodiment of the present application. [Figure 9d] 1 is a diagram of a transistor manufacturing process according to one embodiment of the present application. [Figure 9e] 1 is a diagram of a transistor manufacturing process according to one embodiment of the present application. [Figure 9f] 1 is a diagram of a transistor manufacturing process according to one embodiment of the present application. [Figure 9g] 1 is a diagram of a transistor manufacturing process according to one embodiment of the present application. [Figure 9h] 1 is a diagram of a transistor manufacturing process according to one embodiment of the present application. [Explanation of symbols]

[0034] 101 baseband processing unit; 102 transmitter; 1021 radio frequency signal generating circuit; 1022 power amplifier; 1023 filters; 1024 antennas; 10 boards; 11 epitaxial layer; 101 first epitaxial layer; 102 second epitaxial layer; 111 semiconductor film; 12 source; 13 first conductive layer; 14 second conductive layer; 21 source conductive layer; 211 first source; 212 second source; 22 drain; 221 first drain; 222 second drain; 231 first gate; 232 second gate; 33 third photoresist pattern. DETAILED DESCRIPTION OF THE INVENTION

[0035] Hereinafter, the technical solutions in the embodiments of this application will be clearly and completely described with reference to the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only a part, but not all, of the embodiments of this application. Any other embodiments obtained by those skilled in the art based on the embodiments of this application without creative efforts shall all fall within the protection scope of this application.

[0036] The term "and / or" in this specification simply describes an associative relationship for describing related objects and represents that three relationships may exist. For example, A and / or B may represent three cases: only A exists, both A and B exist, and only B exists.

[0037] In the description and claims of the embodiments of this application, terms such as "first," "second," etc. are intended to distinguish between different objects and do not indicate a particular order of the objects. For example, terms such as "first target object," "second target object," etc. are used to distinguish between different target objects and are not used to describe a particular order of the target objects.

[0038] Additionally, in the embodiments of this application, the terms "exemplary" or "for example" are used to indicate providing an example, instance, or explanation. Any embodiment or design scheme described as an "example" or "for example" in the embodiments of this application should not be described as preferred or having more advantages than other embodiments or design schemes. Rather, the terms "example," "for example," and the like are intended to concretely present the related concept.

[0039] In describing the embodiments of this application, unless otherwise specified, "plurality" means two or more. For example, a plurality of processing units is two or more processing units, and a plurality of systems is two or more systems.

[0040] One embodiment of this application provides a termination such that the parasitic capacitance of the source of the transistor can be reduced, the gain of the transistor can be increased, and the layout area of the transistor can be reduced.

[0041] The specific structure and use of the terminal provided in this embodiment of this application will now be described.

[0042] The terminal 1 may be a base station, a computer, a tablet computer, a personal digital assistant (PDA), an intelligent wearable device, a smart home device, or the like, which is not limited in this embodiment of this application.

[0043] FIG. 1 is a diagram of an application scenario of a terminal 1 according to one embodiment of this application. The terminal 1 can be a base station, which includes a baseband processing unit To 1 101 and a transmitter 102. The transmitter 102 may include a radio frequency signal generating circuit 1021, a power amplifier 1022, a filter 1023, and an antenna 1024.

[0044] The baseband processing unit 101 is configured to generate a baseband digital signal.

[0045] The radio frequency signal generation circuit 1021 is configured to process the baseband digital signal to obtain a radio frequency signal.

[0046] The power amplifier 1022 is configured to perform power amplification on the radio frequency signal.

[0047] The filter 1023 is configured to perform a filtering process on the power amplified radio frequency signal to obtain the signal to be transmitted.

[0048] Antenna 1024 is configured to transmit a signal to be transmitted.

[0049] 2 shows a circuit diagram of the power amplifier 1022. The power amplifier 1022 includes a DC input terminal Vgate, a radio frequency input terminal RF In, a voltage terminal VDD, a transistor, and an output terminal RF Out.

[0050] In the example where the transistor is an N-type transistor and the radio frequency signal is a sine wave, the gate Gate of the transistor receives a DC signal input through the DC input terminal Vgate and a radio frequency signal input through the radio frequency input terminal RF In. When the radio frequency signal is positive, the transistor is connected and the voltage terminal VDD is grounded through the transistor; when the radio frequency signal is negative, the transistor is cut off and the voltage terminal VDD is connected to the output terminal RF Out, and the power-amplified radio frequency signal is output through the output terminal RF Out.

[0051] As proposed in the background art, currently, the source of a transistor is grounded, and this may be done through a conductive wire. However, the conductive wire has parasitic inductance. As a result, the parasitic inductance of the source is increased, and the performance of the transistor is reduced (gain is reduced). Alternatively, the source may be grounded through a backhole in the substrate. However, since it is necessary to reserve space in the chip design for providing the backhole in the substrate, the layout area of the chip increases, and the cost increases.

[0052] 3a, the transistor includes an epitaxial layer 11, a source 12, and a first conductive layer 13 disposed on a substrate 10, and further includes a second conductive layer 14. A via is formed in the substrate 10 and the epitaxial layer 11 through a backside lithography process along a direction from the substrate 10 to the epitaxial layer 11, and the second conductive layer 14 is disposed in the via to contact the first conductive layer 13. Thus, when the transistor is connected, the epitaxial layer 11 transmits a current to the source 12 along a direction from the epitaxial layer 11 to the source 12. Also, the source 12 transmits a current through the first conductive layer 13 to the second conductive layer 14, which is grounded.

[0053] However, in the related art solution, after the source 12 is formed, the substrate and epitaxial layer 11 are patterned through etching using a backside lithography process. As shown in FIG. 3b, the alignment accuracy of the backside lithography process is too low (a contact lithography machine is usually selected for this lithography process), resulting in an alignment error of typically 3 μm or more. When the epitaxial layer 11 is etched, it may be over-etched, resulting in insufficient contact between the epitaxial layer 11 and the source 12. Furthermore, as shown in FIG. 3b, the epitaxial layer 11 is usually etched using a chlorine-based gas, which also has an etching effect on the source 12. Therefore, when the epitaxial layer 11 is etched, the source 12 may also be etched, shortening the length L1 of the source 12. As a result, the epitaxial layer 11 cannot make sufficient contact with the source 12, resulting in an abnormal ohmic contact. If epitaxial layer 11 does not make sufficient contact with source 12 , epitaxial layer 11 may fail to transmit current to source 12 .

[0054] It should be mentioned here that the source 12 is patterned and a high-temperature annealing process is performed on the source 12 before the transistor gate is formed. Therefore, a mutual capacitance can be realized between the source 12 and the epitaxial layer 11 to form an ohmic contact. The first conductive layer 13 is formed after the gate is formed. To avoid the influence of the annealing process on the gate and the problem of controlling the epitaxial layer 11 by the gate, the annealing process is not performed after the first conductive layer 13 is patterned. Therefore, even though the first conductive layer 13 contacts the epitaxial layer 11, a mutual capacitance cannot be realized between the first conductive layer 13 and the epitaxial layer 11 (where an ohmic contact is formed). In other words, the epitaxial layer 11 cannot directly transmit current to the first conductive layer 13.

[0055] As shown in FIG. 4a, to solve the problem of partially damaging the source 12, the related art proposes that the epitaxial layer 11 may protrude from the source 12, where the length of the epitaxial layer 11 protruding from the source 12 is L2. However, doing so increases the layout area of the transistor, especially when multiple transistors are typically connected in parallel on a chip, resulting in a significant increase in chip area. Furthermore, as shown in FIG. 4b, due to poor alignment accuracy in the backside lithography process, there are still cases where the via in the epitaxial layer 11 is formed directly under the source 12. Therefore, there are still cases where the source 12 is etched while the epitaxial layer 11 is being etched.

[0056] Based on the above-mentioned problem, one embodiment of this application provides a chip manufacturing method. As shown in Figure 5, multiple transistors can be arranged on a chip, each transistor including a source 211 / 212 and a drain 22, and the drain 22 can be arranged between the source 211 and the source 212 of two adjacent transistors so that the two adjacent transistors share the same drain 22. The multiple transistors can include a first transistor and a second transistor. The first transistor and the second transistor can be a gallium nitride (GaN)-based high electron mobility transistor (HEMT), a gallium arsenide (GaAs)-based pseudomorphic high electron mobility transistor (PHEMT), or the like.

[0057] In this application, the first epitaxial layer 101 of the first transistor and the second epitaxial layer 102 of the second transistor can be etched by a front lithography process. In other words, the first epitaxial layer 101 of the first transistor and the second epitaxial layer 102 of the second transistor can be etched along the direction from the epitaxial layer 11 to the substrate 10, so as to avoid the influence of etching the first epitaxial layer 101 and the second epitaxial layer 102 on the pattern of the source 12. In addition, the layout area occupied by the first transistor and the second transistor can be further reduced. Specifically, the transistors can be formed in the following two embodiments.

[0058] In one embodiment, as shown in FIG. 6, the process of forming a transistor can be performed through the following steps.

[0059] S110: As shown in FIG. 7a, a semiconductor film 111 and a source conductive layer 21 are sequentially formed on a substrate 10. The source conductive layer 21 includes a first source 211 and a second source 212 spaced apart from each other. In an example where a chip includes a first transistor and a second transistor, the first source 211 can be used as the source 12 of the first transistor, and the second source 212 can be used as the source 12 of the second transistor.

[0060] In some possible implementations, a specific process for forming the semiconductor film 111 and the source conductive layer 21 may include: first, sequentially forming the semiconductor film 111, a first conductive film, and a first photoresist on the substrate 10, then exposing the first photoresist, developing the first photoresist to obtain a first photoresist pattern, etching the first conductive film under the protection of the first photoresist pattern to obtain a pattern of the source conductive layer 21, removing the first photoresist pattern, and then performing a high-temperature annealing treatment on the pattern of the source conductive layer 21 to obtain the source conductive layer 21. Obviously, the source conductive layer 21 may be formed by other methods instead, which is not particularly limited in this embodiment of the present application.

[0061] 7b, when the source conductive layer 21 is formed, a first drain 221 of the first transistor and a second drain 222 of the second transistor may be further formed through the same semiconductor process, thereby omitting the process of additionally forming the first drain 221 and the second drain 222 and saving a mask. The first drain 221 and the second drain 222 are disposed in the same layer as the first source 211 and the second source 212, and the first drain 221 is disposed on the opposite side of the first source 211 from the second source 212, and the second drain 222 is disposed on the opposite side of the second source 212 from the first source 211.

[0062] 7c, after step S110 and before step S120, the transistor manufacturing method may further include forming a first gate 231 of the first transistor and a second gate 232 of the second transistor. Specifically, a specific process for forming the first gate 231 and the second gate 232 includes sequentially forming a gate film and a second photoresist on the side of the semiconductor film 111 opposite the substrate 10, exposing the second photoresist, developing the second photoresist to obtain a second photoresist pattern, etching the gate film under the protection of the second photoresist pattern to obtain the patterns of the first gate 231 and the second gate 232, removing the second photoresist pattern, and performing a high-temperature annealing treatment on the patterns of the first gate 231 and the second gate 232 to obtain the first gate 231 and the second gate 232. Obviously, the process of forming the first gate 231 and the second gate 232 may be performed between step S120 and step S130, but this is not limited to this embodiment of the present application.

[0063] As shown in FIG. 7c, the first gate 231 and the second gate 232 are arranged on the side of the semiconductor film 111 opposite the substrate 10, the first gate 231 is arranged on the side of the first source 211 opposite the second source 212, and the second gate 232 is arranged on the side of the second source 212 opposite the first source 211.

[0064] In some possible implementations, the first source 211 and the second source 212 may have a single layer or may be stacked. The material of the first source 211 and the second source 212 may include at least one of metals, such as titanium (Ti), titanium nitride (TiN), aluminum (Al), nickel (Ni), platinum (Pt), palladium (Pd), chromium (Cr), and gold (Au). The material of the first source 211 and the second source 212 may alternatively include a conductive oxide material, such as indium tin oxide (ITO). Considering that the first source 211 and the second source 212 can be manufactured through the same semiconductor process, the first source 211 and the second source 212 can have the same number of layers, and each layer of the first source 211 and the second source 212 has the same material.

[0065] S120: As shown in FIG. 7d, a first via is provided in the semiconductor film 111 to obtain an epitaxial layer 11 including a first epitaxial layer 101 and a second epitaxial layer 102, and the first via is located between the first epitaxial layer 101 and the second epitaxial layer 102. In addition, a first source 211 is disposed on the opposite side of the first epitaxial layer 101 from the substrate 10, and a second source 212 is disposed on the opposite side of the second epitaxial layer 102 from the substrate 10.

[0066] In some possible implementations, as shown in FIG. 7d, a specific process for providing a first via in the semiconductor film 111 to obtain an epitaxial layer 11 may include forming a third photoresist on the side of the semiconductor film 111 opposite the substrate 10, exposing the third photoresist, developing the third photoresist to obtain a third photoresist pattern 33, and etching the semiconductor film 111 under the protection of the third photoresist pattern 33 to obtain an epitaxial layer 11 including a first epitaxial layer 101, a second epitaxial layer 102, and a first via.

[0067] Based on this, after step S120 and before step S130, the chip manufacturing method may further include stripping the third photoresist pattern 33.

[0068] In one possible implementation, although commonly used chlorine-based gases have an etching effect on the materials of the epitaxial layer 11 and the source 12, in this application, the semiconductor film is etched through a front lithography process, and the alignment precision of the front lithography process is very high, which is much higher than that of the back lithography process, so the chlorine-based gas is not used as the first source. 211 and second source 212 Therefore, when the semiconductor film 111 is etched by using a chlorine-based gas in the lithography method of this application, the first source 211 and second source 212 The first epitaxial layer 101 is then exposed to the first source. 211 The second epitaxial layer 102 does not make sufficient contact with the second source. 212 This will not result in cases where there is insufficient contact with the patient.

[0069] Based on this, in this application, the semiconductor film 111 can be etched along the direction from the source conductive layer 21 to the semiconductor film 111 by using a chlorine-based gas, and the epitaxial layer 11 including the first epitaxial layer 101, the second epitaxial layer 102, and the first via can be obtained. Obviously, the semiconductor film 111 can also be etched using other etching materials, which is not limited in this embodiment of this application.

[0070] It should be mentioned here that, as shown in FIG. 7d, the third photoresist pattern 33 can expose the portion of the semiconductor film 111 where the first via is to be formed, and cover each exposed surface of the source conductive layer 21 and the portion of the semiconductor film 111 other than the portion where the first via is to be formed, thereby avoiding the case where the source conductive layer 21 is inaccurately etched in the process of etching the semiconductor film 111 (especially in the process of etching the semiconductor film 111 by using a chlorine-based gas).

[0071] Based on this, in this application, the epitaxial layer 11 is formed through a front lithography process. Specifically, lithography is performed on the semiconductor film 111 along a direction from the source conductive layer 21 to the semiconductor film 111. The alignment accuracy of the front lithography process can be less than 100 nm, which is much higher than the alignment accuracy of the back lithography process. Therefore, when the semiconductor film 111 is etched, the source conductive layer 21 is not inaccurately etched due to an error in the lithography process, which would result in over-etching of the first epitaxial layer 101 and the second epitaxial layer 102. As a result, it is possible to ensure that the first epitaxial layer 101 is in sufficient contact with the first source 211, and that the second epitaxial layer 102 is in sufficient contact with the second source 212. When the first transistor is connected, the first epitaxial layer 101 can effectively transmit current to the first source 211, through which the current is discharged to ground. When the second transistor is connected, the second epitaxial layer 102 can effectively transmit current to the second source 212, through which the current is discharged to ground.

[0072] In the first and second transistors formed in the above-described steps S110 to S130, the positional relationship between the source conductive layer 21 and the epitaxial layer 11 may have the following several cases.

[0073] 7e, the edge of the first source 211 facing the second source 212 can be flush with the edge of the first via close to the first source 211, and the edge of the second source 212 facing the first source 211 can be flush with the edge of the first via close to the second source 212. In other words, the edge of the first source 211 is flush with the edge of the first epitaxial layer 101 close to the first via side, and the edge of the second source 212 is flush with the edge of the second epitaxial layer 102 close to the first via side. Also, along the direction from the first source 211 to the second source 212, the length L1′ of the first source 211 and the length L1″ of the second source 212 are both equal to the length L1 of the source 12 in the related art shown in FIG. 4a. However, in the solution of the present application, the first epitaxial layer 101 does not need to protrude from the first source 211 along the direction from the first source 211 to the second source 212, and the second epitaxial layer 102 does not need to protrude from the second source 212 along the direction from the second source 212 to the first source 211. In other words, the length of the first epitaxial layer 101 protruding from the first source 211 is 0, and the length of the second epitaxial layer 102 protruding from the second source 212 is 0. Therefore, the layout area occupied by the first transistor and the second transistor can be reduced, and the layout area of the entire chip is further reduced.

[0074] For example, along the direction from the first source 211 to the second source 212, the length L1' of the first source 211 and the length L1" of the second source 212 are both 8 μm. In the related art shown in FIG. 4a, the length L2 of the epitaxial layer 11 protruding from the source 12 is 8 μm. Therefore, compared with the related art, in the solution of this application, the layout of the source 12 occupied by one first transistor and one second transistor can be reduced by 2*L2=16 μm, which is a reduction rate of 50%.

[0075] 7f, in the source conductive layer 21 and epitaxial layer 11 formed through the above-mentioned process, the first epitaxial layer 101 protrudes from the first source 211 along the direction from the first source 211 to the second source 211, and the length of the protruding portion is L2', and the second epitaxial layer 102 protrudes from the second source 212 along the direction from the second source 212 to the first source 212, and the length of the protruding portion is L2'. However, in this application, the first epitaxial layer 101 and the second epitaxial layer 102 are formed through a front lithography process, and the alignment accuracy of the front lithography process is much higher than that of the back lithography process. Therefore, in this application, the length L2' of the first epitaxial layer 101 protruding from the first source 211 and the length L2' of the second epitaxial layer 102 protruding from the second source 212 can be much shorter than the length L2 of the epitaxial layer 11 protruding from the source 12 in the related art shown in Figure 4a. Therefore, the layout area occupied by the first transistor and the second transistor can be reduced, and the layout area of the entire chip is further reduced.

[0076] For example, along the direction from the first source 211 to the second source 212, the length L1' of the first source 211 and the length L1" of the second source 212 are both 8 μm. In the related art shown in FIG. 4a, the length L2 of the epitaxial layer 11 protruding from the source 12 is 8 μm. However, in this application, the length L2' of the first epitaxial layer 101 protruding from the first source 211 and the length L2' of the second epitaxial layer 102 protruding from the second source 212 are both 1 μm. Therefore, compared with the related art, in the solution of this application, the layout of the source 12 occupied by one first transistor and one second transistor can be reduced by 2*(L2-L2')=14 μm, which is a reduction rate of 44%.

[0077] Alternatively, for process reasons, there may be a tolerance between the actually formed first epitaxial layer 101 and first source 211, and there may be a tolerance between the actually formed second epitaxial layer 102 and second source 212. Thus, in some possible implementations, as shown in FIG. 7d , the surface of the first epitaxial layer 101 opposite the substrate 10 may be flush with the edge of the first source 211, and the surface of the second epitaxial layer 102 opposite the substrate 10 may be flush with the edge of the second source 212. However, the surface of the first epitaxial layer 101 facing the substrate 10 may protrude from the edge of the first source 211, and the surface of the second epitaxial layer 102 facing the substrate 10 may protrude from the edge of the second source 212.

[0078] In some possible implementations, the first epitaxial layer 101 and the second epitaxial layer 102 may include a multi-layer structure. When the first transistor and the second transistor are GaN-based HEMTs, the material of the multi-layer structure may be Al x Ga y N, where 0≦x≦1, 0≦y≦1, and x+y=1. When the first transistor and the second transistor are GaAs-based PHEMTs, the material of the multi-layer structure may include AlGaAs or high-purity GaAs. Considering that the first epitaxial layer 101 and the second epitaxial layer 102 can be manufactured through the same semiconductor process, the first epitaxial layer 101 and the second epitaxial layer 102 can have the same number of layers, and each layer of the first epitaxial layer 101 and the second epitaxial layer 102 has the same material.

[0079] S130: As shown in Figures 7g-7i, a first conductive layer 13 is formed. The first conductive layer 13 is filled in the first via and contacts the first source 211 and the second source 212 separately.

[0080] In some possible implementations, a specific process for forming the first conductive layer 13 may include first sequentially forming a second conductive film and a fourth photoresist on the side of the source conductive layer 21 opposite the substrate 10, then exposing the fourth photoresist, developing the fourth photoresist to obtain a fourth photoresist pattern, etching the second conductive film under the protection of the fourth photoresist pattern to obtain the first conductive layer 13, and then removing the fourth photoresist pattern. Obviously, the source conductive layer 21 may be formed by other methods instead, which is not particularly limited in this embodiment of the present application.

[0081] In some possible implementations, the specific location where the first conductive layer 13 is disposed is not limited to this embodiment of the present application, as long as the first conductive layer 13 is filled in the first via and separately contacts the first source 211 and the second source 212. Optionally, as shown in FIG. 7g, the first conductive layer 13 is filled in the first via and completely covers the surface of the source conductive layer 21 opposite the substrate 10. Alternatively, as shown in FIG. 7h, the first conductive layer 13 is filled in the first via and disposed on the side of the source conductive layer 21 opposite the substrate 10, partially covering the surface of the source conductive layer 21 opposite the substrate 10. Alternatively, as shown in FIG. 7i, the first conductive layer 13 is only filled in the first via and separately contacts the side of the first source 211 facing the second source 212 and the side of the second source 212 facing the first source 211. Compared with the two solutions shown in Figures 7h and 7i, the solution shown in Figure 7g allows the first source 211 and the second source 212 to be in sufficient contact with the first conductive layer 13, and can avoid cases where the first conductive layer 13 is insufficiently in contact with the first source 211 and / or the second source 212 due to process errors.

[0082] In some possible implementations, the first conductive layer 13 may have one layer or may be a multilayer structure. The material of the first conductive layer 13 may be a metal such as Ti, TiN, Al, Ni, Pt, Pd, Cr, or Au, or a conductive oxide material such as ITO.

[0083] S140: As shown in Figure 7j, a second via is formed in the substrate 10 along a direction from the substrate 10 to the epitaxial layer 11. The second via and the first via are at least partially overlapped.

[0084] In some possible implementations, the substrate 10 can be etched through a backside lithography process to obtain a second via. In this example, the material of the substrate 10 includes silicon carbide (SiC) or silicon (Si). The substrate 10 can be etched using a fluorine-based gas to obtain the second via. Because the fluorine-based gas has high etching selectivity with respect to the material of the epitaxial layer 11, the material of the first conductive layer 13, and the material of the second conductive layer 14 to be formed, the fluorine-based gas can remain on the surface of the second via. This does not affect the formation of the second conductive layer 14 in the subsequent step S150 or the patterns of the formed first epitaxial layer 101, second epitaxial layer 102, and first conductive layer 13, and therefore does not affect the subsequent proper contact between the second conductive layer 14 and the first conductive layer 13.

[0085] In some possible implementations, the specific location of the second via is not limited in this embodiment of the present application, as long as it can be ensured that the second conductive layer 14 filled in the second via can contact the first conductive layer 13. The location of the second via is related to the second conductive layer 14 to be formed. The location of the second via will be described in detail when describing the second conductive layer 14 in step S150.

[0086] S150: As shown in Figures 7k-7o, a second conductive layer 14 is formed in the second via. The second conductive layer 14 is in contact with the first conductive layer 13 and is grounded. In this way, the current transmitted by the first epitaxial layer 101 to the first source 211 and the first conductive layer 13 in sequence, and the current transmitted by the second epitaxial layer 102 to the second source 212 and the first conductive layer 13 in sequence, can be transmitted to the second conductive layer 14 and discharged to ground.

[0087] In some possible implementations, as shown in Figures 7k-7n, the second conductive layer 14 may be formed in the second via through an electroplating process. The thickness of the second conductive layer 14 along the direction from the substrate 10 to the epitaxial layer 11 is smaller than the depth of the second via, and the second conductive layer 14 extends from the sidewall of the second via to the surface of the first conductive layer 13 facing the substrate 10. Alternatively, as shown in Figure 7o, the second conductive layer 14 may fill the entire second via.

[0088] In some possible implementations, the specific location of the second conductive layer 14 relative to the first conductive layer 13 is not limited in this embodiment of the application, as long as the second conductive layer 14 and the first conductive layer 13 can be in contact.

[0089] In the first case, as shown in FIG. 7k, the first via and the second via are arranged opposite to each other, and the edge of the first source 211 facing the second source 212 is flush with the edge of the first epitaxial layer 101 facing the second epitaxial layer 102. In other words, the edge of the first source 211 is flush with the edge of the first epitaxial layer 101 close to the first via, and the edge of the second source 212 is flush with the edge of the second epitaxial layer 102 close to the first via. As a result, the second conductive layer 14 contacts the first conductive layer 13. In addition, the length L3 of the first via is the same as the length L4 of the second via along the direction from the first source 211 to the second source 212. Thus, the second conductive layer 14 can be sufficiently in contact with the first conductive layer 13.

[0090] In the second case, as shown in FIG. 7l, the first via and the second via are arranged opposite to each other so that the second conductive layer 14 contacts the first conductive layer 13. In addition, along the direction from the first source 211 to the second source 212, the length L3 of the first via is shorter than the length L4 of the second via. Thus, the second conductive layer 14 to be formed can be in sufficient contact with the first conductive layer 13. Furthermore, the length L3 of the first via can be shortened while the length L4 of the second via remains unchanged. This further reduces the layout area occupied by the first transistor and the second transistor.

[0091] In the third case, as shown in FIG. 7m, the first via and the second via are not disposed opposite to each other, but the second conductive layer 14 still contacts the first conductive layer 13. In addition, along the direction from the first source 211 to the second source 212, the length L3 of the first via is shorter than the length L4 of the second via. Thus, the length L3 of the first via can be shortened while the length L4 of the second via remains unchanged. This further reduces the layout area occupied by the first transistor and the second transistor.

[0092] 7n and 7o, the first via and the second via may or may not be arranged opposite to each other, and the second conductive layer 14 contacts the first conductive layer 13. In addition, the orthogonal projection of the source conductive layer 21 and the first via onto the substrate 10 is within the range of the second via, and the total length L5 from the edge of the first source 211 opposite to the second source 212 along the direction from the first source 211 to the second source 212 to the edge of the second source 212 opposite to the first source 211 is shorter than the length L4 of the second via. Thus, the formed second conductive layer 14 can be in sufficient contact with the first conductive layer 13. 5, 7n, and 7o, a first gate 231 is disposed on the epitaxial layer 11 opposite the substrate 10, the first gate 231 being located on the first source 211 opposite the second source 212, and the second gate 232 being located on the second source 212 opposite the first source 211. The material of the second conductive layer 14 may be a metal material, and the thermal conductivity of the metal material may be higher than the thermal conductivity of the material of the substrate 10. Therefore, when the first gate 231 and the second gate 232 generate heat, the heat on the first gate 231 can be carried away through the first epitaxial layer 101 to the second conductive layer 14, and the heat on the second gate 232 can be carried away through the second epitaxial layer 102 to the second conductive layer 14 (the heat conduction paths are shown by straight lines with arrows in Figures 7n and 7o), thereby preventing the performance of the transistor from being affected by excessively high temperatures of the first gate 231 and the second gate 232.

[0093] For example, as shown in FIG. 7n, the first via and the second via are arranged opposite each other, and along the direction from the first source 211 to the second source 212, the length L' of the first source 211 and the length L" of the second source 212 are both 8 μm, the length L3 of the first via is 8 μm, and the size L4 of the second via is 25 μm. In this case, the orthogonal projections of the source conductive layer 21 and the first via on the substrate 10 are within the range of the second via, and the second via protrudes separately from the first source 211 and the second source 212. In this way, the heat of the gate 23 can be carried away through the second conductive layer 14 filled in the second via.

[0094] In the fourth case, compared to a solution in which the thickness of the second conductive layer 14 is smaller than the depth of the second via and the second conductive layer 14 extends from the sidewall of the second via to the surface of the first conductive layer 13 facing the substrate 10 (Figure 7n), a solution in which the second conductive layer 14 fills the entire second via (Figure 7o) has a better heat conduction effect on the gate 23.

[0095] In the fourth case, the first via and the second via may or may not be arranged opposite to each other. Along the direction from the first source 211 to the second source 212, the length L3 of the first via may be equal to or smaller than the length L4 of the second via.

[0096] Note that the first via and the second via being arranged opposite to each other may be understood as follows, that is, as the center of the first via and the center of the second via overlapping each other.

[0097] Furthermore, all four cases described above are applicable to GaN-based HEMTs. In the case of GaAs-based HEMTs, since the material of the substrate 10 and the materials of the first epitaxial layer 101 and the second epitaxial layer 102 both contain GaAs, the first epitaxial layer 101 and the second epitaxial layer 102 may be inaccurately etched when the substrate 10 is etched through a backside lithography process. Therefore, along the direction from the first source 211 to the second source 212, the size L4 of the second via in the substrate 10 should be less than or equal to the length L3 of the first via.

[0098] In another embodiment, as shown in FIG. 8, the steps of forming the first and second transistors may be performed through the following steps.

[0099] S210: As shown in FIG. 9a, a semiconductor film 111 is formed on a substrate 10.

[0100] S220: As shown in FIG. 9b, a first via is provided in the semiconductor film 111 to obtain an epitaxial layer 11 including a first epitaxial layer 101 and a second epitaxial layer 102.

[0101] In some possible implementations, a specific process for providing the first via in the semiconductor film 111 to obtain the epitaxial layer 11 may include forming a fifth photoresist on the side of the semiconductor film 111 opposite the substrate 10, exposing the fifth photoresist, developing the fifth photoresist to obtain a fifth photoresist pattern, and etching the semiconductor film 111 under the protection of the fifth photoresist pattern to obtain the epitaxial layer 11 including the first epitaxial layer 101, the second epitaxial layer 102, and the first via. Before step S230, the fifth photoresist pattern may further be removed.

[0102] In a possible implementation, the semiconductor film 111 can be etched along the direction from the semiconductor film 111 to the substrate 10 by using a chlorine-based gas, to obtain the first epitaxial layer 101 and the second epitaxial layer 102. Obviously, the semiconductor film 111 can also be etched using other etchants, which is not limited in this embodiment of the present application.

[0103] In some possible implementations, the present application forms the first epitaxial layer 101 and the second epitaxial layer 102 through a front lithography process. Specifically, lithography is performed on the semiconductor film 111 along a direction from the source conductive layer 21 to the semiconductor film 111. The alignment accuracy of the front lithography process can be less than 100 nm, which is much higher than the alignment accuracy of the back lithography process. Therefore, when the semiconductor film 111 is etched, over-etching of the first epitaxial layer 101 and the second epitaxial layer 102 due to imperfections in the lithography process can be avoided. As a result, it is possible to ensure that the first epitaxial layer 101 is in sufficient contact with the first source 211 and that the second epitaxial layer 102 is in sufficient contact with the second source 212. When the first transistor is connected, the first epitaxial layer 101 can effectively transmit current to the first source 211, through which the current is discharged to ground. When the second transistor is connected, the second epitaxial layer 102 can effectively transmit current to the second source 212, through which the current is discharged to ground.

[0104] In some possible implementations, the first epitaxial layer 101 and the second epitaxial layer 102 may include a multi-layer structure. When the first transistor and the second transistor are GaN-based HEMTs, the material of the multi-layer structure may be Al x Ga yN, where 0≦x≦1, 0≦y≦1, and x+y=1. When the first transistor and the second transistor are GaAs-based PHEMTs, the material of the multi-layer structure may include AlGaAs or high-purity GaAs. Considering that the first epitaxial layer 101 and the second epitaxial layer 102 can be manufactured through the same semiconductor process, the first epitaxial layer 101 and the second epitaxial layer 102 can have the same number of layers, and each layer of the first epitaxial layer 101 and the second epitaxial layer 102 has the same material.

[0105] S230: As shown in Figures 9c and 9d, a source conductive layer 21 is formed on the opposite side of the epitaxial layer 11 from the substrate 10. In other words, a first source 211 is formed on the opposite side of the first epitaxial layer 101 from the substrate 10, and a second source 212 is formed on the opposite side of the second epitaxial layer 102 from the substrate 10. Take an example in which the chip includes a first transistor and a second transistor. The first source 211 can be used as the source 12 of the first transistor, and the second source 212 can be used as the source 12 of the second transistor.

[0106] It should be mentioned here that since the first source 211 and the second source 212 are formed after step S220, the etching material for etching the semiconductor film 111 will not affect the patterns of the first source 211 and the second source 212.

[0107] In some possible implementations, a specific process for forming the source conductive layer 21 may include: first, sequentially forming a first conductive film and a first photoresist on the side of the first epitaxial layer 101 opposite to the substrate 10 and the side of the second epitaxial layer 102 opposite to the substrate 10; then exposing the first photoresist, developing the first photoresist to obtain a first photoresist pattern; etching the first conductive film under the protection of the first photoresist pattern to obtain the pattern of the source conductive layer 21; removing the first photoresist pattern; and performing a high-temperature annealing treatment on the pattern of the source conductive layer 21 to obtain the first source 211 and the second source 212. Obviously, the first source 211 and the second source 212 may be formed by other methods instead, which is not particularly limited in this embodiment of the present application.

[0108] Referring to FIG. 7b, in some possible implementations, when the first source 211 and the second source 212 are formed, a first drain 221 of the first transistor and a second drain 222 of the second transistor are further formed through the same semiconductor process, so that the first drain 221 and the second drain 222 are connected to each other. 222 The first drain 221 and the second drain 222 are arranged in the same layer as the first source 211 and the second source 212, the first drain 221 is arranged on the opposite side of the first source 211 to the second source 212, and the second drain 222 is arranged on the opposite side of the second source 212 to the first source 211.

[0109] In some possible implementations, the first source 211 and the second source 212 may have a single layer or may be stacked. The material of the first source 211 and the second source 212 may include at least one of a metal, such as Ti, TiN, Al, Ni, Pt, Pd, Cr, or Au. The material of the first source 211 and the second source 212 may alternatively include a conductive oxide material, such as ITO. Considering that the first source 211 and the second source 212 can be manufactured through the same semiconductor process, the first source 211 and the second source 212 can have the same number of layers, and each layer of the first source 211 and the second source 212 has the same material.

[0110] See FIG. 7c. In some possible implementations, after step S230 and before step S240, the transistor manufacturing method may further include forming a first gate 231 of the first transistor and a second gate 232 of the second transistor. Specifically, a specific process for forming the first gate 231 and the second gate 232 includes sequentially forming a gate film and a second photoresist on the side of the semiconductor film 111 opposite the substrate 10, exposing the second photoresist, developing the second photoresist to obtain a second photoresist pattern, etching the gate film under the protection of the second photoresist pattern to obtain the patterns of the first gate 231 and the second gate 232, removing the second photoresist pattern, and performing a high-temperature annealing treatment on the patterns of the first gate 231 and the second gate 232 to obtain the first gate 231 and the second gate 232.

[0111] In the first and second transistors formed in the above-described steps S210 to S230, the positional relationship between the source conductive layer 21 and the epitaxial layer 11 may have the following several cases.

[0112] See Fig. 7e. The edge of the first source 211 facing the second source 212 can be flush with the edge of the first via close to the first source 211, and the edge of the second source 212 facing the first source 211 can be flush with the edge of the first via close to the second source 212. In other words, the edge of the first source 211 is flush with the edge of the first epitaxial layer 101 close to the first via side, and the edge of the second source 212 is flush with the edge of the second epitaxial layer 102 close to the first via side. Also, along the direction from the first source 211 to the second source 212, the length L1′ of the first source 211 and the length L1″ of the second source 212 are both equal to the length L1 of the source 12 in the related art shown in FIG. 4a. However, in the solution of the present application, the first epitaxial layer 101 does not need to protrude from the first source 211 along the direction from the first source 211 to the second source 212, and the second epitaxial layer 102 does not need to protrude from the second source 212 along the direction from the second source 212 to the first source 211. In other words, the length of the first epitaxial layer 101 protruding from the first source 211 is 0, and the length of the second epitaxial layer 102 protruding from the second source 212 is 0. Therefore, the layout area occupied by the first transistor and the second transistor can be reduced, and the layout area of the entire chip is further reduced.

[0113] For example, along the direction from the first source 211 to the second source 212, the length L1' of the first source 211 and the length L1" of the second source 212 are both 8 μm. In the related art shown in FIG. 4a, the length L2 of the epitaxial layer 11 protruding from the source 12 is 8 μm. Therefore, compared with the related art, in the solution of this application, the layout of the source 12 occupied by one first transistor and one second transistor can be reduced by 2*L2=16 μm, which is a reduction rate of 50%.

[0114] 9d, in the source conductive layer 21 and the epitaxial layer 11 formed through the above-described process, the first source 211 protrudes from the first epitaxial layer 101 along the direction from the first source 211 to the second source 212, and the second source 212 protrudes from the second epitaxial layer 102 along the direction from the second source 212 to the first source 211. In other words, a portion of the first source 211 and a portion of the second source 212 extend further to the first via. Also, in the solution of this application, it is not necessary for the first epitaxial layer 101 to protrude from the first source 211 along the direction from the first source 211 to the second source 212, and it is not necessary for the second epitaxial layer 102 to protrude from the second source 212 along the direction from the second source 212 to the first source 211. In other words, the length of the first epitaxial layer 101 protruding from the first source 211 is 0, and the length of the second epitaxial layer 102 protruding from the second source 212 is 0. Therefore, the layout area occupied by the first transistor and the second transistor can be reduced, and the layout area of the entire chip is further reduced.

[0115] 9e, in the source conductive layer 21 and epitaxial layer 11 formed through the above-mentioned process, the first epitaxial layer 101 protrudes from the first source 211 along the direction from the first source 211 to the second source 211, with the length of the protruding portion being L2', and the second epitaxial layer 102 protrudes from the second source 212 along the direction from the second source 212 to the first source 212, with the length of the protruding portion being L2'. However, in this application, the epitaxial layer 11 is formed through a front lithography process, and the lithography accuracy of the front lithography process is much higher than the alignment accuracy of the back lithography process. Therefore, in this application, the length L2' of the first epitaxial layer 101 protruding from the first source 211 and the length L2' of the second epitaxial layer 102 protruding from the second source 212 can be much shorter than the length L2 of the epitaxial layer 11 protruding from the source 12 in the related art shown in Figure 4a. Therefore, the layout area occupied by the first transistor and the second transistor can be reduced, and the layout area of the entire chip is further reduced.

[0116] For example, along the direction from the first source 211 to the second source 212, the length L1' of the first source 211 and the length L1" of the second source 212 are both 8 μm. In the related art shown in FIG. 4a, the length L2 of the epitaxial layer 11 protruding from the source 12 is 8 μm. However, in this application, the length L2' of the first epitaxial layer 101 protruding from the first source 211 and the length L2' of the second epitaxial layer 102 protruding from the second source 212 are both 1 μm. Therefore, compared with the related art, in the solution of this application, the layout of the source 12 occupied by one first transistor and one second transistor can be reduced by 2*(L2-L2')=14 μm, which is a reduction rate of 44%.

[0117] Alternatively, for process reasons, there may be a tolerance between the actually formed first epitaxial layer 101 and first source 211, and there may be a tolerance between the actually formed second epitaxial layer 102 and second source 212. Thus, in some possible implementations, as shown in FIG. 9c , the surface of the first epitaxial layer 101 opposite the substrate 10 may be flush with the edge of the first source 211, and the surface of the second epitaxial layer 102 opposite the substrate 10 may be flush with the edge of the second source 212. However, the surface of the first epitaxial layer 101 facing the substrate 10 may protrude from the edge of the first source 211, and the surface of the second epitaxial layer 102 facing the substrate 10 may protrude from the edge of the second source 212.

[0118] S240: As shown in Fig. 9f, form a first conductive layer 13. The first conductive layer 13 is filled in the first via and contacts the first source 211 and the second source 212 separately.

[0119] In some possible implementations, a specific process for forming the first conductive layer 13 may include first sequentially forming a second conductive film and a fourth photoresist on the side of the source conductive layer 21 opposite the substrate 10, then exposing the fourth photoresist, developing the fourth photoresist to obtain a fourth photoresist pattern, etching the second conductive film under the protection of the fourth photoresist pattern to obtain the first conductive layer 13, and then removing the fourth photoresist pattern. Obviously, the source conductive layer 21 may be formed by other methods instead, which is not particularly limited in this embodiment of the present application.

[0120] In some possible implementations, the specific location where the first conductive layer 13 is disposed is not limited to this embodiment of the present application, as long as the first conductive layer 13 is filled in the first via and separately contacts the first source 211 and the second source 212. See FIG. 7f. Optionally, the first conductive layer 13 is filled in the first via and completely covers the surface of the source conductive layer 21 opposite the substrate 10. See FIG. 7g. Alternatively, the first conductive layer 13 is filled in the first via and disposed on the side of the source conductive layer 21 opposite the substrate 10, partially covering the surface of the source conductive layer 21 opposite the substrate 10. See FIG. 7h. Alternatively, the first conductive layer 13 is only filled in the first via and separately contacts the side of the first source 211 facing the second source 212 and the side of the second source 212 facing the first source 211. Compared with the two solutions shown in Figures 7g and 7h, the solution shown in Figure 7f allows the first source 211 and the second source 212 to be in sufficient contact with the first conductive layer 13, and can avoid cases where the first conductive layer 13 is insufficiently in contact with the first source 211 and / or the second source 212 due to process errors.

[0121] In some possible implementations, the first conductive layer 13 may have one layer or may be a multilayer structure. The material of the first conductive layer 13 may be a metal such as Ti, TiN, Al, Ni, Pt, Pd, Cr, or Au, or a conductive oxide material such as ITO.

[0122] S250: As shown in Figure 9g, a second via is formed in the substrate 10 along a direction from the substrate 10 to the epitaxial layer 11. The second via and the first via are at least partially overlapped.

[0123] In some possible implementations, the substrate 10 can be etched through a backside lithography process to obtain a second via. In this example, the material of the substrate 10 includes SiC or Si. The substrate 10 can be etched using a fluorine-based gas to obtain the second via. Because the fluorine-based gas has high etching selectivity with respect to the material of the epitaxial layer 11, the material of the first conductive layer 13, and the material of the second conductive layer 14 to be formed, the fluorine-based gas can remain on the surface of the second via. This does not affect the formation of the second conductive layer 14 in the subsequent step S150 or the patterns of the formed first epitaxial layer 101, second epitaxial layer 102, and first conductive layer 13, and therefore does not affect the subsequent proper contact between the second conductive layer 14 and the first conductive layer 13.

[0124] In some possible implementations, the specific location of the second via is not limited in this embodiment of the present application, as long as it can be ensured that the second conductive layer 14 filled in the second via can contact the first conductive layer 13. The location of the second via is related to the second conductive layer 14 to be formed. The location of the second via will be described in detail when describing the second conductive layer 14 in step S150.

[0125] S260: As shown in Fig. 9h, a second conductive layer 14 is formed in the second via. The second conductive layer 14 is in contact with the first conductive layer 13 and is grounded. Thus, the current transmitted by the first epitaxial layer 101 to the first source 211 and the first conductive layer 13 in sequence, and the current transmitted by the second epitaxial layer 102 to the second source 212 and the first conductive layer 13 in sequence, can be transmitted to the second conductive layer 14 and discharged to ground.

[0126] See Figures 7l-7n. In some possible implementations, the second conductive layer 14 can be formed in the second via through an electroplating process. Along the direction from the substrate 10 to the epitaxial layer 11, the thickness of the second conductive layer 14 is smaller than the depth of the second via, and the second conductive layer 14 extends from the sidewall of the second via to the surface of the first conductive layer 13 facing the substrate 10. See Figure 7o. The second conductive layer 14 may also fill the entire second via.

[0127] In some possible implementations, the specific location of the second conductive layer 14 relative to the first conductive layer 13 is not limited in this embodiment of the application, as long as the second conductive layer 14 and the first conductive layer 13 can be in contact.

[0128] See FIG. 7k. In the first case, the first via and the second via are disposed opposite to each other, and the edge of the first source 211 facing the second source 212 is flush with the edge of the first epitaxial layer 101 facing the second epitaxial layer 102. In other words, the edge of the first source 211 is flush with the edge of the first epitaxial layer 101 near the first via side, and the edge of the second source 212 is flush with the edge of the second epitaxial layer 102 near the first via side, so that the second conductive layer 14 contacts the first conductive layer 13. Also, along the direction from the first source 211 to the second source 212, the length L3 of the first via is the same as the length L4 of the second via. Thus, the second conductive layer 14 to be formed can be in sufficient contact with the first conductive layer 13.

[0129] See Figure 7l. In the second case, the first via and the second via are arranged opposite to each other so that the second conductive layer 14 contacts the first conductive layer 13. In addition, along the direction from the first source 211 to the second source 212, the length L3 of the first via is shorter than the length L4 of the second via. Thus, the second conductive layer 14 formed can be in sufficient contact with the first conductive layer 13. Furthermore, the length L3 of the first via can be shortened while the length L4 of the second via remains unchanged. This further reduces the layout area occupied by the first transistor and the second transistor.

[0130] See Figure 7m. In the third case, the first via and the second via are not disposed opposite to each other, but the second conductive layer 14 still contacts the first conductive layer 13. In addition, along the direction from the first source 211 to the second source 212, the length L3 of the first via is shorter than the length L4 of the second via. Thus, the length L3 of the first via can be shortened while the length L4 of the second via remains unchanged. This further reduces the layout area occupied by the first transistor and the second transistor.

[0131] See Figures 7n and 7o. In the fourth case, the first via and the second via may or may not be arranged opposite each other, and the second conductive layer 14 contacts the first conductive layer 13. In addition, the orthogonal projection of the source conductive layer 21 and the first via onto the substrate 10 is within the range of the second via, and the total length L5 from the edge of the first source 211 opposite the second source 212 to the edge of the second source 212 opposite the first source 211 along the direction from the first source 211 to the second source 212 is shorter than the length L4 of the second via. Thus, the formed second conductive layer 14 can be in sufficient contact with the first conductive layer 13. 5, 7n, and 7o, a first gate 231 is disposed on the epitaxial layer 11 opposite the substrate 10, the first gate 231 being located on the first source 211 opposite the second source 212, and the second gate 232 being located on the second source 212 opposite the first source 211. The material of the second conductive layer 14 may be a metal material, and the thermal conductivity of the metal material may be higher than the thermal conductivity of the material of the substrate 10. Therefore, when the first gate 231 and the second gate 232 generate heat, the heat on the first gate 231 can be carried away through the first epitaxial layer 101 to the second conductive layer 14, and the heat on the second gate 232 can be carried away through the second epitaxial layer 102 to the second conductive layer 14 (the heat conduction paths are shown by straight lines with arrows in Figures 7n and 7o), thereby preventing the performance of the transistor from being affected by excessively high temperatures of the first gate 231 and the second gate 232.

[0132] 7n. For example, the first via and the second via are arranged opposite to each other, and along the direction from the first source 211 to the second source 212, the length L' of the first source 211 and the length L" of the second source 212 are both 8 μm, the length L3 of the first via is 8 μm, and the size L4 of the second via is 25 μm. In this case, the orthogonal projections of the source conductive layer 21 and the first via on the substrate 10 are within the range of the second via, and the second via protrudes separately from the first source 211 and the second source 212. In this way, the heat of the gate 23 can be carried away through the second conductive layer 14 filled in the second via.

[0133] In the fourth case, compared to a solution in which the thickness of the second conductive layer 14 is smaller than the depth of the second via and the second conductive layer 14 extends from the sidewall of the second via to the surface of the first conductive layer 13 facing the substrate 10 (Figure 7n), a solution in which the second conductive layer 14 fills the entire second via (Figure 7o) has a better heat conduction effect on the gate 23.

[0134] In the fourth case, the first via and the second via may or may not be arranged opposite to each other. Along the direction from the first source 211 to the second source 212, the length L3 of the first via may be equal to or smaller than the length L4 of the second via.

[0135] Furthermore, all four cases described above are applicable to GaN-based HEMTs. In the case of GaAs-based HEMTs, since the material of the substrate 10 and the materials of the first epitaxial layer 101 and the second epitaxial layer 102 both contain GaAs, the first epitaxial layer 101 and the second epitaxial layer 102 may be inaccurately etched when the substrate 10 is etched through a backside lithography process. Therefore, along the direction from the first source 211 to the second source 212, the size L4 of the second via in the substrate 10 should be less than or equal to the length L3 of the first via.

[0136] In yet another embodiment, an embodiment of the present application further provides a chip. As shown in FIG. 5, the chip includes a substrate 10 and a first transistor and a second transistor disposed on the substrate 10. As shown in FIGS. 7j and 9h, the first transistor includes a first epitaxial layer and a first source 211 disposed in a stacked order, and the second transistor includes a second epitaxial layer and a second source 212 disposed in a stacked order. The first epitaxial layer is disposed between the substrate 10 and the first source 211, and the second epitaxial layer is disposed between the substrate 10 and the second source 212, and a first via is present between the first epitaxial layer 101 and the second epitaxial layer 102. The edge of the first source 211 is flush with the edge of the first epitaxial layer 101 near the first via side, and the edge of the second source 212 is flush with the edge of the second epitaxial layer 102 near the first via side.

[0137] Based on this, the chip may further include a first conductive layer 13 and a second conductive layer 14. The first conductive layer 13 contacts the first source 211 and the second source 212 separately, and is filled in a first via between the first epitaxial layer and the second epitaxial layer. The substrate 10 includes a second via, in which a second conductive layer 14 is filled, and the second conductive layer 14 is connected to the first conductive layer 13. 13 and is grounded.

[0138] It should be mentioned here that the chip can be manufactured by using the chip manufacturing method provided in any of the above-mentioned embodiments.

[0139] In some possible implementations, the first source 211 and the second source 212 may have a single layer or may be stacked. The material of the first source 211 and the second source 212 may include at least one of metals, such as Ti, TiN, Al, Ni, Pt, Pd, Cr, or Au, or may be a conductive oxide material, such as ITO. When the first source 211 and the second source 212 are manufactured using the chip manufacturing method of the above-described embodiment, the first source 211 and the second source 212 may be manufactured through the same semiconductor process. The first source 211 and the second source 212 may have the same number of layers, and each layer of the first source 211 and the second source 212 has the same material.

[0140] In some possible implementations, the first epitaxial layer and the second epitaxial layer are obtained through etching by a front lithography process, which is the same as the first source 211 and the second source 212. However, the alignment accuracy of the front lithography process can be less than 100 nm, which is much higher than the alignment accuracy of the back lithography process. Therefore, when the semiconductor film 111 is etched, the source conductive layer 21 is inaccurately etched due to an error in the lithography process, which results in over-etching of the first epitaxial layer 101 and the second epitaxial layer 102. As a result, it is possible to ensure that the first epitaxial layer 101 is in sufficient contact with the first source 211 and the second epitaxial layer 102 is in sufficient contact with the second source 212. When the first transistor is connected, the first epitaxial layer 101 can effectively transmit current to the first source 211, through which the current is discharged to ground. When the second transistor is connected, the second epitaxial layer 102 can effectively transmit current to the second source 212, through which the current is discharged to ground.

[0141] In the first and second transistors formed by using the above-described method, the positional relationship between the source conductive layer 21 and the epitaxial layer 11 may have the following several cases.

[0142] 7e, the edge of the first source 211 facing the second source 212 can be flush with the edge of the first via close to the first source 211, and the edge of the second source 212 facing the first source 211 can be flush with the edge of the first via close to the second source 212. In other words, the edge of the first source 211 is flush with the edge of the first epitaxial layer 101 close to the first via side, and the edge of the second source 212 is flush with the edge of the second epitaxial layer 102 close to the first via side. Also, along the direction from the first source 211 to the second source 212, the length L1′ of the first source 211 and the length L1″ of the second source 212 are both equal to the length L1 of the source 12 in the related art shown in FIG. 4a. However, in the solution of the present application, the first epitaxial layer 101 does not need to protrude from the first source 211 along the direction from the first source 211 to the second source 212, and the second epitaxial layer 102 does not need to protrude from the second source 212 along the direction from the second source 212 to the first source 211. In other words, the length of the first epitaxial layer 101 protruding from the first source 211 is 0, and the length of the second epitaxial layer 102 protruding from the second source 212 is 0. Therefore, the layout area occupied by the first transistor and the second transistor can be reduced, and the layout area of the entire chip is further reduced.

[0143] For example, along the direction from the first source 211 to the second source 212, the length L1' of the first source 211 and the length L1" of the second source 212 are both 8 μm. In the related art shown in FIG. 4a, the length L2 of the first epitaxial layer 101 protruding from the first source 211 is 8 μm, and the length L2 of the second epitaxial layer 102 protruding from the second source 212 is 8 μm. Therefore, compared with the related art, in the solution of this application, the layout of the source 12 occupied by one first transistor and one second transistor can be reduced by 2*L2=16 μm, which is a reduction rate of 50%.

[0144] Alternatively, as shown in Figure 7f, a source conductive layer 21 is formed through the above-mentioned process. In the first epitaxial layer 101 and the second epitaxial layer 102, the first epitaxial layer 101 protrudes from the first source 211 along the direction from the first source 211 to the second source 211, with the length of the protruding portion being L2', and the second epitaxial layer 102 protrudes from the second source 212 along the direction from the second source 212 to the first source 212, with the length of the protruding portion being L2'. However, in this application, the first epitaxial layer 101 and the second epitaxial layer 102 are formed through a front lithography process, and the alignment accuracy of the front lithography process is much higher than that of the back lithography process. Therefore, in this application, the length L2' of the first epitaxial layer 101 protruding from the first source 211 and the length L2' of the second epitaxial layer 102 protruding from the second source 212 can be much shorter than the length L2 of the epitaxial layer 11 protruding from the source 12 in the related art shown in Figure 4a. Therefore, the layout area occupied by the first transistor and the second transistor can be reduced, and the layout area of the entire chip is further reduced.

[0145] For example, along the direction from the first source 211 to the second source 212, the length L1' of the first source 211 and the length L1" of the second source 212 are both 8 μm. In the related art shown in FIG. 4a, the length L2 of the first epitaxial layer 101 protruding from the first source 211 and the length L2 of the second epitaxial layer 102 protruding from the second source 212 are both 8 μm. However, in this application, the length L2' of the first epitaxial layer 101 protruding from the first source 211 and the length L2' of the second epitaxial layer 102 protruding from the second source 212 are both 1 μm. Therefore, compared with the related art, in the solution of this application, the layout of the source 12 occupied by one first transistor and one second transistor can be reduced by 2*(L2-L2')=14 μm, which is a reduction rate of 44%.

[0146] 9d, in the source conductive layer 21 and epitaxial layer 11 formed through the above-mentioned process, the first source 211 protrudes from the first epitaxial layer 101 along the direction from the first source 211 to the second source 212, and the second source 212 protrudes from the second epitaxial layer 102 along the direction from the second source 212 to the first source 211. Also, in the solution of this application, it is not necessary for the first epitaxial layer 101 to protrude from the first source 211 along the direction from the first source 211 to the second source 212, and it is not necessary for the second epitaxial layer 102 to protrude from the second source 212 along the direction from the second source 212 to the first source 211. In other words, the length of the first epitaxial layer 101 protruding from the first source 211 is 0, and the length of the second epitaxial layer 102 protruding from the second source 212 is 0. Therefore, the layout area occupied by the first transistor and the second transistor can be reduced, and the layout area of the entire chip is further reduced.

[0147] Alternatively, for process reasons, there may be a tolerance between the actually formed first epitaxial layer 101 and first source 211, and there may be a tolerance between the actually formed second epitaxial layer 102 and second source 212. Thus, in some possible implementations, as shown in FIG. 7d , the surface of the first epitaxial layer 101 opposite the substrate 10 may be flush with the edge of the first source 211, and the surface of the second epitaxial layer 102 opposite the substrate 10 may be flush with the edge of the second source 212. However, the surface of the first epitaxial layer 101 facing the substrate 10 may protrude from the edge of the first source 211, and the surface of the second epitaxial layer 102 facing the substrate 10 may protrude from the edge of the second source 212.

[0148] In some possible implementations, the first epitaxial layer 101 and the second epitaxial layer 102 may include a multi-layer structure. When the first transistor and the second transistor are GaN-based HEMTs, the material of the multi-layer structure may be Al x Ga y N, where 0≦x≦1, 0≦y≦1, and x+y=1. When the first transistor and the second transistor are GaAs-based PHEMTs, the material of the multi-layer structure may include AlGaAs or high-purity GaAs. Considering that the first epitaxial layer 101 and the second epitaxial layer 102 can be manufactured through the same semiconductor process, the first epitaxial layer 101 and the second epitaxial layer 102 can have the same number of layers, and each layer of the first epitaxial layer 101 and the second epitaxial layer 102 has the same material.

[0149] In some possible implementations, the specific location where the first conductive layer 13 is disposed is not limited to this embodiment of the present application, as long as the first conductive layer 13 is filled in the first via and separately contacts the first source 211 and the second source 212. Optionally, as shown in FIG. 7g, the first conductive layer 13 is filled in the first via and completely covers the surface of the source conductive layer 21 opposite the substrate 10. Alternatively, as shown in FIG. 7h, the first conductive layer 13 is filled in the first via and disposed on the side of the source conductive layer 21 opposite the substrate 10, partially covering the surface of the source conductive layer 21 opposite the substrate 10. Alternatively, as shown in FIG. 7i, the first conductive layer 13 is only filled in the first via and separately contacts the side of the first source 211 facing the second source 212 and the side of the second source 212 facing the first source 211. Compared with the two solutions shown in Figures 7h and 7i, the solution shown in Figure 7g allows the first source 211 and the second source 212 to be in sufficient contact with the first conductive layer 13, and can avoid cases where the first conductive layer 13 does not contact the first source 211 and / or the second source 212 due to process errors.

[0150] In some possible implementations, the first conductive layer 13 may have one layer or may be a multilayer structure. The material of the first conductive layer 13 may be a metal such as Ti, TiN, Al, Ni, Pt, Pd, Cr, or Au, or a conductive oxide material such as ITO.

[0151] In some possible implementations, the specific location of the second via is not limited in this embodiment of the application, as long as it can be ensured that the second conductive layer 14 filled in the second via can contact the first conductive layer 13.

[0152] In some possible implementations, the specific location of the second conductive layer 14 relative to the first conductive layer 13 is not limited in this embodiment of the application, as long as the second conductive layer 14 and the first conductive layer 13 can be in contact.

[0153] In the first case, as shown in FIG. 7k, the first via and the second via are arranged opposite to each other, and the edge of the first source 211 facing the second source 212 is flush with the edge of the first epitaxial layer 101 facing the second epitaxial layer 102. In other words, the edge of the first source 211 is flush with the edge of the first epitaxial layer 101 close to the first via, and the edge of the second source 212 is flush with the edge of the second epitaxial layer 102 close to the first via. As a result, the second conductive layer 14 contacts the first conductive layer 13. In addition, the length L3 of the first via is the same as the length L4 of the second via along the direction from the first source 211 to the second source 212. Thus, the second conductive layer 14 can be sufficiently in contact with the first conductive layer 13.

[0154] In the second case, as shown in FIG. 7l, the first via and the second via are arranged opposite to each other so that the second conductive layer 14 contacts the first conductive layer 13. In addition, along the direction from the first source 211 to the second source 212, the length L3 of the first via is shorter than the length L4 of the second via. Thus, the second conductive layer 14 to be formed can be in sufficient contact with the first conductive layer 13. Furthermore, the length L3 of the first via can be shortened while the length L4 of the second via remains unchanged. This further reduces the layout area occupied by the first transistor and the second transistor.

[0155] In the third case, as shown in FIG. 7m, the first via and the second via are not disposed opposite to each other, but the second conductive layer 14 still contacts the first conductive layer 13. In addition, along the direction from the first source 211 to the second source 212, the length L3 of the first via is shorter than the length L4 of the second via. Thus, the length L3 of the first via can be shortened while the length L4 of the second via remains unchanged. This further reduces the layout area occupied by the first transistor and the second transistor.

[0156] In the fourth case, Figs. oAs shown in FIG. 5, the first via and the second via may or may not be arranged opposite each other, and the second conductive layer 14 contacts the first conductive layer 13. In addition, the orthogonal projection of the source conductive layer 21 and the first via onto the substrate 10 is within the range of the second via, and the total length L5 from the edge of the first source 211 opposite the second source 212 to the edge of the second source 212 opposite the first source 211 along the direction from the first source 211 to the second source 212 is shorter than the length L4 of the second via. Thus, the second conductive layer 14 to be formed can be in sufficient contact with the first conductive layer 13. Also, as shown in FIGS. 5, 7n, and 7o, a first gate 231 is arranged on the opposite side of the epitaxial layer 11 from the substrate 10, the first gate 231 being located on the opposite side of the first source 211 from the second source 212, and the second gate 232 being located on the opposite side of the second source 212 from the first source 211. The material of the second conductive layer 14 may be a metal material, and the thermal conductivity of the metal material is higher than the thermal conductivity of the material of the substrate 10. Therefore, when the first gate 231 and the second gate 232 generate heat, the heat on the first gate 231 can be carried away to the second conductive layer 14 through the first epitaxial layer 101, and the heat on the second gate 232 can be carried away to the second conductive layer 14 through the second epitaxial layer 102 (the heat conduction paths are shown by straight lines with arrows in Figures 7n and 7o), thereby preventing the performance of the transistor from being affected by excessively high temperatures of the first gate 231 and the second gate 232.

[0157] For example, as shown in FIG. 7n, the first via and the second via are arranged opposite each other, and along the direction from the first source 211 to the second source 212, the length L' of the first source 211 and the length L" of the second source 212 are both 8 μm, the length L3 of the first via is 8 μm, and the size L4 of the second via is 25 μm. In this case, the orthogonal projections of the source conductive layer 21 and the first via on the substrate 10 are within the range of the second via, and the second via protrudes separately from the first source 211 and the second source 212. In this way, the heat of the gate 23 can be carried away through the second conductive layer 14 filled in the second via.

[0158] In the fourth case, compared to a solution in which the thickness of the second conductive layer 14 is smaller than the depth of the second via and the second conductive layer 14 extends from the sidewall of the second via to the surface of the first conductive layer 13 facing the substrate 10 (Figure 7n), a solution in which the second conductive layer 14 fills the entire second via (Figure 7o) has a better heat conduction effect on the gate 23.

[0159] In the fourth case, the first via and the second via may or may not be arranged opposite to each other. Furthermore, along the direction from the first source 211 to the second source 212, the length L3 of the first via may be equal to or smaller than the length L4 of the second via.

[0160] Furthermore, all four cases described above are applicable to GaN-based HEMTs. In the case of GaAs-based HEMTs, since the material of the substrate 10 and the materials of the first epitaxial layer 101 and the second epitaxial layer 102 both contain GaAs, the first epitaxial layer 101 and the second epitaxial layer 102 may be inaccurately etched when the substrate 10 is etched through a backside lithography process. Therefore, along the direction from the first source 211 to the second source 212, the size L4 of the second via in the substrate 10 should be less than or equal to the length L3 of the first via.

[0161] Moreover, the other explanations, descriptions and beneficial effects of this embodiment of this application are the same as those of the above two embodiments, and the details will not be described again here.

[0162] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific implementations described above. The specific implementations described above are merely examples and are not limiting. Taking inspiration from this application, those skilled in the art may make further modifications without departing from the purpose of this application and the scope of protection of the claims, and all such modifications shall fall within the scope of protection of this application.

Claims

1. 1. A method of manufacturing a chip, the chip having a first transistor and a second transistor, the method comprising: forming an epitaxial layer and a source conductive layer stacked in order on a substrate to form a first epitaxial layer of the first transistor and a second epitaxial layer of the second transistor, the epitaxial layer having a first via, the source conductive layer having a first source of the first transistor and a second source of the second transistor, the first source being disposed on a side of the first epitaxial layer opposite to the substrate, the second source being disposed on a side of the second epitaxial layer opposite to the substrate, an edge of the first source being flush with an edge of the first epitaxial layer close to a side of the first via, and an edge of the second source being flush with an edge of the second epitaxial layer close to a side of the first via; forming a first conductive layer, the first conductive layer filling at least the first via and separately contacting the first source and the second source; forming a second via in the substrate, the second via at least partially overlapping the first via; forming a second conductive layer, the second conductive layer being located within the second via, the second conductive layer being in contact with the first conductive layer and being grounded; A chip manufacturing method comprising:

2. forming an epitaxial layer and a source conductive layer disposed in stacked order on a substrate, forming a semiconductor film and the source conductive layer on the substrate in sequence; providing the first via in the semiconductor film to obtain the epitaxial layer; 10. The chip manufacturing method of claim 1, comprising:

3. forming an epitaxial layer and a source conductive layer disposed in stacked order on a substrate, forming a semiconductor film on the substrate; providing the first via in the semiconductor film to obtain the epitaxial layer; forming the source conductive layer on an opposite side of the epitaxial layer from the substrate; 10. The chip manufacturing method of claim 1, comprising:

4. Providing the first via in the semiconductor film to obtain the epitaxial layer includes: forming a photoresist on the semiconductor film opposite the substrate; exposing the photoresist and developing the photoresist to obtain a photoresist pattern; Etching the semiconductor film along a direction from the epitaxial layer to the substrate to obtain the epitaxial layer; 3. The chip manufacturing method of claim 2, comprising:

5. 5. The chip manufacturing method according to claim 4, wherein the alignment accuracy when etching the semiconductor film is less than 100 nm.

6. Etching the semiconductor film to obtain the epitaxial layer includes: Etching the semiconductor film using a chlorine-based gas to obtain the epitaxial layer; 6. The chip manufacturing method of claim 5, comprising:

7. forming a second via in the substrate; Etching the substrate along a direction from the substrate to the epitaxial layer to obtain the second via; 7. The method of claim 1, further comprising:

8. The chip manufacturing method according to claim 1 , wherein a size of the first via is smaller than a size of the second via along a direction from the first source to the second source.

9. an orthogonal projection of the source conductive layer and the first via onto the substrate is within the range of the second via, and a total length from an edge of the first source opposite the second source to an edge of the second source opposite the first source along the direction from the first source to the second source is smaller than the size of the second via; Before forming the second conductive layer, the method for manufacturing a transistor further comprises: forming a first gate of the first transistor and a second gate of the second transistor on the opposite side of the epitaxial layer from the substrate, the first gate being located on the opposite side of the first source from the second source, and the second gate being located on the opposite side of the second source from the first source; 9. The chip manufacturing method of claim 8, comprising:

10. The chip manufacturing method according to claim 1 , wherein a size of the first via is equal to or larger than a size of the second via along a direction from the first source to the second source.

11. The chip manufacturing method of claim 10 , wherein a center of the first via and a center of the second via overlap.

12. A chip having a substrate and a first transistor and a second transistor disposed on the substrate, the first transistor has a first epitaxial layer and a first source stacked in order on the substrate, the second transistor has a second epitaxial layer and a second source stacked in order on the substrate, a first via is provided between the first epitaxial layer and the second epitaxial layer, an edge of the first source is flush with an edge of the first epitaxial layer close to the first via side, and an edge of the second source is flush with an edge of the second epitaxial layer close to the first via side, the chip further has a first conductive layer, the first conductive layer separately contacts the first source and the second source and is filled in the first via, the substrate has a second via, the chip further has a second conductive layer, the second conductive layer is filled in the second via, the second conductive layer is in contact with the first conductive layer and is grounded; Tips.

13. The chip of claim 12 , wherein a size of the first via is smaller than a size of the second via along a direction from the first source to the second source.

14. the first transistor further has a first gate, the second transistor further has a second gate, the first gate being disposed on the first epitaxial layer opposite the substrate and positioned on the first source opposite the second source, the second gate being disposed on the second epitaxial layer opposite the substrate and positioned on the second source opposite the first source; an orthogonal projection of the first source, the first via, and the second source onto the substrate is within the range of the second via, and a total length from an edge of the first source opposite the second source to an edge of the second source opposite the first source along the direction from the first source to the second source is smaller than the size of the second via; The chip of claim 13.

15. The chip of claim 12 , wherein a size of the first via is equal to or greater than a size of the second via along a direction from the first source to the second source.

16. The chip of claim 12 , wherein a center of the first via and a center of the second via overlap.

17. 16. A radio frequency power amplifier having a radio frequency input, a ground, a voltage, an output and a chip according to any one of claims 12 to 15, a first gate and a second gate of the chip are coupled to the radio frequency input terminal, a first source and a second source are coupled to the ground terminal, a first transistor of the chip further has a first drain, and a second transistor of the chip further has a second drain, the first drain and the second drain are coupled to the voltage terminal and the output terminal, respectively; Radio frequency power amplifier.

18. A terminal comprising a transmitter, said transmitter comprising a radio frequency power amplifier according to claim 17.

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