METHOD FOR MANUFACTURING MONITOR WAFER AND METHOD FOR DETECTING ABNORMALITY IN VAPOR PHASE GROWTH EQUIPMENT USING MONITOR WAFER

Abstract

To provide a method for manufacturing a monitor wafer, which can facilitate determination of an abnormality in a gas supply control mechanism for controlling the state of supplying dopant gas to a chamber.SOLUTION: A method for manufacturing a monitor wafer includes: a first growth step of growing a first epitaxial layer to a wafer within a chamber by controlling a source gas channel opening / closing mechanism so as to open a source gas channel; an abnormality confirmation step of maintaining the state of controlling the source gas channel opening / closing mechanism so as to close the source gas channel and controlling a gas supply control mechanism so as to stop the supply of dopant gas to the chamber, for a short period of time; and a second growth step of manufacturing the monitor wafer by controlling the source gas channel opening / closing mechanism so as to open the source gas channel and growing a second epitaxial layer to the wafer within the chamber.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a monitor wafer and a method for determining an abnormality in a vapor phase growth apparatus using a monitor wafer. [Background technology]

[0002] Dopants contained in silicon wafers are impurities necessary for the production of n-type or p-type semiconductors. Generally, the higher the dopant concentration in a silicon wafer, the lower the resistivity of the silicon wafer. As the resistivity of a silicon wafer depends on the dopant concentration, controlling the dopant concentration is essential to ensure that semiconductor devices operate as designed.

[0003] Even if the amount of dopant added during silicon single crystal growth is controlled to control the dopant concentration, dopant may be unintentionally mixed into the silicon wafer due to the surrounding environment during silicon wafer processing, resulting in so-called dopant contamination. As a method for evaluating such dopant contamination, the methods disclosed in Patent Documents 1 and 2, for example, are known.

[0004] In the evaluation method of Patent Document 1, the resistivity of the bulk portion of a silicon wafer is measured by an eddy current method, and the resistivity of the surface layer of the silicon wafer is measured by a surface photovoltage method.The amount of dopant contamination in the silicon wafer is then determined from the difference between the resistivity value of the bulk portion measured by the eddy current method and the resistivity value of the surface layer measured by the surface photovoltage method.

[0005] In the evaluation method of Patent Document 2, a silicon wafer that has been heat-treated in a heat treatment furnace is angle-polished. Then, the resistivity of the angle-polished surface of the silicon wafer is measured by spreading resistivity measurement (SR measurement) to determine the resistivity distribution in the depth direction, thereby detecting the amount of dopant contamination in the silicon wafer.

[0006] Furthermore, although not a method for evaluating dopant contamination, Patent Document 3 discloses a method for evaluating the resistivity of a silicon wafer in which a reverse bias voltage is applied to measure the CV characteristics. In the evaluation method of Patent Document 3, an additional silicon epitaxial layer having a lower resistivity than the silicon wafer to be measured is formed on the main surface of the silicon wafer to be measured. At this time, the thickness of the additional silicon epitaxial layer is set to be thicker than the width of the depletion layer formed at the initial applied voltage and thinner than the width of the depletion layer formed at the final applied voltage. Then, the dopant concentrations of the additional silicon epitaxial layer and the silicon single crystal wafer to be measured are measured, and the resistivity is calculated from the dopant concentration of the silicon wafer to be measured. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-269962 [Patent Document 2] Japanese Patent Application Laid-Open No. 2005-223098 [Patent Document 3] Japanese Patent Application Publication No. 2017-220545 Summary of the Invention [Problem to be solved by the invention]

[0008] In the manufacturing process of epitaxial silicon wafers (hereinafter sometimes referred to as "epi-wafers") used in the manufacture of semiconductor devices, the resistivity of the epi-wafer is adjusted by supplying a dopant gas into a chamber together with a silicon source gas. In this epi-wafer manufacturing process, if dopant flows into the chamber at an unintended time due to, for example, a failure or malfunction of a gas valve, an unintended dopant layer may be formed on the surface of the epi-wafer, causing the resistivity of the epi-wafer to deviate from the designed value. Therefore, in order to determine such a defect, it is conceivable to use the methods disclosed in Patent Documents 1 to 3.

[0009] However, when using the evaluation method of Patent Document 1, two measurement methods (eddy current method and surface photovoltage method) must be used to measure the resistivity of the epitaxial wafer, and the above-mentioned defects cannot be easily determined. Furthermore, when the evaluation method of Patent Document 2 is used, a heat treatment furnace is required for heat treating the epiwafer, and therefore the above-mentioned defects cannot be easily determined. Furthermore, when the evaluation method of Patent Document 3 is used, it is necessary to control the thickness of the additional silicon epitaxial layer, and the above-mentioned defects cannot be easily determined.

[0010] Furthermore, in order to determine the above-mentioned defects, it is conceivable to use the conventionally known CV measurement method, SR measurement method, or SIMS (Secondary Ion Mass Spectrometry) measurement method.

[0011] However, when using the CV measurement method, a depletion layer of a certain thickness is required to measure the dopant concentration in the epitaxial wafer surface layer, making it difficult to measure the dopant concentration, i.e., the resistivity, in the epitaxial wafer surface layer. Furthermore, when using the SR measurement method, the spread range of the measurement current is insufficient to measure the resistivity of the surface layer of the epitaxial wafer, and the resolution in the depth direction is insufficient. Furthermore, when the SIMS measurement method is used, a long measurement time is required.

[0012] The present invention aims to provide a method for manufacturing a monitor wafer that can facilitate abnormality detection of a gas supply control mechanism that controls the supply state of dopant gas to a chamber, and a method for abnormality detection of a vapor phase growth apparatus that uses a monitor wafer. [Means for solving the problem]

[0013] The method for manufacturing a monitor wafer of the present invention is a method for manufacturing a monitor wafer used to determine an abnormality in a vapor phase growth apparatus, the vapor phase growth apparatus comprising a chamber, a source gas flow path, a dopant gas flow path, a growth gas flow path that supplies a source gas flowing in from the source gas flow path and a dopant gas flowing in from the dopant gas flow path to the chamber, a source gas flow path opening / closing mechanism that opens and closes the source gas flow path, and a gas supply control mechanism that controls the supply state of the dopant gas to the chamber, and the method for manufacturing the monitor wafer comprises: a first growth step of growing a first epitaxial layer on a wafer in the chamber by controlling the source gas flow path opening / closing mechanism to open the source gas flow path; an abnormality confirmation step of controlling the source gas flow path opening / closing mechanism to close the source gas flow path and controlling the gas supply control mechanism to stop the supply of the dopant gas to the chamber, and maintaining this state for a predetermined period of time; and a second growth step of manufacturing the monitor wafer by controlling the source gas flow path opening / closing mechanism to open the source gas flow path and growing a second epitaxial layer on the wafer in the chamber.

[0014] In the method for producing a monitor wafer of the present invention, the second growth step preferably includes growing the second epitaxial layer having a resistivity equal to or higher than that of the first epitaxial layer.

[0015] In the method for manufacturing a monitor wafer of the present invention, it is preferable that the vapor phase growth apparatus includes a growth gas exhaust path that exhausts the gas flowing through the growth gas flow path, the gas supply control mechanism includes a supply destination switching mechanism that is provided in the growth gas flow path and switches the gas supply destination between the chamber and the growth gas exhaust path, the first growth step and the second growth step control the supply destination switching mechanism so that the gas supply destination is the chamber, and the abnormality confirmation step controls the supply destination switching mechanism so that the gas supply destination is the growth gas exhaust path.

[0016] In the monitor wafer manufacturing method of the present invention, it is preferable that the gas supply control mechanism includes a dopant gas flow path opening / closing mechanism that opens and closes the dopant gas flow path, and that at least the abnormality confirmation step among the first growth step, the abnormality confirmation step, and the second growth step controls the dopant gas flow path opening / closing mechanism to open the dopant gas flow path.

[0017] In the monitor wafer manufacturing method of the present invention, the predetermined period in the abnormality checking step is preferably 3 seconds or more.

[0018] The method for determining an abnormality in a vapor phase growth apparatus of the present invention includes a monitor wafer manufacturing process for manufacturing a monitor wafer by the above-described manufacturing method, and an abnormality determination process for determining an abnormality in the gas supply control mechanism based on a resistivity profile or a dopant concentration profile in the thickness direction of the monitor wafer.

[0019] In the method for determining an abnormality in a vapor phase growth apparatus of the present invention, it is preferable that the abnormality determination step determines that there is an abnormality in the gas supply control mechanism if there is a resistivity drop portion in the resistivity profile in the thickness direction where the resistivity is locally low, and determines that there is no abnormality in the gas supply control mechanism if there is no resistivity drop portion.

[0020] In the method for determining an abnormality in a vapor phase growth apparatus of the present invention, it is preferable that the portion of decreasing resistivity comprises a first inflection point where the resistivity starts to decrease from a state where the rate of change of resistivity is constant, a second inflection point where the resistivity starts to increase, and a third inflection point where the rate of change of resistivity starts to become constant, and is a portion between the first inflection point and the third inflection point.

[0021] In the method for determining an abnormality in a vapor phase growth apparatus of the present invention, it is preferable that the low-resistivity region corresponding to the portion of reduced resistivity in the monitor wafer is located on the first epitaxial layer side of the second epitaxial layer, and that the second growth step grows the second epitaxial layer having a thickness that exceeds the thickness of the low-resistivity region estimated based on the conditions under which the abnormality confirmation step is performed. [Brief explanation of the drawings]

[0022] [Figure 1] 1 is a schematic diagram showing a general configuration of a vapor phase growth system according to an embodiment. [Figure 2] 1 is a flowchart of a method for manufacturing an epiwafer according to an embodiment. [Figure 3] 1A to 1C are explanatory diagrams of steps in a method for manufacturing an epiwafer according to an embodiment. [Figure 4] 1 is a flowchart of a method for determining an abnormality in a vapor phase growth apparatus according to an embodiment. [Figure 5] 1A to 1C are explanatory diagrams illustrating steps of a method for determining an abnormality in a vapor phase growth apparatus according to an embodiment. [Figure 6] 1A and 1B are diagrams showing resistivity profiles in the thickness direction of a monitor wafer in an embodiment, where (A) shows the resistivity profile when a dopant layer is formed on the surface of the first epilayer, and (B) shows the resistivity profile when a dopant layer is not formed on the surface of the first epilayer. [Figure 7] 1A and 1B are diagrams showing resistivity profiles in the thickness direction of a monitor wafer in Experiment 2 of the embodiment, where (A) shows the resistivity profile of Experimental Example 1, which was manufactured to simulate a case where there is no abnormality in the supply destination switching mechanism, and (B) shows the resistivity profile of Experimental Example 2, which was manufactured to simulate a case where there is an abnormality in the supply destination switching mechanism. DETAILED DESCRIPTION OF THE INVENTION

[0023] [Embodiment] <Configuration of vapor phase growth system> First, the configuration of a vapor phase growth system according to an embodiment of the present invention will be described. FIG. 1 is a schematic diagram showing the general configuration of a vapor phase growth system according to an embodiment.

[0024] The vapor phase growth system 10 shown in FIG. 1 grows an epitaxial layer (hereinafter sometimes referred to as an "epilayer") on a silicon wafer W to manufacture an epiwafer. The vapor phase growth system 10 includes a vapor phase growth apparatus 1, a resistivity profile measuring apparatus 8, and a control apparatus 9.

[0025] The vapor phase growth apparatus 1 includes a chamber 2, a gas supply path 3, a gas exhaust path 4, and a heating unit (not shown). In this embodiment, the gas supply path 3 and the gas exhaust path 4 are formed by the internal space of a pipe, but may also be formed by holes formed in a block-shaped member, for example.

[0026] A silicon wafer W is placed in the chamber 2 so as to be removable.

[0027] The gas supply line 3 supplies the chamber 2 with a growth gas used for growing an epitaxial layer or a purge gas. The gas supply path 3 includes a carrier gas path 31 , a source gas path 32 , a dopant gas path 33 , a purge gas path 34 , and a growth gas path 35 .

[0028] One end of the carrier gas flow path 31 is connected to a hydrogen gas supply unit 51. A carrier gas MFC (Mass Flow Controller) 36A that adjusts the flow rate of the gas flowing through the carrier gas flow path 31 is provided midway along the carrier gas flow path 31.

[0029] One end of the source gas flow path 32 is connected to a source gas supply unit 52. As the silicon-containing source gas supplied from the source gas supply unit 52, for example, trichlorosilane gas (SiHCl3) or dichlorosilane (SiH2Cl2) can be used.

[0030] A source gas flow path opening / closing mechanism 61 that opens and closes the source gas flow path 32 is provided in the source gas flow path 32. The source gas flow path opening / closing mechanism 61 is configured, for example, with a two-way valve. A source gas MFC 36B that adjusts the flow rate of the gas flowing through the source gas flow path 32 is provided at a position in the source gas flow path 32 closer to the source gas supply unit 52 than the source gas flow path opening / closing mechanism 61.

[0031] One end of the dopant gas flow channel 33 is connected to a dopant gas supply unit 53. The dopant gas supplied from the dopant gas supply unit 53 may be, for example, diborane (B2H6) or phosphine (PH3).

[0032] A dopant gas flow path opening / closing mechanism 62 that opens and closes the dopant gas flow path 33 is provided in the dopant gas flow path 33. The dopant gas flow path opening / closing mechanism 62 is configured, for example, by a two-way valve. A dopant gas MFC 36C that adjusts the flow rate of the gas flowing through the dopant gas flow path 33 is provided in a portion of the dopant gas flow path 33 closer to the dopant gas supply unit 53 than the dopant gas flow path opening / closing mechanism 62.

[0033] One end of the purge gas flow path 34 is connected to the carrier gas flow path 31. The other end of the purge gas flow path 34 is connected to a portion of the dopant gas flow path 33 that is closer to the other end than the dopant gas flow path opening and closing mechanism 62.

[0034] A purge gas flow passage opening / closing mechanism 63 that opens and closes the purge gas flow passage 34 is provided midway along the purge gas flow passage 34. The purge gas flow passage opening / closing mechanism 63 is configured by, for example, a two-way valve. A restrictor 36D is provided on the other end side of the purge gas flow passage 34 relative to the purge gas flow passage opening / closing mechanism 63. The hydrogen gas flowing from the hydrogen gas supply unit 51 to the purge gas flow passage 34 via the carrier gas flow passage 31 has its flow rate restricted by the restrictor 36D, and flows into the dopant gas flow passage 33 as a purge gas.

[0035] One end of the growth gas flow path 35 is connected to the other end of the source gas flow path 32 and the other end of the dopant gas flow path 33. The other end of the growth gas flow path 35 is connected to the chamber 2. The other end of the carrier gas flow path 31 is connected to the middle of the growth gas flow path 35. Hydrogen gas flows from the hydrogen gas supply unit 51 into the growth gas flow path 35 via the carrier gas flow path 31 and is supplied into the chamber 2 as a carrier gas.

[0036] A supply destination switching mechanism 64 is provided between a connection portion of the growth gas flow path 35 with the source gas flow path 32 and the dopant gas flow path 33 and a connection portion of the growth gas flow path 35 with the carrier gas flow path 31. The supply destination switching mechanism 64 is configured to switch the supply destination of the gas flowing in from the source gas flow path 32 and the dopant gas flow path 33 to the other end side of the growth gas flow path 35 (hereinafter sometimes referred to as the "gas supply state") or the growth gas exhaust path 37 (hereinafter sometimes referred to as the "gas exhaust state"). The supply destination switching mechanism 64, together with the dopant gas flow path opening / closing mechanism 62, constitutes a gas supply control mechanism 65 provided in the flow path through which the dopant gas flows. The supply destination switching mechanism 64 is configured, for example, by a three-way valve. When the supply destination switching mechanism 64 is set to the gas supply state, the gas flowing into the supply destination switching mechanism 64 is supplied into the chamber 2. On the other hand, when the supply destination switching mechanism 64 is set to the gas stop state, the gas flowing into the supply destination switching mechanism 64 is not supplied to the chamber 2 but is discharged to the outside of the vapor phase growth apparatus 1 via the growth gas discharge path 37. In this embodiment, the gas flowing into the supply destination switching mechanism 64 includes at least the purge gas among the source gas, dopant gas, and purge gas.

[0037] The gas exhaust path 4 is configured to exhaust the gas inside the chamber 2 to the outside of the vapor phase growth apparatus 1. The heating unit heats the inside of the chamber 2 .

[0038] The resistivity profile measuring device 8 measures the resistivity profile in the thickness direction of various wafers and outputs the measurement results to the control device 9. The resistivity profile measuring device 8 measures the resistivity profile by the CV measurement method or the SR measurement method.

[0039] The control device 9 includes an epitaxial wafer production control unit 91, a monitor wafer production control unit 92, and an abnormality determination unit 93.

[0040] The epitaxial wafer manufacturing control unit 91 controls the overall operation of the vapor phase growth apparatus 1 during epitaxial wafer manufacturing. The monitor wafer manufacturing control unit 92 controls the overall operation of the vapor phase growth apparatus 1 during the manufacture of a monitor wafer, which will be described later. The abnormality determination unit 93 determines whether or not there is an abnormality in the supply destination switching mechanism 64 that constitutes the gas supply control mechanism 65, based on the resistivity profile in the thickness direction of the monitor wafer. The monitor wafer manufacturing control unit 92 and the abnormality determination unit 93 constitute an abnormality determination device 90 .

[0041] Here, the abnormality of the supply destination switching mechanism 64 determined by the abnormality determination device 90 will be described. In the vapor phase growth apparatus 1, an abnormality may occur in which dopant gas is supplied into the chamber 2 even though the supply destination switching mechanism 64 is controlled to be set to the gas exhaust state. For example, this may occur when the supply destination switching mechanism 64 does not switch from the gas supply state to the gas exhaust state, or when gas leaks from the supply destination switching mechanism 64 even though the supply destination switching mechanism 64 has switched to the gas exhaust state. Examples of causes of such an abnormality include an initial defect or deterioration over time in the components that make up the supply destination switching mechanism 64 or in the control system of the supply destination switching mechanism 64. When such an abnormality occurs, dopant gas is supplied into the chamber 2, even though it is not necessary to supply the dopant gas into the chamber 2, for example, in the temperature-reducing step S3 described below. As a result, a dopant layer is formed on the silicon wafer, and the resistivity of the epi-wafer deviates from the design value. In order to prevent such a problem from occurring, the abnormality determination device 90 determines whether or not there is an abnormality in the supply destination switching mechanism 64.

[0042] <Vapor growth system operation> <Epiwafer manufacturing method> First, a method for manufacturing an epitaxial wafer will be described. Fig. 2 is a flowchart of the epi-wafer manufacturing method. Fig. 3 and Fig. 5, which will be described later, are diagrams illustrating the steps of the epi-wafer manufacturing method. In Fig. 3, among the lines representing the gas supply path 3 and the gas exhaust path 4, thick lines represent a state in which gas is flowing, and thin lines represent a state in which gas is not flowing.

[0043] As shown in FIG. 2, the method for manufacturing an epi-wafer includes a temperature increasing step S1, a growth step S2, and a temperature decreasing step S3.

[0044] In the temperature-raising step S1, with the silicon wafer W accommodated in the chamber 2, the epi-wafer production control unit 91 controls the source gas flow path opening and closing mechanism 61, the dopant gas flow path opening and closing mechanism 62, and the purge gas flow path opening and closing mechanism 63 to close the source gas flow path 32 and the dopant gas flow path 33 and open the purge gas flow path 34, as shown in Fig. 3. The epi-wafer production control unit 91 also controls the supply destination switching mechanism 64 to set the growth gas flow path 35 to a gas discharge state. Then, the epi-wafer production control unit 91 controls the heating unit to raise the temperature in the chamber 2 to the growth temperature of the epitaxial layer. By such a temperature increasing step S1, the temperature in the chamber 2 is increased to the growth temperature of the epitaxial layer while only the carrier gas is supplied into the chamber 2. The growth temperature of the epitaxial layer is, for example, 1000°C or higher and 1200°C or lower.

[0045] In the growth step S2, the epitaxial wafer manufacturing control unit 91 controls the source gas flow path opening and closing mechanism 61 and the dopant gas flow path opening and closing mechanism 62 to open the source gas flow path 32 and the dopant gas flow path 33 while maintaining the growth temperature inside the chamber 2. The epitaxial wafer manufacturing control unit 91 also controls the supply destination switching mechanism 64 to set the growth gas flow path 35 to a gas supply state. In this growth step S2, a growth gas containing a source gas, a dopant gas, a purge gas, and a carrier gas is newly supplied into the chamber 2, and an epitaxial layer is grown on the surface of the silicon wafer W to produce an epiwafer. In the growth step S2, the dopant gas does not have to be supplied into the chamber 2. In this case, the resistivity of the epitaxial layer becomes higher than when the dopant gas is supplied into the chamber 2.

[0046] In the temperature-lowering step S3, the epitaxial wafer manufacturing control unit 91 controls the source gas flow path opening and closing mechanism 61 and the dopant gas flow path opening and closing mechanism 62 to close the source gas flow path 32 and the dopant gas flow path 33. The epitaxial wafer manufacturing control unit 91 also controls the supply destination switching mechanism 64 to set the growth gas flow path 35 to a gas stop state. The epitaxial wafer manufacturing control unit 91 then controls the heating unit to lower the temperature inside the chamber 2 to a removal temperature at which the epitaxial wafer can be removed from the chamber 2 by a transfer device (not shown). By this temperature decreasing step S3, the temperature inside the chamber 2 is decreased to the removal temperature while only the carrier gas is being supplied into the chamber 2.

[0047] After the temperature lowering step S3 is completed, the epitaxial wafer is removed from the chamber 2.

[0048] <Method for determining abnormality in vapor phase growth apparatus> Next, a method for determining an abnormality in a vapor phase growth apparatus will be described. Note that the same steps as those in the epi-wafer manufacturing method described above are given the same reference numerals, and the description will be simplified. Fig. 4 is a flowchart of a method for determining an abnormality in a vapor phase growth apparatus. Fig. 5 is a process diagram for determining an abnormality in a vapor phase growth apparatus. Fig. 6 shows resistivity profiles in the thickness direction of a monitor wafer, where (A) shows the resistivity profile when a dopant layer is formed on the surface of the first epitaxial layer, and (B) shows the resistivity profile when a dopant layer is not formed on the surface of the first epitaxial layer.

[0049] As shown in FIG. 4, the method for determining an abnormality in the vapor phase growth apparatus 1 includes a monitor wafer manufacturing step S11 and an abnormality determination step S12.

[0050] The monitor wafer manufacturing step S11 is an example of a method for manufacturing a monitor wafer according to the present invention, and manufactures a monitor wafer to be used in the abnormality determination step S12. The monitor wafer manufacturing process S11 includes a temperature increasing step S1, a first growth step S111, an abnormality checking step S112, a second growth step S113, and a temperature decreasing step S3.

[0051] In the temperature increase step S1, the monitor wafer manufacturing control unit 92 controls the source gas flow path opening / closing mechanism 61, the dopant gas flow path opening / closing mechanism 62, the purge gas flow path opening / closing mechanism 63, and the supply destination switching mechanism 64, as shown in FIG. 5, to increase the temperature in the chamber 2 to the growth temperature of the first epitaxial layer.

[0052] In the first growth process S111, the monitor wafer manufacturing control unit 92 controls the source gas flow path opening / closing mechanism 61, the dopant gas flow path opening / closing mechanism 62, and the supply destination switching mechanism 64 in the same manner as in the growth process S2, while maintaining the temperature inside the chamber 2 at the growth temperature. In the first growth step S111, a growth gas containing a source gas, a dopant gas, a purge gas, and a carrier gas is newly supplied into the chamber 2, and a first epitaxial layer is grown on the surface of the silicon wafer W. In the first growth step S111, the dopant gas does not have to be supplied into the chamber 2. In this case, the resistivity of the first epitaxial layer becomes higher than when the dopant gas is supplied into the chamber 2.

[0053] In the abnormality confirmation step S112, the monitor wafer fabrication control unit 92 controls the source gas flow path opening and closing mechanism 61 to close the source gas flow path 32 while keeping the dopant gas flow path 33 and the purge gas flow path 34 open, while maintaining the interior of the chamber 2 at the growth temperature. The monitor wafer fabrication control unit 92 also controls the supply destination switching mechanism 64 to set the growth gas flow path 35 to a gas stop state. In other words, the monitor wafer fabrication control unit 92 controls the source gas flow path opening and closing mechanism 61 and the supply destination switching mechanism 64 to stop the supply of the source gas, dopant gas, and purge gas to the chamber 2. The monitor wafer fabrication control unit 92 then maintains the above-described control state for a predetermined period of time. The predetermined period is preferably 3 seconds or more and 60 seconds or less. By setting the period to 3 seconds or more, a resistivity drop portion (described later) can be present in the resistivity profile in the thickness direction of the monitor wafer. Furthermore, by setting the period to 60 seconds or less, evaporation of the dopant layer formed on the surface layer can be suppressed. Furthermore, it is preferable that the dopant gas MFC 36C be controlled so that the flow rate of the dopant gas passing through the dopant gas flow path opening / closing mechanism 62 is 50 sccm or more and 300 sccm or less. If the flow rate of the dopant gas exceeds 300 sccm, there is a risk that the dopant gas flow path 33 will be contaminated with a high concentration of dopant, and if it is less than 50 sccm, there is a risk that the pressure of the dopant gas will be lower than the pressure of the purge gas, making the flow of the dopant gas unstable and there is a risk that the dopant layer will not be formed sufficiently. Furthermore, the flow rate of the dopant gas passing through the dopant gas flow path opening and closing mechanism 62 is preferably greater than the flow rate of the dopant gas in the first growth step S111 and the second growth step S113. This is because the greater the flow rate of the dopant gas passing through the dopant gas flow path opening and closing mechanism 62 in the abnormality confirmation step S112, the more likely a dopant layer is to be formed when an abnormality occurs in the supply destination switching mechanism 64, which has the advantage of making it easier to detect the abnormality.

[0054] If the supply destination switching mechanism 64 is found to be abnormal by the abnormality confirmation step S112, at least a portion of the dopant gas and purge gas is supplied into the chamber 2 together with the carrier gas without being discharged from the growth gas discharge path 37. In this case, the dopant gas is supplied into the chamber 2 for a predetermined period, and a dopant layer not containing silicon is formed on the surface of the first epitaxial layer.

[0055] On the other hand, if there is no abnormality in the supply destination switching mechanism 64, the dopant gas and purge gas are discharged from the growth gas exhaust path 37, and only the carrier gas is supplied into the chamber 2. In this case, since only the carrier gas is supplied into the chamber 2, no dopant layer is formed on the surface of the first epitaxial layer.

[0056] In the second growth process S113, the monitor wafer manufacturing control unit 92 controls the source gas flow path opening / closing mechanism 61, the dopant gas flow path opening / closing mechanism 62, and the supply destination switching mechanism 64 in the same manner as in the first growth process S111, while maintaining the temperature inside the chamber 2 at the growth temperature. In the second growth step S113, growth gases including a source gas, a dopant gas, a purge gas, and a carrier gas are newly supplied into the chamber 2. In the second growth step S113, the dopant gas does not have to be supplied into the chamber 2. In this case, the resistivity of the second epitaxial layer becomes higher than when the dopant gas is supplied into the chamber 2.

[0057] If a dopant layer is found to have been formed on the surface of the first epitaxial layer in the abnormality confirmation step S112, a monitor wafer is manufactured in which a second epitaxial layer is grown on the surface of the dopant layer using newly supplied growth gas. During growth of the second epitaxial layer on the surface of this dopant layer, the dopant constituting the dopant layer diffuses into the second epitaxial layer. As a result, the resistivity of the portion of the second epitaxial layer closer to the first epitaxial layer becomes lower than the resistivity of the portion closer to the surface of the second epitaxial layer. The resistivity profile through the thickness of the monitor wafer includes a region where the resistivity locally drops (hereinafter sometimes referred to as a "resistivity drop region"), regardless of whether the resistivity of the second epitaxial layer is equal to or higher than that of the first epitaxial layer. The resistivity drop region includes a first inflection point where the resistivity starts to drop from a constant rate of change; a second inflection point located closer to the surface of the monitor wafer than the first inflection point where the resistivity starts to increase; and a third inflection point located closer to the surface of the monitor wafer than the second inflection point where the resistivity starts to become constant. The resistivity drop region is a region between the first and third inflection points.

[0058] 6(A), when the abnormality confirmation step S112 is performed so that the resistivity of the second epilayer is equal to or greater than that of the first epilayer, the resistivity profile of the second epilayer has a resistivity drop region A1 including a first inflection point P11, a second inflection point P12, and a third inflection point P13, as shown by the solid line. On the other hand, when the abnormality confirmation step S112 is performed so that the resistivity of the second epilayer is less than that of the first epilayer, the resistivity profile of the second epilayer has a resistivity drop region A2 including a first inflection point P21, a second inflection point P22, and a third inflection point P23, as shown by the dashed line.

[0059] The difference between the resistivity at the second inflection point and the resistivity at the third inflection point in the resistivity drop portion (hereinafter sometimes referred to as the "dropped portion resistivity difference") is larger when the resistivity of the second epilayer is equal to or greater than that of the first epilayer than when the resistivity of the second epilayer is less than that of the first epilayer, as shown in Fig. 6(A) for example. Furthermore, the larger the dropped portion resistivity difference, the easier it becomes to determine whether the resistivity of the portion of the second epilayer on the first epilayer side has decreased due to the influence of the dopant layer in the abnormality determination step S12, which will be described in detail later. For these reasons, the second growth step S113 is preferably carried out so that the resistivity of the second epitaxial layer is equal to or greater than the resistivity of the first epitaxial layer.

[0060] Furthermore, the thickness of the low-resistivity region corresponding to the resistivity drop portion on the monitor wafer (the region from the position corresponding to the first inflection point to the position corresponding to the third inflection point on the monitor wafer) is determined by the conditions under which the abnormality confirmation step S112 is performed (e.g., the period during which the supply destination switching mechanism 64 is maintained in the gas stop state (the above-mentioned predetermined period), the flow rate of dopant gas passing through the supply destination switching mechanism 64 when it is assumed that there is an abnormality in the supply destination switching mechanism 64, etc.). Therefore, once the conditions under which the abnormality confirmation step S112 is performed are determined, the thickness of the low-resistivity region (e.g., the same thickness as the width D1 of the resistivity drop portion A1 shown in FIG. 6(A)) can be estimated. The second growth step S113 is preferably performed so that the thickness of the second epitaxial layer exceeds the thickness of the low-resistance region estimated in this way. If the thickness of the second epitaxial layer is less than the thickness of the low-resistivity region, when a dopant layer is formed in the abnormality confirmation step S112, the third inflection point will not exist in the resistivity profile in the thickness direction of the monitor wafer, making it difficult to determine whether or not a region of reduced resistivity exists in the abnormality determination step S12.

[0061] On the other hand, if no dopant layer is formed on the surface of the first epitaxial layer in the abnormality confirmation step S112, a monitor wafer is manufactured in which a second epitaxial layer is grown on the surface of the first epitaxial layer using newly supplied growth gas. In this case, the resistivity profile in the thickness direction of the monitor wafer will be a profile without any low resistivity portions, regardless of whether the resistivity of the second epitaxial layer is equal to or higher than that of the first epitaxial layer. 6(B), when the abnormality checking step S112 is performed so that the resistivity of the second epilayer is equal to or greater than that of the first epilayer, the resistivity profile of the second epilayer becomes as shown by the solid line. On the other hand, when the abnormality checking step S112 is performed so that the resistivity of the second epilayer is less than that of the first epilayer, the resistivity profile of the second epilayer becomes as shown by the dashed line.

[0062] In the temperature-lowering process S3, the monitor wafer manufacturing control unit 92 controls the source gas flow path opening / closing mechanism 61, the dopant gas flow path opening / closing mechanism 62, and the supply destination switching mechanism 64, as shown in Figure 5, to lower the temperature inside the chamber 2 to the removal temperature.

[0063] After the temperature lowering step S3 is completed, the monitor wafer is taken out of the chamber 2. Next, the resistivity profile measuring device 8 measures the resistivity profile in the thickness direction of the monitor wafer taken out of the chamber 2, and outputs the measurement result to the control device 9.

[0064] In the abnormality determination step S12, the abnormality determination unit 93 acquires the measurement results of the resistivity profile in the thickness direction of the monitor wafer from the resistivity profile measuring device 8. Then, the abnormality determination unit 93 determines whether or not there is an abnormality in the supply destination switching mechanism 64 based on the acquired resistivity profile in the thickness direction. Specifically, if there is a region of reduced resistivity in the resistivity profile in the thickness direction of the monitor wafer, the abnormality determination unit 93 determines that there is an abnormality in the supply destination switching mechanism 64, and if there is no region of reduced resistivity, it determines that there is no abnormality in the supply destination switching mechanism 64. The abnormality determination unit 93 may display the determination result of whether or not there is an abnormality on a display unit (not shown).

[0065] <Effects of the embodiment> The monitor wafer manufacturing process S11 includes a first growth process S111, an abnormality confirmation process S112, and a second growth process S113. By performing this monitor wafer manufacturing process S11, if there is an abnormality in the supply destination switching mechanism 64, dopant gas will be supplied into the chamber 2 in the abnormality confirmation process S112, and the resistivity profile in the thickness direction of the monitor wafer will be a profile in which a resistivity drop portion is present. On the other hand, if there is no abnormality in the supply destination switching mechanism 64, dopant gas will not be supplied into the chamber 2 in the abnormality confirmation process S112, and the resistivity profile in the thickness direction of the monitor wafer will be a profile in which a resistivity drop portion is not present. The method for determining an abnormality in the vapor phase growth apparatus 1 includes a monitor wafer manufacturing process S11 and an abnormality determination process S12 for determining whether or not there is an abnormality in at least the supply destination switching mechanism 64 based on the resistivity profile in the thickness direction of the monitor wafer. In this way, during the manufacture of the monitor wafer, a second epitaxial layer is grown on a wafer on which a dopant layer may have been formed on the surface of the first epitaxial layer, so that a resistivity profile according to the presence or absence of an abnormality in the supply destination switching mechanism 64 can be obtained without the long time required for SIMS measurement by using either the CV measurement method, which cannot measure the resistivity of the surface layer, or the SR measurement method, which does not have sufficient resolution to measure the resistivity of the surface layer. Furthermore, there is no need to use a heat treatment furnace as in the method described in Patent Document 2, and there is no need to control the thickness of the second epitaxial layer as in the method described in Patent Document 3. Therefore, it is possible to provide a method for determining an abnormality in a vapor phase growth apparatus that can facilitate determination of an abnormality in the supply destination switching mechanism 64 that constitutes the gas supply control mechanism 65. It is also possible to provide a method for determining an abnormality in a vapor phase growth apparatus that can easily determine an abnormality in the supply destination switching mechanism 64.

[0066] By performing the second growth step S113 so that the resistivity of the second epitaxial layer is equal to or greater than that of the first epitaxial layer, the resistivity difference in the decreased region can be made larger, and the presence or absence of a region with decreased resistivity can be easily determined in the abnormality determination step S12.

[0067] In the abnormality confirmation step S112, the dopant gas flow path opening / closing mechanism 62 is controlled so that the dopant gas flows to the supply destination switching mechanism 64. In this way, by actively flowing dopant gas through the supply destination switching mechanism 64 in the abnormality confirmation step S112, it is possible to increase the amount of dopant gas supplied into the chamber 2 when an abnormality occurs in the supply destination switching mechanism 64. This reduces the resistivity at the second inflection point in the resistivity drop region, thereby increasing the difference between the resistivity at the second inflection point and the resistivity at the first inflection point. This makes it easier to determine whether or not there is a resistivity drop region in the abnormality determination step S12.

[0068] By performing the second growth step S113 so that the thickness of the second epitaxial layer exceeds the thickness of the low-resistivity region, if there is an abnormality in the supply destination switching mechanism 64, a third inflection point can be present in the resistivity profile in the thickness direction of the monitor wafer, and the presence or absence of a region of reduced resistivity can be more easily determined in the abnormality determination step S12.

[0069] [Variations] Although an embodiment of the present invention has been described in detail above with reference to the drawings, the specific configuration is not limited to this embodiment, and various improvements and design changes that do not deviate from the gist of the present invention are also included in the present invention.

[0070] For example, the second growth step S113 may be performed so that the resistivity of the second epitaxial layer is less than the resistivity of the first epitaxial layer.

[0071] The abnormality detection method of the present invention may be applied to a vapor phase growth apparatus that does not have a supply destination switching mechanism 64 in the growth gas flow path 35, and may be used to detect an abnormality in the dopant gas flow path opening / closing mechanism 62 that constitutes the gas supply control mechanism 65. In this case, in the first growth step S111 and the second growth step S113, the source gas flow path opening and closing mechanism 61 and the dopant gas flow path opening and closing mechanism 62 are controlled to open the source gas flow path 32 and the dopant gas flow path 33, respectively, to supply the growth gas into the chamber 2 via the growth gas flow path 35. In addition, in the abnormality confirmation step S112, the source gas flow path opening and closing mechanism 61 and the dopant gas flow path opening and closing mechanism 62 are controlled to close the source gas flow path 32 and the dopant gas flow path 33, respectively, to supply the purge gas and the carrier gas into the chamber 2. If there is an abnormality in the dopant gas flow path opening and closing mechanism 62, the dopant gas that has passed through the dopant gas flow path opening and closing mechanism 62 is supplied into the chamber 2, and the resistivity profile in the thickness direction of the monitor wafer will show a profile in which a resistivity drop portion exists. Therefore, an abnormality in the dopant gas flow path opening and closing mechanism 62 can be determined based on the resistivity profile.

[0072] In the abnormality confirmation step S112, the dopant gas flow path opening / closing mechanism 62 may be controlled so that dopant gas does not flow into the supply destination switching mechanism 64. In this case, when the supply destination switching mechanism 64 is switched to the gas stop state, the dopant gas remaining in the portion of the dopant gas flow path 33 downstream of the dopant gas flow path opening / closing mechanism 62 and in the portion of the growth gas flow path 35 upstream of the supply destination switching mechanism 64 passes through the abnormal supply destination switching mechanism 64 and is supplied into the chamber 2. Therefore, if there is an abnormality in the supply destination switching mechanism 64, the resistivity profile in the thickness direction of the monitor wafer will be a profile that indicates the presence of a portion of reduced resistivity. Therefore, an abnormality in the supply destination switching mechanism 64 can be determined based on the resistivity profile in the thickness direction of the monitor wafer.

[0073] Although the configuration in which the abnormality determination step S12 is performed by the abnormality determination unit 93 has been exemplified, the resistivity profile in the thickness direction of the monitor wafer may be presented to an operator, who may then determine whether or not there is an abnormality in the supply destination switching mechanism 64.

[0074] In the abnormality determination step S12, the presence or absence of an abnormality in the supply destination switching mechanism 64 may be determined based on the dopant concentration profile in the thickness direction of the monitor wafer. Even with this configuration, the dopant concentration profile corresponds to the resistivity profile, so that it is possible to determine whether or not there is an abnormality in the supply destination switching mechanism 64 by the same method as in the above embodiment.

[0075] The method for manufacturing a monitor wafer according to the present invention may be applied to a method for manufacturing a monitor wafer used for determining contamination in a predetermined space such as a clean room. The method for manufacturing such a monitor wafer includes a first growth step in which the source gas flow path opening and closing mechanism 61 is controlled to open the source gas flow path 32 and a first epitaxial layer is grown on the silicon wafer W in the chamber 2; an abnormality confirmation step in which the silicon wafer W is removed from the vapor phase growth apparatus 1 and left in a predetermined space for a predetermined period of time; and a second growth step in which the silicon wafer W is placed in the chamber 2 and then the source gas flow path opening and closing mechanism 61 is controlled to open the source gas flow path 32 and a second epitaxial layer is grown on the silicon wafer in the chamber 2, thereby manufacturing a monitor wafer. The resistivity profile in the thickness direction of the monitor wafer manufactured in this manner will have a resistivity drop portion in the anomaly confirmation step if the predetermined space is contaminated with dopant gas because the dopant gas adheres to the surface of the first epitaxial layer. On the other hand, if the predetermined space is not contaminated with dopant gas, the dopant gas does not adhere to the surface of the first epitaxial layer in the anomaly confirmation step, so the resistivity profile in the thickness direction of the monitor wafer will have no resistivity drop portion. If a region of reduced resistivity is present in the resistivity profile in the thickness direction of the monitor wafer, it can be determined that the specified space is contaminated with dopant gas, and if no region of reduced resistivity is present, it can be determined that the specified space is not contaminated with dopant gas. [Example]

[0076] Next, examples of the present invention will be described, but the present invention is not limited to these examples.

[0077] [Experiment 1] Experiment 1 was carried out to examine a measurement method that can be used in the method for determining abnormality in a vapor phase growth apparatus according to the present invention.

[0078] <Comparative Example 1> First, a vapor phase growth system having the same configuration as the vapor phase growth apparatus 1 of the above embodiment was prepared. Also, a p+ silicon wafer W having a diameter of 200 mm and doped with boron so that the resistivity was 10 mΩcm or more and 20 mΩcm or less was prepared. Then, the first growth step S111 of the above embodiment was performed to grow a first epitaxial layer on the silicon wafer W, thereby producing a monitor wafer of level 1. Level 1 is a condition simulating the case where a monitor wafer not having a second epitaxial layer is manufactured using a supply destination switching mechanism 64 that is free of abnormalities. The growth conditions for the first epitaxial layer are as follows: Growth temperature: 1130℃ Dopant gas: Diborane (B2H6) Resistivity of the first epitaxial layer: 10 Ωcm First epitaxial layer thickness: 4.0 μm

[0079] Furthermore, after growing a first epitaxial layer on a silicon wafer W under the same conditions as in Level 1, the supply of source gas into chamber 2 was stopped while maintaining the growth temperature, and dopant gas, purge gas, and carrier gas were supplied into chamber 2 for 3 seconds by controlling source gas flow path opening and closing mechanism 61, dopant gas flow path opening and closing mechanism 62, purge gas flow path opening and closing mechanism 63, and supply destination switching mechanism 64, thereby producing a monitor wafer of Level 2 in which a dopant layer was formed on the surface of the first epitaxial layer. The flow rate of dopant gas supplied into chamber 2 to form the dopant layer was set to 150 sccm. In addition, a monitor wafer of level 3, in which a dopant layer was formed on the surface of the first epitaxial layer, was manufactured under the same conditions as level 2, except that after growing the first epitaxial layer, the time for supplying the dopant gas, purge gas, and carrier gas into chamber 2 was set to 10 seconds. Levels 2 and 3 are conditions that simulate the case where a monitor wafer not having a second epitaxial layer is manufactured using a supply destination switching mechanism 64 that has an abnormality.

[0080] The dopant concentration profile and resistivity profile in the thickness direction were measured using the CV measurement method for the monitor wafers of levels 1, 2, and 3. Table 1 shows the maximum dopant concentration and minimum resistivity. As shown in Table 1, the maximum dopant concentration and the minimum resistivity were almost the same for the monitor wafers of Levels 1, 2, and 3. In other words, it was confirmed that the dopant layer present on the surface of the monitor wafer could not be measured in Comparative Example 1. From this, it was confirmed that the CV measurement method, which cannot measure the resistivity of the surface layer, cannot determine whether or not there is an abnormality in the supply destination switching mechanism 64 using a monitor wafer that does not have a second epitaxial layer and only has the first epitaxial layer (shown as "impossible" in the "determinability" column in Table 1).

[0081] [Table 1]

[0082] <Comparative Example 2> Monitor wafers of levels 1, 2, and 3 were manufactured under the same conditions as those of levels 1, 2, and 3 in Comparative Example 1, and the dopant concentration profile and resistivity profile in the thickness direction of the monitor wafers of levels 1, 2, and 3 were measured using the SR measurement method. The maximum dopant concentration and minimum resistivity are shown in Table 1. As shown in Table 1, similarly to Comparative Example 1, the maximum values of the dopant concentration in the monitor wafers of Levels 1, 2, and 3 were almost the same, and the minimum values of the resistivity were also almost the same. From this, it was confirmed that the SR measurement method, which does not have sufficient resolution to measure the resistivity of the surface layer, cannot determine an abnormality in the supply destination switching mechanism 64 using a monitor wafer that does not have a second epitaxial layer and only has the first epitaxial layer.

[0083] <Comparative Example 3> Monitor wafers for levels 1, 2, and 3 were manufactured under the same conditions as those for levels 1, 2, and 3 in Comparative Example 1, and the dopant concentrations at positions up to a depth of 0.5 μm in the monitor wafers for levels 1, 2, and 3 were measured using SIMS. The measurement results confirmed the difference in dopant concentration between the levels at a depth of 0.036 μm. The measurement results for the dopant concentration at a depth of 0.036 μm are shown in Table 1. As shown in Table 1, the dopant concentration was lowest in level 1 and highest in level 3. In other words, it was confirmed that in comparative example 3, the dopant layer present in the surface layer of the monitor wafer could be measured. From this, it was confirmed that the SIMS measurement method can determine whether or not there is an abnormality in the supply destination switching mechanism 64 by using a monitor wafer that does not have a second epitaxial layer but only the first epitaxial layer.

[0084] Example 1 A monitor wafer was manufactured by growing a first epitaxial layer on a silicon wafer W under the same conditions as in Level 1 of Comparative Example 1, and the monitor wafer was temporarily removed from chamber 2. Thereafter, the monitor wafer was loaded back into chamber 2, and the second growth step S113 of the above embodiment was performed to grow a second epitaxial layer on the surface of the first epitaxial layer, thereby obtaining a monitor wafer of Level 1. Level 1 is a condition simulating the case where a monitor wafer having a first epitaxial layer and a second epitaxial layer is manufactured using a supply destination switching mechanism 64 that is free of abnormalities. The growth conditions for the second epitaxial layer are as follows: Growth temperature: 1130℃ Dopant gas: Diborane (B2H6) Resistivity of the second epitaxial layer: 10 Ωcm Second epitaxial layer thickness: 2.5 μm

[0085] Additionally, a monitor wafer in which a dopant layer was formed on the surface of the first epitaxial layer was manufactured under the same conditions as in Level 2 of Comparative Example 1, and the monitor wafer was temporarily removed from Chamber 2. Thereafter, a second epitaxial layer was grown on the surface of the dopant layer under the same conditions as in Level 1 of Example 1, thereby obtaining a monitor wafer of Level 2. Furthermore, a monitor wafer of level 3 was produced under the same conditions as level 2 of Example 2, except that a dopant layer was formed on the surface of the first epitaxial layer under the same conditions as level 3 of Comparative Example 1. Levels 2 and 3 are conditions that simulate the case where a monitor wafer having a first epitaxial layer and a second epitaxial layer is manufactured using a supply destination switching mechanism 64 that has an abnormality.

[0086] The dopant concentration profile and resistivity profile in the thickness direction were measured using the CV measurement method for the monitor wafers of levels 1, 2, and 3. Table 1 shows the maximum dopant concentration and minimum resistivity. As shown in Table 1, the maximum dopant concentration was lowest in level 1 and highest in level 3. The minimum resistivity was also highest in level 1 and lowest in level 3. In other words, it was confirmed that in Example 1, the dopant layer between the first epitaxial layer and the second epitaxial layer could be measured. From this, it was confirmed that even with the CV measurement method, which cannot measure the resistivity of the surface layer, it is possible to determine an abnormality in the supply destination switching mechanism 64 by using a monitor wafer having a first epitaxial layer and a second epitaxial layer.

[0087] <Example 2> Monitor wafers of levels 1, 2, and 3 were manufactured under the same conditions as those of levels 1, 2, and 3 in Example 1, and the dopant concentration profile and resistivity profile in the thickness direction of the monitor wafers of levels 1, 2, and 3 were measured using the SR measurement method. The maximum dopant concentration and minimum resistivity are shown in Table 1. As shown in Table 1, similarly to Example 1, the maximum value of the dopant concentration was lowest in Level 1 and highest in Level 3. Also, the minimum value of the resistivity was highest in Level 1 and lowest in Level 3. In other words, it was confirmed that in Example 2, the dopant layer between the first epitaxial layer and the second epitaxial layer could be measured. From this, it was confirmed that even if the SR measurement method does not have sufficient resolution to measure the resistivity of the surface layer, it is possible to determine an abnormality in the supply destination switching mechanism 64 by using a monitor wafer having a first epitaxial layer and a second epitaxial layer.

[0088] <Summary> From the above, it was confirmed that an abnormality in the supply destination switching mechanism 64 can be easily determined by measuring the resistivity profile in the thickness direction of the monitor wafer manufactured by the monitor wafer manufacturing method of the present invention using the CV measurement method or the SR measurement method.

[0089] [Experiment 2] Experiment 1 was carried out to confirm the resistivity profile in the thickness direction of a monitor wafer manufactured by the monitor wafer manufacturing method of the present invention. FIG. 7 shows resistivity profiles in the thickness direction of the monitor wafer in Experiment 2 of the embodiment, where (A) shows the resistivity profile of Experimental Example 1, which was manufactured to simulate a case where there is no abnormality in the supply destination switching mechanism, and (B) shows the resistivity profile of Experimental Example 2, which was manufactured to simulate a case where there is an abnormality in the supply destination switching mechanism.

[0090] Example 3 First, a vapor phase growth system having a configuration similar to that of the vapor phase growth apparatus 1 of the above embodiment was prepared. Also, an n+ silicon wafer W having a diameter of 200 mm and doped with arsenic so that the resistivity was 10 mΩcm or more and 20 mΩcm or less was prepared. Then, the first growth step S111 of the above embodiment was carried out to grow a first epitaxial layer on the silicon wafer W. The growth conditions for the first epitaxial layer are as follows: Growth temperature: 1100℃ Dopant gas: phosphine (Ph3) Resistivity of the first epitaxial layer: 10 Ωcm Thickness of first epitaxial layer: 5.0 μm

[0091] Next, the second growth step S113 of the above embodiment was carried out to grow a second epitaxial layer on the surface of the first epitaxial layer, thereby obtaining a monitor wafer of Example 3. The growth conditions for the second epitaxial layer are as follows: Growth temperature: 1100℃ Dopant gas: phosphine (Ph3) Resistivity of the second epitaxial layer: 10 Ωcm Second epitaxial layer thickness: 5.0 μm Example 3 is a condition simulating a case where a monitor wafer is manufactured using a supply destination switching mechanism 64 that is normal.

[0092] Then, the resistivity profile in the thickness direction of the monitor wafer of Example 3 was measured using the SR measurement method. The measurement results are shown in Figure 7(A). As shown in FIG. 7(A), the resistivity profile in the thickness direction of the monitor wafer of Example 3 was a profile that did not have a portion where the resistivity was low.

[0093] Example 4 After growing a first epitaxial layer on the silicon wafer W under the same conditions as in Example 3, the supply of source gas into chamber 2 was stopped while maintaining the growth temperature, and a dopant layer was formed on the surface of the first epitaxial layer by controlling source gas flow path opening and closing mechanism 61, dopant gas flow path opening and closing mechanism 62, purge gas flow path opening and closing mechanism 63, and supply destination switching mechanism 64 so as to supply dopant gas, purge gas, and carrier gas into chamber 2 for 3 seconds. The flow rate of dopant gas supplied into chamber 2 to form the dopant layer was set to 150 sccm. Thereafter, a second epitaxial layer was grown on the surface of the first epitaxial layer under the same conditions as in Example 3, thereby obtaining a monitor wafer for Example 4. Example 4 is a condition simulating a case where a monitor wafer is manufactured using a supply destination switching mechanism 64 having an abnormality.

[0094] Then, the resistivity profile in the thickness direction of the monitor wafer of Example 4 was measured using the SR measurement method. The measurement results are shown in Figure 7(B). As shown in FIG. 7(B), the resistivity profile in the thickness direction of the monitor wafer of Example 4 was a profile having a resistivity drop region A4.

[0095] <Summary> From the above, it was confirmed that an abnormality in the supply destination switching mechanism 64 can be easily determined based on the resistivity profile in the thickness direction of the monitor wafer manufactured by the monitor wafer manufacturing method of the present invention. [Explanation of symbols]

[0096] 1...vapor phase growth apparatus, 2...chamber, 32...source gas flow path, 33...dopant gas flow path, 35...growth gas flow path, 37...growth gas exhaust path, 61...source gas flow path opening / closing mechanism, 62...dopant gas flow path opening / closing mechanism, 64...supply destination switching mechanism, 65...gas supply control mechanism, S11...monitor wafer manufacturing process, S111...first growth process, S112...abnormality confirmation process, S113...second growth process, S12...abnormality determination process, W...silicon wafer.

Claims

1. A method for manufacturing a monitor wafer used to determine an abnormality in a vapor phase growth apparatus, comprising: the vapor phase growth apparatus includes a chamber, a source gas flow path, a dopant gas flow path, a growth gas flow path that supplies the source gas flowing in from the source gas flow path and the dopant gas flowing in from the dopant gas flow path to the chamber, a source gas flow path opening / closing mechanism that opens and closes the source gas flow path, and a gas supply control mechanism that controls the supply state of the dopant gas to the chamber; The method for manufacturing the monitor wafer includes: a first growth step of growing a first epitaxial layer on the wafer in the chamber by controlling the source gas flow path opening and closing mechanism to open the source gas flow path; an abnormality confirmation step of controlling the source gas flow path opening / closing mechanism to close the source gas flow path and controlling the gas supply control mechanism to stop the supply of the dopant gas to the chamber for a predetermined period of time; a second growth step of manufacturing the monitor wafer by controlling the source gas flow path opening and closing mechanism to open the source gas flow path and growing a second epitaxial layer on the wafer in the chamber.

2. 2. The method for manufacturing a monitor wafer according to claim 1, a second epitaxial layer having a resistivity equal to or higher than that of the first epitaxial layer in the second growth step;

3. 2. The method for manufacturing a monitor wafer according to claim 1, the vapor phase growth apparatus includes a growth gas exhaust path that exhausts the gas flowing through the growth gas flow path; The gas supply control mechanism includes: a supply destination switching mechanism provided in the growth gas flow path to switch a gas supply destination between the chamber and the growth gas exhaust path; In the first growth step and the second growth step, the supply destination switching mechanism is controlled so that the supply destination is the chamber; In the abnormality confirmation step, the supply destination switching mechanism is controlled so that the supply destination becomes the growth gas exhaust path.

4. 4. The method for manufacturing a monitor wafer according to claim 3, The gas supply control mechanism includes: a dopant gas flow path opening / closing mechanism that opens and closes the dopant gas flow path; A method for manufacturing a monitor wafer, wherein at least the abnormality confirmation step among the first growth step, the abnormality confirmation step, and the second growth step controls the dopant gas flow path opening and closing mechanism to open the dopant gas flow path.

5. 2. The method for manufacturing a monitor wafer according to claim 1, In the method for manufacturing a monitor wafer, the predetermined period in the abnormality confirmation step is 3 seconds or more.

6. a monitor wafer manufacturing process for manufacturing a monitor wafer by the monitor wafer manufacturing method according to any one of claims 1 to 5; and an abnormality determination step of determining whether the gas supply control mechanism is abnormal based on a resistivity profile or a dopant concentration profile in the thickness direction of the monitor wafer.

7. 7. The method for determining an abnormality in a vapor phase growth apparatus according to claim 6, The abnormality determination step includes: The method for determining an abnormality in a vapor phase growth apparatus includes determining that there is an abnormality in the gas supply control mechanism if there is a resistivity drop region where the resistivity is locally low in the resistivity profile in the thickness direction, and determining that there is no abnormality in the gas supply control mechanism if there is no resistivity drop region.

8. 8. The method for determining an abnormality in a vapor phase growth apparatus according to claim 7, The resistivity reduction portion is A method for determining an abnormality in a vapor phase growth apparatus, comprising: a first inflection point where the resistivity starts to decrease from a constant rate of change; a second inflection point where the resistivity starts to increase; and a third inflection point where the resistivity starts to become constant, the third inflection point being a region between the first inflection point and the third inflection point.

9. 8. The method for determining an abnormality in a vapor phase growth apparatus according to claim 7, a low-resistivity region corresponding to the resistivity-reduced portion in the monitor wafer is located on the first epitaxial layer side of the second epitaxial layer; The method for determining an abnormality in a vapor phase growth apparatus, wherein the second growth step grows the second epitaxial layer to a thickness exceeding a thickness of the low-resistivity region estimated based on the conditions under which the abnormality confirmation step is performed.

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