Image sensor

Abstract

To improve the electric and optical characteristics of an image sensor.SOLUTION: According to an embodiment of the present invention, an image sensor includes a semiconductor substrate including a trench on a first surface, an insulating pattern provided in the trench, and a doping region in the semiconductor substrate and on the insulating pattern. The doping region includes a side part on a side wall of the insulating pattern, and a bottom part on a bottom surface of the insulating pattern. The thickness of the side part of the doping region is 85% to 115% of the thickness of the bottom part. The number of dopants per unit area of the side part of the doping region may be 85% to 115% of the number of dopants per unit area of the bottom part.SELECTED DRAWING: Figure 2D

Description

[Technical Field]

[0001] The present invention relates to an image sensor and a method for forming the same, and more particularly to a doping region of an image sensor and a method for forming the same. [Background technology]

[0002] An image sensor is a device that converts an optical image into an electrical signal. Image sensors can be classified into CCD (Charge Coupled Device) type and CMOS (Complementary Metal Oxide Semiconductor) type. CMOS type image sensors are abbreviated as CIS (CMOS image sensor). The CIS has a number of pixels arranged two-dimensionally. Each pixel includes a photodiode (PD). The photodiode converts incident light into an electrical signal. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent Publication No. 2014 / 0295648 [Patent Document 2] U.S. Patent Publication No. 2019 / 0214297 Summary of the Invention [Problem to be solved by the invention]

[0004] The problem to be solved by the present invention is to improve the electrical and optical characteristics of an image sensor.

[0005] The problems to be solved by the present invention are not limited to those mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0006] An image sensor according to an embodiment of the present invention is provided, which includes a semiconductor substrate having a trench in a first surface thereof, an insulating pattern provided in the trench, and a doped region in the semiconductor substrate and on the insulating pattern, the doped region having a side portion on a sidewall of the insulating pattern and a bottom portion on a bottom surface of the insulating pattern, the thickness of the side portion of the doped region being 85% to 115% of the thickness of the bottom portion, and the number of dopants per unit area of the side portion of the doped region being 85% to 115% of the number of dopants per unit area of the bottom portion.

[0007] According to an embodiment of the present invention, an image sensor includes a semiconductor substrate having a trench, an insulating pattern in the trench of the semiconductor substrate, and a doping region disposed in the semiconductor substrate and on the insulating pattern, the doping region including a first region in contact with the insulating pattern and including a dopant and a first auxiliary element, and a second region interposed between the first region and the semiconductor substrate and including the dopant, and a concentration of the dopant in the first region may be greater than a concentration of the first auxiliary element in the first region.

[0008] According to an embodiment of the present invention, an image sensor includes a substrate having a first surface, a second surface opposite to the first surface, and a trench, the trench being provided in one of the first surface and the second surface; a photoelectric conversion region provided between the first surface and the second surface of the substrate; a color filter disposed on the second surface of the substrate; a fence pattern disposed between the color filters; a microlens layer disposed on the color filter; an impurity region disposed in the substrate and adjacent to the first surface of the substrate; and a wiring layer including a wiring structure; an insulating pattern covering the trench in the substrate; and a doped region provided in the substrate and in contact with the insulating pattern, wherein the insulating pattern has a first surface and a second surface having different slopes from each other, the doped region includes a first portion on the first surface of the insulating pattern and a second portion on the second surface of the insulating pattern, a thickness of the second portion of the doped region is 85% to 115% of a thickness of the first portion, and a number of dopants per unit area of the second portion of the doped region is 85% to 115% of a number of dopants per unit area of the first portion. [Effects of the Invention]

[0009] According to the present invention, the doped region can have a uniform thickness and a uniform dopant concentration, thereby improving the electrical and optical characteristics of the image sensor. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 2 is a circuit diagram of a pixel of the image sensor according to the embodiment. [Figure 2A] 1 is a diagram illustrating a method for manufacturing a semiconductor device including a doped region according to an embodiment; [Figure 2B] 1 is a diagram illustrating a method for manufacturing a semiconductor device including a doped region according to an embodiment; [Figure 2C]1 is a diagram illustrating a method for manufacturing a semiconductor device including a doped region according to an embodiment; [Figure 2D] 1 is a diagram illustrating a method for manufacturing a semiconductor device including a doped region according to an embodiment; [Figure 2E] 1 is a diagram illustrating a semiconductor device including a doped region according to an embodiment; [Figure 3] 1 is a flow chart illustrating a method of forming a doping region according to an embodiment; [Figure 4A] 1 is a diagram illustrating a semiconductor device including a doped region according to an embodiment; [Figure 4B] 4B is an enlarged view of region A in FIG. 4A. [Figure 5A] 1 is a diagram illustrating the manufacturing of a semiconductor device according to an embodiment; [Figure 5B] 5B is an enlarged view of region A in FIG. 5A. [Figure 5C] 1 is a diagram illustrating the manufacturing of a semiconductor device according to an embodiment; [Figure 5D] 1 is a diagram illustrating a doping region and its fabrication according to an embodiment; [Figure 6] FIG. 1 is a plan view showing an image sensor according to an embodiment. [Figure 7A] This is a cross section taken along line II' in FIG. [Figure 7B] 7B is an enlarged view of region B in FIG. 7A. [Figure 7C] 4 is a diagram illustrating an element isolation pattern, a first isolation pattern, and a first doping region according to an embodiment. [Figure 7D] 7D is an enlarged view of the BB region of FIG. 7C. [Figure 7E] 4 is a diagram illustrating an element isolation pattern, a first isolation pattern, and a first doping region according to an embodiment. [Figure 7F] 7B is an enlarged view of region C in FIG. 7A. [Figure 8A]2 is a diagram illustrating a pixel array region of an image sensor according to an embodiment; [Figure 8B] 8B is an enlarged view of region B in FIG. 8A. [Figure 8C] 2 is a diagram illustrating a pixel array region of an image sensor according to an embodiment; [Figure 8D] 8D is an enlarged view of region B in FIG. 8C. [Figure 8E] 2 is a diagram illustrating a pixel array region of an image sensor according to an embodiment; [Figure 9A] 2 is a diagram illustrating a pixel array region of an image sensor according to an embodiment; [Figure 9B] 9B is an enlarged view of region B in FIG. 9A. [Figure 9C] 4 is a diagram illustrating a first separation pattern and a second separation pattern according to an embodiment. [Figure 9D] 4 is a diagram illustrating a first isolation pattern, a second isolation pattern, and a first doping region according to an embodiment. [Figure 9E] 2 is a diagram illustrating a pixel array region of an image sensor according to an embodiment; [Figure 9F] 9B is an enlarged view of region B in FIG. 9E. [Figure 9G] 2 is a diagram illustrating a pixel array region of an image sensor according to an embodiment; [Figure 9H] 2 is a diagram illustrating a pixel array region of an image sensor according to an embodiment; [Figure 10A] 2 is a diagram illustrating a pixel array region of an image sensor according to an embodiment; [Figure 10B] 10B is an enlarged view of region D in FIG. 10A. [Figure 10C] 10 is a view illustrating an isolation pattern and a second doping region according to an embodiment. [Figure 10D]10 is a view illustrating an isolation pattern and a second doping region according to an embodiment. [Figure 10E] 10 is a view illustrating an isolation pattern and a second doping region according to an embodiment. [Figure 11A] 2 is a diagram illustrating a pixel array region of an image sensor according to an embodiment; [Figure 11B] 11B is an enlarged view of region E in FIG. 11A. [Figure 11C] 11B is an enlarged view of region F in FIG. 11A. [Figure 11D] 2 is a diagram illustrating a pixel array region of an image sensor according to an embodiment; [Figure 11E] 11D is an enlarged view of region G in FIG. [Figure 11F] 10 is a view illustrating a gate insulating pattern, a third doping region, and a second additional element region of an isolation pattern according to an embodiment. [Figure 12A] 1 is a diagram illustrating a method for manufacturing an image sensor according to an embodiment; [Figure 12B] 1 is a diagram illustrating a method for manufacturing an image sensor according to an embodiment; [Figure 12C] 1 is a diagram illustrating a method for manufacturing an image sensor according to an embodiment; [Figure 12D] 1 is a diagram illustrating a method for manufacturing an image sensor according to an embodiment; [Figure 12E] 1 is a diagram illustrating a method for manufacturing an image sensor according to an embodiment; [Figure 12F] 1 is a diagram illustrating a method for manufacturing an image sensor according to an embodiment; [Figure 12G] 1 is a diagram illustrating a method for manufacturing an image sensor according to an embodiment; [Figure 12H] 1 is a diagram illustrating a method for manufacturing an image sensor according to an embodiment; [Figure 12I]1 is a diagram illustrating a method for manufacturing an image sensor according to an embodiment; [Figure 13A] 2 is a diagram illustrating a pixel array region of an image sensor according to an embodiment; [Figure 13B] 1 is a diagram illustrating the formation of a conductive separation pattern according to an embodiment; [Figure 13C] 1 is a diagram illustrating the formation of a conductive separation pattern according to an embodiment; [Figure 13D] 1 is a diagram illustrating the formation of a conductive separation pattern according to an embodiment; [Figure 14A] 7 is an enlarged plan view illustrating the arrangement of color filters of the image sensor according to the embodiment, showing a region II in FIG. 6; [Figure 14B] FIG. 2 is a plan view illustrating the arrangement of color filters of the image sensor according to the embodiment. [Figure 14C] This is a cross section taken along line I''-I'''' in Figure 14B. [Figure 14D] FIG. 2 is a plan view illustrating the arrangement of color filters of the image sensor according to the embodiment. [Figure 15A] 7 is a cross-sectional view of the image sensor according to the embodiment taken along line III-III' of FIG. 6; [Figure 15B] 1 is a diagram illustrating an image sensor according to an embodiment; DETAILED DESCRIPTION OF THE INVENTION

[0011] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An image sensor according to an embodiment of the present invention will now be described.

[0012] FIG. 1 is a circuit diagram of a pixel of an image sensor according to an embodiment.

[0013] 1, each pixel of the image sensor may include a photoelectric conversion region PD, a transfer transistor Tx, a source follower transistor Sx, a reset transistor Rx, and a selection transistor Ax, each of which may include a transfer gate TG, a source follower gate SG, a reset gate RG, and a selection gate AG.

[0014] The photoelectric conversion region PD is a photodiode including an n-type impurity region and a p-type impurity region. The floating diffusion region FD can function as the drain of the transfer transistor Tx. The floating diffusion region FD can function as the source of the reset transistor Rx. The floating diffusion region FD can be electrically connected to a source follower gate SG of a source follower transistor Sx. The source follower transistor Sx is connected to a selection transistor Ax.

[0015] The operation of the image sensor can be explained with reference to FIG. 1 as follows. First, with light blocked, a power supply voltage VDD is applied to the drain of the reset transistor Rx and the drain of the source follower transistor Sx, turning the reset transistor Rx on and discharging the charge remaining in the floating diffusion region FD. Then, when the reset transistor Rx is turned off and external light is incident on the photoelectric conversion region PD, electron-hole pairs are generated in the photoelectric conversion region PD. The holes move to the p-type impurity region of the photoelectric conversion region PD, and the electrons move to the n-type impurity region and accumulate there. When the transfer transistor Tx is turned on, these electron and hole charges are transferred to and accumulated in the floating diffusion region FD. The gate bias of the source follower transistor Sx changes in proportion to the amount of accumulated charge, causing a change in the source potential of the source follower transistor Sx. When the select transistor Ax is turned on, a signal corresponding to the charge is read out to the column line.

[0016] A wiring line may be electrically connected to at least one of the transfer gate TG, the source follower gate SG, the reset gate RG, and the select gate AG. The wiring line may be configured to apply a power supply voltage VDD to the drain of the reset transistor Rx or the drain of the source follower transistor Sx. The wiring line may include a column line connected to the select transistor Ax. The wiring line may be a first conductive structure 830, which will be described later with reference to FIGS. 7A and 15A.

[0017] 1 illustrates a pixel having one photoelectric conversion region PD and four transistors Tx, Rx, Ax, and Sx, but the present invention is not limited thereto. For example, multiple pixels may be provided, and the reset transistor Rx, source follower transistor Sx, or selection transistor Ax may be shared by adjacent pixels. This may improve the integration density of the image sensor.

[0018] 2A to 2D are views illustrating a method for fabricating a semiconductor device including a doped region according to an embodiment. FIG. 2C is an enlarged view of region A of FIG. 2B. FIG. 3 is a flowchart illustrating a method for forming a doped region according to an embodiment.

[0019] Referring to FIG. 2A, a substrate 10 may be prepared. The substrate 10 may be a semiconductor substrate or an SOI (Silicon on Insulator) substrate. A trench 19 may be formed on a first surface 10a of the substrate 10. The trench 19 may be formed by an etching process. During the formation of the trench 19, interface defects may be formed on a sidewall 19c and a bottom surface 19b of the trench 19. The interface defects may include oxides or dangling bonds. The trench 19 may have a first surface and a second surface having different slopes. For example, the first surface and the second surface of the trench 19 may be the sidewall 19c and the bottom surface 19b, respectively. The slope of the sidewall 19c of the trench 19 may be different from the slope of the bottom surface 19b of the trench 19. For example, the bottom surface 19b of the trench 19 may be substantially parallel to the first surface 10a of the substrate 10. The sidewall 19c of the trench 19 may be inclined with respect to the first surface 10a of the substrate 10. The angle between the sidewall 19c of the trench 19 and the first surface 10a of the substrate 10 can be greater than or equal to 90° and less than 180°.

[0020] The first and second surfaces of the trench 19 are not limited to the sidewalls 19c and bottom surface 19b, respectively. Although not shown, the sidewalls 19c of the trench may have first and second surfaces with different slopes. The bottom surface 19b of the trench 19 may have first and second surfaces with different slopes.

[0021] The substrate 10 may be placed in a reactor (not shown). The reactor may be a batch-type reactor or a single-wafer reactor, and the batch-type reactor may include a single gas supply pipe or dual gas supply pipes. The reactor may further include an exhaust line, a pump, or a scrubber.

[0022] 2B, 2C, and 3, a doping region 40 may be formed on the sidewall 19c and bottom surface 19b of the trench 19 in the substrate 10. Forming the doping region 40 may be performed by a gas-phase doping (GPD) method. For example, forming the doping region 40 may include performing a first purge process (S10), a gas-phase doping process (S20), and a second purge process (S30).

[0023] The first purge process (S10) may be performed by supplying hydrogen purge gas to the first surface 10a of the substrate 10 and into the trench 19. The hydrogen purge gas can remove interfacial defects in the trench 19, as described in FIG. 2A. Therefore, dislocation of the semiconductor material (e.g., silicon) due to the interfacial defects can be prevented. The first purge process may be performed at a temperature of approximately 200°C to 700°C and a pressure of 20 Pa to 2000 Pa for 1 second to 480 minutes. An inert gas, such as nitrogen gas, may be used as a carrier gas. The flow rates of the hydrogen purge gas and the inert gas in the first purge process may be 0.01 sccm to 2000 sccm.

[0024] After the first purge process is completed, a vapor-phase doping process may be performed. Performing the vapor-phase doping process (S20) may include supplying a doping gas 400 onto the sidewalls 19c and bottom surface 19b of the trench 19. The doping gas 400 may include a Group III element such as aluminum (Al), boron (B), indium (In), and / or gallium (Ga). For example, the doping gas 400 may include a boron-containing gas such as BCl3 or B2H6. For another example, the doping gas 400 may include BF3. The vapor-phase doping process may be performed at a higher temperature than the first purge process. For example, the vapor-phase doping process may be performed at a temperature of approximately 200°C to 800°C. The vapor-phase doping process may be performed at a pressure of 20 Pa to 2000 Pa for 1 second to 480 minutes. The doping gas 400 may be supplied together with a carrier gas and hydrogen gas. An inert gas such as nitrogen gas may be used as a carrier gas. In the gas-phase doping process, the total flow rate of hydrogen gas, the doping gas 400, and the carrier gas may be 0.01 sccm to 2000 sccm. Through the gas-phase doping process, the doping gas 400 may be injected into the substrate 10 through the sidewalls 19c and bottom 19b of the trench 19. Thus, a doped region 40 may be formed in the substrate 10 and on the sidewalls 19c and bottom 19b of the trench 19. The doped region 40 may include a dopant 401. The dopant 401 may include a Group III element. For example, the dopant 401 may include boron (B). For another example, the dopant 401 may include aluminum (Al), indium (In), and / or gallium (Ga). For another example, the doping gas 400 and the dopant 401 may include a Group V element.

[0025] When the doping region 40 is formed by an ion implantation process or a plasma implantation process, it is difficult to control the position and doping concentration of the implanted dopant 401. In this case, the doping region 40 may have a non-uniform thickness and a non-uniform doping concentration. Also, the doping region 40 may have a relatively large thickness and a high doping concentration.

[0026] According to the embodiment, the doping region 40 is formed by a gas-phase doping process, so that the doping gas 400 can be uniformly injected onto the sidewalls 19c and bottom surface 19b of the trench 19. Therefore, the doping region 40 can conformally cover the sidewalls 19c and bottom surface 19b of the trench 19 and have a uniform thickness. For example, the thickness tolerance of the doping region 40 can be 15% or less. Herein, the tolerance of a given configuration can refer to the difference between the maximum and minimum values of the configuration. The doping region 40 can include a side portion 40X and a bottom portion 40Y. The side portion 40X of the doping region 40 can be provided on the sidewall 19c of the trench 19 and can contact the sidewall 19c of the trench 19. The side portion 40X of the doping region 40 can have a first thickness T1, which can be substantially uniform. For example, the tolerance of the first thickness T1 can be 15% or less. The bottom 40Y of the doping region 40 may be provided on the bottom surface 19b of the trench 19 and may contact the bottom surface 19b of the trench 19. The bottom 40Y of the doping region 40 may be connected to the side portion 40X. The bottom 40Y of the doping region 40 may have a second thickness T2. The second thickness T2 may be substantially uniform. For example, the tolerance of the second thickness T2 may be 15% or less. The second thickness T2 may be the same as or similar to the first thickness T1. For example, the second thickness T2 may be 85% to 115% of the first thickness T1.

[0027] Because the doping region 40 is formed by a gas phase doping process, it is possible to form the doping region 40 to a small thickness. For example, the first thickness T1 may be approximately 30 nm to 180 nm, and the second thickness T2 may be approximately 30 nm to 180 nm.

[0028] Because the doped region 40 is formed by a gas-phase doping process, the doped region 40 may have a uniform dopant 401 concentration. For example, the dopant 401 concentration of the doped region 40 may have a tolerance of 15% or less. For example, the dopant 401 concentration of the side portion 40X may have a tolerance of 15% or less. The dopant 401 concentration of the bottom portion 40Y may have a tolerance of 15% or less. The dopant 401 concentration of the bottom portion 40Y may be 85% to 115% of the dopant 401 concentration of the side portion 40X. Herein, the dopant 401 concentration may be expressed as the number of dopants 401 per unit area. For example, the number of dopants 401 per unit area of the side portion 40X of the doped region 40 may be 85% to 115% of the number of dopants 401 per unit area of the bottom portion 40Y.

[0029] The doping region 40 may have one surface in contact with the trench 19 and another surface opposite the one surface in contact with the substrate 10. The maximum concentration of the dopant 401 may be measured on either one of the one surface and the other surface of the doping region 40. The minimum concentration of the dopant 401 may be measured at the midpoint between the one surface and the other surface of the doping region 40.

[0030] Since the doped region 40 is formed by a gas phase doping process, the concentration of the dopant 401 in the doped region 40 can be easily adjusted. The doped region 40 can have a relatively low concentration of the dopant 401. The number of dopants 401 per unit area of the doped region 40 is 5.0×10 11 atoms / cm 2 ~1.0x10 14 atoms / cm 2 The number of dopants 401 per unit area of the side 40X can be 5.0×10 11 atoms / cm 2 ~1.0x10 14 atoms / cm 2 and the number of dopants 401 per unit area of the bottom 40Y is 5.0×1011 atoms / cm 2 ~1.0x10 14 atoms / cm 2 It could be.

[0031] The doping region 40 further includes an extension (not shown), which may contact the first surface 10 a of the substrate 10 .

[0032] After the vapor-phase doping process is completed, a second purge process (S30) may be performed. The second purge process (S30) may include supplying an oxygen purge gas onto the doping region 40. The temperature of the second purge process is lower than the vapor-phase doping process temperature but higher than the temperature of the first purge process. For example, the second purge process may be performed at a temperature of approximately 200°C to 800°C. The second purge process may be performed at a pressure of 20 Pa to 2000 Pa for 1 second to 480 minutes. The oxygen purge gas may be supplied together with a carrier gas. An inert gas such as nitrogen gas may be used as the carrier gas. The total flow rate of the oxygen purge gas and the carrier gas in the second purge process may be 0.01 sccm to 2000 sccm.

[0033] The second purge process can prevent the doping gas 400 or dopant 401 injected into the substrate 10 from being released to the outside. That is, the second purge process can prevent outgassing or out-diffusion of the injected doping gas 400. While performing the second purge process (S30), the exposed surface of the doping region 40 can be oxidized. The thickness of the oxidized surface is between 1 Å and 30 Å, but is not limited thereto.

[0034] As another example, at least one of performing the first purge process (S10) and performing the second purge process (S30) may be omitted.

[0035] 2D, a buried pattern 25 may be formed in the trench 19 to cover the doping region 40. The buried pattern 25 may be provided on the sidewall 19c and bottom 19b of the trench 19 and fill the trench 19. One surface of the side 40X and one surface of the bottom 40Y of the doping region 40 may be exposed to the trench 19. One surface of the side 40X and one surface of the bottom 40Y of the doping region 40 may contact the buried pattern 25. One surface of the side 40X of the doping region 40 may correspond to the sidewall 19c of the trench 19. One surface of the bottom of the doping region 40 may correspond to the bottom 19b of the trench 19. The buried pattern 25 may include, for example, a conductive material, an insulating material, or a semiconductor material. The buried pattern 25 may be a gate electrode, an isolation layer, or a deep isolation layer. Although not shown, an insulating pattern may be further formed between the buried pattern 25 and the doping region 40.

[0036] FIG. 2E is a view illustrating a semiconductor device including a doped region according to an embodiment.

[0037] Referring to FIG. 2E, a semiconductor device may include a substrate 10, a doping region 40, and a buried pattern 25. The semiconductor device may be an image sensor. The substrate 10, the doping region 40, and the buried pattern 25 may be formed as in the examples of FIGS. 2A to 2D and 3. However, the thickness T2' of the bottom 40Y of the doping region 40 may be greater than the thickness T1' of the side 40X. The side 40X' of the doping region 40 may include an upper portion and a lower portion. The lower portion of the side 40X' of the doping region 40 may be disposed between the upper portion and the bottom 40Y of the side 40X'. The upper portion of the side 40' of the doping region 40 may have a smaller thickness than the lower portion of the side 40X'. For example, the thickness T1' of the side 40X' of the doping region 40 may decrease toward the top surface of the doping region 40. According to the embodiment, since the doping region 40 is formed by a gas-phase doping process, it is possible to form the thickness T2' of the bottom portion 40Y of the doping region 40 to be greater than the thickness T1' of the side portion 40X. The dopant concentration of the doping region 40 may be the same as that described above.

[0038] 4A is a view illustrating a semiconductor device including a doped region according to an embodiment, and FIG. 4B is an enlarged view of region A of FIG. 4A.

[0039] 4A and 4B, a semiconductor device may include a substrate 10, a doping region 40, and a buried pattern 25. The substrate 10, the doping region 40, and the buried pattern 25 may be formed as in the examples of Figures 2A to 2D and 3. For example, the doping region 40 may be formed by a gas phase doping process.

[0040] The side 40X of the doping region 40 may include a first region 41X and a second region 42X. The first region 41X of the side 40X of the doping region 40 may contact the sidewall 19c of the trench 19. For example, the second region 42X of the side 40X of the doping region 40 may be interposed between the substrate 10 and the first region 41X. The bottom 40Y of the doping region 40 may include a first region 41Y and a second region 42Y. The first region 41Y of the bottom 40Y of the doping region 40 may contact the bottom surface 19b of the trench 19. The first region 41Y of the bottom 40Y of the doping region 40 may be connected to the first region 41X of the side 40X of the doping region 40. The second region 42Y of the bottom 40Y of the doping region 40 may be interposed between the substrate 10 and the first region 41Y of the bottom 40Y. The second region 42Y of the bottom 40Y of the doping region 40 may be connected to the second region 42X of the side 40X. Hereinafter, unless otherwise specified, the first region 41X, 41Y of the doping region 40 may refer to the region including the first region 41X of the side 40X and the first region 41Y of the bottom 40Y. The second region 42X, 42Y of the doping region 40 may refer to the second region 42X of the side 40X and the second region 42Y of the bottom 40Y. The second region 42X, 42Y of the doping region 40 may be a peripheral region.

[0041] The first regions 41X and 41Y of the doping region 40 may be auxiliary element regions. For example, as shown in FIG. 4B, the first regions 41X and 41Y of the doping region 40 may include a dopant 401 and a first auxiliary element 403. The first auxiliary element 403 may be a different element from the dopant 401. For example, the first auxiliary element 403 may be chlorine. As another example, the first auxiliary element 403 may include fluorine or hydrogen. The thickness of the first regions 41X and 41Y of the doping region 40 may be smaller than the thickness of the doping region 40. For example, the thickness T3 of the first region 41X of the side 40X of the doping region 40 may be smaller than the thickness T1 of the side 40X at a corresponding position. The thickness T4 of the first region 41Y of the bottom 40Y of the doping region 40 may be smaller than the thickness T2 of the bottom 40Y at a corresponding position. The thickness T3 of the first region 41X of the side 40X of the doping region 40 may have a tolerance of 15% or less. The thickness T3 of the first region 41Y of the bottom 40Y of the doping region 40 may have a tolerance of 15% or less. The thickness T3 of the first region 41X of the side 40X of the doping region 40 may be 85% to 115% of the thickness T4 of the first region 41Y of the bottom 40Y.

[0042] The concentration of the first auxiliary element 403 in the first regions 41X and 41Y of the doping region 40 may be lower than the concentration of the dopant 401 in the first regions 41X and 41Y. Therefore, the electrical characteristics of the image sensor may be improved. The concentration of the first auxiliary element 403 in the first region 41X of the side portion 40X of the doping region 40 may be 85% to 115% of the concentration of the first auxiliary element 403 in the first region 41X of the bottom portion 40Y.

[0043] The second regions 42X, 42Y of the doped region 40 may contain the dopant 401 but may not contain the first auxiliary element 403. The concentration of the dopant 401 in the second region 42X of the side portion 40X of the doped region 40 may be 85% to 115% of the concentration of the dopant 401 in the second region 42Y of the bottom portion 40Y. The concentration of the dopant 401 in the second regions 42X, 42Y of the doped region 40 may be greater than the concentration of the first auxiliary element 403 in the first regions 41X, 41Y.

[0044] The first thickness T1, the second thickness T2 of the doping region 40, the concentration of the dopant 401 in the side portion 40X, and the concentration of the dopant 401 in the bottom portion 40Y can satisfy the conditions described in the examples of Figures 2B and 2C.

[0045] 5A and 5C are views illustrating the manufacturing method of a semiconductor device according to an embodiment, and FIG. 5B is an enlarged view of region A of FIG. 5A.

[0046] 5A and 5B, a trench 19 may be formed on a first surface 10a of a substrate 10. An insulating pattern 21 may be formed in the trench 19 to cover a bottom surface 19b and a sidewall 19c of the trench 19. Although not shown, the insulating pattern 21 may extend further onto the first surface 10a of the substrate 10. The insulating pattern 21 may have an amorphous structure. For example, the insulating pattern 21 may include a silicon-based insulating material such as silicon oxide. As another example, the insulating pattern 21 may include a high-dielectric material such as hafnium oxide and / or aluminum oxide.

[0047] The doping region 40 may be formed by substantially the same method as described with reference to FIGS. 2B and 2C. However, the vapor-phase doping process may be performed after the insulating pattern 21 is formed. The doping gas 400 may be provided on the insulating pattern 21. The doping gas 400 may migrate into the substrate 10 through the insulating pattern 21 to form the doping region 40. Therefore, as shown in FIG. 5B, the doping region 40 may include a dopant 401, and the insulating pattern 21 may further include a first additional element 401A. The first additional element 401A may be the same element as the dopant 401 of the doping region 40. For example, the first additional element 401A may be a Group III element such as boron. As another example, the first additional element 401A may include a Group V element. Because the insulating pattern 21 has an amorphous structure and functions as an insulator, the first additional element 401A may not function as a dopant in the insulating pattern 21. The first additional element 401A may be disposed adjacent to the doping region 40 or the trench 19 in the insulating pattern 21. The concentration of the dopant 401 in the doping region 40, the first thickness T1, and the second thickness T2 may satisfy the conditions described above with reference to FIGS. 2B and 2C.

[0048] 5C, a buried pattern 25 may be formed in the insulating pattern 21 to fill the trench 19. The insulating pattern 21 may be interposed between the doping region 40 and the buried pattern 25.

[0049] FIG. 5D is a diagram illustrating the doping region and its fabrication according to the embodiment, and corresponds to an enlarged view of region A in FIG. 5C.

[0050] Referring to Figures 5C and 5D, the first regions 41X, 41Y and the second regions 42X, 42Y of the doping region 40 may be substantially the same as those described in the examples of the first regions 41X, 41Y and the second regions 42X, 42Y of Figures 4A and 4B, respectively.

[0051] An insulating pattern 21 may be formed on the trench 19 of the substrate 10. A gas-phase doping process may be performed on the insulating pattern 21 to form a doped region 40. The insulating pattern 21 may further include a second auxiliary element 403A in addition to a first additional element 401A. The first additional element 401A may be the same element as the dopant 401 of the doped region 40. The second auxiliary element 403A may be the same material as the first auxiliary element 403 in the first regions 41X and 41Y. The concentration of the second auxiliary element 403A may be less than the concentration of the first additional element 401A, but is not limited thereto.

[0052] Figure 6 is a plan view showing an image sensor according to an embodiment. Figure 7A is a cross-sectional view taken along line II' in Figure 6. Figure 7B is an enlarged view of region B in Figure 7A. Hereinafter, any overlapping content with that previously described will be omitted.

[0053] 6, 7A, and 7B, the image sensor may include a first substrate 100, a first wiring layer 800, a first doping region 410, a first isolation pattern 210, an element isolation pattern 220, a gate pattern 300, a color filter CF, and a microlens layer 600.

[0054] The first substrate 100 may have a first surface 100a and a second surface 100b opposite to each other. The first surface 100a of the first substrate 100 is the front surface, and the second surface 100b is the rear surface. Light may be incident on the second surface 100b of the first substrate 100.

[0055] As shown in FIG. 6, the first substrate 100 may include a pixel array region APS, an optical black region OB, and a pad region PAD in a plan view. The pixel array region APS may be disposed in a central portion of the first substrate 100 in a plan view. The pixel array region APS may include a plurality of pixel regions PX. The pixels described with reference to FIG. 1 may be formed in the pixel regions PX of the substrate 100. For example, pixel components may be provided in the pixel regions PX. The pixel regions PX may output photoelectric signals from incident light. The pixel regions PX may be arranged two-dimensionally in rows and columns. The rows may be parallel to a first direction D1, and the columns may be parallel to a second direction D2. In this specification, the first direction D1 may be parallel to a first surface 100a of the first substrate 100. The second direction D2 is parallel to the first surface 100a of the first substrate 100 and may be different from the first direction D1. For example, the second direction D2 can be substantially perpendicular to the first direction D1. The third direction D3 can intersect the first direction D1 and the second direction D2. For example, the third direction D3 can be substantially perpendicular to the first surface 100a of the substrate 100.

[0056] The pad area PAD may be provided at an edge portion of the first substrate 100 and may surround the pixel array area APS. A pad terminal 900 may be provided on the pad area PAD. The pad terminal 900 may output an electrical signal generated in the pixel area PX to the outside, or an external electrical signal or voltage may be transmitted to the pixel area PX through the pad terminal 900. Because the pad area PAD is provided at the edge portion of the first substrate 100, the pad terminal 900 may be easily connected to the outside. For simplicity, the following description will be limited to a single pad terminal 900. The optical black area OB will be described later. The pixel array area APS of the sensor chip of the image sensor will be described in more detail.

[0057] The first substrate 100 may be a semiconductor substrate or an SOI (Silicon on Insulator) substrate. The first substrate 100 may further include a group III element. The group III element is an impurity of a first conductivity type. The first substrate 100 may include an impurity of the first conductivity type to have the first conductivity type. The first conductivity type may be P-type. For example, the impurity of the first conductivity type may include aluminum (Al), boron (B), indium (In), and / or gallium (Ga). The first substrate 100 may have a plurality of pixel regions PX.

[0058] As shown in FIGS. 7A and 7B, the first substrate 100 may include a photoelectric conversion region PD. The photoelectric conversion region PD may be interposed between the first surface 100a and the second surface 100b of the substrate 100. The photoelectric conversion region PD may be provided in each pixel region PX within the substrate 100. Each photoelectric conversion region PD may perform the same function and role as the photoelectric conversion region PD of FIG. 1. The photoelectric conversion region PD may further include a group V element. The group V element is a second conductive type impurity. The photoelectric conversion region PD is a region within the first substrate 100 doped with second conductive type impurities. The second conductive type impurities may have a conductivity type opposite to that of the first conductive type impurities. For example, the second conductive type may be n-type. The second conductive type impurities may include n-type impurities such as phosphorus, arsenic, bismuth, and / or antimony. The photoelectric conversion region PD may be disposed deep within the first surface 100a of the first substrate 100. In this specification, the term "impurities of a first conductivity type" may refer to dopants of the first conductivity type, and the term "impurities of a second conductivity type" may refer to dopants of the second conductivity type.

[0059] A first isolation pattern 210 may be provided in the first substrate 100 to define a pixel region PX. For example, the first isolation pattern 210 may be provided between the pixel regions PX of the first substrate 100. The first isolation pattern 210 is a pixel isolation pattern. The first isolation pattern 210 may be provided in a first trench 191, which may be recessed from the first surface 100a of the first substrate 100. The first isolation pattern 210 may be a deep trench isolation layer. The first isolation pattern 210 may penetrate through the second surface 100b of the first substrate 100. A width W2 of an upper surface of the first isolation pattern 210 may be greater than a width W1 of a lower surface of the first isolation pattern 210. In this case, the upper surface of the first isolation pattern 210 may be coplanar with the first surface 100a of the first substrate 100. The lower surface of the first isolation pattern 210 may be opposite to the upper surface. The bottom surface of the first separated pattern 210 may be coplanar with the second surface 100 b of the first substrate 100 .

[0060] The first isolation pattern 210 may include a first insulating pattern 211, a conductive isolation pattern 215, and a capping pattern 217. The first insulating pattern 211 may be provided along the sidewall of the first trench 191. The first insulating pattern 211 may include, for example, a silicon-based insulating material (e.g., silicon nitride, silicon oxide, and / or silicon oxynitride) and / or a high-k material (e.g., hafnium oxide and / or aluminum oxide). As another example, the first insulating pattern 211 may include multiple layers, each of which may include different materials. The first insulating pattern 211 may have a lower refractive index than the first substrate 100. Therefore, crosstalk between the pixel regions PX of the first substrate 100 may be prevented or reduced.

[0061] The conductive isolation pattern 215 may be provided in the first trench 191 and cover the first insulating pattern 211. The conductive isolation pattern 215 may fill the lower portion of the first trench 191. The top surface of the conductive isolation pattern 215 may be disposed at a level lower than the first surface 100a of the first substrate 100. Therefore, the conductive isolation pattern 215 may not be provided on the upper sidewall of the first insulating pattern 211. In this specification, the term "level" may refer to a vertical level, and the term "level difference" may refer to a level difference in the third direction D3. The first insulating pattern 211 may be interposed between the conductive isolation pattern 215 and the substrate 100. The conductive isolation pattern 215 may be separated from the first substrate 100 by the first insulating pattern 211. Therefore, the conductive isolation pattern 215 may be electrically isolated from the first substrate 100 during operation of the image sensor.

[0062] The conductive isolation patterns 215 may include a crystalline semiconductor material, such as polysilicon. For example, the conductive isolation patterns 215 may further include a dopant. The dopant may include impurities of a first conductivity type or impurities of a second conductivity type. For example, the conductive isolation patterns 215 may include doped polysilicon.

[0063] Since the conductive isolation patterns 215 have a uniform dopant concentration, the characteristics of the image sensor can be improved. For example, the dopant concentration in the conductive isolation patterns 215 can have a tolerance of 15% or less. The number of dopants per unit area in the conductive isolation patterns 215 can be 5.0×10 11 atoms / cm 2 ~1.0x10 14 atoms / cm 2The conductive isolation patterns 215 may further include an auxiliary element. The auxiliary element may include chlorine. As another example, the auxiliary element may include fluorine or hydrogen. The concentration of the auxiliary element in the conductive isolation patterns 215 may be less than the concentration of the dopant in the conductive isolation patterns 215. Therefore, the reliability of the image sensor may be improved. As another example, the conductive isolation patterns 215 may include a conductive material such as a metal.

[0064] The top surface of the conductive separated pattern 215 may be convex downward. For example, the center portion of the top surface of the conductive separated pattern 215 may be positioned at a lower level than the edge portion of the top surface. However, the shape of the top surface of the conductive separated pattern 215 is not limited thereto and may be variously modified.

[0065] The capping pattern 217 may be disposed on the upper surface of the conductive isolation pattern 215. The capping pattern 217 may fill the upper portion of the first trench 191. The first insulating pattern 211 may further extend between the first substrate 100 and the capping pattern 217. For example, the first insulating pattern 211 may be interposed between the device isolation pattern 220 and the capping pattern 217. The capping pattern 217 may include, for example, a silicon-containing insulating material (e.g., silicon oxide, tetraethyl orthosilicate (TEOS), and / or silicon oxynitride).

[0066] A first doping region 410 may be provided in the first substrate 100 and may be in contact with the first insulating pattern 211. The first doping region 410 may be interposed between the first isolation pattern 210 and the first substrate 100. The first doping region 410 may be formed by substantially the same method as that described for the doping region 40 of FIGS. 2B and 2C. However, the first doping region 410 may not include a bottom portion.

[0067] During operation of the image sensor, the photoelectric conversion region PD may output a photoelectric signal from incident light. During the formation of the first trench 191, interface defects may be formed in the sidewall of the first trench 191. During operation of the image sensor, the interface defects may generate additional electrons (e.g., noise electrons). The electrons may generate dark current. For example, when the electrons are transferred to the photoelectric conversion region PD, not only a photoelectric signal but also a noise signal may be output from the pixel region PX of the first substrate 100. Here, the noise signal may include an electrical signal generated by the electrons generated by the interface defects. According to the embodiment, the first doping region 410 may contact the sidewall of the first trench 191. The noise electrons and dark current generated by the interface defects on the sidewall of the first trench 191 may be trapped by the first doping region 410. Therefore, the phenomenon of noise signals being output from the pixel region PX may be prevented, and the optical characteristics of the image sensor may be improved.

[0068] If the first doping region 410 has an excessively large thickness or an excessively high doping concentration, the size of the photoelectric conversion region PD may be reduced, and the full well capacity of the pixel region PX may be reduced. According to the embodiment, since the first doping region 410 is formed by a gas phase doping method, the first thickness T11 of the first doping region 410 may be relatively small. For example, the first thickness T11 may be approximately 30 nm to 180 nm. When the first thickness T11 is 180 nm or less, the full well capacity of the pixel region PX may be improved. When the first thickness T11 is 30 nm or more, the first doping region 410 may sufficiently remove noise signals.

[0069] The first doped region 410 includes a dopant, and the concentration of the dopant can satisfy the conditions described in FIGS. 2B and 2C. For example, the number of dopants per unit area of the first doped region 410 is 5.0×10 11 atoms / cm 2 ~1.0x1014 atoms / cm 2 The number of dopants per unit area of the first doped region 410 may be 5.0×10 11 atoms / cm 2 Since the number of dopants per unit area of the first doped region 410 is 1.0×10 14 atoms / cm 2 Since the number of dopants per unit area in the first doping region 410 has a tolerance of 15% or less, the full well capacitance of the pixel region PX can be improved. Since the number of dopants per unit area in the first doping region 410 has a tolerance of 15% or less, the optical characteristics of the image sensor can be further improved.

[0070] As shown in FIG. 7A, the first substrate 100 may include impurity regions 111. The impurity regions 111 may be disposed in the pixel regions PX within the first substrate 100. The impurity regions 111 may be disposed adjacent to the first surface 100a of the first substrate 100. The bottom surfaces of the impurity regions 111 may be disposed within the first substrate 100 and may be separated from the photoelectric conversion regions PD. The impurity regions 111 are regions doped with impurities of a second conductivity type (e.g., n-type impurities). The impurity regions 111 may be active regions. In this case, the active regions may refer to regions for operating transistors and may include the floating diffusion regions FD and source / drain regions of the transistors described with reference to FIG. 1. The transistors may include the transfer transistor Tx, source follower transistor Sx, reset transistor Rx, or selection transistor Ax described with reference to FIG. 1.

[0071] The isolation pattern 220 may be provided in the first substrate 100. The isolation pattern 220 may be provided in the second trench 192, which may be recessed from the first surface 100a of the first substrate 100. The isolation pattern 220 may define an active region. Specifically, in each pixel region PX, the isolation pattern 220 may define an impurity region 111, and the impurity regions 111 may be isolated from each other by the isolation pattern 220. For example, the isolation pattern 220 may be disposed on one side of one of the impurity regions 111 in the first substrate 100. The isolation pattern 220 may be a shallow isolation STI layer. For example, the height of the isolation pattern 220 may be smaller than the height of the first isolation pattern 210. A portion of the isolation pattern 220 may be disposed on a sidewall of the first insulating pattern 211. The isolation pattern 220 may include a silicon-based insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride. The isolation pattern 220 may include multiple layers, but is not limited to this.

[0072] 7B, the isolation pattern 220 may further include a first additional element region 240. The first additional element region 240 of the isolation pattern 220 may contact an upper sidewall of the first trench 191. For example, the first additional element region 240 may be disposed on an upper sidewall of the first insulating pattern 211 and may be interposed between the lower surface of the first wiring layer 800 and the upper surface of the first doping region 410. For example, the bottom surface of the first additional element region 240 may be physically connected to the upper surface of the first doping region 410. The first additional element region 240 may include a second additional element 401B. The second additional element 401B may include the same material as the dopant of the first doping region 410. For example, the second additional element 401B may include, but is not limited to, boron. The number of second additional elements 401B per unit area of the first additional element region 240 may be smaller than the number of dopants per unit area of the first doping region 410. The thickness T15 of the first additional element region 240 may be smaller than the first thickness T11. Therefore, the characteristics of the image sensor may be improved. The first additional element region 240 may be formed together with the first doping region 410 by a single vapor-phase doping process. For simplicity, the second additional element 401B is omitted in the drawings except for FIGS. 7B, 7D, and 7E, but the present invention is not limited thereto.

[0073] As shown in FIG. 7A , a gate pattern 300 may be disposed on the first surface 100a of the first substrate 100. The gate pattern 300 may function as a gate electrode of the transfer transistor Tx, source follower transistor Sx, reset transistor Rx, or select transistor Ax, as previously described in FIG. 1 . For example, the gate pattern 300 may include a transfer gate TG, a source follower gate SG, a reset gate RG, or a select gate AG. For simplicity, FIG. 7A illustrates a single gate pattern 300 disposed on each pixel region PX, but multiple gate patterns 300 may be disposed on each pixel region PX. Hereinafter, a single gate pattern 300 will be described for simplicity.

[0074] The gate pattern 300 may have a recessed gate structure. For example, the gate pattern 300 may include a first portion 310 and a second portion 320. The first portion 310 of the gate pattern 300 may protrude into the first substrate 100. For example, the first portion 310 of the gate pattern 300 may be provided in the third trench 193, and the third trench 193 may be recessed from the first surface 100a of the first substrate 100. The second portion 320 of the gate pattern 300 may be disposed on the first surface 100a of the first substrate 100. The second portion 320 of the gate pattern 300 may be connected to the first portion 310. Unlike what is illustrated, the gate pattern 300 may have a planar gate structure. In this case, the gate pattern 300 may not include the first portion 310. As another example, the gate pattern 300 may not include the second portion. The gate pattern 300 may include a metal material, a metal silicide material, doped polysilicon, and combinations thereof.

[0075] The image sensor may further include a gate insulating pattern 231. The gate insulating pattern 231 may be interposed between the gate pattern 300 and the first substrate 100. The gate insulating pattern 231 may include, for example, a silicon-based insulating material (e.g., silicon oxide, silicon nitride, and / or silicon oxynitride) and / or a high-k material (e.g., hafnium oxide and / or aluminum oxide).

[0076] A first wiring layer 800 may be disposed on the first surface 100a of the first substrate 100. The first wiring layer 800 may include a first insulating layer 810, a second insulating layer 820, and a first conductive structure 830. The first insulating layer 810 may be provided on the first surface 100a of the first substrate 100 and on sidewalls of the gate pattern 300. The second insulating layer 820 may be stacked on the first insulating layer 810. The first and second insulating layers 810 and 820 may include a silicon-based insulating material such as, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0077] A first conductive structure 830 may be provided in the insulating layers 810 and 820. The first conductive structure 830 may include a contact plug portion, a wiring portion, and a via portion. The contact plug portion may be provided in the first insulating layer 810 or the lowermost second insulating layer 820 and may be electrically connected to any one of the impurity region 111 and the gate pattern 300. The wiring portion of the first conductive structure 830 may be interposed between two adjacent insulating layers 810 and 820. The wiring portion may be connected to the contact plug portion. The via portion of the first conductive structure 830 may penetrate at least one of the second insulating layers 820 and be connected to the wiring portion. The first conductive structure 830 may transmit a photoelectric signal output from the photoelectric conversion region PD.

[0078] The color filters CF may be disposed on the pixel regions PX on the second surface 100b of the first substrate 100. For example, the color filters CF may be provided at positions corresponding to the photoelectric conversion regions PD. The color filters CF may be disposed next to each other. Each of the color filters CF may include one of a red color filter, a blue color filter, and a green color filter. For example, the color filters CF may be arranged in an array along a first direction D1 and a second direction D2 in a plan view.

[0079] The image sensor may further include a fence pattern 550. The fence pattern 550 may be disposed on the first separation pattern 210. For example, the fence pattern 550 may overlap the separation pattern 210 in a plan view. The fence pattern 550 may be interposed between two adjacent color filters CF to separate the color filters CF. The fence pattern 550 may have a grid shape in a plan view and may surround each pixel region PX. The fence pattern 550 may include a metal, a metal nitride, or a low refractive index material. For example, the fence pattern 550 may include titanium and / or titanium nitride. The low refractive index material may include a polymer and silica nanoparticles within the polymer. The low refractive index material may have insulating properties.

[0080] The image sensor may further include an insulating layer 500. The insulating layer 500 may cover the second surface 100b of the first substrate 100 and the lower surface of the separation pattern 210. The insulating layer 500 may be interposed between the first substrate 100 and the color filter CF and between the separation pattern 210 and the fence pattern 550. The insulating layer 500 is a rear insulating layer. The insulating layer 500 may include a bottom antireflective coating (BARC) layer. The insulating layer 500 may include multiple layers. For example, the insulating layer 500 may include a fixed charge layer, a buried insulating layer, a silicon nitride layer, and a capping layer stacked on the second surface 100b of the first substrate 100. The fixed charge layer may be made of a metal oxide or metal fluoride containing at least one metal selected from the group consisting of hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), yttrium, and lanthanides. The buried insulating layer may include tetraethylorthosilicate (TEOS) or silicon oxide. The capping layer may include a metal oxide layer such as hafnium oxide. At least one of the fixed charge layer, buried insulating layer, silicon nitride layer, and capping layer may be omitted.

[0081] The image sensor may further include a protective layer 530. The protective layer 530 may be interposed between the insulating layer 500 and the color filter CF and between the fence pattern 550 and the color filter CF. For example, the protective layer 530 may include aluminum oxide or hafnium oxide.

[0082] The microlens layer 600 may be disposed on the second surface 100b of the first substrate 100. For example, the microlens layer 600 may be disposed on the lower surface of the color filter CF. The microlens layer 600 may include a planar portion and a lens portion. The lens portions may be provided at positions corresponding to the photoelectric conversion regions PD of the first substrate 100 and may protrude away from the second surface 100b of the first substrate 100. The lens portions may be arranged in an array along a first direction D1 and a second direction D2 in a planar view. The planar portion of the microlens layer 600 may be interposed between the color filter CF and the lens portion. The planar portion may be integrally formed with the lens portion and connected without an interface. Alternatively, the planar portion may be omitted, and the lens portions of the microlens layer 600 may not be connected to each other. The microlens layer 600 is transparent and thus allows light to pass through. The microlens layer 600 may include an organic material such as a polymer.

[0083] The image sensor may further include a lens coating layer (not shown), which conformally covers the lower surface of the microlens layer 600 to protect the microlens layer 600. The lens coating layer may be transparent.

[0084] 7C is an enlarged view of region B in FIG. 7A, illustrating an isolation pattern, a first isolation pattern, and a first doping region according to an embodiment, and FIG. 7D is an enlarged view of region BB in FIG. 7C.

[0085] 7C and 7D, the first region 411 and the second region 412 of the first doping region 410 may be substantially the same as the examples of the first region 41X and the second region 42X of the side 40X of the doping region 40 in FIGS. 4A and 4B. For example, the first region 411 of the first doping region 410 may include a dopant and a first auxiliary element. The second region 412 of the first doping region 410 may include a dopant but not the first auxiliary element.

[0086] The isolation pattern 220 may include a first additional element region 240. The arrangement, thickness T15, and concentration of the second additional element 401B of the first additional element region 240 may be the same as those described in the example of the arrangement, thickness T15, and concentration of the second additional element 401B of the first additional element region 240 of FIG. 7B . However, the first additional element region 240 may include a first sub-region 241 and a second sub-region 242. The first sub-region 241 may contact the first trench 191. For example, the first sub-region 241 may be disposed on an upper sidewall of the first insulating pattern 211. The first sub-region 241 may be interposed between the second sub-region 242 and the first insulating pattern 211. The first sub-region 241 may be an auxiliary element region. The first sub-region 241 may include a third auxiliary element 403B in addition to the second additional element 401B. The third auxiliary element 403B may be the same element as the first auxiliary element 403 in the first region 411 of the first doping region 410. As an example, the third auxiliary element 403B may be chlorine, fluorine, or hydrogen. The second sub-region 242 may include the second additional element 401B but may not include the third auxiliary element 403B.

[0087] 7E is a view illustrating an element isolation pattern, a first isolation pattern, and a first doping region according to an embodiment, and is an enlarged view of region BB in FIG. 7C. In the description of FIG. 7E, both FIGS. 5C and 5D will be referred to.

[0088] 7E, the first doping region 410 may include a first region 411 and a second region 412. The isolation pattern 220 may include a first additional element region 240. The first doping region 410, the isolation pattern 220, and the first additional element region 240 are the same as those described in the examples of FIGS. 7C and 7D.

[0089] However, the first insulating pattern 211 may further include a first additional element 401A. The first additional element 401A may be the same element as the dopant 401 in the doping region 410. The formation of the first doping region 410 and the first insulating pattern 211 may be performed by the method described for the example of the doping region 40 in FIGS. 5C and 5D. For example, the first doping region 410 may be formed by performing a vapor phase doping process in the first trench 191 and on the first insulating pattern 211. Therefore, the first insulating pattern 211 may further include a first additional element 401A as shown in FIG. 7E, and the first additional element 401A may be the same material as the dopant 401 in the first doping region 410.

[0090] The first insulating pattern 211 may further include second auxiliary elements 403A. The second auxiliary elements 403A may be the same element as the first auxiliary elements 403 and the third auxiliary elements 403B. The number of the second auxiliary elements 403A per unit area in the first insulating pattern 211 may be smaller than the number of the first additional elements 401A per unit area in the first insulating pattern 211. Therefore, the characteristics of the image sensor may be improved.

[0091] Unlike the illustration, the first auxiliary element 403, the second auxiliary element 403A, and the third auxiliary element 403B may be omitted, in which case the first insulating pattern 211 and the first doping region 410 may be substantially the same as those described in the examples of the insulating pattern 21 and the doping region 40 in FIGS. 5A and 5B, respectively.

[0092] FIG. 7F is a view illustrating an element isolation pattern, a first isolation pattern, and a first doping region according to an embodiment, and is an enlarged view of region C in FIG. 7A.

[0093] 7F, the isolation pattern 220 may include multiple layers. The isolation pattern 220 may include a second insulating pattern 221, a third insulating pattern 223, and a buried insulating pattern 225. The second insulating pattern 221 may conformally cover the sidewalls and bottom surface of the second trench 192. The second insulating pattern 221 may include an oxide such as silicon oxide and / or silicon oxynitride. The buried insulating pattern 225 may be disposed on the second insulating pattern 221. The buried insulating pattern 225 may fill the second trench 192. For example, the buried insulating pattern 225 may include silicon oxide, tetraethyl orthosilicate (TEOS), and / or silicon oxynitride. The third insulating pattern 223 may be interposed between the second insulating pattern 221 and the buried insulating pattern 225. The third insulating pattern 223 may include the second insulating pattern 221, the buried insulating pattern 225, and other materials. For example, the third insulating pattern 223 may include a nitride, such as silicon nitride, silicon oxynitride, and / or silicon carbonitride. Each of the second insulating pattern 221, the third insulating pattern 223, and the buried insulating pattern 225 may be in physical contact with the isolation pattern 200.

[0094] The isolation pattern 220 may include a first additional element region 240. The first additional element region 240 may include a first sub-region 2401, a second sub-region 2402, and a third sub-region 2403. The first sub-region 2401 may be provided in the second insulating pattern 221 and may contact a sidewall of the first trench 191. The second sub-region 2402 may be provided in the third insulating pattern 223 and may contact a sidewall of the first trench 191. The third sub-region 2403 may be provided in the buried insulating pattern 225 and may contact a sidewall of the first trench 191.

[0095] Each of the first sub-region 2401, the second sub-region 2402, and the third sub-region 2403 may include a second additional element. The second additional element may be the same material as the dopant in the first doping region 410. The concentration of the dopant in the first doping region 410 may be greater than the concentrations of the second additional element in the first sub-region 2401, the second sub-region 2402, and the third sub-region 2403. The first thickness T11 of the first doping region 410 may be greater than the thicknesses T15′ of the first sub-region 2401, the second sub-region 2402, and the third sub-region 2403. The thicknesses T15′ of the first sub-region 2401, the second sub-region 2402, and the third sub-region 2403 may be the same or different.

[0096] When the first doping region 410 further includes a first auxiliary element, each of the first sub-region 2401, the second sub-region 2402, and the third sub-region 2403 may further include a third auxiliary element. The third auxiliary element may be the same element as the first auxiliary element. For example, the first auxiliary element and the third auxiliary element may be chlorine, fluorine, or hydrogen. In each of the first to third sub-regions 2401, 2402, and 2403, the concentration of the second additional element may be greater than the concentration of the third auxiliary element.

[0097] The first doping region 410 may be formed together with the first sub-region 2401, the second sub-region 2402, and the third sub-region 2403 by a single vapor phase doping process.

[0098] In the drawings except for Figures 7A to 7F, Figures 9A to 9D, Figure 11A, Figure 11D, and Figures 12A to 12F, the first additional element region 240 is not shown for simplicity, but the present invention is not limited to this.

[0099] Figure 8A is a view illustrating a pixel array region of an image sensor according to an embodiment, and corresponds to a cross section taken along line II' in Figure 6. Figure 8B is an enlarged view of region B in Figure 8A.

[0100] 8A and 8B, a second isolation pattern 210A may be provided in the first substrate 100 to define a pixel region PX. The second isolation pattern 210A may be similar to the first isolation pattern 210 described in FIG. 7A. For example, the second isolation pattern 210A may be disposed between photoelectric conversion regions PD in the first substrate 100 to define the pixel region PX. However, the second isolation pattern 210A may be provided in a back trench 191A, and the back trench 191A may penetrate the second surface 100b of the first substrate 100. The bottom of the back trench 191A may be provided in the first substrate 100. The top surface of the second isolation pattern 210A may correspond to the bottom surface of the back trench 191A. The top surface of the second isolation pattern 210A may be spaced apart from the first surface 100a of the first substrate 100 and may be disposed at a lower level than the first surface 100a. Alternatively, the back trench 191A and the second isolation pattern 210A may further penetrate the first surface 100a of the first substrate 100. The bottom surface of the second isolation pattern 210A may be disposed at substantially the same level as the second surface 100b of the first substrate 100. A width W3 of the top surface of the second isolation pattern 210A may be smaller than a width W4 of the bottom surface of the second isolation pattern 210A. The second isolation pattern 210A does not include the conductive isolation pattern 215 and the capping pattern 217 described in Figures 7A and 7B, but may include the same material as the first insulating pattern 211. For example, the second isolation pattern 210A may include a silicon-based insulating material filled in the back trench 191A.

[0101] A pixel isolation region 120 may be provided in the first substrate 100. The pixel isolation region 120 may be provided between the upper surface of the second isolation pattern 210A and the first surface 100a of the first substrate 100. The pixel isolation region 120 may include a group III element. For example, the pixel isolation region 120 is a region doped with impurities of a first conductivity type (e.g., p-type). The pixel isolation region 120 may define a pixel region PX together with the second isolation pattern 210A. As another example, the first substrate 100 may not include a pixel isolation region 120.

[0102] A dopant region 410A may be provided in the first substrate 100 and may be in physical contact with the sidewalls and top surface of the second isolated pattern 210A. The dopant region 410A may have a bottom 410AY and a side 410AX. The dopant region 410A may be formed by the same method as described for the doped region 40 of FIGS. 2B and 2C. The bottom 410AY and side 410AX of the dopant region 410A may be substantially identical to the bottom 40Y and side 40X of the doped region 40 of FIGS. 2B and 2C, respectively. For example, as shown in FIG. 8B, the first thickness T21 of the side 410AX of the dopant region 410A may have a tolerance of 15% or less. The first thickness T21 may be 30 nm to 180 nm. The second thickness T22 of the bottom 410AY of the dopant region 410A may have a tolerance of 15% or less. The second thickness T22 may be 85% to 115% of the first thickness T21. The second thickness T22 may be 30 nm to 180 nm.

[0103] The doping concentration of side portion 410AX of dopant region 410A can have a tolerance of 15% or less, and the doping concentration of bottom portion 410AY can have a tolerance of 15% or less. The number of dopants per unit area in side portion 410AX of dopant region 410A can be 85% to 115% of the number of dopants per unit area in bottom portion 410AY. The number of dopants per unit area in side portion 410AX of dopant region 410A and the number of dopants per unit area in bottom portion 410AY can each be 5.0x10 11 atoms / cm 2 ~1.0x10 14 atoms / cm 2 It could be.

[0104] Although not shown, each of the side 410AX and bottom 410AY of the dopant region 410A includes a first region and a second region, which may be substantially the same as those described in the examples of the first regions 41X and 41Y and the second regions 42X and 42Y in FIGS. 4A and 4B. For example, the first region of the dopant region 410A contacts the sidewall and bottom of the back trench 191A and may further include a first auxiliary element (403 in FIG. 4B). The first region of the dopant region 410A may be interposed between the second isolation pattern 210A and the second region. The first auxiliary element may include chlorine, fluorine, or hydrogen. The second region of the dopant region 410A is a peripheral region and may not include the first auxiliary element. The concentration of the first auxiliary element in the first region of dopant region 410A may be less than the concentration of the dopant in the first region of dopant region 410A and the concentration of the dopant in the second region of dopant region 410A.

[0105] Figure 8C is a view illustrating a pixel array region of an image sensor according to an embodiment, and corresponds to a cross section taken along line II' in Figure 6. Figure 8D is an enlarged view of region B in Figure 8C.

[0106] 8C and 8D, a plurality of photoelectric conversion regions PD may be provided in each pixel region PX of the first substrate 100. A plurality of back trenches 191A may be provided between the plurality of photoelectric conversion regions PD. Some of the back trenches 191A may be formed between the pixel regions PX. The arrangement of some of the back trenches 191A may be the same as that described above for the example of the back trench 191A in FIGS. 8A and 8B. Other portions of the back trenches 191A may be formed within the pixel regions PX and overlap the pixel regions PX.

[0107] The second isolation pattern 210A may be the same as or similar to that described in the examples of FIGS. 8A and 8B. However, the second isolation pattern 210A may include a protrusion 2103 and a planarized portion 2105. The protrusions 2103 of the second isolation pattern 210A may be provided in the corresponding back trenches 191A. The protrusions 2103 of the second isolation pattern 210A may include a first protrusion 2101 and a second protrusion 2102. The first protrusion 2101 of the second isolation pattern 210A may be provided between the pixel regions PX to define the pixel regions PX. The second protrusion 2102 may be disposed within any one of the pixel regions PX. For example, the second protrusion 2102 may be interposed between the photoelectric conversion regions PD within any one of the pixel regions PX. The second protrusion 2102 may separate the photoelectric conversion regions PD within the pixel region PX. The width W3 of the upper surface of each protrusion 2103 may be smaller than the width W4' of the lower surface. At this time, the width W4′ of the lower surface of the protrusion 2103 may correspond to the width of the second separated pattern 210A on the second surface 100b of the first substrate 100.

[0108] The gate patterns 300 may be disposed in the pixel region PX. The first portions 310 of the gate patterns 300 may protrude into or toward the photoelectric conversion region PD. Each of the gate patterns 300 may be the transfer gate TG described in FIG. 1.

[0109] At least some of the impurity regions 111 may be floating diffusion regions FD. The floating diffusion regions FD may be disposed between the first portions 310 of the gate patterns 300 of each pixel region PX. The gate patterns 300 of each pixel region PX may share the floating diffusion regions FD. The floating diffusion regions FD may overlap the second protrusions 2102 of the second isolation patterns 210A in a vertical direction. In this specification, the vertical direction may refer to the third direction D3 or the direction opposite to the third direction D3. The floating diffusion regions FD may be disposed between the second protrusions 2102 and the first surface 100a of the first substrate 100.

[0110] The planarized portion 2105 of the second separated pattern 210A may be provided on the second surface 100b of the first substrate 100 and may cover the second surface 100b of the first substrate 100. The planarized portion 2105 of the second separated pattern 210A may be connected to the protrusion 2103 without an interface. The second separated pattern 210A may include at least one of the materials described in the examples of the insulating layer 500 of FIGS. 7A and 7B, and the insulating layer 500 may be omitted.

[0111] The image sensor may further include a protective film 530 and a fence pattern 550. The protective film 530 and the fence pattern 550 may be disposed on the lower surface of the planarized portion 2105 of the second isolation pattern 210A.

[0112] The dopant region 410A may have a side 410AX, a bottom 410AY, and an extension 410AZ. The side 410AX and bottom 410AY of the dopant region 410A may be substantially the same as those described in the examples of FIGS. 8A and 8B. For example, the bottom 410AY of the dopant region 410A may cover the top surface of the protrusion 2103 of the second isolation pattern 210A and contact the bottom surface of the back trench 191A. The side 410AX of the dopant region 410A may cover the sidewall of the protrusion 2103 of the second isolation pattern 210A and contact the sidewall of the back trench 191A.

[0113] The extension 410AZ of the dopant region 410A may cover the planarized portion 2105 of the second isolation pattern 210A. The extension 410AZ of the dopant region 410A may be connected to the side 410AX without a boundary surface. According to the embodiment, manufacturing the image sensor may include performing a thinning process on the second surface 100b of the first substrate 100. During the thinning process, interface defects may be formed on the second surface 100b of the first substrate 100. During operation of the image sensor, dark current may be generated due to the interface defects. The extension 410AZ of the dopant region 410A contacts the second surface 100b of the first substrate 100 and can trap noise electrons generated on the second surface 100b of the first substrate 100. Therefore, the generation of dark current may be prevented, and the optical characteristics of the image sensor may be further improved.

[0114] The dopant region 410A may have substantially the same thickness. Referring to FIG. 8D, the first thickness T21 of the side portion 410AX and the second thickness T22 of the bottom portion 410AY of the dopant region 410A may be the same as those described in FIG. 8B. The extension portion 410AZ of the dopant region 410A may have a third thickness T23. The third thickness T23 may have a tolerance of 15% or less with respect to the first thickness T21 and the second thickness T22. The third thickness T23 may be 85% to 115% of the first thickness T21 and 85% to 115% of the second thickness T22. The third thickness T23 may be 30 nm to 180 nm. The dopant concentration within the extension portion 410AZ of the dopant region 410A may have a tolerance of 15% or less. The dopant concentration in extensions 410AZ of dopant region 410A may be 85% to 115% of the dopant concentration in side portions 410AX and 85% to 115% of the dopant concentration in bottom portion 410AY. The number of dopants per unit area in extensions 410AZ of dopant region 410A is 5.0×10 11 atoms / cm 2 ~1.0x10 14 atoms / cm 2 It could be.

[0115] Although not shown, the side 410AX, bottom 410AY, and extension 410AZ of the dopant region 410A each include a first region and a second region, which may be substantially the same as those described in the examples of the first regions 41X, 41Y and second regions 42X, 42Y of the doping region 40 in FIGS. 4A and 4B. The first region of the extension 410AZ of the dopant region 410A contacts the second surface 100b of the first substrate 100 and may further include a first auxiliary element. The concentration of the first auxiliary element in the first region of the extension 410AZ may be lower than the concentration of the dopant in the first region of the extension 410AZ and the concentration of the dopant in the second region of the extension 410AZ. The first auxiliary element may be chlorine, fluorine, or hydrogen.

[0116] FIG. 8E is a view illustrating a pixel array region of an image sensor according to an embodiment, and corresponds to a cross section taken along line II' of FIG. Referring to FIG. 8E, a plurality of photoelectric conversion regions PD may be arranged within each pixel region PX.

[0117] The dopant region 410A, second isolation pattern 210A, floating diffusion region FD, and gate pattern 300 may be substantially the same as those described in the examples of FIGS. 8C and 8D. However, the second isolation pattern 210A may include a first protrusion 2101 and a planarized portion 2105, and may not include the second protrusion 2102 of the examples of FIGS. 8C and 8D. Instead, the first substrate 100 may include an isolation doping region 130. The isolation doping region 130 may be provided between the photoelectric conversion regions PD within each pixel region PX. The isolation doping region 130 may optically and electrically isolate the photoelectric conversion regions PD within each pixel region PX. The isolation doping region 130 may be disposed adjacent to the second surface 100b of the first substrate 100. The floating diffusion region FD may vertically overlap the isolation doping region 130. The top surface of the isolation doping region 130 may be separated from the bottom surface of the floating diffusion region FD. The isolated doped region 130 may include a group III element. The isolated doped region 130 is a region doped with impurities of a first conductivity type (for example, p-type).

[0118] Figure 9A is a view illustrating a pixel array region of an image sensor according to an embodiment, corresponding to a cross section taken along line II' in Figure 6. Figure 9B is an enlarged view of region B in Figure 9A. Figure 9C is a view illustrating first and second separation patterns according to an embodiment, corresponding to an enlarged view of region B in Figure 9A.

[0119] 9A, 9B, and 9C, a second separated pattern 210A may be provided between photoelectric conversion regions PD in the first substrate 100. The second separated pattern 210A may be substantially the same as that described in the example of FIG. 8E. For example, the second separated pattern 210A may include a first protrusion 2101 and a planarized portion 2105. As another example, the second separated pattern 210A may not include the planarized portion 2105.

[0120] A first separated pattern 210 may be provided between the photoelectric conversion regions PD in the first substrate 100. The first separated pattern 210 may be substantially the same as that described in the examples of FIGS. 7A to 7E. However, the lower surface of the first separated pattern 210 may be disposed at a higher level than the second surface 100b of the first substrate 100. The first separated pattern 210 may be disposed between the second separated pattern 210A and the first surface 100a of the first substrate 100. The first separated pattern 210 may be connected to the second separated pattern 210A. For example, the lower surface of the first separated pattern 210 may contact the upper surface of the first protrusion 2101 of the second separated pattern 210A. Therefore, the first separated pattern 210 and the second separated pattern 210A may define a pixel region PX.

[0121] A first doping region 410 may be provided in the first substrate 100 and may contact a sidewall of the first isolated pattern 210. The first doping region 410 may be substantially the same as that described in the examples of FIGS. 7A to 7E. At least a portion of the first doping region 410 may further contact an upper portion of a sidewall of the second isolated pattern 210A. The first thickness T11 and dopant concentration of the first doping region 410 may satisfy the conditions described in the examples of FIGS. 7A and 7B, 7C, 7D, or 7E. Although not shown, the first insulating pattern 211 may further include a first additional element 401A as described in the example of FIG. 7E.

[0122] 9B and 9C, the width W3 of the upper surface of the second separated pattern 210A may be smaller than the width W4 of the lower surface, and the width W2 of the upper surface of the first separated pattern 210 may be larger than the width W1 of the lower surface.

[0123] As shown in FIG. 9B, the width W3 of the upper surface of the second separated pattern 210A may be substantially the same as the width W1 of the lower surface of the first separated pattern 210.

[0124] As shown in FIG. 9C, the width W3 of the upper surface of the second separated pattern 210A may be greater than the width W1 of the lower surface of the first separated pattern 210.

[0125] FIG. 9D is a view illustrating a first isolation pattern, a second isolation pattern, and a first doping region according to an embodiment, and corresponds to an enlarged view of region B in FIG. 9A.

[0126] 9D, the width W1 of the bottom surface of the first isolated pattern 210 may be greater than the width W3 of the top surface of the second isolated pattern 210A. The first doping region 410 may include a first side 410X and a first bottom 410Y. The first side 410X and the first bottom 410Y of the first doping region 410 may be provided on the sidewall and bottom surface of the first isolated pattern 210, respectively. The first side 410X and the first bottom 410Y of the first doping region 410 may be substantially the same as the side 40X and the bottom 40Y of the doping region 40 in the examples of FIGS. 2B and 2C, 4A and 4B, or 5C and 5D, respectively. For example, the first thickness T11 of the first side 410X may be 85% to 115% of the second thickness T12 of the first bottom 410Y. The dopant concentration of the first side portion 410X may be 85% to 115% of the dopant concentration of the first bottom portion 410Y. The number of dopants per unit area of each of the first side portion 410X and the first bottom portion 410Y is 5.0×10 11 atoms / cm 2 ~1.0x10 14 atoms / cm 2 However, the second isolated pattern 210A may penetrate the first bottom portion 410Y of the first doping region 410 and contact the lower surface of the first isolated pattern 210.

[0127] As another example, the first insulating pattern 211 may further include the first additional element (401A in FIG. 5B) described in the examples of FIGS. 5A and 5B.

[0128] As another example, each of the first side 410X and the first bottom 410Y of the first doping region 410 may further include a first region and a second region. The first region and the second region of the first doping region 410 may be substantially the same as the first regions 41X, 41Y and the second regions 42X, 42Y of the doping region 40 in the examples of Figures 4A and 4B or 5C and 5D. For example, the first region of the first doping region 410 may further include a first auxiliary element.

[0129] As another example, the first region of the first doping region 410 may further include a first auxiliary element, and the first insulating pattern 211 may further include a first additional element and a second auxiliary element.

[0130] Figure 9E is a view illustrating a pixel array region of an image sensor according to an embodiment, and corresponds to a cross section taken along line II' in Figure 6. Figure 9F is an enlarged view of region B in Figure 9E.

[0131] 9E and 9F, the first and second separated patterns 210 and 210A may be substantially the same as those described in the examples of FIGS. 9A and 9C. The width W3 of the top surface of the second separated pattern 210A may be greater than the width W1 of the bottom surface of the first separated pattern 210.

[0132] A dopant region 410A may be provided in the first substrate 100 and contact the sidewalls and bottom surface of the back trench 191A. The dopant region 410A may include a side portion 410AX and a bottom portion 410AY, which may be substantially the same as those described in the examples of Figures 8A and 8B and 8C and 8D.

[0133] The dopant region 410A may further include an extension 410AZ, which may contact the second surface 100b of the first substrate 100. The extension 410AZ may be substantially the same as that described in the examples of Figures 8C and 8D. For example, the first thickness T21 of the side 410AX of the dopant region 410A, the second thickness T22 of the bottom 410AY, and the third thickness T23 of the extension 410AZ may satisfy the conditions described in the examples of Figures 8A and 8B and the examples of Figures 8C and 8D.

[0134] Contrary to what is shown in the drawing, the width W3 of the upper surface of the second isolated pattern 210A may be the same as or smaller than the width W1 of the lower surface of the first isolated pattern 210. In this case, the dopant region 410A may not include the bottom portion 410AY.

[0135] FIG. 9G is a view illustrating a pixel array region of an image sensor according to an embodiment, and corresponds to a cross section taken along line II' of FIG.

[0136] Referring to FIG. 9G, the first and second isolated patterns 210 and 210A may define pixel regions PX within the first substrate 100.

[0137] A first doping region 410 may be provided in the first substrate 100 and may contact a sidewall of the first isolation pattern 210. The first doping region 410 may be substantially the same as that described in the example of Figures 9A to 9D.

[0138] A dopant region 410A may be provided in the first substrate 100 and may contact the sidewalls of the first protruding portions 2101 and the upper surface of the planarized portion 2105 of the second isolated pattern 210A. The dopant region 410A may include a side portion 410AX and an extension portion 410AZ. The lower surface of the first isolated pattern 210 may have the same width as or a larger width than the upper surface of the second isolated pattern 210A, and the dopant region 410A may not include a bottom portion 410AY. As another example, if the lower surface of the first isolated pattern 210 has a larger width than the upper surface of the second isolated pattern 210A, the first doped region 410 may further include a first bottom portion 410Y as shown in FIG. 9D. As another example, if the lower surface of the first isolated pattern 210 has a smaller width than the upper surface of the second isolated pattern 210A, the dopant region 410A may further include a bottom portion (410AY as shown in FIG. 9F).

[0139] FIG. 9H is a view illustrating a pixel array region of an image sensor according to an embodiment, and corresponds to a cross section taken along line II' of FIG.

[0140] Referring to FIG. 9H, a plurality of photoelectric conversion regions PD may be provided within each pixel region PX.

[0141] The second isolated pattern 210A may include a first protruding portion 2101, a second protruding portion 2102, and a planarized portion 2105. The arrangement of the second protruding portion 2102, the floating diffusion region FD, and the gate pattern 300 may be substantially the same as that described in the examples of Figures 8C and 8D. For example, the upper surface of the second protruding portion 2102 may be disposed within the first substrate 100 and may not be in physical contact with the first isolated pattern 210.

[0142] The dopant region 410A may include a side portion 410AX and an extension portion 410AZ. The side portion 410AX of the dopant region 410A may be disposed on the sidewalls of the first and second protrusions 2101 and 2102 of the second isolated pattern 210A. The extension portion 410AZ may be disposed on the upper surface of the planarized portion 2105 of the second isolated pattern 210A and may contact the second surface 100b of the first substrate 100. As another example, either the bottom 410AY or the extension portion 410AZ of the dopant region 410A may be omitted. As another example, at least one of the first doping region 410 and the dopant region 410A may be omitted.

[0143] Figure 10A is a view illustrating a pixel array region of an image sensor according to an embodiment, and corresponds to a cross section taken along line II' in Figure 6. Figure 10B is an enlarged view of region D in Figure 10A.

[0144] 10A and 10B, the image sensor may include an isolation pattern 220, a first doping region 410, and a second doping region 420.

[0145] An isolation pattern 220 may be provided in the second trench 192. According to an embodiment, the isolation pattern 220 may include a second insulating pattern 221, a third insulating pattern 223, and a buried insulating pattern 225, as shown in Fig. 10B. The second insulating pattern 221, the third insulating pattern 223, and the buried insulating pattern 225 may be substantially the same as those described in Fig. 7F.

[0146] A second doping region 420 may be provided in the first substrate 100 and may contact the sidewalls and bottom surface of the isolation pattern 220. The second doping region 420 may be interposed between the isolation pattern 220 and the first substrate 100. The second doping region 420 may contact the sidewalls and bottom surface of the second trench 192.

[0147] The second doping region 420 may include a second side 420X and a second bottom 420Y, which may be substantially identical to the side 40X and bottom 40Y in the examples of FIGS. 2B and 2C. For example, the second side 420X and the second bottom 420Y may contact the sidewall and bottom surface of the second trench 192, respectively. Noise electrons generated by interface defects on the sidewall and bottom surface of the second trench 192 may be trapped by the second doping region 420.

[0148] The first thickness T31 of the second side portion 420X of the second doping region 420 may be 85% to 115% of the second thickness T32 of the second bottom portion 420Y. The tolerance of the first thickness T31 may be 15% or less, and the tolerance of the second thickness T32 may be 15% or less. The first thickness T31 may be approximately 30 nm to 180 nm, and the second thickness T32 may be 30 nm to 180 nm.

[0149] The dopant concentration in the second side 420X of the second doping region 420 may have a tolerance of 15% or less, and the dopant concentration in the second bottom 420Y may have a tolerance of 15% or less. The number of dopants per unit area in the second side 420X may be 85% to 115% of the number of dopants per unit area in the second bottom 420Y. The number of dopants per unit area in each of the second side 420X and second bottom 420Y may each be 5.0x10 11 atoms / cm 2 ~1.0x10 14 atoms / cm 2 It could be.

[0150] 10C, 10D, and 10E are views illustrating an isolation pattern and a second doping region according to an embodiment, and correspond to an enlarged view of region DD in FIG. 10B. Hereinafter, in the description of FIGS. 10C, 10D, and 10E, reference will be made to FIG. 10A.

[0151] 10C, 10D, and 10E, a first region 421X of a side 420X of the second doping region 420 may contact a sidewall of the second trench 192 and be interposed between the first substrate 100 and the second region 422X. A bottom 420Y of the second doping region 420 may include a first region 421Y and a second region 422Y. The first region 421Y of the bottom 420Y of the second doping region 420 may contact a bottom surface of the second trench 192 and be interposed between the first substrate 100 and the second region 422Y.

[0152] The first regions 421X, 421Y and second regions 422X, 422Y of the second doping region 420 may be substantially the same as those described above for the first regions 41X, 41Y and second regions 42X, 42Y of the doping region 40 in FIGS. 4A and 4B. For example, the first regions 421X, 421Y may include a dopant 401 and a first auxiliary element 403. The first auxiliary element 403 may include, for example, chlorine, fluorine, or hydrogen. The second regions 422X, 422Y of the second doping region 420 may be interposed between the first regions 421X, 421Y and the first substrate 100. The second regions 422X, 422Y may include the dopant 401 but not the first auxiliary element 403. As another example, the first regions 421X, 421Y of the second doping region 420 may not include the first auxiliary element 403.

[0153] 10C, forming the second doping region 420 may include performing a gas-phase doping process on the sidewalls and bottom surface of the second trench 192. Then, the second insulating pattern 221, the third insulating pattern 223, and the buried insulating pattern 225 may be formed in the second trench 192.

[0154] 10D, the second insulating pattern 221 may further include a first additional element 401A. The formation of the first additional element 401A and the second doped region 420 may be substantially the same as that described in the examples of FIGS. 5A and 5B or 5C and 5D. According to the embodiment, after the second insulating pattern 221 is formed in the second trench 192, a vapor-phase doping process may be performed on the second insulating pattern 221. During the vapor-phase doping process, the doping gas may migrate into the first substrate 100 through the second insulating pattern 221 to form the second doped region 420. Therefore, the second doped region 420 may include the dopant 401, and the second insulating pattern 221 may include the first additional element 401A. The first additional element 401A may be the same element as the dopant 401 of the second doped region 420.

[0155] The second insulating pattern 221 may further include a second auxiliary element 403A. The second auxiliary element 403A may be the same material as the first auxiliary element 403 of the second doping region 420. As another example, the first auxiliary element 403 and the second auxiliary element 403A may not be provided.

[0156] 10E, the third insulating pattern 223 may include a third additional element 401C, and the second insulating pattern 221 may include a first additional element 401A. Each of the third additional element 401C and the first additional element 401A may be the same element as the dopant 401 of the second doping region 420.

[0157] According to the embodiment, the second insulating pattern 221 and the third insulating pattern 223 may be sequentially formed in the second trench 192. Then, a vapor-phase doping process may be performed on the third insulating pattern 223. During the vapor-phase doping process, a doping gas may move into the first substrate 100 through the third insulating pattern 223 and the second insulating pattern 221 to form the second doped region 420. Therefore, the second doped region 420 may include the dopant 401, and the second insulating pattern 221 and the third insulating pattern 223 may include the first additional element 401A and the third additional element 401C, respectively.

[0158] As another example, a first vapor phase doping process may be formed on the second insulating pattern 221. After the first vapor phase doping process, a third insulating pattern 223 may be formed on the second insulating pattern 221. A second vapor phase doping process may be performed on the third insulating pattern 223. The first and second vapor phase doping processes may be performed under the conditions described in the example of FIG.

[0159] The first regions 411X and 421X of the doping region 410 may further include a first auxiliary element 403. The third insulating pattern 223 may further include a fourth auxiliary element 403C, and the second insulating pattern 221 may further include a second auxiliary element 403A. The first auxiliary element 403 of the second doping region 420 may be the same material as the second auxiliary element 403A and the fourth auxiliary element 403C. For example, each of the second auxiliary element 403A and the fourth auxiliary element 403C may be chlorine, fluorine, or hydrogen.

[0160] As another example, the first auxiliary element 403, the second auxiliary element 403A, and the fourth auxiliary element 403C may not be provided.

[0161] Figure 11A is a view illustrating a pixel array region of an image sensor according to an embodiment, and corresponds to a cross section taken along line II' in Figure 6. Figure 11B is an enlarged view of region E in Figure 11A. Figure 11C is an enlarged view of region F in Figure 11A.

[0162] 11A and 11B, the image sensor may include a first isolation pattern 210, an isolation pattern 220, a first doping region 410, a second doping region 420, a third doping region 430, and a backside doping region 440.

[0163] A third doped region 430 may be provided in the first substrate 100 and may contact the sidewalls and bottom surface of the gate insulating pattern 231. The third doped region 430 may be interposed between the gate insulating pattern 231 and the first substrate 100. The third isolated doped region 430 may be a region doped with impurities of a first conductivity type (e.g., p-type). The third doped region 430 may be formed by the method described for the doped region 40 of FIGS. 2B and 2C. The third doped region 430 may contact the sidewalls and bottom surface of the third trench 193. Electrons generated by interface defects on the sidewalls and bottom surface of the third trench 193 may be trapped by the third doped region 430. This prevents dark current from being generated by noise electrons, improving the optical characteristics of the image sensor.

[0164] A gate pattern 300 and a gate insulation pattern 231 may be provided in the third trench 193. For example, the gate pattern 300 may be the transfer transistor Tx described in FIG. 1. During operation of the image sensor, when a turn-on voltage is applied to the gate pattern 300, electrons generated in the photoelectric conversion region PD may be transferred to the floating diffusion region FD. Because the third doping region 430 is provided on the bottom surface and sidewalls of the gate pattern 300, electrons generated in the photoelectric conversion region PD may be transferred to the floating diffusion region FD more quickly through the third doping region 430. Therefore, the optical characteristics and sensing speed of the image sensor may be improved.

[0165] The third doping region 430 may include a third side 430X and a third bottom 430Y. The third side 430X and the third bottom 430Y of the third doping region 430 may be disposed on the side and bottom surfaces of the first portion 310 of the gate pattern 300, respectively. The third side 430X and the third bottom 430Y may contact the sidewall and bottom surface of the third trench 193, respectively. The third side 430X and the third bottom 430Y of the third doping region 430 may be substantially the same as the description of the side 40X and the bottom 40Y of the doping region 40 in FIGS. 2B and 2C, respectively. For example, as shown in FIG. 11B, the first thickness T41 of the third side 430X may be 85% to 115% of the second thickness T42 of the third bottom 430Y. The first thickness T41 may be approximately 30 nm to 180 nm, and the second thickness T42 may be approximately 30 nm to 180 nm. The dopant concentration in the third side portion 430X may have a tolerance of 15% or less. The dopant concentration in the third bottom portion 430Y may have a tolerance of 15% or less. The number of dopants per unit area in the third side portion 430X may be 85% to 115% of the number of dopants per unit area in the third bottom portion 430Y. The number of dopants per unit area in each of the third side portion 430X and the third bottom portion 430Y may each be 5.0x10 11 atoms / cm 2 ~1.0x10 14atoms / cm 2 It could be.

[0166] The third side 430X of the third doping region 430 may include a first region 431X and a second region 432X. The first region 431X of the third side 430X of the third doping region 430 may contact a sidewall of the gate insulation pattern 231 and be disposed between the gate insulation pattern 231 and the second region 432X. The third bottom 430Y of the third doping region 430 may include a first region 431Y and a second region 432Y. The first region 431Y of the third bottom 430Y of the third doping region 430 may contact a bottom surface of the gate insulation pattern 231 and be disposed between the gate insulation pattern 231 and the second region 432Y. The first regions 431X, 431Y and second regions 432X, 432Y of the third doping region 430 may be substantially the same as those described in the examples of the first regions 41X, 41Y and second regions 42X, 42Y of the doping region 40 in FIGS. 4A and 4B. For example, the first regions 431X, 431Y may include a dopant and a first auxiliary element. The second regions 432X, 432Y of the third doping region 430 may include a dopant but not the first auxiliary element. The concentrations of the dopant and the first auxiliary element may be the same as those described in FIGS. 4A and 4B.

[0167] Although not shown, the gate insulating pattern 231 may further include a first additional element. The first additional element in the gate insulating pattern 231 may be the same element as the dopant in the third doping region 430. If the first regions 431X and 431Y of the third doping region 430 further include a first auxiliary element, the gate insulating pattern 231 may include a second auxiliary element. The second auxiliary element may include the same material as the first auxiliary element. For example, the second auxiliary element may be chlorine, hydrogen, or fluorine. The first additional element and second auxiliary element in the gate insulating pattern 231 may be the same as those described in the example of the insulating pattern 21 of FIG. 5D.

[0168] As another example, the third doping region 430 may not include the first auxiliary element.

[0169] 11A and 11C, a backside doped region 440 may be provided in the first substrate 100 and may be in contact with the second surface 100b of the first substrate 100. The backside doped region 440 may prevent dark current from occurring due to interface defects on the second surface 100b of the first substrate 100. The interface defects may occur during a thinning process on the second surface 100b of the first substrate 100. Therefore, the optical characteristics of the image sensor may be further improved.

[0170] The backside doped region 440 can include a dopant. The dopant can include a Group III element. As an example, the dopant can include boron (B). As another example, the dopant can include aluminum (Al), indium (In), and / or gallium (Ga). For example, the number of dopants per unit area of the backside doped region 440 can be 5.0×10 11 atoms / cm 2 ~1.0x10 14 atoms / cm 2 The number of dopants per unit area of the back doped region 440 can be 5.0×10 11 atoms / cm 2 Since the number of dopants per unit area of the back doped region 440 is 1.0×10 14 atoms / cm 2 Since the full well capacitance of the pixel region PX is less than 15%, the dopant concentration of the back doped region 440 has a tolerance of 15% or less, which further improves the optical characteristics of the image sensor.

[0171] The thickness T51 of the back doped region 440 may have a tolerance of 15% or less. The thickness T51 of the back doped region 440 may be 30 nm to 180 nm. Because the first thickness is 180 nm or less, the full well capacitance of the pixel region PX may be further improved. The back doped region 440 may have a thickness T51 of 30 nm or more to sufficiently remove noise signals.

[0172] The first insulating pattern 211 may further include a third additional element region 212. The third additional element region 212 may be disposed between the back doped region 440 and the conductive isolation pattern 215 and may contact the second surface 100b of the first substrate 100. The third additional element region 212 may include an additional element, and the additional element may include the same material as the dopant of the back doped region 440. For example, the additional element in the third additional element region 212 may include boron. The number of additional elements per unit area of the third additional element region 212 may be less than the number of dopants per unit area of the first doped region 410. A thickness T55 of the third additional element region 212 may be less than a thickness T51 of the back doped region 440. The third additional element region 212 and the back doped region 440 may be formed by a single vapor doping process. For simplicity, the third additional element region 212 is omitted from the drawings except for FIG. 7C , but the present invention is not limited thereto.

[0173] According to the embodiment, at least one of the first doping region 410, the second doping region 420, the third doping region 430, and the backside doping region 440 may be omitted.

[0174] Figure 11D is a view illustrating a pixel array region of an image sensor according to an embodiment, and corresponds to a cross section taken along line II' in Figure 6. Figure 11E is an enlarged view of region G in Figure 11D.

[0175] 11D and 11E, the third trench 193 may include a first sub-trench 1931 and a second sub-trench 1932. The first sub-trench 1931 may be provided in the first substrate 100 and may be laterally separated from the isolation pattern 220. The second sub-trench 1932 may be disposed on the first sub-trench 1931 and connected to the first sub-trench 1931. The second sub-trench 1932 may have a width greater than that of the first sub-trench 1931. At least a portion of the second sub-trench 1932 may expose the isolation pattern 220. For example, the bottom surface of the second sub-trench 1932 may be provided in the isolation pattern 220. The slope of the second sidewall of the second sub-trench 1932 may be different from the slope of the first sidewall of the first sub-trench 1931. As shown in FIG. 11E, the third trench 193 may further have an edge 193E, which may be provided at a position where a first sidewall of the first sub-trench 1931 and a second sidewall of the second sub-trench 1932 meet.

[0176] The gate pattern 300 may include a first portion 310 and a second portion 320. The first portion 310 of the gate pattern 300 may include a vertical portion 311 and a horizontal portion 312. The vertical portion 311 may be provided in the first sub-trench 1931. The vertical portion 311 may protrude toward the photoelectric conversion region PD. Unlike what is shown, the bottom surface of the vertical portion 311 may be provided in the photoelectric conversion region PD. The vertical portion 311 of the gate pattern 300 may be disposed laterally with the device isolation pattern 220. The vertical portion 311 may not overlap with the device isolation pattern 220 in the vertical direction.

[0177] The horizontal portion 312 of the gate pattern 300 may be disposed between the vertical portion 311 and the second portion 320. The horizontal portion 312 may be provided in the second sub-trench 1932. The sidewalls of the horizontal portion 312 may have a different slope than the sidewalls of the vertical portion 311. For example, the horizontal portion 312 may be disposed on the vertical portion 311 and further protrude laterally. The horizontal portion 312 may protrude into the device isolation pattern 220 and overlap with the device isolation pattern 220 in the vertical direction. The width of the horizontal portion 312 of the gate pattern 300 may be greater than the width of the vertical portion 311. When the gate pattern 300 includes the horizontal portion 312, components in the pixel region PX can be more highly integrated.

[0178] The gate pattern 300 may be the transfer gate TG described in FIG. 1. A floating diffusion region FD may be disposed on one side of the gate pattern 300. For example, the first portion 310 of the gate pattern 300 may be disposed between the device isolation pattern 220 and the floating diffusion region FD. The floating diffusion region FD may function as a drain of the gate pattern 300.

[0179] The gate insulating pattern 231 may be interposed between the gate pattern 300 and the isolation pattern 220 and between the gate pattern 300 and the first substrate 100 .

[0180] A third doping region 430 may be provided in the first substrate 100 and may be in contact with the gate insulating pattern 231. The third doping region 430 may not be interposed between the gate insulating pattern 231 and the device isolation pattern 220. The third doping region 430 may include a third side 430X and a third bottom 430Y. The third bottom 430Y may be disposed on a lower surface of the vertical portion 311 of the gate pattern 300 and may be in contact with a bottom surface of the first sub-trench 1931. The third side 430X may include a first sub-side 430A and a second sub-side 430B. The first sub-side 430A may be disposed on a sidewall of the vertical portion 311 of the gate pattern 300 and may be in contact with a first sidewall of the first sub-trench 1931. The first sub-side 430A may be connected to the third bottom 430Y without an interface. The second sub-side 430B may be disposed on the sidewall of the horizontal portion 312 of the gate pattern 300 and may contact the second sidewall of the second sub-trench 1932. The second sub-side 430B may be connected to the first sub-side 430A without an interface.

[0181] The thickness of the third doping region 430 may be substantially uniform. For example, the second thickness T42 of the third bottom portion 430Y may have a tolerance of 15% or less. The first sub-thickness T411 of the first sub-side portion 430A may have a tolerance of 15% or less. The first sub-thickness T411 may be 85% to 115% of the second thickness T42. The second sub-thickness T412 of the second sub-side portion 430B may have a tolerance of 15% or less. The second sub-thickness T412 may be 85% to 115% of the second thickness T42 and 85% to 115% of the first sub-thickness T411. Each of the second thickness T42, the first sub-thickness T411, and the second sub-thickness T412 may be 30 nm to 180 nm. Therefore, the optical characteristics of the image sensor may be improved.

[0182] When the doped region is formed by ion implantation or plasma implantation, the thickness of the doped region in the edge region where the first and second sidewalls meet may be less than 85% of the thickness of the doped region on the first sidewall of the trench and the thickness of the doped region on the second sidewall, in which case dark current may be generated from the edge region.

[0183] According to the embodiment, the third sub-thickness T413 of the third doping region 430 on the edge 193E of the third trench 193 may be the same as or similar to the second thickness T42, the first sub-thickness T411, and the second sub-thickness T412. For example, the third sub-thickness T413 may be 85% to 115% of the second thickness T42, 85% to 115% of the first sub-thickness T411, and 85% to 115% of the second sub-thickness T412. The third sub-thickness T413 may be 30 nm to 180 nm. Therefore, the third doping region 430 may improve dark current generation at the edge 193E of the third trench 193.

[0184] The third doped region 430 may have a uniform dopant concentration and a low dopant concentration. For example, the dopant concentration of the third bottom portion 430Y may have a tolerance of 15% or less. The dopant concentration of the first sub-side portion 430A may have a tolerance of 15% or less. The dopant concentration of the first sub-side portion 430A may be 85% to 115% of the dopant concentration of the third bottom portion 430Y. The dopant concentration of the second sub-side portion 430B may have a tolerance of 15% or less. The dopant concentration of the second sub-side portion 430B may be 85% to 115% of the dopant concentration of the third bottom portion 430Y and 85% to 115% of the dopant concentration of the first sub-side portion 430A. For example, each of the third bottom portion 430Y, the first sub-side portion 430A, and the second sub-side portion 430B may have a dopant concentration of 5.0×10 11 atoms / cm 2 ~1.0x10 14 atoms / cm 2 Therefore, the optical characteristics of the image sensor can be further improved.

[0185] The isolation pattern 220 may further include a second additional element region 250. The second additional element region 250 may contact the gate insulating pattern 231 within the isolation pattern 220. The second additional element region 250 may contact the third trench 193. Specifically, the second additional element region 250 may contact the sidewall and bottom surface of the second sub-trench 1932. The second additional element region 250 may further extend onto the sidewall of the first sub-trench 1931. The second additional element region 250 may include a fourth additional element. The fourth additional element may be the same element as the dopant of the third doping region 430. For example, the fourth additional element may be a Group III element such as boron. The concentration of the fourth additional element in the second additional element region 250 may be lower than the concentration of the dopant in the third doping region 430.

[0186] The tolerance of the thickness of the second additional element region 250 may be 15% or less. For example, the third thickness T35 of the second additional element region 250 on the second sidewall of the second sub-trench 1932 may be 85% to 115% of the fourth thickness T36 of the second additional element region 250 on the bottom surface of the second sub-trench 1932. The third thickness T35 of the second additional element region 250 may be smaller than the first sub-thickness T411, the second sub-thickness T412, and the third sub-thickness T413. The fourth thickness T36 may be smaller than the second thickness T42, the first sub-thickness T411, the second sub-thickness T412, and the third sub-thickness T413.

[0187] According to the embodiment, forming the third trench 193 may include performing an etching process on the first substrate 100 and the isolation pattern 220 to form a first sub-trench 1931 and a second sub-trench 1932. Then, a vapor-phase doping process may be performed in the third trench 193 to form a third doped region 430 in the first substrate 100. The second additional element region 250 may be formed together with the third doped region 430 by a single vapor-phase doping process. For example, during the vapor-phase doping process, a portion of the isolation pattern 220 may be exposed to a doping gas to form the second additional element region 250. However, the formation of the third trench 193, the second additional element region 250, and the third doped region 430 is not limited thereto.

[0188] The gate insulating pattern 231 may further include a first additional element. The first additional element may be the same element as the dopant of the third doping region 430 and the fourth additional element of the second additional element region 250. In this case, the third doping region 430 and the gate insulating pattern 231 may be the same as or similar to the doping region 40 and the insulating pattern 21 described in the examples of FIGS. 5A and 5B, respectively.

[0189] The isolation pattern 220 may further include a first additional element region 240, which may be substantially the same as that described in Figures 7A to 7F. The first additional element region 240 may be formed in a single process together with the first doping region 410.

[0190] FIG. 11F is a view illustrating a gate insulating pattern, a third doping region, and a second additional element region of an isolation pattern according to an embodiment, and is an enlarged view of region G in FIG. 11D.

[0191] 11F, the third side 430X of the second doping region 420 may include a first sub-side 430A and a second sub-side 430B. The first sub-side 430A, the second sub-side 430B, and the third bottom 430Y of the third doping region 430 may be substantially the same as those described in the examples of FIGS. 11D and 11E.

[0192] However, the third bottom 430Y of the third doping region 430 may include a first region 431X and a second region 432Y. The first region 431Y of the third bottom 430Y may be disposed on a bottom surface of the vertical portion 311 of the gate pattern 300 and may contact a bottom surface of the first sub-trench 1931. The second region 432Y of the third bottom 430Y may be disposed between the first region 431Y and the first substrate 100.

[0193] The first sub-side 430A of the third doping region 430 may include a first region 431A and a second region 432A. The first region 431A of the first sub-side 430A may be disposed on a sidewall of the vertical portion 311 of the gate pattern 300 and may contact a first sidewall of the first sub-trench 1931. The second region 432A of the first sub-side 430A may be disposed between the first region 431A and the first substrate 100. The first region 431A and the second region 432A of the first sub-side 430A may be connected to the first region 431Y and the second region 432Y of the third bottom 430Y, respectively.

[0194] The second sub-side 430B of the third doping region 430 may include a first region 431B and a second region 432B. The first region 431B of the second sub-side 430B may be disposed on a sidewall of the horizontal portion 312 of the gate pattern 300 and may contact a second sidewall of the second sub-trench 1932. The second region 432B of the second sub-side 430B may be disposed between the first region 431B and the first substrate 100. The first region 431B and the second region 432B of the second sub-side 430B may be connected to the first region 431A and the second region 432B of the first sub-side 430A, respectively.

[0195] The first regions 431A, 431B, and 431Y and the second regions 432A, 432B, and 432Y of the third doping region 430 may be the same as or similar to those described in the examples of FIGS. 4A and 4B or the examples of the first regions 41X, 41Y and the second regions 42X, 42Y of FIG. 5D. For example, the first region 431A of the first sub-side 430A, the first region 431B of the second sub-side 430B, and the first region 431Y of the third bottom 430Y may include a dopant and a first auxiliary element. The first auxiliary element may be chlorine, fluorine, or hydrogen. The second region 432A of the first sub-side 430A, the second region 432B of the second sub-side 430B, and the second region 432Y of the third bottom 430Y may include a dopant but not the first auxiliary element. The concentration of the first auxiliary element in the first regions 431A, 431B, and 431Y of the third doping region 430 may be lower than the dopant concentration in the first regions 431A, 431B, and 431Y and the dopant concentration in the second regions 432A, 432B, and 432Y, thereby improving the reliability of the image sensor.

[0196] The second additional element region 250 may include a first region 251 and a second region 252. The first region 251 of the second additional element region 250 may be disposed between the second region 252 and the gate insulating pattern 231. The first region 251 of the second additional element region 250 may contact the bottom surface and the second sidewall of the second sub-trench 1932. The first region 251 of the second additional element region 250 may further include a fifth auxiliary element in addition to the first additional element. The fifth auxiliary element may be the same element as the first auxiliary element of the first regions 431A, 431B, and 431Y of the third doping region 430. The fifth auxiliary element may include chlorine, fluorine, or hydrogen.

[0197] For example, the gate insulating pattern 231 may not include the first additional element. For another example, the gate insulating pattern 231 may further include a second auxiliary element in addition to the first additional element. The second auxiliary element in the gate insulating pattern 231 may be the same element as the first auxiliary element in the third doping region 430 and the fifth auxiliary element in the second additional element region 250.

[0198] The gate pattern 300 and the third trench 193 may be substantially the same as those described in the example of FIGS. 11C and 11D.

[0199] 12A to 12I are views illustrating a method for manufacturing an image sensor according to an embodiment. Details that overlap with those previously described will be omitted. In the description of the example of manufacturing an image sensor, the pixel region may be interpreted as including the region where the pixel described with reference to FIG. 1 is formed and the region for forming the pixel.

[0200] 12A, a first substrate 100 having a first surface 100a and a second surface 100b opposite to each other may be prepared. Photoelectric conversion regions PD may be formed in pixel regions PX within the substrate 100. A mask film 109 may be formed on the first surface 100a of the first substrate 100. A second trench 192 may be formed in the first surface 100a of the first substrate 100. The second trench 192 may be formed by an etching process using the mask film 109. Interfacial defects may be formed on the bottom and sidewalls of the second trench 192 due to the etching process.

[0201] A second doping region 420 may be formed in the first substrate 100. Forming the second doping region 420 may include performing a first purge process (S10), a vapor phase doping process (S20), and a second purge process (S30) as described in FIG. 3. The second doping region 420 may be substantially the same as the example of the doping region 40 in FIGS. 2A and 2B and the example of the second doping region 420 in FIGS. 10A to 10C. The mask film 109 may be removed.

[0202] 12B, a second preliminary insulation pattern 221P, a third preliminary insulation pattern 223P, and a preliminary buried insulation pattern 225P may be sequentially formed in the second trench 192 to form a preliminary isolation pattern 220P. The second preliminary insulation pattern 221P may conformally cover the sidewalls and bottom of the second trench 192 and may extend onto the first surface 100a of the first substrate 100. The third preliminary insulation pattern 223P may be formed in the second trench 192 and on the first surface 100a of the first substrate 100 to conformally cover the second preliminary insulation pattern 221P. The preliminary buried insulation pattern 225P may be formed on the third preliminary insulation pattern 223P to fill the second trench 192.

[0203] Unlike the description of FIG. 12A, the formation of the second doping region 420 may be performed after the formation of the second preliminary insulation pattern 221P. In this case, the device isolation pattern 220 and the second doping region 420 described in the example of FIG. 10D may be formed. As another example, the formation of the second doping region 420 may be performed after the formation of the third preliminary insulation pattern 223P. In this case, the device isolation pattern 220 and the second doping region 420 described in the example of FIG. 10E may be formed.

[0204] 12C, a first trench 191 may be formed between pixel regions PX in the first substrate 100. Forming the first trench 191 may include performing an etching process on the first surface 100a of the substrate. The first trench 191 may be formed deeper than the second trench 192. A portion of the first trench 191 may penetrate the preliminary device isolation pattern 220P. In this case, the lower portion of the sidewall of the first trench 191 may expose the first substrate 100, and the upper portion of the sidewall of the first trench 191 may expose the preliminary device isolation pattern 220P. The etching process may form interface defects on the bottom and sidewall of the first trench 191.

[0205] A first doping region 410 may be formed in the first substrate 100 and may contact the sidewall and bottom surface of the first trench 191. Forming the first doping region 410 may include performing a first purge process (S10), a vapor phase doping process (S20), and a second purge process (S30), as described with reference to FIG. 3. The first doping region 410 may include a first side portion 410X and a first bottom portion 410Y. The first side portion 410X may contact the sidewall of the first trench 191. The first bottom portion 410Y may contact the bottom surface of the first trench 191 and be connected to the first side portion 410X.

[0206] During the formation of the first doping region 410, the preliminary isolation pattern 220P may be exposed to a doping gas. Therefore, a first additional element region 240 may be further formed in the preliminary isolation pattern 220P. The first additional element region 240 may be formed by a single vapor-phase doping process together with the first doping region 410. The first additional element region 240 may contact the sidewall of the first trench 191 and the top surface of the preliminary isolation pattern 220P. The first additional element region 240 may be conformally formed along the sidewall of the first trench 191 and the top surface of the preliminary isolation pattern 220P. The first additional element region 240 may include a second additional element. Referring to FIG. 12D, a first preliminary insulation pattern 211P, a conductive isolation pattern 215, and a preliminary capping pattern 217P may be formed in the first trench 191 to form the preliminary isolation pattern 210P. The first preliminary insulation pattern 211P may be formed by depositing a silicon-based insulating material. The first preliminary insulation pattern 211P may be conformally formed on the sidewalls and bottom surface of the first trench 191 and the preliminary isolation pattern 220P. The first preliminary insulation pattern 211P may contact the first doping region 410 and the first additional element region 240 of the preliminary isolation pattern 220P.

[0207] A conductive isolation pattern 215 may be formed on the first preliminary insulation pattern 211P and may fill the lower portion of the first trench 191. The conductive isolation pattern 215 does not have to fill the upper portion of the first trench 191. The upper inner wall and top surface of the first preliminary insulation pattern 211P may be exposed and not covered by the conductive isolation pattern 215. Forming the conductive isolation pattern 215 may include depositing a crystalline semiconductor material and doping the crystalline semiconductor material.

[0208] A preliminary capping pattern 217P may be formed on the upper surface of the conductive isolation pattern 215 to fill the first trench 191. The preliminary capping pattern 217P may cover the exposed first preliminary insulation pattern 211P. For example, the preliminary capping pattern 217P may be extended onto the first surface 100a of the first substrate 100 to cover the first preliminary insulation pattern 211P.

[0209] Unlike the example of FIG. 12C, the first doping region 410 may be formed after the first preliminary insulation pattern 211P is formed. In this case, the first insulation pattern 211 and the first doping region 410 described in the example of FIG. 7E may be formed.

[0210] 12E, a recess process may be performed to form the isolation pattern 200 and the first isolation pattern 210. The recess process may include an etch-back process or a planarization process. The recess process may be performed until the first surface 100a of the first substrate 100 is exposed.

[0211] The preliminary capping pattern 217P and the first preliminary insulating pattern 211P on the first surface 100a of the first substrate 100 may be removed by the recess process to form the capping pattern 217 and the first insulating pattern 211, respectively. Thus, the first isolated pattern 210 may be formed. The first isolated pattern 210 may include the first insulating pattern 211, the conductive isolated pattern 215, and the capping pattern 217.

[0212] The recessing process may remove the second preliminary insulation pattern 221P, the third preliminary insulation pattern 223P, and the preliminary buried insulation pattern 225P on the first surface 100a of the first substrate 100, thereby forming the second insulation pattern 221, the third insulation pattern 223, and the buried insulation pattern 225, respectively. Thus, the isolation pattern 220 may be formed, and the isolation pattern 220 may include the second insulation pattern 221, the third insulation pattern 223, and the buried insulation pattern 225. At this time, a portion of the first additional element region 240 on the top surface of the preliminary isolation pattern 220P may also be removed. The first additional element region 240 may contact the first trench 191 within the isolation pattern 20. The first additional element region 240 may include a first sub-region 2401, a second sub-region 2402, and a third sub-region 2403, as described in the example of FIG. 7F.

[0213] Hereinafter, in the illustrations of Figures 12F to 12I, for the sake of simplicity, the second insulating pattern 221, the third insulating pattern 223, the buried insulating pattern 225, and the first additional element region 240 are not separately illustrated, but the present invention is not limited to this.

[0214] 12F, a third trench 193 may be formed on the first surface 100a of the first substrate 100 by an etching process. The etching process may result in interface defects on the bottom and sidewalls of the third trench 193. Forming the third doping region 430 may include performing a first purge process (S10), a vapor phase doping process (S20), and a second purge process (S30), as described with reference to FIG. 3. The third doping region 430 may contact the sidewalls and bottom of the third trench 193.

[0215] 12G, a gate insulating pattern 231 and a gate pattern 300 may be formed in the third trench 193. The gate insulating pattern 231 may be conformally formed on the sidewalls and bottom surface of the third trench 193 and may contact the third doping region 430. Unlike the description of FIG. 12F, the third doping region 430 may be formed after the formation of the gate insulating pattern 231. In this case, the gate insulating pattern 231 may further include a first additional element. The first additional element may be the same element as the dopant of the third doping region 430.

[0216] The gate pattern 300 may be formed on the gate insulation pattern 231. The gate pattern 300 may fill the third trench 193 and may further extend onto the first surface 100a of the first substrate 100. The gate pattern 300 may include a first portion 310 in the third trench 193 and a second portion 320 on the first surface 100a of the first substrate 100. Although not shown, a gate spacer may be formed on a sidewall of the second portion 320 of the gate pattern 300 on the first surface 100a of the substrate 100. Impurities of the second conductivity type may be implanted into the first substrate 100 to form an impurity region 111.

[0217] 12H, a first insulating layer 810, a second insulating layer 820, and a plurality of first conductive structures 830 may be formed on the first surface 100a of the first substrate 100 to form the wiring layer 800. One of the first conductive structures 830 may be electrically connected to the impurity region 111, and another of the first conductive structures 830 may be electrically connected to the gate pattern 300.

[0218] 12I, a thinning process may be performed on the second surface 100b of the first substrate 100, thereby exposing the first isolation pattern 210 on the second surface 100b of the first substrate 100. The thinning process may be performed by an etch-back process or a chemical mechanical polishing process. The thinning process may be performed until the bottom surface of the conductive isolation pattern 215 is exposed on the second surface 100b of the first substrate 100. The first bottom portion 410Y of the first doping region 410 may be removed during the thinning process. After the thinning process is completed, the first side portion 410X of the first doping region 410 may remain. As a result of the thinning process, interface defects may further be formed on the second surface 100b of the first substrate.

[0219] After the thinning process, a backside doping region 440 may be further formed on the second surface 100b of the first substrate 100. Forming the backside doping region 440 may include performing the first purge process (S10), the vapor-phase doping process (S20), and the second purge process (S30) described with reference to FIG. 3. During the process of forming the backside doping region 440, the lower surface of the first insulating pattern 211 may be exposed to the doping gas. Therefore, a third additional element region may be further formed in the first insulating pattern 211. The third additional element region of the first insulating pattern 211 is the same as that described for the example of the third additional element region 212 of FIG. 11C.

[0220] 11A, an insulating layer 500, a color filter CF, a fence pattern 550, a protective film 530, and a microlens layer 600 may be formed on the second surface 100b of the substrate 100. The image sensor described in FIG. 11A may be manufactured according to the examples described above.

[0221] FIG. 13A is a view illustrating a pixel array region of an image sensor according to an embodiment, and corresponds to a cross section taken along line II' of FIG.

[0222] 13A, the first isolation pattern 210 may include a first insulating pattern 211, a conductive isolation pattern 215, and a capping pattern 217. The conductive isolation pattern 215 may include a conductive liner pattern 2151 and a conductive buried pattern 2153. The conductive liner pattern 2151 may be provided on a sidewall of the first insulating pattern 211. The bottom surface of the conductive liner pattern 2151 may be disposed at substantially the same level as the second surface 100b of the first substrate 100. The conductive liner pattern 2151 may include a crystalline semiconductor material and a dopant. For example, the conductive liner pattern 2151 may be doped polysilicon. The dopant may include a Group III element. For example, the dopant may include boron (B), aluminum (Al), indium (In), and / or gallium (Ga). The conductive liner pattern 2151 may have a uniform dopant concentration. For example, the dopant concentration within the conductive liner pattern 2151 may have a tolerance of 15% or less. The number of dopants per unit area of the conductive liner pattern 2151 is 5.0×10 11 atoms / cm 2 ~1.0x10 14 atoms / cm 2For example, the conductive liner pattern 2151 may further include an auxiliary element. The auxiliary element may include chlorine, hydrogen, or fluorine. The conductive liner pattern 2151 may have a uniform concentration of the auxiliary element. For example, the concentration of the auxiliary element in the conductive liner pattern 2151 may have a tolerance of 15% or less. However, the concentration of the auxiliary element in the conductive liner pattern 2151 may be less than the concentration of the dopant. Therefore, the electrical properties of the conductive isolation pattern 215 may be improved.

[0223] The conductive filled pattern 2153 may be disposed on the conductive liner pattern 2151 and may be spaced apart from the first insulating pattern 211. A sidewall of the conductive filled pattern 2153 may be surrounded by the conductive liner pattern 2151. The conductive liner pattern 2151 may be interposed between the conductive filled pattern 2153 and the first insulating pattern 211. The conductive filled pattern 2153 may be in physical contact with and electrically connected to the conductive liner pattern 2151. The conductive filled pattern 2153 may include a crystalline semiconductor material and a dopant. The conductive filled pattern 2153 may include the same material as the conductive liner pattern 2151. For example, the crystalline semiconductor material of the conductive filled pattern 2153 may be the same material as the crystalline semiconductor material of the conductive liner pattern 2151. The dopant in the conductive filled pattern 2153 may be the same material as the dopant in the conductive liner pattern 2151. The dopant in the conductive filled pattern 2153 may include a Group III element such as boron. The conductive fill pattern 2153 may include doped polysilicon.

[0224] The conductive fill pattern 2153 may have a uniform dopant concentration. For example, the dopant concentration within the conductive fill pattern 2153 may have a tolerance of 15% or less. The number of dopants per unit area of the conductive fill pattern 2153 may be 5.0x10 11 atoms / cm 2 ~1.0x10 14atoms / cm 2 The dopant concentration of the conductive fill pattern 2153 may be substantially the same as the dopant concentration of the conductive liner pattern 2151. For example, the dopant concentration of the conductive fill pattern 2153 may be 85% to 115% of the dopant concentration of the conductive liner pattern 2151.

[0225] For example, the conductive fill pattern 2153 may further include an auxiliary element. The auxiliary element may include chlorine, hydrogen, or fluorine. The concentration of the auxiliary element in the conductive fill pattern 2153 may have a tolerance of 15% or less. However, the concentration of the auxiliary element in the conductive fill pattern 2153 may be lower than the concentration of the dopant in the conductive fill pattern 2153. Therefore, the electrical properties of the conductive isolation pattern 215 may be improved. The concentration of the auxiliary element in the conductive fill pattern 2153 may be 85% to 115% of the concentration of the auxiliary element in the conductive liner pattern 2151. As another example, at least one of the conductive liner pattern 2151 and the conductive fill pattern 2153 may not include an auxiliary element.

[0226] During operation of the image sensor, a first voltage may be applied to the conductive isolation pattern 215. The first voltage may be a negative bias voltage. Therefore, during operation of the image sensor, formation of dark current between the first isolation pattern 210 and the first substrate 100 may be prevented. The dark current may be generated by interfacial bonding on the sidewalls of the first trench 191. The image sensor may exhibit improved characteristics.

[0227] The dopant concentration of the conductive filled pattern 2153 is 85% to 115% of the dopant concentration of the conductive liner pattern 2151, so that the first voltage can be effectively applied within the conductive separation pattern 215. Therefore, the formation of dark current can be more effectively prevented. The dopant concentrations of the conductive liner pattern 2151 and the conductive filled pattern 2153 have a tolerance of 15% or less, so that the generation of dark current can be further prevented. Although not shown, an oxide layer can be further provided between the conductive liner pattern 2151 and the conductive filled pattern 2153.

[0228] The first insulating pattern 211 may further include an additional element region 218. The additional element region 218 may be interposed between the capping pattern 217 and the isolation pattern 200. The additional element region 218 may further include a first additional element, which may be the same material as the dopant of the conductive liner pattern 2151 and the dopant of the conductive buried pattern 2153. The concentration of the first additional element in the additional element region 218 may have a tolerance of 15% or less.

[0229] When the conductive liner pattern 2151 or the conductive fill pattern 2153 further includes an auxiliary element, the additional element region 218 may further include the auxiliary element. The auxiliary element in the additional element region 218 may be the same material as the auxiliary element in the conductive liner pattern 2151 or the auxiliary element in the conductive fill pattern 2153. The concentration of the auxiliary element in the additional element region 218 may be lower than the concentration of the first additional element in the additional element region 218.

[0230] The image sensor may further include a second doping region 420. Although not shown, the image sensor may further include at least one of the third doping region 430 and the backside doping region 440 described in Figures 11A and 11B. As another example, at least one of the first doping region 410 and the second doping region 420 may not be formed.

[0231] 13B and 13C are views for explaining the formation of a conductive separation pattern according to an embodiment. Hereinafter, the same content as that previously described will be omitted.

[0232] 13B, a second trench 192, a second doping region 420, a preliminary isolation pattern 220P, a first doping region 410, and a first trench 191 may be formed in a first substrate 100 by the same method as described in the examples of FIGS. 12A through 12C. A first preliminary insulation pattern 211P may be formed in the first trench 191.

[0233] A conductive liner pattern 2151 may be formed in the first trench 191 to cover the bottom surface and sidewalls of the first trench 191. The first trench 191 may have first and second sidewalls facing each other. The conductive liner pattern 2151 may include a first portion, a second portion, and a third portion. The first and second portions of the conductive liner pattern 2151 may be disposed on the first and second sidewalls of the first trench 191. The sidewalls of the second portion of the conductive liner pattern 2151 may face and be spaced apart from the sidewalls of the first portion. The third portion of the conductive liner pattern 2151 may be disposed on the bottom surface of the first trench 191 and connected to the first and second portions.

[0234] Forming the conductive liner pattern 2151 may include depositing a crystalline semiconductor material in the first trench 191 and doping the crystalline semiconductor material. Doping the crystalline semiconductor material may include performing a first purge process (S10), a vapor-phase doping process (S20), and a second purge process (S30), as described with reference to FIG. 3. The vapor-phase doping process allows a doping gas to be uniformly provided on the sidewalls of the first and second portions and the top surface of the third portion of the conductive liner pattern 2151, thereby doping the conductive liner pattern 2151. For example, a dopant may be provided in the conductive liner pattern 2151. The vapor-phase doping process may allow the dopant concentration in the conductive liner pattern 2151 to satisfy the conditions described in the example of FIG. 13A. An auxiliary element may be further implanted into the conductive liner pattern 2151 along with the dopant.

[0235] A portion of the first preliminary insulation pattern 211P is exposed to the vapor phase doping process, and a fourth additional element region 218 may be formed in the first preliminary insulation pattern 211P. Therefore, the additional element in the fourth additional element region 218 may be the same material as the dopant of the conductive liner pattern 2151. The fourth additional element region 218 may be formed in a portion of the first preliminary insulation pattern 211P exposed to the conductive liner pattern 2151.

[0236] 13C, a conductive fill pattern 2153 may be formed on the conductive liner pattern 2151 to fill the lower portion of the first trench 191. The conductive fill pattern 2153 does not have to fill the upper portion of the first trench 191. Formation of the conductive fill pattern 2153 may include depositing a crystalline semiconductor material in the first trench 191 and doping the crystalline semiconductor material. The doping may be performed by the method described with reference to FIG. 3. Thus, a doping gas may be uniformly injected onto the upper surface of the conductive fill pattern 2153, providing the dopant within the conductive fill pattern 2153. Because the doping process is performed by a vapor-phase doping process, the dopant concentration within the conductive fill pattern 2153 may satisfy the conditions described in the example of FIG. 13A. An auxiliary element may be further injected into the conductive fill pattern 2153 along with the dopant.

[0237] Thereafter, an annealing process may be further performed, which may allow the dopant to be uniformly diffused within the conductive liner pattern 2151 and the conductive buried pattern 2153.

[0238] 12D, a preliminary capping pattern 217P may be formed on the conductive isolation pattern 215. Thereafter, the processes described in the examples of FIGS. 12E to 12I and the example of FIG. 7A may be performed to manufacture the image sensor of FIG. 13A. At this time, a portion of the fourth additional element region 218 may be removed by the recess process of the first preliminary insulation pattern 211P, and another portion of the fourth additional element region 218 may remain in the first insulation pattern 211.

[0239] 13D is a diagram illustrating the formation of a conductive separation pattern according to an embodiment of the present invention. Hereinafter, the same content as that previously described will be omitted.

[0240] Referring to FIG. 13D, the second trench 192, the preliminary isolation pattern 220P, the second doping region 420, the first doping region 410, and the first trench 191 may be formed in the first substrate 100.

[0241] A conductive isolation pattern 215 may be formed on the first preliminary insulating pattern 211P and may fill the lower portion of the first trench 191. At this time, the process of forming the conductive liner pattern (2151 in FIG. 13A) may not be performed. Formation of the conductive isolation pattern 215 may include depositing a crystalline semiconductor material in the first trench 191 and doping the crystalline semiconductor material. The crystalline semiconductor material does not have to be provided in the upper portion of the first trench 191. The doping may be performed by the method described with reference to FIG. 3. Thus, a doping gas may be uniformly injected onto the upper surface of the conductive isolation pattern 215, and the dopant may be provided in the conductive isolation pattern 215. Since the doping process is performed by a vapor-phase doping process, the dopant concentration may satisfy the conditions described in the examples of FIGS. 7A and 7B. An auxiliary element may also be implanted into the conductive isolation pattern 215 during the vapor-phase doping process. The auxiliary element in the conductive isolation pattern 215 is the same as that described in the example of FIG. 7A. A portion of the first preliminary insulating pattern 211P may be exposed to the vapor phase doping process, so that a fourth additional element region 218 may be formed in the first preliminary insulating pattern 211P.

[0242] 12D, preliminary capping pattern 217P may be formed on conductive isolation pattern 215. Thereafter, the processes described in connection with the examples of FIGS. 12E to 12I and the example of FIG. 7A may be performed to manufacture the image sensor of FIG. 7A. At this time, a portion of fourth additional element region 218 may be removed by a recess process of first preliminary insulation pattern 211P, and another portion of fourth additional element region 218 may remain in first insulation pattern 211. In the drawings except for FIGS. 13A to 13D, the fourth additional element region 218 in first insulation pattern 211 is not separately illustrated for simplicity, but the present invention is not limited thereto.

[0243] 14A is a plan view illustrating the arrangement of color filters of the image sensor according to the embodiment, and is an enlarged view of region II in FIG. 6. Hereinafter, the content overlapping with that described above will be omitted, and reference will be made to FIG. 6.

[0244] 14A, the pixel array region (APS in FIG. 6) of the first substrate 100 may include a plurality of pixel regions PX. The pixel regions PX may be arranged two-dimensionally along rows and columns in a plan view. The rows may be aligned in a first direction D1, and the columns may be aligned in a second direction D2. The pixel regions PX may be defined by first separation patterns 210. For example, the first separation patterns 210 may surround each pixel region PX in a plan view.

[0245] A color filter CF may be disposed on each pixel region PX. The color filter CF may be substantially the same as the color filter CF described above in the examples of FIGS. 7A and 7B. The color filter CF may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1 may be a green color filter. The second color filter CF2 may be a red color filter, and the third color filter CF3 may be a blue color filter.

[0246] The color filters CF may be arranged in a Bayer pattern. For example, the number of first color filters CF1 may be at least twice the number of second color filters CF2. The number of first color filters CF1 may be at least twice the number of third color filters CF3. The first color filters CF1 may be arranged in a first diagonal direction D4. The first diagonal direction D4 is parallel to the first surface 100a of the first substrate 100 and may intersect the first direction D1 and the second direction D2 in a plan view. Each second color filter CF2 may be disposed between two adjacent first color filters CF1. Each third color filter CF3 may be disposed between two adjacent first color filters CF1. The third color filter CF3 may be arranged with the second color filters CF2 in a second diagonal direction D5. The second diagonal direction D5 is parallel to the first surface 100a of the first substrate 100 and may be substantially perpendicular to the first diagonal direction D4 in a plan view.

[0247] 14B is a plan view illustrating the arrangement of color filters in the image sensor according to the embodiment, and corresponds to an enlarged view of region II in FIG. 6. FIG. 14C is a cross-sectional view taken along line I"-I'" in FIG. 14B.

[0248] 14B and 14C, the pixel array region (APS in FIG. 6) of the first substrate 100 may include pixel groups PG. The pixel groups PG may be arranged two-dimensionally along a first direction D1 and a second direction D2 in a plan view. Each pixel group PG may include a plurality of pixel regions PX. For example, the pixel regions PX of a pixel group PG may be arranged two-dimensionally in two rows and two columns.

[0249] The color filters CF may be disposed on the pixel regions PX on the second surface 100b of the first substrate 100. The color filters CF may be substantially the same as the color filters CF described above in the example of FIG. 14A. The color filters CF may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be arranged in a Bayer pattern as described in FIG. 14A. However, a single color filter CF may be disposed on a pixel group PG and overlap with the plurality of pixel regions PX of the pixel group PG in a plan view. A single color filter CF may be disposed on the photoelectric conversion region PD of the plurality of pixel regions PX of the pixel group PG.

[0250] Therefore, multiple pixel regions PX of a pixel group PG can share the single color filter CF. For example, a first color filter CF1 can be disposed on multiple pixel regions PX of one pixel group PG. A second color filter CF2 can be disposed on multiple pixel regions PX of another pixel group PG. A third color filter CF3 can be disposed on multiple pixel regions PX of another pixel group PG. The image sensor can have a tetra-cell structure.

[0251] FIG. 14D is a plan view illustrating the arrangement of color filters of the image sensor according to the embodiment, and corresponds to an enlarged view of region II in FIG.

[0252] Referring to FIG. 14D, the pixel array region of the image sensor may have a nona-cell structure. In this case, each pixel group PG may include nine pixel regions PX. The nine pixel regions PX may be arranged two-dimensionally, forming three rows and three columns. A color filter CF may be provided on each pixel group PG. That is, a single color filter CF may be provided in each of the nine pixel regions PX of the pixel group PG and may vertically overlap the photoelectric conversion regions PD of the nine pixel regions PX. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be arranged in a Bayer pattern, as illustrated in FIG. 14A.

[0253] FIG. 15A is a cross-sectional view of the image sensor according to the embodiment taken along line III-III' in FIG.

[0254] 6 and 15A, the image sensor may include a sensor chip 1 and a logic chip 2. The sensor chip 1 may include a first substrate 100, a first wiring layer 800, a first isolation pattern 210, an isolation pattern 220, first to third doping regions 410, 420, and 430, a backside doping region 440, a gate pattern 300, a color filter CF, and a microlens layer 600. The sensor chip 1 may further include at least one of an insulating layer 500, a passivation film 530, and a fence pattern 550.

[0255] The first substrate 100 may include, in a plan view, a pixel array region APS, an optical black region OB, and a pad region PAD. The components within the pixel array region APS of the first substrate 100 are the same as those described above. The optical black region OB of the first substrate 100 may be interposed between the pixel array region APS and the pad region PAD. The optical black region OB may include a first reference pixel region RPX1 and a second reference pixel region RPX2. The first reference pixel region RPX1 may be disposed between the second reference pixel region RPX2 and the pixel array region APS. In the optical black region OB, a photoelectric conversion region PD may be provided within the first reference pixel region RPX1. The photoelectric conversion region PD of the first reference pixel region RPX1 may have the same planar area and volume as the photoelectric conversion region PD of the pixel region PX. The photoelectric conversion region PD may not be provided within the second reference pixel region RPX2. The impurity region 111, the gate pattern 300, and the isolation pattern 220 may be disposed in each of the first and second reference pixel regions RPX1 and RPX2. At least one of the first doping region 410, the second doping region 420, the third doping region 430, and the backside doping region 440 may be further disposed in the first and second reference pixel regions RPX1 and RPX2. The insulating layer 500 may extend over the optical black region OB and the pad region PAD of the first substrate 100 and cover the first surface 100a of the first substrate 100.

[0256] The sensor chip 1 may further include a light-shielding film 950, a first conductive film 911, a filtering film 650, an organic film 601, and a contact plug 960. The light-shielding film 950, the first conductive film 911, the filtering film 650, the organic film 601, and the contact plug 960 may be provided on an optical black area OB of the first substrate 100.

[0257] The light-shielding film 950 may be provided on the second surface 100b of the optical black area OB of the first substrate 100. The light-shielding film 950 may be disposed on the lower surface of the insulating layer 500. The light-shielding film 950 prevents light from being incident on the photoelectric conversion area PD of the optical black area OB. The pixels of the first and second reference pixel areas RPX1 and RPX2 in the optical black area OB may output noise signals instead of photoelectric signals. The noise signals may be generated by electrons generated by heat generation, dark current, or the like. Since the light-shielding film 950 does not cover the pixel array area APS, light may be incident on the photoelectric conversion area PD in the pixel array area APS. The noise signals may be removed from the photoelectric signals output from the pixel area PX. The light-shielding film 950 may include a metal such as tungsten, copper, aluminum, or an alloy thereof.

[0258] A first conductive layer 911 may be provided on the optical black area OB and the pad area PAD of the first substrate 100. The first conductive layer 911 may be disposed between the insulating layer 500 and the light-shielding layer 950. The first conductive layer 911 may serve as a barrier layer or an adhesion layer. The first conductive layer 911 may include metal and / or metal nitride. For example, the first conductive layer 911 may include titanium and / or titanium nitride. The first conductive layer 911 may not extend onto the pixel array area APS of the first substrate 100.

[0259] A contact plug 960 may be provided on the second surface 100b of the first substrate 100 in the optical black region OB. The contact plug 960 may be disposed in the insulating layer 500 and on a lower surface of the outermost portion of the isolation pattern 210. A contact trench may be formed on the second surface 100b of the first substrate 100, and the contact plug 960 may be provided in the contact trench. The contact plug 960 may include a different material from the light-shielding layer 950. For example, the contact plug 960 may include aluminum. The first conductive layer 911 may extend between the contact plug 960 and the insulating layer 400 and between the contact plug 960 and the isolation pattern 210. The contact plug 960 may be electrically connected to the conductive isolation pattern 215 through the first conductive layer 911. Therefore, a negative bias voltage may be applied to the conductive isolation pattern 215.

[0260] A protective insulating layer 531 may be disposed on the lower surface of the light-shielding layer 950 and the lower surface of the contact plug 960. The protective insulating layer 531 may include the same material as the protective layer 530 and may be connected to the protective layer 530. The protective insulating layer 531 may be formed integrally with the protective layer 530. As another example, the protective insulating layer 531 may be formed in a separate process from the protective layer 530 and may be separated from the protective layer 530. The protective insulating layer 531 may include a high-dielectric material (e.g., aluminum oxide and / or hafnium oxide).

[0261] A filtering film 650 may be disposed on the second surface 100b of the optical black region OB to cover the lower surface of the protective insulating film 531. The filtering film 650 may block light of a different wavelength than the color filter CF. For example, the filtering film 650 may block infrared light. The filtering film 650 may include, but is not limited to, a blue color filter.

[0262] The organic film 601 may be disposed on the lower surface of the filtering film 650 in the optical black area OB. The organic film 601 may be transparent. The lower surface of the organic film 601 is opposite to the first substrate 100 and may be substantially flat. The organic film 601 may include, for example, a polymer. The organic film 601 may have insulating properties. Unlike what is shown, the organic film 601 may be connected to the microlens layer 600. The organic film 601 may include the same material as the microlens layer 600. Although not shown, a coating layer may be further provided on the lower surface of the organic film 601 to conformally cover the lower surface of the organic film 601.

[0263] The first wiring layer 800 covers the first surface 100 a of the first substrate 100 and may be provided on the pixel array region APS, the optical black region OB, and the pad region PAD of the first substrate 100 .

[0264] The image sensor may further include a circuit chip 2. The circuit chip 2 may be stacked on the sensor chip 1. The circuit chip 2 may include a second wiring layer 1800, an integrated circuit 1700, and a second substrate 1100. The second wiring layer 1800 may be interposed between the first wiring layer 800 and the second substrate 1100. The integrated circuit 1700 may be disposed on the underside of the second substrate 1100 or within the second substrate 1100. The integrated circuit 1700 may include a logic circuit, a memory circuit, or a combination thereof. The integrated circuit 1700 may include, for example, a transistor. The second wiring layer 1800 may include a third insulating layer 1820 and a second conductive structure 1830. The second conductive structure 1830 may be provided between the third insulating layer 1820 or within the third insulating layer 1820. The second conductive structure 1830 may be electrically connected to the integrated circuit 1700. The second conductive structure 1830 may include a via pattern and a wiring pattern. The following description will refer to a single second conductive structure 1830 for simplicity.

[0265] The following describes the configuration on the pad region PAD of the first substrate 100. The sensor chip 1 may further include a pad terminal 900, a first buried pattern 921, a first capping pattern 931, a second buried pattern 922, and a second capping pattern 932 provided on the pad region PAD of the first substrate 100. The backside doping region 440 may further extend onto the pad region PAD of the substrate 100.

[0266] The pad terminal 900 may be disposed on the second surface 100b of the pad area PAD of the first substrate 100. The pad terminal 900 may be embedded in the first substrate 100. For example, a pad trench 990 may be formed on the second surface 100b of the pad area PAD of the first substrate 100, and the pad terminal 900 may be provided in the pad trench 990. The pad terminal 900 may include a metal such as aluminum, copper, tungsten, titanium, tantalum, or an alloy thereof. During the mounting process of the image sensor, a bonding wire may be formed on the pad terminal 900 to connect to the pad terminal 900. The pad terminal 900 may be electrically connected to an external device through the bonding wire.

[0267] The first through hole 901 may be disposed on a first side of the pad terminal 900. The first through hole 901 may be provided between the pad terminal 900 and the contact plug 960. The first through hole 901 may penetrate the insulating layer 500, the first substrate 100, and the first wiring layer 800. The first through hole 901 may further penetrate at least a portion of the second wiring layer 1800. The first through hole 901 may have a first bottom surface and a second bottom surface. The first bottom surface of the first through hole 901 may expose the first conductive structure 830. The second bottom surface of the first through hole 901 may be disposed at a higher level than the first bottom surface. The second bottom surface of the first through hole 901 may expose the second conductive structure 1830.

[0268] The first conductive layer 911 may extend over the pad region PAD of the first substrate 100. The first conductive layer 911 may be disposed on the second surface 100b of the pad region PAD of the first substrate 100 and cover the inner wall and bottom surface of the first through-hole 901. As shown in FIG. 6, a plurality of pad terminals 900 may be provided. The plurality of pad terminals 900 may include a first pad terminal and a second pad terminal 920. Although not shown, the first conductive layer 911 may be provided on the top surface and sidewall of one of the plurality of pad terminals 900 (e.g., the first pad terminal) and may be electrically connected to the one of the pad terminals 900 (e.g., the first pad terminal).

[0269] The first conductive layer 911 may cover the sidewall and the first bottom surface of the first through hole 901. The first conductive layer 911 may be in contact with the bottom surface of the first conductive structure 830. Therefore, the first conductive structure 830 may be electrically connected to one of the pad terminals 900 (e.g., the first pad terminal) through the first conductive layer 911. When the image sensor operates, a voltage may be applied to the first conductive structure 830 through the one of the pad terminals 900 and the first conductive layer 911. The voltage may be applied to the conductive isolation pattern 215 through the first conductive layer 911 and the contact plug 960. The voltage may be the negative bias voltage described above.

[0270] The first conductive layer 911 may cover the second bottom surface of the first through hole 901 and be connected to the bottom surface of the second conductive structure 1830. The integrated circuit 1700 in the circuit chip 2 may be electrically connected to one of the pad terminals 900 (e.g., the first pad terminal) through the second conductive structure 1830 and the first conductive layer 911. As another example, the first conductive layer 911 may be connected to the first conductive structure 830 and the second conductive structure 1830 without being connected to the contact plug 960. The first conductive layer 911 may function as an electrical path between the integrated circuit 1700 of the circuit chip 2 and the transistor of the sensor chip 1. The first conductive layer 911 may include a metal such as copper, tungsten, aluminum, titanium, tantalum, or an alloy thereof.

[0271] A first filled pattern 921 may be provided in the first through hole 901 to fill the first through hole 901. The first filled pattern 921 may not extend onto the second surface 100b of the first substrate 100. The first filled pattern 921 may include a low refractive index material and have insulating properties. The first filled pattern 921 may include the same material as the fence pattern 550. For example, the first filled pattern 921 may include a polymer and nanoparticles. The bottom surface of the first filled pattern 921 may have a recess. For example, a center portion of the bottom surface of the first filled pattern 921 may be positioned at a higher level than the edge portions.

[0272] A first capping pattern 931 may be disposed on the lower surface of the first filled pattern 921 to fill the recess. The upper surface of the first filled pattern 921 may be convex. The lower surface of the first capping pattern 931 may be substantially flat. The first capping pattern 931 may include an insulating polymer such as a photoresist material.

[0273] The second through-hole 902 may be disposed on a second side of the pad terminal 900. The second side of the pad terminal 900 may be different from the first side. The second through-hole 902 may penetrate the insulating layer 500, the first substrate 100, and the first wiring layer 800. The second through-hole 902 may penetrate a portion of the second wiring layer 1800 to expose the second conductive structure 1830.

[0274] As shown, the second conductive layer 912 may be interposed between another one of the pad terminals 900 (e.g., the second pad terminal 920) and the first substrate 100 and may be electrically connected to the second pad terminal 920. The second conductive layer 912 may extend into the second through hole 902 and conformally cover the sidewall and bottom surface of the second through hole 902. The second conductive layer 912 may be electrically connected to the second conductive structure 1830. During operation of the image sensor, the integrated circuit 1700 of the circuit chip 2 may transmit and receive electrical signals through the second conductive structure 1830, the second conductive layer 912, and the second pad terminal 920.

[0275] A second buried pattern 922 may be provided in the second through hole 902 to fill the second through hole 902. The second buried pattern 922 may not extend onto the second surface 100b of the first substrate 100. The second buried pattern 922 may include a low refractive index material and have insulating properties. For example, the second buried pattern 922 may include the same material as the fence pattern 550. The bottom surface of the second buried pattern 922 may have a recess.

[0276] A second capping pattern 932 may be disposed on the lower surface of the second buried pattern 922 to fill the recess. The upper surface of the second capping pattern 932 may be convex. The lower surface of the second capping pattern 932 may be substantially flat. The second capping pattern 932 may include an insulating polymer, such as a photoresist material.

[0277] The protective insulating film 531 may be provided to extend over the pad region PAD of the first substrate 100. The protective insulating film 531 may be provided on the lower surface of the insulating layer 500 and extend into the first through-hole 901 and the second through-hole 902. The protective insulating film 531 may be interposed between the second conductive film 912 and the second filled pattern 922 in the first through-hole 901. The protective insulating film 531 may be interposed between the second conductive film 912 and the second filled pattern 922 in the first through-hole 901. The protective insulating film 531 may expose the pad terminal 900.

[0278] The organic film 601 may cover a portion of the first capping pattern 931 and the protective insulating film 531 on the second surface 100b of the pad area PAD of the first substrate 100. The organic film 601 may expose the lower surface of the pad terminal 900.

[0279] FIG. 15B is a view illustrating an image sensor according to an embodiment, and corresponds to a cross section taken along line III-III' in FIG.

[0280] Referring to FIG. 15B, the image sensor may include a sensor chip 1 and a circuit chip 2. The sensor chip 1 and the circuit chip 2 may be substantially the same as those described above in the example of FIG. 15A. However, the sensor chip 1 may further include a first connection pad 850. The first connection pad 850 may be exposed on the upper surface of the sensor chip 1. For example, the first connection pad 850 may be disposed in the uppermost second insulating layer 820. The first connection pad 850 may be electrically connected to the first conductive structure 830. The first connection pad 850 may include a conductive material such as metal. For example, the first connection pad 850 may include copper. As another example, the first connection pad 850 may include aluminum, tungsten, titanium, and / or an alloy thereof.

[0281] The circuit chip 2 may further include second connection pads 1850. The second connection pads 1850 may be exposed on the bottom surface of the circuit chip 2. The second connection pads 1850 may be disposed in the lowermost third insulating layer 1820. The second connection pads 1850 may be electrically connected to the integrated circuit 1700 through the second conductive structures 1830. The second connection pads 1850 may include a conductive material such as metal. For example, the second connection pads 1850 may include copper. As another example, the second connection pads 1850 may include aluminum, tungsten, titanium, and / or alloys thereof.

[0282] The circuit chip 2 may be connected to the sensor chip 1 by direct bonding. For example, the first connection pad 850 and the second connection pad 1850 may be vertically aligned and in contact with each other. Therefore, the second connection pad 1850 may be directly bonded to the first connection pad 850. An electrical signal from the integrated circuit 1700 of the circuit chip 2 may be transmitted to the transistor or pad terminal 900 of the sensor chip 1 through the second conductive structure 1830, the second connection pad 1850, the first connection pad 850, and the first conductive structure 830. The uppermost second insulating layer 820 may be directly bonded to the lowermost third insulating layer 1820. In this case, the uppermost second insulating layer 820 may be chemically bonded to the lowermost third insulating layer 1820, but the present invention is not limited thereto.

[0283] The first through hole 901 may include a first through hole portion 91, a second through hole portion 92, and a third through hole portion 93. The first through hole portion 91 may penetrate the insulating layer 500, the first substrate 100, and the first wiring layer 800 and may have a first bottom surface. The second through hole portion 92 may penetrate the insulating layer 500, the first substrate 100, and the first wiring layer 800 and extend into the second wiring layer 1800. The second through hole portion 92 may have a second bottom surface, and the second bottom surface may expose a lower surface of the second conductive structure 1830. A sidewall of the second through hole portion 92 may be spaced apart from a sidewall of the first through hole portion 91. The third through hole portion 93 may be provided between a lower portion of the first through hole portion 91 and a lower portion of the second through hole portion 92 and may be connected to the lower portions of the first through hole portion 91 and the second through hole portion 92. A first conductive layer 911, a protective insulating layer 531, and a first filled pattern 921 may be provided in the first through hole 901. The first conductive layer 911 may cover the inner walls of the first through hole portion 91, the second through hole portion 92, and the third through hole portion 93.

[0284] In this specification, different embodiments may be combined with each other, for example, the embodiments of Figures 7A to 15B may be combined with each other. [Explanation of symbols]

[0285] 10 Substrate 19 Trench 21 Insulation pattern 25 Embedded Patterns 40 Doping Region 400 Doping Gas 401 Dopant PD photoelectric conversion region

Claims

1. a semiconductor substrate having a trench in a first surface; an insulating pattern provided in the trench; a doped region in the semiconductor substrate and on the insulating pattern; The doped region is a side portion on a sidewall of the insulating pattern; a bottom portion on the bottom surface of the insulating pattern; the thickness of the side of the doped region is between 85% and 115% of the thickness of the bottom; the number of dopants per unit area of the side of the doped region is between 85% and 115% of the number of dopants per unit area of the bottom; The number of dopants per unit area of the side of the doped region is 5.0×10 １１ atoms / cm ２ ~1.0x10 １４ atoms / cm ２ and The number of dopants per unit area of the bottom of the doped region is 5.0×10 １１ atoms / cm ２ ~1.0x10 １４ atoms / cm ２ and Each of the sides and the bottom of the doped region has a first region contacting the insulating pattern and including a dopant and a first auxiliary element, the first auxiliary element including chlorine, fluorine, or hydrogen; a second region interposed between the first region and the semiconductor substrate, the second region including the dopant and not including the first auxiliary element; The concentration of the dopant in the first region is greater than the concentration of the first auxiliary element in the first region.

2. the insulating pattern further comprises an additional element; The image sensor of claim 1 , wherein the additional element comprises the same element as the dopant in the doping region.

3. 3. The image sensor of claim 1, wherein the thickness of the side and the thickness of the bottom of the doped region are between 30 nm and 180 nm.

4. 4. The image sensor of claim 1, further comprising a gate pattern provided on the insulating pattern within the trench, the gate pattern being a gate electrode of a transfer transistor, a source follower transistor, a reset transistor, or a select transistor, and the insulating pattern being interposed between the gate pattern and the doped region.

5. The semiconductor device further includes an isolation pattern provided in the semiconductor substrate, The gate pattern is a vertical portion disposed laterally of the isolation pattern within the semiconductor substrate; a horizontal portion provided in the semiconductor substrate and connected to the vertical portion; The image sensor according to claim 4 , wherein at least a portion of the horizontal portion is provided within the element isolation pattern.

6. The side of the doped region is a first sub-side portion on a sidewall of the vertical portion of the gate pattern; a second sub-side portion on a sidewall of the horizontal portion of the gate pattern; 6. The image sensor of claim 5, wherein the thickness of the second sub-side of the doped region is between 85% and 115% of the thickness of the first sub-side.

7. an impurity region provided in the semiconductor substrate and disposed adjacent to the first surface of the semiconductor substrate; an isolation pattern disposed on one side of the impurity region in the semiconductor substrate, The image sensor of claim 1 , wherein the element isolation pattern includes the insulating pattern.

8. a semiconductor substrate having a trench; an insulating pattern within the trench of the semiconductor substrate; a doped region disposed in the semiconductor substrate and on the insulating pattern; The number of dopants per unit area of the doped region is 5.0×10 １１ atoms / cm ２ ~1.0x10 １４ atoms / cm ２ and the insulating pattern includes a first surface and a second surface having different gradients; The doped region is a first portion on the first surface of the insulating pattern; a second portion on the second surface of the insulating pattern; the thickness of the second portion of the doped region is between 85% and 115% of the thickness of the first portion; the number of dopants per unit area of the second portion of the doped region is between 85% and 115% of the number of dopants per unit area of the first portion; Each of the first and second portions of the doped region comprises: a first region contacting the insulating pattern and including a dopant and a first auxiliary element, the first auxiliary element including chlorine, fluorine, or hydrogen; a second region interposed between the first region and the semiconductor substrate, the second region including the dopant and not including the first auxiliary element; The concentration of the dopant in the first region is greater than the concentration of the first auxiliary element in the first region.

9. the insulating pattern further includes an additional element and a second auxiliary element; the additional element is the same element as the dopant, The image sensor of claim 8 , wherein the second auxiliary element is the same element as the first auxiliary element.

10. The image sensor according to claim 8 , wherein the first auxiliary element comprises chlorine.

11. a photoelectric conversion region provided within the semiconductor substrate; a conductive pixel isolation pattern provided in the trench and covering the insulating pattern; The image sensor of claim 8 , wherein the conductive pixel separating pattern is disposed between the photoelectric conversion regions.

12. a substrate having a first surface, a second surface opposite to the first surface, and a trench, the trench being provided in one of the first surface and the second surface; a photoelectric conversion region provided between the first surface and the second surface of the substrate; a color filter disposed on the second surface of the substrate; a fence pattern disposed between the color filters; a microlens layer disposed on the color filter; an impurity region disposed within the substrate and adjacent to the first surface of the substrate; a wiring layer disposed on the first surface of the substrate, the wiring layer including a lower insulating layer and a wiring structure; an insulating pattern covering the trench in the substrate; a doped region provided in the substrate and in contact with the insulating pattern; the insulating pattern includes a first surface and a second surface having different gradients; The doped region is a first portion on the first surface of the insulating pattern; a second portion on the second surface of the insulating pattern; the thickness of the second portion of the doped region is between 85% and 115% of the thickness of the first portion; the number of dopants per unit area of the second portion of the doped region is between 85% and 115% of the number of dopants per unit area of the first portion; The number of dopants per unit area of the first portion of the doped region is 5.0×10 １１ atoms / cm ２ ~1.0x10 １４ atoms / cm ２ and The number of dopants per unit area of the second portion of the doped region is 5.0×10 １１ atoms / cm ２ ~1.0x10 １４ atoms / cm ２ and Each of the first and second portions of the doped region comprises: a first region in contact with the insulating pattern and containing a dopant and an auxiliary element, the auxiliary element containing chlorine, fluorine or hydrogen; a second region interposed between the first region and the substrate, the second region including the dopant and not including the auxiliary element.

13. The image sensor of claim 12 , wherein a concentration of the auxiliary element in the first region is less than a concentration of the dopant in the first region.

14. the substrate includes, in a plan view, a pixel array region, a pad region, and an optical black region between the pixel array region and the pad region; the photoelectric conversion region, the color filter, and the microlens layer overlap with the pixel array region of the substrate in a plan view; The image sensor of claim 12 , wherein the doped region overlaps the pixel array region and the optical black region.

15. The image sensor of claim 12 , wherein the first surface of the insulating pattern is a side surface and the second surface of the insulating pattern is a bottom surface.

Images