SiC substrate manufacturing method

Abstract

The present invention addresses the problem of providing a novel SiC substrate production method. The SiC substrate production method according to the present invention comprises an etching step S10 of etching a SiC raw substrate 10, a crystal growth step S20 of growing a SiC substrate layer 13 on the SiC raw substrate 10 to produce a SiC substrate body 20, and a peeling step S30 of peeling at least a portion of the SiC substrate body 20 to produce a SiC substrate 30, the method being characterized in that each of the etching step S10 and the crystal growth step S20 is a step of arranging the SiC raw substrate 10 and a SiC material 40 so as to face each other and heating the SiC raw substrate 10 and the SiC material 40 so as to form a temperature gradient between the SiC raw substrate 10 and the SiC material 40.

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a SiC substrate. [Background technology]

[0002] SiC (silicon carbide) semiconductor devices are capable of higher voltage resistance, higher efficiency, and higher temperature operation than Si (silicon) and GaAs (gallium arsenide) semiconductor devices, and development is underway with a view to industrialization.

[0003] Generally, SiC substrates (SiC wafers) are manufactured by forming an SiC ingot by crystal growth of single crystal SiC on a seed crystal substrate by sublimation or the like, and slicing the ingot.

[0004] In addition, a method for manufacturing SiC wafers having epitaxial layers one by one has been proposed. Patent Document 1 describes a technique for manufacturing SiC wafers one by one by growing an epitaxial layer and a SiC substrate on a seed crystal substrate and then removing the SiC wafer from the seed crystal substrate. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-24932 Summary of the Invention [Problem to be solved by the invention]

[0006] However, in Patent Document 1, it is necessary to perform CMP polishing on the growth surface of the seed crystal substrate every time a SiC substrate is manufactured, which poses a problem of increased costs for CMP polishing.

[0007] Patent Document 1 also describes that the SiC substrate is grown using a solution method, a high-temperature CVD method, or a sublimation method. In particular, it describes that "by growing a SiC substrate using a solution method, growth can be achieved at a high growth rate, and crystal growth is performed in a state close to thermal equilibrium, resulting in a high-quality substrate with few defects." However, the solution method has the problem of making it difficult to obtain large-diameter SiC substrates. In addition, the high-temperature CVD method has the problem of low productivity in addition to the difficulty of increasing the diameter, while the sublimation method has the problem of high defect density in addition to the difficulty of increasing the diameter.

[0008] An object of the present invention is to provide a novel method for manufacturing a SiC substrate. Another object of the present invention is to provide a method for manufacturing a SiC substrate that allows for the manufacture of a large-diameter SiC substrate. [Means for solving the problem]

[0009] The present invention, which solves the above problems, includes an etching step of etching an SiC substrate; a crystal growth step of growing a SiC substrate layer on the SiC base substrate to obtain a SiC substrate body; a peeling step of peeling off a portion of the SiC substrate body to obtain a SiC substrate, The etching step and the crystal growth step are steps of placing the SiC substrate and a SiC material opposite each other and heating them so as to form a temperature gradient between the SiC substrate and the SiC material, in the method for manufacturing a SiC substrate.

[0010] In this way, by including the etching step and the crystal growth step, it is possible to manufacture a SiC substrate without carrying out CMP polishing. Furthermore, the etching process and the crystal growth process can be performed in the same environment (equipment system) on the SiC substrate. This means that the removal of the process-affected layer and the crystal growth of the SiC substrate layer can be performed in a single equipment system, eliminating the need to install multiple pieces of equipment and significantly reducing costs. Furthermore, by including the etching step and the crystal growth step, the life of the SiC material of the present invention can be extended.

[0011] In a preferred embodiment of the present invention, the etching step and the crystal growth step are steps of heating the SiC substrate and the SiC material in an atmosphere containing Si and C elements. In this way, the etching step and the crystal growth step are steps of heating in an atmosphere containing Si element and C element, so that a higher quality SiC substrate can be manufactured.

[0012] In a preferred embodiment of the present invention, the etching step and the crystal growth step are steps of heating the SiC substrate and the SiC material in a semi-closed space. In this way, the etching step and the crystal growth step are steps of heating in a semi-closed space, so that a higher quality SiC substrate can be manufactured.

[0013] In a preferred embodiment of the present invention, the etching step and the crystal growth step are steps of placing the SiC substrate in a main body vessel containing the SiC material and heating the substrate. In this way, by using a main body container containing a SiC material in the etching step and the crystal growth step, a semi-closed space with an atmosphere containing Si elements and C elements can be easily formed.

[0014] In a preferred embodiment of the present invention, the etching step is a step of placing the SiC substrate and the SiC material opposite each other and heating the SiC substrate to a higher temperature side and the SiC material to a lower temperature side. In a preferred embodiment of the present invention, the etching step includes a step of placing the SiC substrate and the SiC material opposite each other in a semi-closed space in which the atomic ratio Si / C exceeds 1, and heating the SiC substrate to a higher temperature side and the SiC material to a lower temperature side. In this way, by etching the SiC substrate using the temperature gradient as a driving force, it is possible to remove or reduce the damaged layer and macrostep bunching, and to manufacture a higher quality SiC substrate. Furthermore, since the surface of the SiC substrate is etched by providing a temperature gradient between the SiC substrate and the SiC material, it is possible to prevent the temperature distribution in the surface of the SiC substrate from varying significantly depending on the position, making it possible to manufacture high-quality, large-diameter (6 inches or more, even 8 inches or more) substrates.

[0015] In a preferred embodiment of the present invention, the crystal growth step is a step of placing the SiC substrate and the SiC material opposite each other and heating the SiC substrate to a low temperature side and the SiC material to a high temperature side. In a preferred embodiment of the present invention, the crystal growth step includes a step of arranging the SiC substrate and the SiC material so as to face each other in a semi-closed space in which the atomic ratio Si / C exceeds 1, and heating the SiC substrate so that it is on the low-temperature side and the SiC material is on the high-temperature side. In a preferred embodiment of the present invention, the crystal growth step includes a step of arranging the SiC substrate and the SiC material so as to face each other in a semi-closed space having an atomic ratio Si / C of 1 or less, and heating the SiC substrate so that it is on the low-temperature side and the SiC material is on the high-temperature side. In this way, by growing the SiC substrate layer using the temperature gradient as the driving force, basal plane dislocations and macrostep bunching can be eliminated or reduced, and a higher quality SiC substrate can be manufactured. Furthermore, since the SiC substrate layer is grown by providing a temperature gradient between the SiC substrate and the SiC material, it is possible to prevent the temperature distribution in the surface of the SiC substrate from varying significantly depending on the position, making it possible to manufacture high-quality, large-diameter (6 inches or more, even 8 inches or more) substrates.

[0016] In a preferred embodiment of the present invention, the delamination step includes a laser irradiation step of introducing a damage layer into the SiC substrate body, and a separation step of separating the SiC substrate body starting from the damage layer. In this way, by including the laser irradiation step and the separation step, it is possible to reduce material loss, and therefore there is no limit to the thickness of the SiC substrate body, and it is not necessary to form the SiC substrate body thick.

[0017] In a preferred embodiment of the present invention, the method further includes an etching step of etching the peeled SiC base substrate, a crystal growth step of growing a SiC substrate layer on the SiC base substrate to obtain a SiC substrate body, and a peeling step of peeling off a part of the SiC substrate body.

[0018] In a preferred embodiment of the present invention, the method further includes an etching step of etching the peeled SiC substrate layer, a crystal growth step of growing another SiC substrate layer on the SiC substrate layer to obtain a SiC substrate body, and a peeling step of peeling off a part of the SiC substrate body. [Effects of the Invention]

[0019] According to the present invention, a novel method for manufacturing a SiC substrate can be provided. Furthermore, according to the present invention, it is possible to provide a method for manufacturing a SiC substrate that is capable of manufacturing a large-diameter SiC substrate.

[0020] Other objects, features and advantages will become apparent from a reading of the following detailed description when taken in conjunction with the drawings and claims. [Brief explanation of the drawings]

[0021] [Figure 1] 1A to 1C are schematic diagrams illustrating a manufacturing process of a SiC substrate according to an embodiment. [Figure 2] 1A to 1C are explanatory diagrams of a manufacturing process of a SiC substrate according to an embodiment. [Figure 3] FIG. 2 is an explanatory diagram showing an outline of the etching process of the present invention. [Figure 4]FIG. 1 is an explanatory diagram showing an outline of a crystal growth process according to the present invention. [Figure 5] 1 is an explanatory diagram of an SiC substrate manufacturing apparatus according to an embodiment. [Figure 6] 1 is a schematic diagram of a main container and a high-melting-point container according to an embodiment. [Figure 7] 1 is a schematic diagram of a main container and a high-melting-point container according to an embodiment. [Figure 8] FIG. 2 is an explanatory diagram of a SiC substrate obtained by the etching process of the present invention. [Figure 9] FIG. 2 is an explanatory diagram of the surface of a SiC substrate obtained by the etching process of the present invention. [Figure 10] 2 is an explanatory diagram of the surface of a SiC substrate layer obtained in the crystal growth process of the present invention. FIG. [Figure 11] FIG. 1 is an explanatory diagram of a method for determining the BPD conversion rate in the crystal growth process of the present invention. [Figure 12] 2 is an explanatory diagram of a SiC substrate layer formed by the crystal growth process of the present invention. FIG. [Figure 13] 2 is an explanatory diagram of a SiC substrate layer formed by the crystal growth process of the present invention. FIG. [Figure 14] 1 is an Arrhenius plot of the etching process and the crystal growth process of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0022] The following describes in detail preferred embodiments of the present invention with reference to the accompanying drawings. The technical scope of the present invention is not limited to the embodiments shown in the accompanying drawings, and can be modified as appropriate within the scope of the claims.

[0023] <SiC substrate manufacturing method> As shown in FIGS. 1 and 2 , the present invention is a method for producing a new SiC substrate 30 from a SiC original substrate 10, and includes an etching step S10 of etching away a processed-affected layer 12 of the SiC original substrate 10, a crystal growth step S20 of growing a SiC substrate layer 13 on the SiC original substrate 10 to obtain a SiC substrate body 20, and a peeling step S30 of peeling off a portion of the SiC substrate body 20 to obtain a SiC substrate 30.

[0024] The etching step S10 and the crystal growth step S20 according to the present invention are steps of arranging the SiC substrate 10 and the SiC material 40 so as to face each other and heating them so as to form a temperature gradient between the SiC substrate 10 and the SiC material 40. By heating in this manner, the damaged layer 12 can be removed in the etching step S10, and the SiC substrate layer 13 can be grown in the crystal growth step S20. Each step of the present invention will be described in detail below.

[0025] Etching process As shown in FIG. 3, the etching step S10 is a step in which the SiC substrate 10 and the SiC material 40 are arranged opposite each other and heated to transport raw materials (Si element, C element, and dopant) from the SiC substrate 10 to the SiC material 40, thereby etching the surface of the SiC substrate 10.

[0026] In this etching step S10, it is preferable to heat the SiC substrate 10 and the SiC material 40 while placing them in a semi-closed space. This semi-closed space can be formed, for example, by accommodating them in a main body container 50, which will be described later. In this specification, the term "semi-closed space" refers to a space in which the container can be evacuated but in which at least a portion of the vapor generated in the container can be confined.

[0027] (SiC substrate) The SiC substrate 10 may be, for example, a single-crystal SiC processed into a plate shape. Specifically, it may be a SiC wafer sliced into a disk shape from a SiC ingot produced by a sublimation method or the like. Note that any polytype of single-crystal SiC may be used. Moreover, the SiC substrate 30 manufactured by the method for manufacturing a SiC substrate according to the present invention can also be used as an original SiC substrate.

[0028] Typically, a SiC substrate 10 that has undergone mechanical processing (e.g., slicing, grinding, and polishing) or laser processing has a process-affected layer 12 in which processing damage such as scratches, latent scratches, and distortion has been introduced, and a bulk layer 11 in which such processing damage has not been introduced (see FIG. 2).

[0029] The presence or absence and depth of this damaged layer 12 can be confirmed by SEM-EBSD, TEM, μXRD, Raman spectroscopy, etc. In order to produce a high-quality SiC substrate 10, it is preferable to remove the damaged layer 12 and expose the bulk layer 11 that is not damaged by processing.

[0030] Furthermore, a step-terrace structure is observed on the atomically planarized surface of the SiC base substrate 10 and the SiC substrate 30. This step-terrace structure is a staircase structure in which steps, which are step portions of one molecular layer or more, and terraces, which are flat portions where the {0001} plane is exposed, are arranged alternately.

[0031] The minimum height (minimum unit) of a step is one molecular layer (0.25 nm), and multiple layers of this single molecular layer form various step heights. In the explanations herein, steps that bunch together and become gigantic, with heights exceeding one unit cell of each polytype, are referred to as macrostep bunching (MSB).

[0032] That is, an MSB refers to a bunched step exceeding four molecular layers (five molecular layers or more) in the case of 4H-SiC, and to a bunched step exceeding six molecular layers (seven molecular layers or more) in the case of 6H-SiC.

[0033] It is desirable that these MSBs are not formed on the surface of the SiC substrate 10, since defects caused by the MSBs may occur during crystal growth.

[0034] The dopant may be any element that is generally doped into a SiC substrate, and specifically, nitrogen (N), phosphorus (P), aluminum (Al), boron (B), etc. are preferred.

[0035] The doping concentration of the SiC substrate 10 is preferably 1×10 17 cm -3 Higher concentrations, preferably 1×10 18 cm -3 or more, and more preferably 1×10 19 cm -3 That's all.

[0036] The dopants and doping concentrations can be confirmed by Raman spectroscopy or secondary ion mass spectroscopy (SIMS).

[0037] (SiC material) The SiC material 40 is made of SiC, which can supply elemental Si, elemental C, and dopants to the SiC substrate 10 by heating the SiC material 40 in opposition to the SiC substrate 10. For example, it includes a SiC container (main container 50) and a SiC substrate. Specifically, it is possible to form at least a portion of the container that houses the SiC substrate 10 (particularly the portion facing the SiC substrate 10) from the SiC material 40, or to arrange the SiC substrate that will become the SiC material 40 in the container so as to face the SiC substrate 10. That is, it is preferable that the SiC material 40 is single crystal SiC or polycrystalline SiC. Note that any polytype can be adopted as the crystal polymorph of the SiC material 40.

[0038] The dopant can be the same element as that used in the SiC substrate 10. Specifically, nitrogen (N), phosphorus (P), aluminum (Al), boron (B), etc. are preferred.

[0039] The doping concentration of the SiC material 40 may be set to the doping concentration of the SiC substrate 30 to be manufactured. For example, if a SiC substrate 30 with a high doping concentration is to be manufactured, the doping concentration of the SiC material 40 is preferably set to 1×10 17 cm -3 A higher concentration is used, preferably 1×10 18 cm -3 or more, more preferably 1×10 19 cm -3 The above can be adopted. On the other hand, if it is desired to manufacture a SiC substrate 30 with a high doping concentration, it is preferable to use a doping concentration of 1×10 17 cm -3 Use less than 1×10, more preferably 1×10 16 cm -3 The following is used, and more preferably 1 × 10 15 cm -3 The following may be adopted:

[0040] The dopants and doping concentrations can be confirmed by Raman spectroscopy or secondary ion mass spectroscopy (SIMS).

[0041] (Semi-closed space) The semi-closed space may be configured so that the atomic ratio Si / C is 1 or less. For example, when a SiC substrate 10 having a stoichiometric ratio of 1:1 is placed in a main body container 50 made of SiC and having a stoichiometric ratio of 1:1, the atomic ratio Si / C in the main body container 50 is 1 (see FIG. 7). Alternatively, a C vapor supply source (C pellets, etc.) may be placed to make the atomic ratio Si / C 1 or less.

[0042] The semi-closed space may also be configured so that the atomic ratio Si / C exceeds 1. For example, when a SiC substrate 10 having a stoichiometric ratio of 1:1 and a Si vapor supply source 55 (such as Si pellets) are placed in a main body vessel 50 made of SiC and having a stoichiometric ratio of 1:1, the atomic ratio Si / C in the main body vessel 50 exceeds 1 (see FIG. 6).

[0043] (Overview of the etching process) 3 is an explanatory diagram showing an outline of the etching step S10. In this etching step S10, the SiC substrate 10 is placed in a semi-closed space where the SiC material 40 is exposed, and is heated in a temperature range of 1400°C to 2300°C, whereby the following reactions 1) to 5) are continuously carried out, resulting in the progress of etching.

[0044] 1) SiC(s) → Si(v) + C(s) 2) 2C(s) + Si(v) → SiC2(v) 3) C(s) + 2Si(v) → SiC(v) 4) Si(v) + SiC2(v) → 2SiC(s) 5) SiC(v) → Si(v) + SiC(s)

[0045] Explanation of 1): When the SiC substrate 10 (SiC(s)) is heated, Si atoms (Si(v)) are desorbed from the surface of the SiC substrate 10 by thermal decomposition (Si atom sublimation process). Explanation of 2) and 3): As a result of the desorption of Si atoms (Si(v)), the C (C(s)) remaining on the surface of the SiC substrate 10 reacts with the Si vapor (Si(v)) in the semi-closed space. As a result, the C (C(s)) becomes SiC, SiC, etc., and sublimes from the surface of the SiC substrate 10 (C atom sublimation process). Explanation of 4) and 5): The sublimated Si2C or SiC2 etc. reaches the SiC material 40 in the semi-closed space due to the temperature gradient, and crystals grow.

[0046] Thus, the etching process S10 includes a Si atom sublimation process in which Si atoms are thermally sublimated from the surface of the SiC substrate 10, and a C atom sublimation process in which C atoms remaining on the surface of the SiC substrate 10 are sublimated from the surface of the SiC substrate 10 by reacting with Si vapor in the semi-closed space.

[0047] The etching step S10 is a step in which the SiC substrate 10 and the SiC material 40 are arranged opposite to each other and heated so that the SiC substrate 10 is on the high temperature side and the SiC material 40 is on the low temperature side. This forms an etching space X between the SiC substrate 10 and the SiC material 40, and the surface of the SiC substrate 10 can be etched using the temperature gradient as a driving force.

[0048] The etching step S10 also includes a step of placing the SiC substrate 10 and the SiC material 40 opposite each other in a semi-closed space in which the atomic ratio Si / C exceeds 1, and heating the SiC substrate 10 to be on the high temperature side and the SiC material 40 to be on the low temperature side. In this way, by etching the surface of the SiC substrate 10 in a semi-closed space in which the atomic ratio Si / C exceeds 1, the damaged layer 12 can be removed, and the MSB can also be removed.

[0049] <Crystal growth process> 4, the crystal growth step S20 is a step in which the SiC base substrate 10 and the SiC material 40 are arranged opposite each other and heated to transport raw materials (Si element, C element, dopant) from the SiC material 40 to the SiC base substrate 10, thereby growing the SiC substrate layer 13. By this crystal growth step S20, a SiC substrate body 20 is obtained in which the SiC substrate layer 13 is grown on the SiC base substrate 10.

[0050] In the crystal growth step S20, similarly to the etching step S10, it is preferable to heat the SiC substrate 10 and the SiC material 40 in a semi-closed space. This semi-closed space is formed by, for example, accommodating them in a main body container 50.

[0051] (Overview of the crystal growth process) 4 is an explanatory diagram showing an overview of the crystal growth step S20. In this crystal growth step S20, the SiC substrate 10 is placed in a semi-closed space where the SiC material 40 is exposed, and is heated in a temperature range of 1400°C to 2300°C, whereby the following reactions 1) to 5) are continuously carried out, which is thought to result in the progress of crystal growth.

[0052] 1) Poly-SiC(s) → Si(v) + C(s) 2) 2C(s) + Si(v) → SiC2(v) 3) C(s) + 2Si(v) → SiC(v) 4) Si(v) + SiC2(v) → 2SiC(s) 5) SiC(v) → Si(v) + SiC(s)

[0053] Explanation of 1): When SiC material (Poly-SiC(s)) is heated, Si atoms (Si(v)) are released from the SiC due to thermal decomposition. Explanation of 2) and 3): When Si atoms (Si(v)) are released, the remaining C (C(s)) reacts with the Si vapor (Si(v)) in the semi-closed space. As a result, the C (C(s)) becomes Si2C or SiC2, etc., and sublimes into the semi-closed space. Explanation of 4) and 5): The sublimated SiC or SiC, etc. reaches the terraces of the SiC substrate 10 due to the temperature gradient (or chemical potential difference), diffuses, and reaches the steps, whereby it grows while inheriting the polytype of the underlying SiC substrate 10 (step-flow growth).

[0054] Thus, the crystal growth process S20 includes a Si atom sublimation process in which Si atoms are thermally sublimated from the surface of the SiC material 40, a C atom sublimation process in which C atoms remaining on the surface of the SiC material 40 are sublimated by reacting with Si vapor in the semi-closed space, a raw material transport process in which the raw material is transported to the surface of the SiC original substrate 10 using a temperature gradient or a chemical potential difference as a driving force, and a step flow growth process in which the raw material reaches the steps of the SiC original substrate 10 and grows.

[0055] The raw materials herein include Si element, C element, and dopant. Therefore, the dopant of the SiC material 40 is transported together with the Si element and C element. As a result, the SiC substrate layer 13 grows while inheriting the doping concentration of the SiC material 40. Therefore, when it is desired to obtain a SiC substrate 30 having a specific doping concentration, the SiC substrate 30 having the desired doping concentration can be manufactured by employing a SiC material 40 having the desired doping concentration.

[0056] The crystal growth step S20 is a step in which the SiC substrate 10 and the SiC material 40 are arranged opposite to each other and heated so that the SiC substrate 10 is on the low temperature side and the SiC material 40 is on the high temperature side. This forms a crystal growth space Y between the SiC substrate 10 and the SiC material 40, and crystal growth can be performed on the SiC substrate 10 using the temperature gradient as a driving force.

[0057] The crystal growth process S20 also includes a process of placing the SiC substrate 10 and the SiC material 40 opposite each other in a semi-closed space in which the atomic ratio Si / C exceeds 1, and heating the SiC substrate 10 to be on the low temperature side and the SiC material 40 to be on the high temperature side. In this way, by growing the crystal in a semi-closed space in which the atomic ratio Si / C exceeds 1, it is possible to suppress the formation of MSBs on the surface of the SiC substrate layer 13.

[0058] The crystal growth process S20 also includes a process of placing the SiC substrate 10 and the SiC material 40 opposite each other in a semi-closed space with an atomic ratio Si / C of 1 or less, and heating the SiC substrate 10 to be on the low temperature side and the SiC material 40 to be on the high temperature side. In this way, by growing a crystal in a quasi-closed space with an atomic ratio Si / C of 1 or less, basal plane dislocations (BPDs) in the SiC substrate layer 13 can be eliminated or reduced.

[0059] When single-crystal SiC is used for the SiC substrate 10 and polycrystalline SiC is used for the SiC material 40, the partial pressure difference (chemical potential difference) generated at the surfaces of the polycrystalline SiC and single-crystal SiC can be used as the driving force for transporting the raw material to grow the crystal.

[0060] Peeling process The peeling step S30 is a step of peeling off a portion of the SiC substrate body 20 obtained in the crystal growth step S20 to obtain a SiC substrate 30. Examples of means for peeling off the SiC substrate 30 include multi-wire saw cutting, which cuts the substrate by reciprocating a plurality of wires, an electric discharge machining method, which cuts the substrate by intermittently generating plasma discharge, and a laser cutting method, which irradiates and focuses a laser into the crystal to form a layer that serves as a cutting base point.

[0061] Among these, it is preferable to employ a method using a laser, which results in less loss of material. The method of peeling using a laser will be described in detail below.

[0062] The peeling step S30 according to this embodiment includes a laser irradiation step S31 for introducing a damaged layer 14 into the SiC substrate body 20, and a separation step S32 for separating the SiC substrate body 20 from the damaged layer 14 as a starting point.

[0063] The laser irradiation step S31 is a step in which the focal point of a laser beam having a wavelength that is transparent to single-crystal SiC is positioned inside the SiC substrate body 20, and the laser beam is irradiated onto the SiC substrate body 20 to form a damaged layer 14 (see Figure 2).

[0064] The laser irradiation means L used in the laser irradiation step S31 includes, for example, a laser light source L1 that pulses laser light and a focusing lens L2 that focuses the laser light. By scanning this laser light, a damaged layer 14 is introduced into the SiC substrate body 20.

[0065] The separation step S32 is a step of separating the SiC substrate 30 from the SiC substrate body 20 along the damaged layer 14 by a wafer separation means P. An example of this wafer separation means P is a method of separating the SiC substrate body 20 by adsorbing the front and back surfaces of the SiC substrate body 20 to a pedestal or the like, as shown in Fig. 2. Separation may also be achieved by reciprocating a thin wire along the damaged layer 14, or by applying ultrasonic vibrations to cause separation starting from the damaged layer 14.

[0066] The laser irradiation step S31 and the separation step S32 can employ known techniques, such as those described in JP 2013-49161 A, JP 2018-207034 A, JP 2017-500725 A, and JP 2017-526161 A.

[0067] By going through the etching step S10, the crystal growth step S20, and the peeling step S30 described above, the SiC substrate 30 can be manufactured from the SiC base substrate 10. Although one SiC substrate 30 is peeled from one SiC base substrate 10 in Fig. 2, the SiC substrate layer 13 may be formed thick and multiple SiC substrates 30 may be peeled from it.

[0068] Furthermore, by performing the etching step S10 through the peeling step S30 on the original SiC substrate 10 from which the SiC substrate 30 has been peeled, the SiC substrate 30 can be repeatedly manufactured.

[0069] Furthermore, it is also possible to manufacture a new SiC substrate 30 using the SiC substrate 30 (SiC substrate layer 13) separated from the SiC substrate body 20. That is, the manufacturing method of the SiC substrate according to the other embodiment further includes an etching step S10 for removing a process-affected layer of the peeled SiC substrate layer 13, a crystal growth step S20 for growing another SiC substrate layer 13 on the SiC substrate layer 13 to obtain the SiC substrate body 20, and a peeling step S30 for peeling off a part of the SiC substrate body 20.

[0070] In this way, by using the manufactured SiC substrate 30 as the original SiC substrate 10, it is possible to manufacture further SiC substrates 30.

[0071] Furthermore, the damaged layer 14 remains on the separated SiC original substrate 10 and the SiC substrate 30. Therefore, as shown in FIG. 2, the separated SiC original substrate 10 and the SiC substrate 30 may be subjected to an etching step S10 to remove the damaged layer 14 (process-affected layer).

[0072] Furthermore, if undulations are formed on the surfaces of the SiC base substrate 10 and the SiC substrate 30 after separation, the undulations may be removed by performing a mechanical polishing process such as a lapping process.

[0073] According to the SiC substrate manufacturing method of the present invention, the etching step S10 and the crystal growth step S20 heat-treat the SiC substrate 10 in the same environment (equipment system). Conventionally, it was necessary to separately introduce or outsource an apparatus for CMP polishing to remove the damaged layer 12 and an apparatus for crystal growth. According to the present invention, multiple steps can be performed using a single equipment system, which allows for significant cost reductions.

[0074] Furthermore, when the etching step S10 and the crystal growth step S20 are performed using the same SiC material 40, the raw material consumed in the crystal growth step S20 is replenished in the etching step S10, thereby extending the life of the SiC material 40.

[0075] Furthermore, according to the crystal growth step S20 of the present invention, SiC substrates 30 having desired specifications can be manufactured one by one (or a small number of substrates at a time). Therefore, SiC substrates 30 having desired doping concentrations can be manufactured one by one. Furthermore, by selecting the SiC material 40, it is possible to manufacture the SiC substrates 30 by controlling the doping concentration one by one.

[0076] Furthermore, according to the crystal growth step S20 of the present invention, it is only necessary to grow the crystal to the thickness of the SiC substrate layer 13, which makes it easy to maintain an environment for forming a high-quality SiC substrate 30. That is, compared to forming an ingot whose growth point changes as the growth progresses (sublimation method), it is possible to manufacture a high-quality SiC substrate 30 with less material loss. Furthermore, since a temperature gradient is provided along the direction in which the SiC substrate 10 and the SiC material 40 face each other, it is possible to easily control the temperature distribution within the surface of the SiC substrate 10 to be approximately uniform. This makes it possible to manufacture SiC substrates with large diameters, such as 6 inches or more or 8 inches or more.

[0077] <SiC substrate manufacturing equipment> A manufacturing apparatus for realizing the manufacturing method of a SiC substrate according to the present invention will be described in detail below. In this embodiment, components that are basically the same as those shown in the previous manufacturing method will be assigned the same reference numerals and their description will be simplified.

[0078] As shown in FIG. 5, the SiC substrate manufacturing apparatus according to this embodiment includes a main body container 50 capable of accommodating the SiC base substrate 10 and containing the SiC material 40, and a heating furnace 60 capable of heating so as to form a temperature gradient between the SiC base substrate 10 and the SiC material 40.

[0079] (Main container) The main container 50 is a fitting container that includes an upper container 51 and a lower container 52 that can fit together. A minute gap 53 is formed at the fitting portion between the upper container 51 and the lower container 52, and the main container 50 is configured to be able to be evacuated (vacuumed) through this gap 53.

[0080] The main container 50 also has a SiC material 40 arranged opposite the SiC substrate 10, and a raw material transport space S1 for transporting raw material between the SiC material 40 and the SiC substrate 10. The doping concentration of the SiC material 40 is preferably set to a doping concentration corresponding to the desired SiC substrate 30.

[0081] The upper container 51 and the lower container 52 according to this embodiment are made of polycrystalline SiC. Therefore, the main container 50 itself is made of the SiC material 40. Note that only the portion of the main container 50 facing the SiC substrate 10 may be made of the SiC material 40. In this case, a high-melting-point material (the same material as the high-melting-point container 70 described later) can be used for the portions other than the SiC material 40.

[0082] Although not shown, a high-melting-point material may be used for the entire main container 50, and a substrate-like SiC material 40 may be separately housed therein. In this case, a spacer (such as a substrate holder 54 described later) may be disposed between the substrate-like SiC material 40 and the SiC base substrate 10 to form the etching space X or the crystal growth space Y.

[0083] That is, the main body container 50 is configured to generate an atmosphere containing Si and C elements in the internal space when heat treatment is performed with the SiC base substrate 10 housed therein. In this embodiment, the main body container 50 made of polycrystalline SiC is heated to form an atmosphere containing Si and C elements in the internal space.

[0084] Furthermore, the space inside the heat-treated main container 50 is preferably a vapor pressure environment of a mixture of gaseous species containing Si element and gaseous species containing C element. Examples of gaseous species containing Si element include Si, Si2, Si3, Si2C, SiC2, and SiC. Examples of gaseous species containing C element include Si2C, SiC2, SiC, and C. In other words, it is preferable that the SiC-based gas exists in a semi-closed space.

[0085] The raw material transport space S1 is a space for transporting raw materials from the SiC substrate 10 to the SiC material 40 using the temperature gradient established between the SiC substrate 10 and the SiC material 40 as a driving force, and is also a space for transporting raw materials from the SiC material 40 to the SiC substrate 10.

[0086] For example, consider a case where the SiC substrate 10 is arranged so that the temperature of the surface of the SiC substrate 10 is higher than that of the SiC material 40 facing this surface (see FIG. 6). In this way, when the SiC substrate 10 and the SiC material 40 are arranged facing each other and heated so that the SiC substrate 10 is on the high temperature side and the SiC material 40 is on the low temperature side, raw material is transported from the SiC substrate 10 to the SiC material 40, and the SiC substrate 10 is etched. That is, by setting such a temperature gradient and heating, an etching space X is formed in the raw material transport space S1.

[0087] 6, the main vessel 50 may have a substrate holder 54 for placing the SiC substrate 10 on the high-temperature side of the temperature gradient. By providing the substrate holder 54 in this manner, the SiC substrate 10 can be placed on the high-temperature side of the temperature gradient formed by the heating furnace 60, thereby forming an etching space X for the SiC substrate 10. Note that the substrate holder 54 is preferably made of the same high-melting-point material as the high-melting-point vessel 70.

[0088] On the other hand, consider a case where the SiC substrate 10 is arranged so that the temperature of the SiC substrate 10 side is lower and the temperature of the upper container 51 is higher when comparing the temperature of the surface of the SiC substrate 10 with the temperature of the SiC material 40 facing this surface (see FIG. 7). In this way, when the SiC substrate 10 and the SiC material 40 are arranged opposite each other and heated so that the SiC substrate 10 is on the low temperature side and the SiC material 40 is on the high temperature side, raw material is transported from the SiC material 40 to the SiC substrate 10, and a SiC substrate layer 13 grows on the SiC substrate 10. That is, by setting such a temperature gradient and heating, a crystal growth space Y is formed in the raw material transport space S1.

[0089] 6 is the etching step S10 of the SiC substrate manufacturing method of the present invention, and the step shown in Fig. 7 is the crystal growth step S20. In this case, the SiC material 40 undergoes crystal growth in the etching step S10, and the SiC material 40 is etched in the crystal growth step S20. Therefore, it is preferable that the SiC material 40 facing the SiC substrate 10 is a partial portion in the etching step S10 and the crystal growth step S20.

[0090] Specifically, since crystal growth occurs in the lower container 52 in the etching step S10 of Fig. 6, it is preferable to place the lower container 52 on the high temperature side of the temperature gradient in the crystal growth step S20 of Fig. 7 to supply material to the SiC base substrate 10. In this way, by etching the portion of the SiC material 40 grown in the etching step S10 in the crystal growth step S20, the life of the SiC material 40 can be extended. 6 and 7 show an example in which the main vessel 50 is inverted, but it is also possible to use the same portion of the SiC material 40 by reversing the temperature gradient of the heating furnace 60.

[0091] 6, main container 50 may be provided with a Si vapor supply source 55 capable of supplying Si vapor into the container. Examples of this Si vapor supply source 55 include solid Si (single crystal Si pieces, Si pellets such as Si powder, etc.) and Si compounds.

[0092] For example, when the entire main body container 50 is made of polycrystalline SiC as in this embodiment, the atomic ratio Si / C in the main body container 50 exceeds 1 by arranging the Si vapor supply source 55. Specifically, when a SiC substrate 10 having a stoichiometric ratio of 1:1 and a Si vapor supply source 55 (such as Si pellets) are placed in a main body container 50 made of polycrystalline SiC having a stoichiometric ratio of 1:1, the atomic ratio Si / C in the main body container 50 exceeds 1.

[0093] In this way, by heating a space where the atomic ratio Si / C exceeds 1, it is possible to approach a vapor pressure environment (SiC-Si equilibrium vapor pressure environment) when SiC (solid) and Si (liquid phase) are in phase equilibrium via the gas phase.

[0094] On the other hand, if no Si vapor supply source is provided inside main vessel 50, the atomic ratio Si / C inside main vessel 50 will be 1 or less. Specifically, when a SiC substrate 10 having a stoichiometric ratio of 1:1 is placed inside a main body container 50 made of polycrystalline SiC having a stoichiometric ratio of 1:1, the atomic ratio Si / C inside the main body container 50 becomes 1.

[0095] In this way, by heating a space where the atomic ratio Si / C is 1 or less, it is possible to approach a vapor pressure environment (SiC-C equilibrium vapor pressure environment) when SiC (solid phase) and C (solid phase) are in phase equilibrium via the gas phase.

[0096] In this specification, the SiC-Si equilibrium vapor pressure environment and the SiC-C equilibrium vapor pressure environment include a near-thermal equilibrium vapor pressure environment that satisfies the relationship between growth rate and growth temperature derived from a theoretical thermal equilibrium environment.

[0097] (heating furnace) As shown in FIG. 5, the heating furnace 60 includes a main heating chamber 61 capable of heating the workpiece (such as a SiC substrate 10) to a temperature of 1000°C or higher and 2300°C or lower, a preheating chamber 62 capable of preheating the workpiece to a temperature of 500°C or higher, a high-melting-point container 70 capable of accommodating the main container 50, and a moving means 63 (moving table) capable of moving the high-melting-point container 70 from the preheating chamber 62 to the main heating chamber 61.

[0098] The main heating chamber 61 is formed in a regular hexagonal shape in a planar cross section, and a high-melting-point container 70 is placed inside the main heating chamber 61. A heater 64 (mesh heater) is provided inside the main heating chamber 61. In addition, multi-layer heat-reflecting metal plates (not shown) are fixed to the side walls and ceiling of the main heating chamber 61. The multi-layer heat-reflecting metal plates are configured to reflect heat from the heater 64 toward approximately the center of the main heating chamber 61.

[0099] As a result, within the main heating chamber 61, a heating heater 64 is arranged to surround the high-melting-point container 70 in which the workpiece is housed, and a multilayer heat-reflecting metal plate is further arranged on the outside of that, allowing the temperature to be raised to a temperature of 1000°C or higher and 2300°C or lower. The heater 64 may be, for example, a resistance heating heater or a high-frequency induction heating heater.

[0100] The heater 64 may also be configured to be capable of forming a temperature gradient within the high-melting-point container 70. For example, the heater 64 may be configured so that more heaters are arranged on the upper side. The heater 64 may also be configured so that its width increases toward the upper side. Alternatively, the heater 64 may be configured so that the power supplied to it increases toward the upper side.

[0101] In addition, the main heating chamber 61 is connected to a vacuum forming valve 65 that evacuates the main heating chamber 61, an inert gas injection valve 66 that introduces inert gas into the main heating chamber 61, and a vacuum gauge 67 that measures the degree of vacuum inside the main heating chamber 61.

[0102] The vacuum forming valve 65 is connected to a vacuum pump (not shown) that evacuates the main heating chamber 61 to create a vacuum. By using the vacuum forming valve 65 and the vacuum pump, the degree of vacuum in the main heating chamber 61 can be set to, for example, 10 Pa or less, more preferably 1 Pa or less, and even more preferably 10 -3 The pressure can be adjusted to below Pa. An example of the vacuum pump is a turbo molecular pump.

[0103] The inert gas injection valve 66 is connected to an inert gas supply source (not shown). The inert gas is injected into the heating chamber 61 by the inert gas injection valve 66 and the inert gas supply source. -5 It can be introduced at a pressure in the range of up to 10,000 Pa. As this inert gas, Ar, He, N2, etc. can be selected.

[0104] The inert gas injection valve 66 is a dopant gas supply means capable of supplying a dopant gas into the main body container 50. That is, by selecting a dopant gas (e.g., N2, etc.) as the inert gas, the doping concentration of the SiC substrate layer 13 can be adjusted.

[0105] The preheating chamber 62 is connected to the main heating chamber 61, and is configured so that the high-melting-point container 70 can be moved by a moving means 63. The preheating chamber 62 of this embodiment is configured so that it can be heated by the residual heat of the heater 64 of the main heating chamber 61. For example, when the main heating chamber 61 is heated to 2000°C, the preheating chamber 62 is heated to about 1000°C, and degassing of the workpieces (SiC base substrate 10, main container 50, high-melting-point container 70, etc.) can be performed.

[0106] The moving means 63 is configured to be able to place the high-melting-point container 70 and move it between the main heating chamber 61 and the preheating chamber 62. The transfer between the main heating chamber 61 and the preheating chamber 62 by the moving means 63 can be completed in as little as one minute, making it possible to achieve a temperature increase and decrease rate of 1 to 1000°C / min. Since the temperature can be increased and decreased rapidly in this manner, it is possible to observe the surface shape that does not have a history of low-temperature growth during the temperature increase and decrease, which was difficult with conventional devices. In addition, in FIG. 3, the preheating chamber 62 is arranged below the main heating chamber 61, but this is not limitative and the chamber may be arranged in any direction.

[0107] Furthermore, the moving means 63 according to this embodiment is a moving stage on which the high-melting-point container 70 is placed. A small amount of heat is released from the contact area between the moving stage and the high-melting-point container 70. This allows a temperature gradient to be formed inside the high-melting-point container 70 (and inside the main container 50). That is, in the heating furnace 60 of this embodiment, the bottom of the high-melting-point container 70 is in contact with the moving stage, so a temperature gradient is provided such that the temperature decreases from the upper container 71 to the lower container 72 of the high-melting-point container 70. This temperature gradient is preferably formed along the front-to-back direction of the SiC substrate 10. As described above, a temperature gradient may be formed by the configuration of the heater 64. The heater 64 may be configured to be reversible.

[0108] (High melting point container) The heating furnace 60 preferably forms an atmosphere containing Si element and is capable of heating the main container 50 in this atmosphere. The atmosphere containing Si element in the heating furnace 60 according to this embodiment is formed using a high-melting-point container 70 and a Si vapor supply source 74. Naturally, any method can be used as long as it can form an atmosphere containing Si elements around main vessel 50.

[0109] The high-melting-point container 70 is configured to contain a high-melting-point material, such as C, which is a general-purpose heat-resistant member; W, Re, Os, Ta, and Mo, which are high-melting-point metals; Ta9C8, HfC, TaC, NbC, ZrC, Ta2C, TiC, WC, and MoC, which are carbides; HfN, TaN, BN, Ta2N, ZrN, and TiN, which are nitrides; HfB2, TaB2, ZrB2, Nb2, and TiB2, which are borides; and polycrystalline SiC.

[0110] Like the main container 50, the high-melting-point container 70 is a fitting container having an upper container 71 and a lower container 72 that can fit together, and is configured to be able to accommodate the main container 50. A minute gap 73 is formed at the fitting portion between the upper container 71 and the lower container 72, and the high-melting-point container 70 is configured to be able to be evacuated (vacuumed) through this gap 73.

[0111] The high-melting-point container 70 preferably has a Si vapor supply source 55 capable of supplying the vapor pressure of a gaseous species containing Si element into the high-melting-point container 70. The Si vapor supply source 55 may be configured to generate Si vapor in the high-melting-point container 70 during heat treatment, and examples of the Si vapor supply source include solid Si (single-crystal Si pieces, Si pellets such as Si powder, etc.) and Si compounds.

[0112] The SiC substrate manufacturing apparatus according to this embodiment employs TaC as the material of the high-melting-point container 70 and tantalum silicide as the Si vapor supply source 55. That is, as shown in Fig. 4, a tantalum silicide layer is formed inside the high-melting-point container 70, and Si vapor is supplied from the tantalum silicide layer into the container during heat treatment, thereby creating a Si vapor pressure environment. In addition to this, any other configuration can be adopted as long as the vapor pressure of the gaseous species containing the Si element is generated in the high-melting-point container 70 during the heat treatment. [Example]

[0113] The present invention will be described more specifically below with reference to Examples 1, 2, 3, 4, 5 and 6. Example 1 is an example that specifically describes the removal or reduction of the process-affected layer 12 in the etching step S10. Example 2 is an example that specifically describes the removal or reduction of MSB in the etching step S10. Example 3 is an example that specifically describes the removal or reduction of MSB in the crystal growth step S20. Example 4 is an example that specifically describes the removal or reduction of BPD in the crystal growth step S20. Examples 5 and 6 are examples that describe the control of the doping concentration in the crystal growth step S20.

[0114] Example 1: Removal or reduction of process-affected layer in etching process The SiC substrate 10 was placed in the main body container 50 and the high-melting-point container 70, and was heat-treated under the following heat-treatment conditions.

[0115] [SiC substrate 10] Polymorphism: 4H-SiC Board size: 10mm wide x 10mm long x 0.45mm thick Off direction and off angle: 4° off in the <11-20> direction Etched surface: (0001) surface Depth of processing-affected layer 12: 5 μm The depth of the damaged layer 12 was confirmed by SEM-EBSD. The damaged layer 12 can also be confirmed by TEM, μXRD, or Raman spectroscopy.

[0116] [Main container 50] Material: Polycrystalline SiC Container size: diameter 60mm x height 4mm Material of substrate holder 54: Single crystal SiC Distance between the SiC substrate 10 and the bottom of the main container 50: 2 mm Atomic ratio Si / C in the container: 1 or less

[0117] [High melting point container 70] Material: TaC Container size: diameter 160mm x height 60mm Si vapor source 74 (Si compound): TaSi2

[0118] [Heat treatment conditions] The SiC substrate 10 arranged under the above conditions was subjected to a heat treatment under the following conditions. Heating temperature: 1800℃ Heating time: 20min Etching amount: 5 μm Temperature gradient: 1°C / mm Etching speed: 0.25 μm / min Main heating chamber vacuum degree: 10 -5 Pa

[0119] [Measurement of processing-affected layers using SEM-EBSD method] The lattice strain of the SiC substrate 10 can be determined by comparing it with a reference crystal lattice. For example, the SEM-EBSD method can be used to measure this lattice strain. The SEM-EBSD method is a technique (Electron Backscattering Diffraction (EBSD)) that can measure strain in a microscopic area based on a Kikuchi diffraction pattern obtained by backscattering electron beams in a scanning electron microscope (SEM). This technique can determine the amount of lattice strain by comparing the diffraction pattern of the reference crystal lattice with the diffraction pattern of the measured crystal lattice.

[0120] For the reference crystal lattice, a reference point is set in a region where lattice distortion is not considered to occur. That is, it is desirable to place the reference point in the region of the bulk layer 11. It is generally accepted that the depth of the damaged layer 12 is about 10 μm. Therefore, it is sufficient to set the reference point at a depth of about 20 to 35 μm, which is considered to be sufficiently deeper than the damaged layer 12.

[0121] Next, the diffraction pattern of the crystal lattice at this reference point is compared with the diffraction pattern of the crystal lattice in each measurement area measured at a pitch on the order of nanometers, allowing the amount of lattice strain in each measurement area relative to the reference point to be calculated.

[0122] Furthermore, although the case where a reference point where no lattice distortion is thought to occur is set as the reference crystal lattice has been shown, it is of course also possible to use an ideal crystal lattice of single crystal SiC as the reference, or to use a crystal lattice that occupies the majority (e.g., more than half) of the surface of the measurement area as the reference.

[0123] By measuring whether or not lattice strain exists using the SEM-EBSD method, it is possible to determine the presence or absence of the process-affected layer 12. That is, if processing damage such as scratches, latent scratches, or strain has been introduced, lattice strain occurs in the SiC base substrate 10, and therefore stress can be observed using the SEM-EBSD method.

[0124] The damaged layer 12 present on the SiC substrate 10 of Example 1 before and after the etching step S10 was observed by the SEM-EBSD method, and the results are shown in Figures 8(a) and 8(b).

[0125] In this measurement, the cross section of the cleaved SiC substrate 10 before and after the etching step S10 in Example 1 was measured using a scanning electron microscope under the following conditions. SEM equipment: Zeiss Merline EBSD analysis: TSL Solutions OIM crystal orientation analyzer Accelerating voltage: 15 kV Probe current: 15nA Step size: 200nm Reference point R depth: 20 μm

[0126] FIG. 8(a) is a cross-sectional SEM-EBSD image of the SiC substrate 10 before the etching step S10 in Example 1. As shown in Fig. 8(a), before the etching step S10, lattice strain was observed to a depth of 5 µm in the SiC base substrate 10. This is lattice strain introduced during machining, and it is clear that there is a work-affected layer 12. Note that compressive stress is observed in Fig. 8(a).

[0127] FIG. 8(b) is a cross-sectional SEM-EBSD image of the SiC substrate 10 after the etching step S10 in Example 1. 8(b), after the etching step S10, no lattice distortion was observed in the SiC substrate 10. That is, it can be seen that the damaged layer 12 was removed by the etching step S10. After etching, MSBs were formed on the surface of the SiC substrate 10.

[0128] Thus, according to the etching step S10, the SiC original substrate 10 and the SiC material 40 are disposed opposite to each other, and etching is performed by heating the SiC original substrate 10 to the high temperature side and the SiC material 40 to the low temperature side, thereby removing or reducing the damaged layer 12. This allows the SiC substrate layer 13 to be formed on the bulk layer 11 from which the damaged layer 12 has been reduced or removed, thereby manufacturing a high-quality SiC substrate 30.

[0129] Example 2: Elimination or reduction of MSB in the etching process The SiC substrate 10 was placed in the main body container 50 and the high-melting-point container 70, and was heat-treated under the following heat-treatment conditions.

[0130] [SiC substrate 10] Polymorphism: 4H-SiC Board size: 10mm wide x 10mm long x 0.3mm thick Off direction and off angle: 4° off in the <11-20> direction Etched surface: (0001) surface MSB: Yes

[0131] The step height, terrace width, and presence or absence of MSB can be confirmed by an atomic force microscope (AFM) or a method for evaluating the contrast of a scanning electron microscope (SEM) image described in JP 2015-179082 A.

[0132] [Main container 50] Material: Polycrystalline SiC Container size: diameter 60mm x height 4mm Material of substrate holder 54: Single crystal SiC Distance between the SiC substrate 10 and the bottom of the main container 50: 2 mm Si vapor source 55: single crystal Si piece The atomic ratio in the container is Si / C: more than 1

[0133] In this way, by storing the Si pieces together with the SiC base substrate 10 in the main container 50, the atomic ratio Si / C in the container exceeds 1.

[0134] [High melting point container 70] Material: TaC Container size: diameter 160mm x height 60mm Si vapor source 74 (Si compound): TaSi2

[0135] [Heat treatment conditions] The SiC substrate 10 arranged under the above conditions was subjected to a heat treatment under the following conditions. Heating temperature: 1900℃ Heating time: 60min Temperature gradient: 1°C / mm Etching speed: 300nm / min Main heating chamber vacuum degree: 10 -5 Pa

[0136] The steps on the surface of the SiC substrate 10 of Example 2 before and after the etching step S10 were observed by SEM. The results are shown in Figures 9(a) and 9(b). The step height was measured by an atomic force microscope (AFM). The terrace width was also measured by SEM. The terrace width was calculated by drawing a line perpendicular to the steps in the SEM image and counting the number of steps on this line (terrace width = line length / number of steps on the line).

[0137] 9(a) is an SEM image of the surface of the SiC substrate 10 before the etching step S10 in Example 2. MSBs with a height of 3 nm or more were formed on the surface of the SiC substrate 10 before the etching step S10. The step height was measured by AFM.

[0138] 9(b) is an SEM image of the surface of the SiC substrate 10 after the etching step S10 of Example 2. It can be seen that no MSBs are formed on the surface of the SiC substrate 10 after the etching step S10 of Example 2, and steps of 1.0 nm (full unit cell) are regularly arranged.

[0139] Thus, according to the etching step S10, the MSBs can be reduced or removed by etching the SiC base substrate 10 in a semi-closed space in which the atomic ratio Si / C exceeds 1. This allows the SiC substrate layer 13 to be formed on the bulk layer 11 in which the MSBs have been reduced or removed, and a high-quality SiC substrate 30 can be manufactured.

[0140] Furthermore, when observed by the SEM-EBSD method, the damaged layer 12 was also removed from the SiC substrate 10 after the etching step S10 in Example 2.

[0141] Example 3: Removal or reduction of MSB in the crystal growth process The SiC substrate 10 was placed in the main body container 50 and the high-melting-point container 70, and was heat-treated under the following heat-treatment conditions.

[0142] [SiC substrate 10] Polymorphism: 4H-SiC Board size: 10mm wide x 10mm long x 0.3mm thick Off direction and off angle: 4° off in the <11-20> direction Etched surface: (0001) surface MSB: Yes

[0143] [Main container 50] Material: Polycrystalline SiC Container size: diameter 60mm x height 4mm Distance between the SiC substrate 10 and the bottom of the main container 50: 2 mm Si vapor source 55: single crystal Si piece The atomic ratio in the container is Si / C: more than 1

[0144] In this way, by storing the Si pieces together with the SiC base substrate 10 in the main container 50, the atomic ratio Si / C in the container exceeds 1.

[0145] [High melting point container 70] Material: TaC Container size: diameter 160mm x height 60mm Si vapor source 74 (Si compound): TaSi2

[0146] [Heat treatment conditions] The SiC substrate 10 arranged under the above conditions was subjected to a heat treatment under the following conditions. Heating temperature: 1800℃ Heating time: 60min Temperature gradient: 1°C / mm Growth rate: 68nm / min Main heating chamber 61 vacuum degree: 10 -5 Pa

[0147] The steps on the surface of the SiC substrate 10 of Example 3 after the crystal growth step S20 were observed by SEM. The results are shown in Fig. 10. The step height was measured by an atomic force microscope (AFM), and the terrace width was measured by SEM.

[0148] Fig. 10 is an SEM image of the surface of the SiC base substrate 10 after the crystal growth step S20 of Example 3. Similar to Fig. 9(a), MSBs with a height of 3 nm or more were formed on the surface of the SiC base substrate 10 before the crystal growth step S20. As shown in Fig. 10, no MSBs were formed on the surface of the SiC base substrate 10 after the crystal growth step S20 of Example 3, and steps of 1.0 nm (full unit cell) were found to be regularly arranged.

[0149] Thus, according to the crystal growth step S20, it is possible to form a SiC substrate layer 13 free of MSBs by growing the SiC base substrate 10 in a semi-closed space in which the atomic ratio Si / C exceeds 1. This makes it possible to manufacture a SiC substrate 30 in which MSBs are reduced or removed.

[0150] Example 4: Removal or reduction of BPD in the crystal growth process The SiC substrate 10 was placed in the main body container 50 and the high-melting-point container 70, and was heat-treated under the following heat-treatment conditions.

[0151] [SiC substrate 10] Polymorphism: 4H-SiC Board size: 10mm wide x 10mm long x 0.3mm thick Off direction and off angle: 4° off in the <11-20> direction Growth plane: (0001) plane MSB: None Presence or absence of processing-affected layer 12: None

[0152] [Main container 50] Material: Polycrystalline SiC Container size: diameter 60mm x height 4mm Distance between SiC substrate 10 and SiC material 40: 2 mm Atomic ratio Si / C in the container: 1 or less

[0153] [High melting point container 70] Material: TaC Container size: diameter 160mm x height 60mm Si vapor source 74 (Si compound): TaSi2

[0154] [Heat treatment conditions] The SiC substrate 10 arranged under the above conditions was subjected to a heat treatment under the following conditions. Heating temperature: 1700℃ Heating time: 300min Temperature gradient: 1°C / mm Growth rate: 5nm / min Main heating chamber 61 vacuum degree: 10 -5 Pa

[0155] (BPD conversion rate in SiC substrate layer) FIG. 11 is an explanatory diagram of a method for determining the conversion rate of BPDs into other defects / dislocations (TEDs, etc.) in the SiC substrate layer 13. In FIG. 11(a) shows the state of growing the SiC substrate layer 13 in the crystal growth step S20. In this heating step, the BPDs present in the SiC original substrate 10 are converted to TEDs with a certain probability. Therefore, unless 100% conversion is achieved, TEDs and BPDs will be mixed on the surface of the SiC substrate layer 13. Figure 11(b) shows the state of defects in the SiC substrate layer 13 confirmed using the KOH dissolution etching method. This KOH dissolution etching method involves immersing the SiC substrate in molten salt (such as KOH) heated to approximately 500°C, forming etch pits at dislocations or defect locations, and identifying the type of dislocation based on the size and shape of the etch pits. This method allows the number of BPDs present on the surface of the SiC substrate layer 13 to be obtained. 11(c) shows the removal of the SiC substrate layer 13 after KOH dissolution etching. In this method, after planarization to the depth of the etch pits by mechanical polishing, CMP, or the like, the SiC substrate layer 13 is removed by thermal etching to expose the surface of the SiC original substrate 10. 11(d) shows the state in which defects in the SiC original substrate 10 are confirmed by KOH dissolution etching for the SiC original substrate 10 from which the SiC substrate layer 13 has been removed. By this method, the number of BPDs present on the surface of the SiC original substrate 10 is obtained.

[0156] By following the sequence shown in Figure 11, the number of BPDs present on the surface of the SiC substrate layer 13 (see Figure 11(b)) can be compared with the number of BPDs present on the surface of the SiC base substrate 10 (see Figure 11(d)), thereby obtaining the BPD conversion rate of BPDs converted to other defects and dislocations during the crystal growth step S20.

[0157] The number of BPDs present on the surface of the SiC substrate layer 13 in Example 4 was 0 cm -2 The number of BPDs present in the bulk layer 11 is about 1000 cm -2 It was. That is, it can be seen that BPDs can be reduced or eliminated by placing the SiC substrate 10, which does not have MSBs on its surface, in a semi-closed space where the atomic ratio Si / C is 1 or less and growing the crystal.

[0158] Thus, according to the crystal growth step S20, it is possible to form a SiC substrate layer 13 having a surface in which BPDs are reduced or removed by growing the SiC base substrate 10 in a semi-closed space in which the atomic ratio Si / C is 1 or less. This makes it possible to manufacture a SiC substrate 30 having a SiC substrate layer 13 in which BPDs are reduced or removed.

[0159] Example 5: Control of doping concentration in the crystal growth process The SiC substrate 10 was placed in the main body container 50 and the high-melting-point container 70, and was heat-treated under the following heat-treatment conditions.

[0160] [SiC substrate 10] Polymorphism: 4H-SiC Board size: 10mm wide x 10mm long x 0.3mm thick Off direction and off angle: 4° off in the <11-20> direction Growth plane: (0001) plane Dopant: N Doping concentration: 3×10 18 cm -3 MSB: None Presence or absence of processing-affected layer 12: None

[0161] The dopants and doping concentrations of the SiC substrate 10 were confirmed by Raman spectroscopy.

[0162] [Main container 50] Material: Polycrystalline SiC Container size: diameter 60mm x height 4mm Distance between SiC substrate 10 and SiC material 40: 2 mm Dopant: N Doping concentration: 1×10 17 cm -3 or less (below the detection limit of Raman spectroscopy) Atomic ratio Si / C in the container: 1 or less

[0163] [High melting point container 70] Material: TaC Container size: diameter 160mm x height 60mm Si vapor source 74 (Si compound): TaSi2

[0164] [Heat treatment conditions] The SiC substrate 10 arranged under the above conditions was subjected to a heat treatment under the following conditions. Heating temperature: 1700℃ Heating time: 300min Temperature gradient: 1°C / mm Growth rate: 5nm / min Main heating chamber 61 vacuum degree: 10 -5 Pa

[0165] 12 is an SEM image of the cross section of the SiC substrate of Example 5 grown under the above conditions, observed at a magnification of ×10000. The thickness of the SiC substrate layer 13 of Example 5 was 1.5 μm.

[0166] The doping concentration of the SiC substrate layer 13 in Example 5 is 1×10 17 cm -3 The doping concentration of the SiC substrate 10 is 3×10 18 cm -3 This shows that the SiC substrate layer 13 inherits the doping concentration of the SiC material 40. Furthermore, as shown in FIG. 12 , the SEM image contrast of the SiC substrate layer 13 is brighter than that of the SiC original substrate 10, which also shows that the doping concentration of the SiC substrate layer 13 is lower than that of the SiC original substrate 10.

[0167] Example 6: Control of doping concentration in the crystal growth process The SiC substrate 10 was housed in the main container 50 and the high-melting-point container 70 under the following conditions.

[0168] [SiC substrate 10] The same SiC substrate 10 as in Example 5 was used.

[0169] [Main container 50] The same main container 50 as in Example 5 was used.

[0170] [High melting point container 70] The same high-melting-point container 70 as in Example 5 was used.

[0171] [Heat treatment conditions] The SiC substrate 10 arranged under the above conditions was subjected to a heat treatment under the following conditions. Heating temperature: 1800℃ Heating time: 60min Temperature gradient: 1°C / mm Growth rate: 50nm / min Etching speed: 50nm / min Heating chamber 61 vacuum: 13 Pa (N2 gas introduced)

[0172] FIG. 13 is an SEM image of the cross section of the SiC substrate 30 of Example 6 grown under the above conditions, observed at a magnification of 10,000. The thickness of the SiC substrate layer 13 in Example 6 was 3 μm.

[0173] The doping concentration of the SiC substrate layer 13 in Example 6 is 2×10 19 cm -3 and the doping concentration of the bulk layer 11 is 3×10 18 cm -3 That is, the doping concentration of the SiC substrate layer 13 is higher than that of the SiC original substrate 10. This can also be confirmed by the fact that the SEM image contrast of the SiC substrate layer 13 is darker than that of the bulk layer 11, as shown in FIG.

[0174] According to the method for manufacturing a SiC substrate of the present invention, the doping concentration of the SiC substrate layer 13 can be controlled by selecting the doping concentration of the SiC material 40 or by introducing N2 gas during the crystal growth step S20. This allows the manufacture of a SiC substrate 30 with a desired doping concentration.

[0175] <Thermodynamic calculation> 14(a) is a graph showing the relationship between the heating temperature and the etching rate in the etching process of the present invention, where the horizontal axis of the graph represents the reciprocal of the temperature and the vertical axis of the graph represents the logarithmic etching rate. 14(b) is a graph showing the relationship between heating temperature and growth rate in the crystal growth process of the present invention, where the horizontal axis of the graph represents the reciprocal of temperature and the vertical axis of the graph represents the logarithmic growth rate.

[0176] 14, the results of heat treatment of the SiC base substrate 10 placed in a space (inside the main container 50) where the atomic ratio Si / C exceeds 1 are indicated by circles, and the results of heat treatment of the SiC base substrate 10 placed in a space (inside the main container 50) where the atomic ratio Si / C is 1 or less are indicated by crosses.

[0177] In addition, no MSB was formed on the surface of the SiC substrate 10 at any of the locations marked with a circle, and the steps had a height of one unit cell. On the other hand, MSB was formed on the surface of the SiC substrate 10 at any of the locations marked with an x.

[0178] In addition, in the graph of FIG. 14, the results of thermodynamic calculations in a SiC-Si equilibrium vapor pressure environment are shown by a dashed line (Arrhenius plot), and the results of thermodynamic calculations in a SiC-C equilibrium vapor pressure environment are shown by a two-dot chain line (Arrhenius plot). The thermodynamic calculations for the etching process and the crystal growth process will be explained in detail below.

[0179] (Thermodynamic calculation of the etching process) In the thermodynamic calculation of the etching process, the amount of vapor (vapor phase species containing Si element and vapor phase species containing C element) generated from the SiC base substrate 10 when the main container 50 is heated can be converted into an etching amount. In this case, the etching rate of the SiC base substrate 10 can be calculated using the following equation 1.

[0180]

number

[0181] where T is the temperature of the SiC substrate 10, m i is the gas phase species (Si x C y ) and k is the Boltzmann constant. Also, P i is the sum of the vapor pressures generated in the main container 50 when the SiC substrate 10 is heated. i The gas phase species are expected to be SiC, Si2C, SiC2, etc.

[0182] The dashed line in Figure 14(a) shows the results of thermodynamic calculations performed when etching single-crystal SiC in a vapor pressure environment where SiC (solid) and Si (liquid) are in phase equilibrium via the gas phase. Specifically, using Equation 1, the thermodynamic calculations were performed under the following conditions (i) to (iv): (i) a constant-volume SiC-Si equilibrium vapor pressure environment, (ii) the etching driving force is the temperature gradient within the main vessel 50, (iii) the source gases are SiC, Si2C, and SiC2, and (iv) the desorption coefficient for the source material sublimating from the step is 0.001.

[0183] The two-dot chain line in Figure 14(a) is the result of a thermodynamic calculation of etching single-crystal SiC in a vapor pressure environment where SiC (solid phase) and C (solid phase) are in phase equilibrium via the gas phase. Specifically, using Equation 1, the thermodynamic calculation was performed under the following conditions (i) to (iv): (i) a constant-volume SiC-C equilibrium vapor pressure environment, (ii) the etching driving force is the temperature gradient inside the main body container 50, (iii) the source gases are SiC, Si2C, and SiC2, and (iv) the desorption coefficient for the source material sublimating from the step is 0.001. The data for each chemical species used in the thermodynamic calculations were taken from the JANAF thermochemical table.

[0184] According to the graph in FIG. 14(a), it can be seen that the results (marked with circles) of etching the SiC base substrate 10 when the SiC base substrate 10 is placed in a space (inside the main container 50) where the atomic ratio Si / C exceeds 1, show a trend consistent with the results of thermodynamic calculations of single-crystal SiC etching in a SiC-Si equilibrium vapor pressure environment. Furthermore, the SiC substrate 10 was placed in a space (inside the main container 50) where the atomic ratio Si / C was 1 or less, and the results (marked with x) of etching the SiC substrate 10 showed a tendency consistent with the results of thermodynamic calculations of single-crystal SiC etching in a SiC-C equilibrium vapor pressure environment.

[0185] It can be seen that under the conditions indicated by the circles, which were etched under a SiC-Si equilibrium vapor pressure environment, the formation of MSBs was decomposed and suppressed, and steps with a height of 1 nm (1 unit cell) were aligned on the surface of the original SiC substrate 10. On the other hand, it can be seen that MSBs are formed under the conditions of the x marks, which are etched under the SiC-C equilibrium vapor pressure environment.

[0186] (Thermodynamic calculation of the crystal growth process) Next, in the thermodynamic calculation of the crystal growth process, the partial pressure difference between the SiC raw material and the vapor generated from the SiC substrate when the main vessel 50 is heated can be converted into the growth amount. The growth driving force at this time can be assumed to be a chemical potential difference or a temperature gradient. Note that this chemical potential difference can be assumed to be the partial pressure difference between the gas phase species generated on the surfaces of the polycrystalline SiC (SiC material 40) and the single-crystalline SiC (SiC substrate 10). In this case, the growth rate of SiC can be calculated using the following equation 2.

[0187]

number

[0188] where T is the temperature of the SiC raw material side, m i is the gas phase species (Si x C y ) and k is the Boltzmann constant. Also, P 原料 -P基板 is the amount of SiC deposited when the source gas becomes supersaturated, and the source gas is assumed to be SiC, Si2C, or SiC2.

[0189] That is, the dashed line in Figure 14(b) is the result of a thermodynamic calculation when single-crystal SiC is grown using polycrystalline SiC as a raw material in a vapor pressure environment where SiC (solid) and Si (liquid phase) are in phase equilibrium via the gas phase. Specifically, thermodynamic calculations were performed using Equation 2 under the following conditions (i) to (iv): (i) a SiC-Si equilibrium vapor pressure environment with a constant volume, (ii) the growth driving force was the temperature gradient in the main vessel 50 and the vapor pressure difference (chemical potential difference) between polycrystalline SiC and single-crystal SiC, (iii) the source gases were SiC, SiC, and SiC, and (iv) the adsorption coefficient of the source material adsorbed to the steps of the SiC substrate 10 was 0.001.

[0190] The dashed double-dashed line in Figure 14(b) represents the results of thermodynamic calculations when single-crystal SiC is grown using polycrystalline SiC as a raw material in a vapor pressure environment where SiC (solid phase) and C (solid phase) are in phase equilibrium via the gas phase. Specifically, thermodynamic calculations were performed using Equation 2 under the following conditions (i) to (iv): (i) a SiC-C equilibrium vapor pressure environment with a constant volume, (ii) the growth driving force was the temperature gradient in the main vessel 50 and the vapor pressure difference (chemical potential difference) between polycrystalline SiC and single-crystal SiC, (iii) the source gases were SiC, Si2C, and SiC2, and (iv) the adsorption coefficient of the source material adsorbed to the steps of the SiC base substrate 10 was 0.001. The data for each chemical species used in the thermodynamic calculations were taken from the JANAF thermochemical table.

[0191] According to the graph in FIG. 14(b), it can be seen that the results (marked with circles) of placing the SiC substrate 10 in a space (inside the main body container 50) where the atomic ratio Si / C exceeds 1 and growing the SiC substrate layer 13 on the SiC substrate 10 are consistent with the results of thermodynamic calculations of SiC growth in a SiC-Si equilibrium vapor pressure environment. Furthermore, the SiC substrate 10 was placed in a space (inside the main body container 50) where the atomic ratio Si / C was 1 or less, and the SiC substrate layer 13 was grown on the SiC substrate 10 (marked with an x). It was found that the results showed a trend consistent with the results of thermodynamic calculations of SiC growth in a SiC-C equilibrium vapor pressure environment.

[0192] In a SiC-Si equilibrium vapor pressure environment, it is estimated that a growth rate of 1.0 μm / min or more can be achieved at a heating temperature of 1960°C, and a growth rate of 2.0 μm / min or more can be achieved at a heating temperature of 2000°C or higher. On the other hand, under a SiC-C equilibrium vapor pressure environment, it is estimated that a growth rate of 1.0 μm / min or more can be achieved at a heating temperature of 2000°C, and a growth rate of 2.0 μm / min or more can be achieved at a heating temperature of 2030°C or higher. [Explanation of symbols]

[0193] 10 SiC substrate 11 Bulk layer 12 Processing-affected layer 13 SiC substrate layer 20 SiC substrate body 30 SiC substrate 40 SiC material 50 Main container 51 Upper container 52 Lower container 53 Gap 54 PCB holder 55 Si vapor source 60 Furnace 61 main heating chamber 62 Pre-heating chamber 63 Transportation 64 Heater 65 Vacuum forming valve 66 Inert gas injection valve 67 Vacuum Gauge 70 High-melting-point container 71 Upper container 72 Lower container 73 Gap 74 Si vapor source S1 Raw material transportation space X Etching Space Y crystal growth space S10 Etching process S20 Crystal growth process S30 Peeling process S31 Laser irradiation process S32 Separation process

Claims

1. an etching step of etching the original SiC substrate; a crystal growth step of growing a SiC substrate layer on the SiC base substrate to obtain a SiC substrate body; a peeling step of peeling off a portion of the SiC substrate body to obtain a SiC substrate, the etching step and the crystal growth step are steps of arranging the SiC base substrate and a SiC material so as to face each other inside a SiC main body container, and heating the SiC base substrate and the SiC material so as to form a temperature gradient between the SiC base substrate and the SiC material, The method for manufacturing a SiC substrate, wherein the etching step is a step of heating at a temperature range of 1400°C or more and 2300°C or less.

2. 2. The method for manufacturing a SiC substrate according to claim 1, wherein in the etching step and the crystal growing step, at least a part of the main body container made of SiC as the SiC material is opposed to the original SiC substrate.

3. 2. The method for manufacturing a SiC substrate according to claim 1, wherein in the etching step and the crystal growth step, a substrate made of SiC as the SiC material is placed opposite to the original SiC substrate.

4. 4. The method for manufacturing a SiC substrate according to claim 1, wherein the etching step and the crystal growth step are steps of heating the SiC base substrate and the SiC material in an atmosphere containing Si elements and C elements.

5. 5. The method for manufacturing a SiC substrate according to claim 1, wherein the etching step and the crystal growth step are steps of heating the original SiC substrate and the SiC material in a semi-closed space.

6. 6. The method for manufacturing a SiC substrate according to claim 1, wherein the etching step is a step of disposing the SiC original substrate and the SiC material opposite to each other and heating the SiC original substrate so that the SiC substrate is on a higher temperature side and the SiC material is on a lower temperature side.

7. the etching step includes a step of arranging the SiC base substrate and the SiC material so as to face each other in a semi-closed space, and heating the SiC base substrate so that it is on a high temperature side and the SiC material so that it is on a low temperature side; 7. The method for manufacturing a SiC substrate according to claim 1, wherein the semi-closed space is configured so that an atomic ratio Si / C exceeds 1.

8. 8. The method for manufacturing a SiC substrate according to claim 1, wherein the crystal growth step is a step of disposing the SiC base substrate and the SiC material opposite to each other and heating the SiC base substrate so that the SiC substrate is on a low-temperature side and the SiC material is on a high-temperature side.

9. the crystal growth step includes a step of arranging the SiC base substrate and the SiC material so as to face each other in a semi-closed space, and heating the SiC base substrate so that it is on the low temperature side and the SiC material so that it is on the high temperature side; 9. The method for manufacturing a SiC substrate according to claim 1, wherein the semi-closed space is configured so that an atomic ratio Si / C exceeds 1.

10. the crystal growth step includes a step of arranging the SiC base substrate and the SiC material so as to face each other in a semi-closed space, and heating the SiC base substrate so that it is on the low temperature side and the SiC material so that it is on the high temperature side; 10. The method for manufacturing a SiC substrate according to claim 1, wherein the semi-closed space is configured so that an atomic ratio Si / C is 1 or less.

11. The peeling step includes a laser irradiation step of introducing a damage layer into the SiC substrate body. The method for manufacturing a SiC substrate according to claim 1, further comprising: a separation step of separating the substrate from the damaged layer as a starting point.

12. In the peeling step, a first SiC substrate that was the original SiC substrate of the SiC substrate body and a second SiC substrate that was the SiC substrate layer of the SiC substrate body are obtained as the SiC substrate; an etching step of etching the first SiC substrate; a crystal growth step of growing another SiC substrate layer on the first SiC substrate to obtain another SiC substrate body; The method for manufacturing a SiC substrate according to any one of claims 1 to 11, further comprising: a peeling step of peeling off a part of the other SiC substrate body.

13. In the peeling step, a first SiC substrate that was the original SiC substrate of the SiC substrate body and a second SiC substrate that was the SiC substrate layer of the SiC substrate body are obtained as the SiC substrate; an etching step of etching the second SiC substrate; a crystal growth step of growing another SiC substrate layer on the second SiC substrate to obtain another SiC substrate body; The method for manufacturing a SiC substrate according to any one of claims 1 to 12, further comprising: a peeling step of peeling off a part of the other SiC substrate body.

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