Low-voltage flash memory with integrated vertical field-effect transistors

Abstract

The circuit may include a low-voltage flash memory integrating a vertical field-effect transistor and a nonvolatile memory element. The low-voltage flash memory may be connected to the nonvolatile memory element by a vertical field-effect transistor, one or more bit lines, and one or more word lines. The low-voltage flash memory may provide a lower significant conductance, and the nonvolatile memory element may provide a higher significant conductance. The low-voltage flash memory may include a source and a drain. The source may be separated from the drain by an epitaxial channel. The low-voltage flash memory may include a floating gate. The floating gate may be separated from the epitaxial channel by a first dielectric layer. The low-voltage flash memory may include a control gate. The control gate may be separated from the floating gate by a second dielectric layer.

Description

[Technical Field]

[0001] The present invention relates generally to semiconductor structures and methods for forming same. In particular, the present invention relates to semiconductor structures and methods for forming vertical field effect transistors (VFETs). Integrated with The present invention relates to semiconductor structures including low voltage flash memory. [Background technology]

[0002] Deep learning is a machine learning method based on artificial neural networks inspired by information processing in biological systems. In neuromorphic computing, electronic analog circuits are used to mimic the neurobiological architecture present in the nervous system. Summary of the Invention

[0003] According to one embodiment of the present invention, there is provided a circuit, the circuit comprising a vertical field effect transistor and a non-volatile memory element. Integrated with The nonvolatile memory element may include a low-voltage flash memory, which may be connected to the nonvolatile memory element by the vertical field effect transistor, one or more bit lines, and one or more word lines. Lower side conductance (a lower significance conductance) and the nonvolatile memory element can be provided with Upper side conductance (a higher significance conductance) The low-voltage flash memory may include a source and a drain. The source may be separated from the drain by an epitaxial channel. The low-voltage flash memory may include a floating gate. The floating gate may be separated from the epitaxial channel by a first dielectric layer. The low-voltage flash memory may include a control gate. The control gate may be separated from the floating gate by a second dielectric layer. The low-voltage flash memory may include a control gate. Multiple of opposite polarity Multiple voltage pulse (voltage pulses of opposite polarities) The low-voltage flash memory may be programmed by turning off the vertical field effect transistor and applying a program voltage to the control gate of the low-voltage flash memory. The low-voltage flash memory may be read by turning on the vertical field effect transistor and applying a read voltage to the control gate of the low-voltage flash memory. The source, the drain, and the epitaxial channel may be doped with an n-type dopant. The nonvolatile memory element may be a phase change memory, a resistive random access memory, a magnetic random access memory, or a flash memory.

[0004] According to another embodiment of the present invention, there is provided a semiconductor structure, the semiconductor structure comprising a vertical field effect transistor and a non-volatile memory element. Integrated withThe nonvolatile memory element may include a low-voltage flash memory. The low-voltage flash memory may be connected to the nonvolatile memory element by the vertical field-effect transistor, one or more bit lines, and one or more word lines. The low-voltage flash memory may include a first source / drain, a second source / drain, a floating gate, and a control gate. The second source / drain may be separated from the first source / drain by an epitaxial channel. The floating gate may be separated from the epitaxial channel by a first dielectric layer. The control gate may be separated from the floating gate by a second dielectric layer. The floating gate may have a doping type opposite to that of the epitaxial channel. The first source / drain, the second source / drain, and the epitaxial channel may be doped with an n-type dopant. The first dielectric may be made of a high-k dielectric material. The low-voltage flash memory may be vertical and may be separated from the vertical field-effect transistor by shallow trench isolation. The non-volatile memory element may be a phase change memory, a resistive random access memory, a magnetic random access memory, or a flash memory.

[0005] According to another embodiment of the present invention, there is provided a method, comprising: forming a vertical field effect transistor and a non-volatile memory element; Integrated withThe method may include forming a low-voltage flash memory. The method may include forming a shallow trench isolation between the low-voltage flash memory and the vertical field-effect transistor. The low-voltage flash memory may be connected to the nonvolatile memory element by the vertical field-effect transistor. Forming the low-voltage flash memory may include growing a first source / drain on a substrate, epitaxially growing an epitaxial channel on the first source / drain, epitaxially growing a second source / drain on the epitaxial channel, forming a floating gate around the epitaxial channel, and forming a control gate around the floating gate, wherein the control gate is separated from the floating gate by a first dielectric layer. The first dielectric may be made of a high-k dielectric material. The first source / drain, the epitaxial channel, and the second source / drain may be doped with an n-type dopant. The non-volatile memory element may be a phase change memory, a resistive random access memory, a magnetic random access memory, or a flash memory. The floating gate may have a doping type that is opposite to the doping type of the epitaxial channel.

[0006] The following detailed description, given by way of example and not by way of limitation alone, is best understood in conjunction with the accompanying drawings, in which: [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a cross-sectional view illustrating a dummy gate and a dielectric capping layer disposed on a substrate in accordance with an illustrative embodiment. [Figure 2] 1 is a cross-sectional view illustrating a trench formed to expose a source according to an exemplary embodiment. [Figure 3]1 is a cross-sectional view illustrating an epitaxial layer and a dielectric cap according to an exemplary embodiment. [Figure 4] 10A-10C are cross-sectional views illustrating forming a drain on an epitaxial channel in accordance with an exemplary embodiment. [Figure 5] 10A and 10B are cross-sectional views illustrating the removal of the dummy gate and oxide layer according to an exemplary embodiment. [Figure 6] 1A-1C are cross-sectional views illustrating depositing a first dielectric layer and a floating gate material according to an exemplary embodiment. [Figure 7] 10 is a cross-sectional view illustrating the removal of a portion of the first dielectric layer and the floating gate material to form a floating gate according to an exemplary embodiment. [Figure 8] 10A-10C are cross-sectional views illustrating depositing a second dielectric layer and a control gate material according to an exemplary embodiment. [Figure 9] 10 is a cross-sectional view illustrating the removal of a portion of the second dielectric layer and the control gate material to form a control gate according to an exemplary embodiment. [Figure 10] 1A-1C are cross-sectional views illustrating depositing an interlayer dielectric and forming contacts in accordance with exemplary embodiments. [Figure 11] 1 is a cross-sectional view illustrating a vertical field effect transistor and a low voltage flash according to an exemplary embodiment. [Figure 12] 1 is a graph showing drain current as a function of total floating gate charge (c), according to an embodiment. [Figure 13] FIG. 2 is a simplified circuit diagram of a memory array of analog memory unit cells, according to an exemplary embodiment. [Figure 14] FIG. 2 is a simplified circuit diagram illustrating a vertical field effect transistor and a low voltage flash according to an exemplary embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] The drawings are not necessarily to scale. The drawings are merely schematic representations and do not portray specific parameters of the invention. The drawings depict only typical embodiments of the invention. In the drawings, like numbers represent like elements.

[0009] Although detailed embodiments of the claimed structures and methods are disclosed herein, it will be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods, which may be embodied in a variety of forms. However, the present invention may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0010] For purposes of the following description, the terms "upper," "lower," "right," "left," "vertical," "horizontal," "top," "bottom," and their derivatives shall refer to the disclosed structures and methods as oriented in the depicted figures. The terms "overlying," "atop," "on top," "positioned on," or "positioned atop" mean that a first element, such as a first structure, is above a second element, such as a second structure, where an intervening element, such as an interfacial structure, may be present between the first and second elements. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediate conductive, insulating, or semiconducting layer at the interface between the two elements.

[0011] In order not to obscure the presentation of embodiments of the present invention, in the following detailed description, some process steps or operations known in the art may be combined together for purposes of presentation and explanation, and in some instances may not be described in detail. In other instances, some process steps or operations known in the art may not be described at all. It should be understood that the following description will instead focus on unique features or elements of various embodiments of the present invention.

[0012] FIELD OF THE INVENTION Embodiments of the present invention generally relate to semiconductor structures and methods of forming same. In particular, the present invention relates to a vertical field effect transistor (VFET). Integrated with The present invention relates to semiconductor structures including low voltage flash memory.

[0013] Deep learning is a machine learning method based on artificial neural networks. The use of computers for deep neural networks can involve both training and forward inference. For neuromorphic computing, memory elements that are sufficiently linear and have sufficiently long retention times are required. However, conventional single-device memory elements are either sufficiently linear or have sufficiently long retention times, but not both. As a result, hybrid designs are considered. Conventional hybrid designs integrate phase-change memory cells with capacitors. Phase-change memory can provide long retention times, and capacitors can provide linearity. Nevertheless, even with hybrid configurations, the capacitors have short retention times. As a result, a capacitor is required to transfer the program state to the phase-change memory to avoid data loss. Furthermore, utilizing a phase-change memory cell in combination with a capacitor requires complex circuitry including several transistors, phase-change memory cells, and capacitors. Therefore, it is necessary to fabricate devices that are sufficiently linear, have sufficiently long retention times, and allow for simple circuit designs.

[0014] An embodiment of the present invention is a VFET Integrated with In particular, embodiments of the present invention relate to semiconductor structures including low voltage flash memory. Integrated with It provides new structures and integration techniques for vertically fabricating low-voltage flash memory, thus reducing the device footprint and allowing more devices to be integrated within a given chip area. New circuit structures are also being developed for VFETs and non-volatile memory. Integrated with May contain low-voltage flash memory.

[0015] 1-11 illustrate a method for fabricating a vertical low-voltage flash memory. 12-14 illustrate a VFET and a nonvolatile memory. and Accumulation was 1 illustrates an exemplary circuit structure including a vertical low-voltage flash memory.

[0016] 1 , a structure 100 is shown according to one embodiment. The structure 100 may include a substrate 102, a counter-doped layer 104, a source 106, a first spacer 108, a dummy gate 110, a second spacer 112, and a dielectric capping layer 114. The substrate 102 may include one or more semiconductor materials. Non-limiting examples of suitable substrate 102 materials include Si (silicon), strained Si, Ge (germanium), SiGe (silicon germanium), Si alloys, Ge alloys, III-V materials (e.g., GaAs (gallium arsenide), InAs (indium arsenide), InP (indium phosphide), or aluminum arsenide (AlAs)), II-VI materials (e.g., CdSe (cadmium selenide), CdS (cadmium sulfide), CdTe (cadmium telluride), ZnO (zinc oxide), ZnSe (zinc selenide), ZnS (zinc sulfide), or ZnTe (zinc telluride)), or any combination thereof. In one embodiment, the substrate 102 may include silicon.

[0017] A counter-doped layer 104 is deposited on the top surface of the substrate 102. A source 106 is then disposed on the substrate 102 over the counter-doped layer 104. The source 106 and counter-doped layer 104 may be formed on the substrate 102 by incorporating dopants into the substrate 102 or by forming epitaxial growth on the substrate 102. In one embodiment, the source 106 is heavily doped with an n-type dopant, such as phosphorus or arsenic. The dopant level in the source 106 is about 3E20 atoms / cm. 3 to approximately 8E20 atoms / cm 3 In an alternative embodiment, the source 106 is heavily doped with a p-type dopant, such as boron or gallium. In one embodiment, the source 106 may be referred to as a first source-drain.

[0018] The counter-doped layer 104 includes a dopant that is different / opposite to the dopant in the doped source 106. For example, when the doped source 106 includes an n-type dopant, the counter-doped layer 104 includes a p-type dopant, and when the doped source 106 includes a p-type dopant, the counter-doped layer 104 includes an n-type dopant. In one embodiment, the counter-doped layer 104 is lightly doped with a p-type dopant, such as boron or gallium. The thickness of the counter-doped layer 104 may be in the range of about 5 to about 50 nm, or about 10 to about 20 nm. The thickness of the source 106 may be in the range of about 50 to about 250 nm, or about 70 to about 150 nm. The counter-doped layer 104 forms a diode and acts as an insulator, insulating the source 106 from the substrate 102 so that current does not dissipate into the substrate 102.

[0019] A dummy gate 110 is deposited on the source 106 between the first spacer 108 and the second spacer 112. The first spacer 108 is deposited on the source 106, the dummy gate 110 is deposited on the first spacer 108, and the second spacer 112 is deposited on the dummy gate 110.

[0020] The first spacer 108 and the second spacer 112 can include an insulating material such as, for example, silicon dioxide, silicon nitride, SiOCN, or SiBCN. Other non-limiting examples of materials for the first spacer 108 and the second spacer 112 can include a dielectric oxide (e.g., silicon oxide), a dielectric nitride (e.g., silicon nitride), a dielectric oxynitride, or any combination thereof. The first spacer 108 material and the second spacer 112 material are deposited by a deposition process, for example, chemical vapor deposition (CVD) or physical vapor deposition (PVD). The first spacer 108 and the second spacer 112 can each have a thickness of about 3 to about 15 nm, or about 5 to about 10 nm.

[0021] The dummy gate 110 may comprise a sacrificial gate material, such as amorphous silicon (α-Si) or polycrystalline silicon (poly-Si). The sacrificial material may be deposited by a deposition process, including, but not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), inductively coupled plasma chemical vapor deposition (ICP CVD), or any combination thereof. The sacrificial material forming the dummy gate 110 may have a thickness of from about 8 nm to about 100 nm, or from about 10 nm to about 30 nm.

[0022] A dielectric capping layer 114 is deposited on the second spacer 112, covering the dummy gate 110. The dielectric capping layer 114 may also be referred to as an oxide layer. Non-limiting examples of materials for the dielectric capping layer 114 may include silicon dioxide, tetraethoxyorthosilicate (TEOS) oxide, high aspect ratio plasma (HARP) oxide, high temperature oxide (HTO), high density plasma (HDP) oxide, oxide formed by an atomic layer deposition (ALD) process (e.g., silicon oxide), or any combination thereof. The dielectric capping layer 114 may have a thickness ranging from about 30 nm to about 200 nm, or from about 50 nm to about 100 nm.

[0023] 2, structure 100 is shown having trench 116, according to one embodiment. Trench 116 extends from the top surface of dielectric capping layer 114 to source 106, exposing the top surface of source 106. Trench 116 is formed by performing an etching process that is selective to (does not substantially remove) the source 106 material. The etching process may be, for example, selective ion etching.

[0024] Multiple etching processes may be performed to form trenches 116 within the structure 100. For example, a first etching process may be performed to remove a portion of the dielectric capping layer 114 selective to the material of the second spacers 112. A second etching process may then be performed to remove a portion of the second spacers 112 underlying the portion of the trench 116 formed from the first etching process, selective to the material of the dummy gate 110. A third etching process may then be performed to remove a portion of the dummy gate 110 underlying the portion of the trench 116 formed from the second etching process, selective to the material of the first spacers 108. A fourth etching process may then be performed to remove a portion of the first spacers 108, thereby exposing the top surface of the source 106. The resulting trench 116 may extend through the top surface of the dielectric capping layer 114 down to the top surface of the exposed portion of the source 106. The width of trench 116 may be from about 3 nm to about 20 nm, or from about 5 nm to about 10 nm, and the depth of trench 116 may be from about 50 nm to about 300 nm, or from about 100 nm to about 200 nm.

[0025] Once trench 116 is formed, portions of the sidewalls of dummy gate 110 are oxidized. The oxidation allows an oxide layer 118 to form along the sidewalls of trench 116. The oxidation may be performed by a plasma oxidation process or any other oxidation process that forms oxide layer 118. Portions of first spacer 108 or source 106 may also be oxidized. However, any oxide formed in these regions may be removed before performing the additional steps described herein with reference to FIGS. 3-11.

[0026] 3, a structure 100 having an epitaxial channel 120 and a dielectric cap 122 is shown according to one embodiment. Once the exposed portions of the dummy gate 110 sidewalls are oxidized, an epitaxial layer is grown on top of the source 106 to form the epitaxial channel 120. The epitaxial growth may include epitaxial semiconductor material, and the epitaxial growth and / or deposition process may be selective to forming on the semiconductor surface and not deposit material on other surfaces, such as the oxide layer 118, the first spacer 108, or the second spacer 112.

[0027] The epitaxial channel 120 is doped with the same type of dopant as the source 106. In one embodiment, the epitaxial channel 120 is doped with an n-type dopant, such as phosphorus or arsenic. The dopant level in the epitaxial channel 120 is lower than the dopant level in the source 106. The dopant level in the epitaxial channel 120 is about 5E20 atoms / cm 3 is.

[0028] The epitaxial channel 120 may be grown using any suitable growth process, such as chemical vapor deposition (CVD), liquid phase (LP) or reduced pressure chemical vapor deposition (RPCVD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), metalorganic chemical vapor deposition (MOCVD), or any other suitable process.

[0029] The source material for the epitaxial channel material may be, for example, n-type silicon, germanium, or a combination thereof. The gas source for depositing the epitaxial semiconductor material may include a silicon-containing gas source, a germanium-containing gas source, or a combination thereof. For example, an epitaxial silicon layer may be deposited from a silicon gas source selected from the group consisting of silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, and combinations thereof. An epitaxial germanium layer may be deposited from a germanium gas source selected from the group consisting of germane, digermane, halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane, and combinations thereof. An epitaxial silicon-germanium alloy layer may be formed using a combination of such gas sources. Carrier gases such as hydrogen, nitrogen, helium, and argon may be used.

[0030] During the growth process, the epitaxial growth in the epitaxial channel 120 may extend over the dielectric capping layer 114 (not shown). For example, a planarization process, such as a chemical-mechanical polishing (CMP) process, may be used to remove excess epitaxial growth overlying the dielectric capping layer 114. In addition, the epitaxial channel 120 may be partially recessed and then backfilled with a dielectric cap 122. The epitaxial channel 120 may be partially recessed to a level that is still within the dielectric capping layer 114 but above the second spacer 112. The epitaxial channel 120 may be recessed by etching, for example, by a reactive ion etching process or a wet etching process.

[0031] The opening formed above the recessed epitaxial channel 120 is filled with a dielectric material to form a dielectric cap 122 covering the epitaxial channel 120. The dielectric cap 122 may be made of a dielectric material such as, for example, a dielectric oxide (e.g., silicon oxide), a dielectric nitride (e.g., silicon nitride), a dielectric oxynitride, or any combination thereof. The dielectric material is deposited by a deposition process, for example, chemical vapor deposition (CVD) or physical vapor deposition (PVD). After the formation of the dielectric material, the dielectric cap 122 is planarized, for example, by CMP.

[0032] Referring now to FIG. 4 , a structure 100 having a drain 124 is shown, according to one embodiment. Substantially all of the dielectric capping layer 114 is removed, thereby exposing the top surface of the second spacer 112. The dielectric capping layer 114 may be etched using a process that is selective to (does not substantially remove) the second spacer 112. Once the dielectric capping layer 114 is removed, the drain 124 is epitaxially grown from the exposed sidewalls of the epitaxial channel 120. The drain 124 is doped with the same type of dopant as the source 106 and the epitaxial channel 120. In one embodiment, the drain is doped with an n-type dopant, such as phosphorus or arsenic. The dopant level in the drain 124 is higher than the dopant level in the epitaxial channel 120. The dopant level in the drain 124 is approximately 3E20 atoms / cm 3 In one embodiment, the drain 124 and the source 106 have a higher doping concentration than the epitaxial channel 120. In one embodiment, the drain 124 may be referred to as a second source-drain.

[0033] The drain 124 is disposed between the dielectric cap 122 and the epitaxial channel 120. The drain 124 is also disposed between the dielectric cap 122 and the dummy gate 110. The portion of the epitaxial channel 120 covering the second spacer 112 may be recessed along its sidewalls before forming the drain 124. The drain 124 is a faceted epitaxial source-drain region of a vertical transistor. The faceted drain 124 is grown in a pointed pyramid shape, where the tip of the drain 124 extends horizontally away from the epitaxial channel 120. The pointed pyramid shape of the drain 124 enhances the electric field at the tip of the pyramid.

[0034] Referring now to FIG. 5 , the structure 100 is shown after the dummy gate and oxide layer have been removed and third spacers 126 have been deposited, according to one embodiment. The third spacers 126 are deposited on the drain 124 to protect it during subsequent fabrication. The third spacers 126 are also deposited on the sidewalls of the dielectric cap 122. The third spacers 126 may comprise an insulating material, such as a dielectric oxide (e.g., silicon oxide), a dielectric nitride (e.g., silicon nitride), a dielectric oxynitride, or any combination thereof. The third spacer 126 material is deposited by a deposition process, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). The third spacers 126 may be etched by a dry etching process, such as an RIE process, so that the third spacers cover the drain 124 and are removed from the top surfaces of the dielectric cap 122 and the second spacers 112.

[0035] Once the third spacers 126 are deposited, the second spacers 112 and portions of the dummy gate 110 are removed. The second spacers 112 and dummy gate 110 are recessed to remove portions that extend horizontally beyond the third spacer 126 material. An etching process that is selective to (does not substantially remove) the first spacers 108 is performed. The etching process may be a dry etching process, such as an RIE process. Another etching process, such as a wet etching process including high-temperature ammonia, is used to remove the second spacers 112 and the remaining dummy gate below the oxide layer 118 so that the sidewalls of the epitaxial channel 120 are exposed.

[0036] 6, a structure 100 is shown having a first dielectric layer 128 and a floating gate material 130, according to one embodiment. The first dielectric layer 128 is conformally deposited along the top surface of the structure 100. The first dielectric layer 128 is deposited over the first spacer 108, the epitaxial channel 120, the third spacer 126, and the remaining portion of the second spacer 112 below the drain 124.

[0037] The first dielectric layer 128 may be made of a high-k dielectric material having a dielectric constant greater than 3.9, 7.0, or 10.0. Non-limiting examples of suitable materials for the first dielectric layer 128 include oxides, nitrides, oxynitrides, silicates (e.g., metal silicates), aluminates, titanates, nitrides, or any combination thereof. Examples of high-k materials (having a dielectric constant greater than 7.0) include, but are not limited to, metal oxides such as hafnium oxide, silicon hafnium oxide, hafnium silicon oxynitride, lanthanum oxide, aluminum lanthanum oxide, zirconium oxide, silicon zirconium oxide, zircon silicon oxynitride, tantalum oxide, titanium oxide, strontium barium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, tantalum scandium lead oxide, and zinc lead niobate. The high-k material may further include dopants, such as lanthanum and aluminum.

[0038] In one embodiment, the first dielectric layer 128 is between 1 and 2 nm thick. The first dielectric layer 128 separates the epitaxial channel 120 from the floating gate material 130, reducing leakage current effects. The first dielectric layer 128 may have a smaller conduction band offset with the epitaxial channel 120 than the valence band offset and a smaller effective mass for electrons than for holes. Additionally, the first dielectric layer 128 is a tunneling dielectric that allows for direct tunneling of carriers compared to traditional thick dielectrics used for Fowler-Nordheim tunneling.

[0039] The first dielectric layer 128 may be formed by a suitable deposition process, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), evaporation, physical vapor deposition (PVD), chemical solution deposition, or other similar process.

[0040] The floating gate material 130 is deposited on the top surface of the first dielectric layer 128 such that the top portion of the floating gate material 130 is substantially flush with the top portion of the first dielectric layer 128. The floating gate material 130 can act as a conductor. Non-limiting examples of materials used to form the floating gate material 130 include aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), or any combination thereof, polysilicon, or a dielectric material such as, for example, silicon nitride. The conductive material may be deposited by a suitable deposition process, such as, for example, CVD, PECVD, PVD, plating, thermal or electron beam evaporation, and sputtering. The floating gate material 130 may be doped with a dopant that is opposite to the dopant used to dope the epitaxial channel 120. For example, if the epitaxial channel 120 is doped with an n-type dopant, then the floating gate material 130 may be doped with a p-type dopant.

[0041] After the floating gate material 130 is deposited, a planarization process, such as, for example, a CMP process, may be used to remove excess floating gate material 130 from the top surface of the structure 100. Thereafter, an anisotropic etch, such as, for example, an RIE process, may be performed to recess the floating gate material 130 so that the top surface of the floating gate material 130 extends above the top surface of the second spacer 112.

[0042] Referring now to FIG. 7 , the structure 100 is shown with portions of the first dielectric layer 128 and the floating gate material 130 removed, according to one embodiment. The structure 100 may be subjected to an etching process, such as an RIE process, to remove the exposed portions of the first dielectric layer 128, exposing the sidewalls of the third spacers 126 and the top portion of the dielectric cap 122. Furthermore, the floating gate material 130 is recessed to remove portions of the floating gate material 130 that extend horizontally beyond the third spacer 126 material, thus forming the floating gate 132. An etching process is performed that is selective to (does not substantially remove) the first dielectric layer 128. The etching process may be a dry etching process, such as an RIE process. The floating gate 132 may have a doping type that is opposite to the doping type of the epitaxial channel 120. Additionally, the first dielectric layer 128 may have a lower barrier to tunneling of majority carriers from the epitaxial channel 120 to the floating gate 132 compared to tunneling for minority carriers within the epitaxial channel 120 .

[0043] 8, a structure 100 having a second dielectric layer 134 and a control gate material 136 is shown according to one embodiment. The second dielectric layer 134 is conformally deposited along the top surface of the structure 100. The second dielectric layer 134 is deposited over the first dielectric layer 128, the third spacer 126, and the dielectric cap 122.

[0044] The second dielectric layer 134 may be made of a dielectric material having a dielectric constant greater than 3.9, 7.0, or 10.0. Non-limiting examples of suitable materials for the second dielectric layer 134 include oxides, nitrides, oxynitrides, silicates (e.g., metal silicates), aluminates, titanates, nitrides, or any combination thereof. Examples of high-k materials (having a dielectric constant greater than 7.0) include, but are not limited to, metal oxides such as hafnium oxide, silicon hafnium oxide, hafnium silicon oxynitride, lanthanum oxide, aluminum lanthanum oxide, zirconium oxide, silicon zirconium oxide, zircon silicon oxynitride, tantalum oxide, titanium oxide, strontium barium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, tantalum scandium lead oxide, and zinc lead niobate. The high-k materials may further include dopants, such as lanthanum and aluminum.

[0045] The second dielectric layer 134 separates the first dielectric layer 128 and the floating gate 132 from the control gate material 136. The second dielectric layer 134 may be formed by a suitable deposition process, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), evaporation, physical vapor deposition (PVD), chemical solution deposition, or other similar processes. The thickness of the second dielectric layer 134 may vary depending on the deposition process and the composition and number of high-k dielectric materials used.

[0046] The control gate material 136 is deposited onto the top surface of the second dielectric layer 134 such that the top portions of the control gate material 136 and the second dielectric layer 134 are substantially flush with each other. The control gate material 136 can act as a conductor. Non-limiting examples of materials used to form the control gate material 136 can include aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), or any combination thereof, polysilicon, or a dielectric material such as, for example, silicon nitride. The conductive material may be deposited by a suitable deposition process, such as CVD, PECVD, PVD, plating, thermal or electron beam evaporation, and sputtering.

[0047] After the control gate material 136 is deposited, a planarization process, such as, for example, a CMP process, may be used to remove excess control gate material 136 from the top surface of the structure 100. Thereafter, an anisotropic etch, such as, for example, an RIE process, may be performed to recess the control gate material 136. The control gate material 136 is recessed such that the top surface of the control gate material 136 extends above the top surfaces of the second spacers 112 and the bottom portion of the third spacers 126.

[0048] 9, structure 100 is shown with portions of second dielectric layer 134 and control gate material 136 removed to form control gate 138, according to one embodiment. Structure 100 may be subjected to an etching process, such as, for example, an RIE process, to remove the exposed portions of second dielectric layer 134, exposing sidewalls of third spacers 126 and a top portion of dielectric cap 122.

[0049] Once portions of the second dielectric layer 134 are removed, the control gate material 136 is patterned. The patterning may be performed by lithography and etching. The pattern is transferred to the control gate material 136, and an etching process is used to remove portions of the control gate material 136 and define the control gate 138. The etching process is selective to (does not substantially remove) the first spacers 108. The etching process may be a dry etching process, such as an RIE process. The control gate 138 surrounds the floating gate 132.

[0050] Referring now to FIG. 10 , a structure 100 is shown having an interlayer dielectric (ILD) 140, a control gate contact 142, and a drain contact 144, according to one embodiment. Once the control gate 138 is defined, the ILD 140 may be deposited such that the top surface of the ILD 140 is above the top surfaces of the dielectric cap 122 and the third spacer 126. The ILD 140 may be formed from a low-k material (having k<4.0), including, for example, but not limited to, silicon oxide, spin-on glass, flowable oxide, high-density plasma oxide, borophosphosilicate glass (BPSG), or any combination thereof. The ILD 140 is deposited by a deposition process, including, but not limited to, CVD, PVD, plasma-enhanced CVD, atomic layer deposition (ALD), evaporation, chemical solution deposition, or a similar process. After the ILD 140 is deposited, a planarization process, such as a CMP process, may be used to remove excess ILD 140 from the top surface of the structure 100.

[0051] The control gate contact 142 extends from the surface of the ILD 140 to the control gate 138. The control gate contact 142 is formed by patterning a trench in the ILD 140. A resist, such as photoresist, may be deposited and patterned to remove the ILD 140 and form the control gate contact trench. An etching process, such as RIE, may be performed using the patterned resist as an etch mask to remove the ILD 140 until the control gate 138 is exposed. The control gate contact trench is filled with a conductive material or a combination of conductive materials to form the control gate contact 142. The conductive material may be a conductive metal, such as aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), or any combination thereof. The conductive material may be deposited by a suitable deposition process, such as CVD, PECVD, PVD, plating, thermal or electron beam evaporation, or sputtering. A planarization process, such as CMP, is performed to remove all conductive material from the surface of ILD 140 .

[0052] The drain contact 144 extends through the ILD 140 and the dielectric cap 122 to the drain 124 and is formed inside the trench. A resist, such as photoresist, may be deposited and patterned to remove the ILD 140 and form the drain trench. An etching process, such as RIE, may be performed using the patterned resist as an etch mask to remove the ILD 140 and the dielectric cap 122 until the drain 124 is exposed. The drain trench is filled with a conductive material or a combination of conductive materials to form the drain contact 144 (e.g., a bit line). The conductive material fill may be a conductive metal, such as aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), or any combination thereof. The conductive material may be deposited by a suitable deposition process, such as CVD, PECVD, PVD, plating, thermal or electron beam evaporation, or sputtering. A planarization process, such as CMP, is performed to remove all conductive material from the surface of ILD 140 .

[0053] Referring now to FIG. 11 , structure 300 is shown according to one embodiment. Structure 300 includes structure 100 and structure 200. Structure 100 is a low-voltage flash memory, while structure 200 is a VFET. Structure 100 may be isolated from structure 200 by a shallow trench isolation (STI) 146. Forming STI 146 may be done in a number of ways known in the art, such as using a single etch process or multiple etch processes. STI 146 is a form of dielectric plug that separates structure 100 from structure 200 so that current applied to structure 100 does not affect structure 200. Typically, STI 146 extends through a portion of substrate 102 to a depth that allows the two structures 100, 200 to be electrically isolated.

[0054] The resulting structure 300 includes a vertical low-voltage flash memory (structure 100) and a VFET (structure 200) separated by an STI 146, as shown in Figure 11. The vertical low-voltage flash memory includes a floating gate 132 surrounded by a control gate 138.

[0055] 12 to 14 show the VFET and the nonvolatile memory element. Integrated with 1 illustrates an exemplary circuit diagram including a vertical low-voltage flash memory.

[0056] Referring now to FIG. 12, a simulated graph showing drain current as a function of floating gate total charge (C) is shown, according to one embodiment. The floating gate of a vertical low-voltage flash memory (structure 100) may be charged linearly as a function of time. Therefore, the graph illustrates that a vertical low-voltage flash memory may be programmed in a linear manner. A substantially linear response is achieved for at least up to fifty microseconds (50 μs). The drain-source voltage (V DS ) is 0.0 V, and the control gate voltage V GS is 1.5V.

[0057] 13, a simplified memory array 400 is shown, according to one embodiment. The memory array 400 may include array blocks 150 and unit cells 152. The unit cells 152 may be standard unit cells 154 and shared unit cells 156.

[0058] A standard unit cell 154 is, for example, G + and G -The right-hand memory array 400 may include one or more non-volatile memory elements, such as a phase-change memory (PCM) labeled "P", as well as structure 100 (low-voltage flash memory) and structure 200 (VFET). Other examples of non-volatile memory elements may include, but are not limited to, a resistive random access memory, a magnetic random access memory, or a flash memory. The right-hand memory array 400 may also include an intermediate terminal 158 integrated with the standard unit cell 154 and the shared unit cell 156. The intermediate terminal 158 may be located between the structure 100 and the structure 200.

[0059] The structure 100 (low voltage flash memory) Lower side conductance (a lower significance conductance) while non-volatile memory gives Upper side conductance (a higher significance conductance) In the conventional unit cell, Lower side Conductance is provided by a capacitor. Low-voltage flash memory offers a longer retention time compared to the capacitor in a conventional unit cell. As a result, the memory state does not have to be transferred to the PCM as frequently to achieve long-term storage. 、 Low-Voltage Flash Memory Integrated with VFET and PCM This provides a simple circuit compared to conventional circuits that utilize capacitors.

[0060] 14, according to one embodiment, a simplified circuit diagram shows the low-voltage flash memory / VFET portion of shared unit cell 156, or equivalently, standard unit cell 154, with middle terminal 158 on the right and without middle terminal 158 on the left. Without middle terminal 158, when the VFET (structure 200), which functions as a pass transistor, is turned off, the low-voltage flash memory (structure 100) operates in the linear (triode) region because no or very little current flows through the VFET. Therefore, the source and drain of the low-voltage flash memory have approximately the same voltage as bit line 160.

[0061] During the training phase, the VFET is switched off. The low voltage flash memory has a control gate 138 shown in FIG. 9, for example, a positive or negative Multiple Voltage pulse ( positive or negative voltage pulses ) etc. Multiple Opposite polarity appropriate Multiple voltage pulse (suitable voltage pulses of opposite polarities) The low-voltage flash memory is programmed by applying a voltage to the epitaxial channel 120. The resistance of the epitaxial channel 120 of the low-voltage flash memory shown in FIG. 7 is increased or decreased by charging or discharging the floating gate 132, depending on the polarity of the voltage applied to the control gate 138. Therefore, during programming, the low-voltage flash memory is disconnected from the bit lines 160 and / or word lines. The low-voltage flash memory may be programmed by direct tunneling of charge carriers into and out of the floating gate 132.

[0062] Once training / programming is complete, the VFET may be switched on so that the resistance of the low-voltage flash memory can be read and / or transferred to the nonvolatile memory. During reading, the low-voltage flash memory is connected to the bit line 160 and / or the word line. An appropriate read voltage is applied to the control gate 138 of the low-voltage flash memory. The current flowing through the bit line 160, which is a measure of the memory state, is detected by peripheral circuitry, which may include, for example, a sense amplifier. The detected memory state may then be transferred to the nonvolatile memory by the peripheral circuitry (e.g., by programming a corresponding conductivity change into the nonvolatile memory).

[0063] The intermediate terminal 158 shown in the circuit diagram to the right provides greater flexibility in terms of circuit programming in some embodiments. For example, having the intermediate terminal 158 allows a desired program voltage to be applied between the intermediate terminal 158 and the control gate 138 of the low-voltage flash memory independently of the voltage present on the bit line. In one embodiment, the intermediate terminal may be connected to a desired voltage, such as ground, thus allowing the low-voltage flash memory to be biased across its drain-source at a desired voltage. In one example, if the low-voltage flash memory is an n-channel device, the intermediate terminal 158 is biased at a lower voltage than the bit line 160 (and thus functions as a source terminal), allowing the low-voltage flash memory to be programmed independently of the bit line 160 voltage to a first order.

[0064] The description of various embodiments of the present invention has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein has been selected to best explain the principles of the embodiments, practical applications or technical improvements beyond those found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A low-voltage flash memory integrated with a vertical field-effect transistor and a nonvolatile memory element, the low-voltage flash memory having a control gate, the low-voltage flash memory being connected to the vertical field-effect transistor and connected to one or more bit lines and one or more word lines, a first line being common to the nonvolatile memory element and a third line different from a second line to which the nonvolatile memory element is connected. wherein the low-voltage flash memory is programmed by applying a plurality of positive or negative voltage pulses to the control gate while the vertical field effect transistor is off, switching on the vertical field effect transistor, detecting a memory state of the low-voltage flash memory, and transferring the memory state to the non-volatile memory element.

2. The low voltage flash memory a first source / drain; a second source-drain separated from the first source-drain by an epitaxial channel; a floating gate separated from the epitaxial channel by a first dielectric layer; the control gate separated from the floating gate by a second dielectric layer; The circuit of claim 1 , comprising:

3. 3. The circuit of claim 2, wherein the floating gate has a doping type that is opposite to the doping type of the epitaxial channel.

4. 3. The circuit of claim 2, wherein the first source-drain, the second source-drain, and the epitaxial channel are doped with an n-type dopant.

5. The circuit of claim 2 , wherein the first dielectric layer is made from a high-k dielectric material.

6. 2. The circuit of claim 1, wherein the low-voltage flash memory is vertical.

7. 2. The circuit of claim 1, wherein the low voltage flash memory is separated from the vertical field effect transistor by shallow trench isolation.

8. The circuit according to any one of claims 1 to 7, wherein the non-volatile memory element is a phase change memory, a resistive random access memory, a magnetic random access memory, or a flash memory.

9. A circuit as claimed in any preceding claim, wherein the low voltage flash memory provides a low side conductance and the non-volatile memory element provides a high side conductance.

10. 9. The circuit of claim 1, wherein the low-voltage flash memory is read by turning on the vertical field effect transistor and applying a read voltage to the control gate of the low-voltage flash memory.

11. The circuit of any one of claims 1 to 10, further comprising an intermediate terminal interposed between the low-voltage flash memory and the vertical field-effect transistor.

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