Vertically Integrated Bipolar Junction Transistor with Resistor

Abstract

A vertical bipolar junction transistor (VBJT) is disclosed having one or more resistors, each connected in a circuit with a different circuit configuration. The VBJT has an emitter sub-structure comprising an emitter layer, a collector, an intrinsic base, one or more doped epitaxy regions, and one or more resistors. The intrinsic base, the doped epitaxy region(s), and the resistor(s) are stacked together in a channel between the emitter layer and the collector. Various circuit configurations and structures are described, including common collector circuits, common emitter circuits, and emitter degeneration circuits. Methods for manufacturing these configurations / structures are disclosed.

Description

[Technical Field]

[0001] The present invention relates to integrating passive electrical devices with transistors, and more particularly to integrating resistors with bipolar junction transistors in a vertical structure. [Background technology]

[0002] Resistors are well-known electrical components that limit or control the flow of electrical current in electronic circuits. Resistors can be active resistors (e.g., diode-connected transistors) or passive resistors.

[0003] Passive resistors have superior temperature stability, linearity (bias stability), and low noise compared to active resistors. Therefore, passive resistors are preferred in applications where small changes in bias can cause large changes in output, such as biasing high-gain amplifiers or analog computing devices. The integration of passive resistors with transistors is fundamental in many circuit applications.

[0004] However, a major problem associated with the monolithic integration of passive resistors and transistors in a circuit is the large area consumed by the passive resistors on the circuit floorplan: the resistance of the passive resistor is generally larger, or much larger, than the on-resistance of the transistor, resulting in the passive resistor using more material and therefore more circuit surface area.

[0005] Bipolar junction transistors (BJTs) have large drive currents at a given operating voltage. This makes BJTs advantageous for use in certain applications, such as ultra-low power systems. Furthermore, BJTs are used in many standard circuit building blocks. For example, BJTs are used in common-collector circuits (e.g., analog voltage buffers), common-emitter circuits (e.g., analog voltage amplifiers or digital inverter / NOT gates), and emitter-degenerated circuits (e.g., analog voltage amplifiers or digital inverters).

[0006] Therefore, there is a need to integrate passive resistors with active components such as BJTs so that the passive resistors use the minimum surface area in the circuit. Summary of the Invention [Means for solving the problem]

[0007] In accordance with the present invention, several embodiments of a vertical bipolar junction transistor (VBJT) are disclosed, each connected in a circuit with one or more resistors. The VBJT and VBJT circuit have an emitter sub-structure including an emitter layer made of an emitter semiconductor, a collector made of a collector semiconductor, an intrinsic base made of an undoped or moderately doped semiconductor, one or more doped epitaxy regions made of a highly doped semiconductor, and one or more resistors. The intrinsic base, doped epitaxy region(s), and resistor(s) are stacked together in a channel in different configurations between the emitter layer and the collector.

[0008] Various circuit configurations and structures are described, including common collector circuits, common emitter circuits, and emitter degeneration circuits. Methods for fabricating these configurations and structures are disclosed.

[0009] Various embodiments of the present invention will now be described in more detail below with reference to the accompanying drawings, which will now be briefly described, in which various devices, structures and associated method steps of the present invention are shown. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a cross-sectional view of an intermediate multi-layer stack structure used to form a passive resistor (e.g., a resistor) vertically stacked with a bipolar junction transistor (BJT) in a common-collector circuit. [Figure 2]FIG. 2 is a cross-sectional view of the middle multi-layer stack structure of the initial middle common-collector circuit embodiment of FIG. 1 after the trench has been etched and a thin oxide layer has been formed on the dummy layer surfaces exposed in the trench opening. [Figure 3] FIG. 3 is a cross-sectional view of the intermediate multi-layer stack structure of a common-collector circuit embodiment after growing the resistor body and transistor intrinsic base from the emitter layer surface in the trench. [Figure 4] FIG. 4 is a cross-sectional view of the middle multi-layer stack structure of a common collector circuit embodiment after dielectric addition to the cap dielectric layer, chemical mechanical polishing, and base mask deposition. [Figure 5] FIG. 5 is a cross-sectional view of the middle multi-layer stack structure of a common collector circuit embodiment after removal of the dummy layers. [Figure 6] FIG. 6 is a cross-sectional view of the middle multi-layer stack structure of a common-collector circuit embodiment after removal of the thin oxide layer and epitaxial growth of the extrinsic base layer. [Figure 7] FIG. 7 is a cross-sectional view of the middle multi-layer stack structure of a common collector circuit embodiment after a base mask etch and inter-layer dielectric (ILD) deposition. [Figure 8] FIG. 8 is a cross-sectional view of the middle multi-layer stack structure of a common-collector circuit embodiment after removal of the base region hard mask and deposition of the collector mask. [Figure 9] FIG. 9 is a cross-sectional view of the middle multi-layer stack structure of a common collector circuit embodiment after the collector mask etch. [Figure 10] FIG. 10 is a cross-sectional view of the middle multi-layer stack structure of a common-collector circuit embodiment after collector deposition. [Figure 11] FIG. 11 is a cross-sectional view of the middle multi-layer stack structure of a common collector circuit embodiment after removal of the collector mask. [Figure 12] FIG. 12 is a cross-sectional view of a common collector circuit embodiment of a vertical BJT with a stacked vertical resistor including external contacts. [Figure 13]13A and 13B are cross-sectional and top views, respectively, of a common-collector circuit embodiment of a vertical BJT with stacked emitter resistors. [Figure 14] FIG. 14 is a circuit diagram of a common collector circuit embodiment of a vertical BJT with stacked emitter resistors. [Figure 15] FIG. 15 is a cross-sectional view of an intermediate multi-layer stack structure used to form a passive resistor (eg, a resistor) vertically stacked with a bipolar junction transistor (BJT) in a common-emitter circuit. [Figure 16] FIG. 16 is a cross-sectional view of an intermediate multi-layer stack structure used to form a passive resistor (e.g., resistor) vertically stacked with a bipolar junction transistor (BJT) in a common-emitter circuit embodiment after the formation of intrinsic and extrinsic base and collector resistors. [Figure 17] FIG. 17 is a cross-sectional view of a common-emitter circuit embodiment of a vertical BJT with a stacked vertical collector resistor including external contacts. [Figure 18] Figures 18A and 18B are cross-sectional and top views, respectively, of a common-emitter circuit embodiment of a vertical BJT with a stacked collector resistor shown in Figure 18A. [Figure 19] FIG. 19 is a circuit diagram of a common-emitter circuit embodiment of a vertical BJT with stacked collector resistors. [Figure 20] FIG. 20 is a cross-sectional view of an intermediate multi-layer stack structure used to form upper and lower passive resistors (e.g., resistors) vertically stacked with bipolar junction transistors (BJTs) in an emitter degeneration circuit. [Figure 21] Figure 21 is a cross-sectional view of an intermediate multi-layer stack structure used to form a bipolar junction transistor (BJT) and two resistors stacked vertically within the channel in an emitter-degeneration circuit embodiment. [Figure 22]Figure 22A is a cross-sectional view of an emitter degeneration circuit embodiment of a vertical BJT with a stacked first / emitter resistor Re, a stacked second / collector resistor Rc, and external connections. Figure 22B is a top view of the emitter degeneration circuit embodiment of Figure 22A. [Figure 23] FIG. 23 is a circuit diagram of an emitter degeneration circuit embodiment of a vertical BJT with stacked first / emitter resistor Re and second / collector resistor Rc. [Figure 24] FIG. 24 is a flow chart of a manufacturing process for a vertical BJT with one or more stacked resistors. DETAILED DESCRIPTION OF THE INVENTION

[0011] It should be understood that embodiments of the present invention are not limited to the exemplary methods, apparatus, structures, systems and devices disclosed herein, but instead have broader applicability to other alternative and broader methods, apparatus, structures, systems and devices that will become apparent to those skilled in the art from this disclosure.

[0012] Furthermore, it should be understood that the various layers, structures, or regions, or combinations thereof, shown in the accompanying figures are not drawn to scale, and that one or more layers, structures, or regions, or combinations thereof, of a commonly used type may not be explicitly shown in a given figure, without implying that the not explicitly shown layer, structure, or region, or combinations thereof, are omitted from the actual device.

[0013] Also, certain elements may be omitted from the figures for clarity or simplicity, or both, unless the description necessarily focuses on such omitted elements. Furthermore, the same or similar reference numbers used throughout the figures are used to indicate the same or similar features, elements, or structures, and thus, a detailed description of the same or similar features, elements, or structures may not be repeated for each of the figures.

[0014] The semiconductor devices, structures, and methods disclosed in accordance with embodiments of the present invention can be employed in applications, hardware, or electronic systems, or combinations thereof. Hardware and systems suitable for practicing embodiments of the present invention may include, but are not limited to, personal computers, communication networks, e-commerce systems, portable communication devices (e.g., cell phones and smartphones), solid-state media storage devices, expert and artificial intelligence systems, functional circuits, neural networks, etc. Systems and hardware incorporating semiconductor devices and structures are contemplated embodiments of the present invention.

[0015] As used herein, "height" refers to the vertical extent of an element (e.g., layer, trench, hole, opening, etc.) in a cross-sectional view as measured from the bottom to the top of the element, or as measured relative to the surface on which the element is located, or a combination thereof.

[0016] Conversely, "depth" refers to the vertical extent of an element (e.g., a layer, trench, hole, opening, etc.) in a cross-sectional view measured from the top surface to the bottom surface of the element. Terms such as "thick," "thickness," "thin," or derivatives thereof may be used in place of "height" where indicated.

[0017] As used herein, "lateral," "side," "side," and "exterior" refer to a side of an element (e.g., a layer, an opening, etc.), such as the left or right side in a drawing.

[0018] As used herein, "width" or "length" refers to the dimension measured from the side of an element (e.g., a layer, trench, hole, opening, etc.) in the drawing to the opposite surface of the element. Terms such as "thick," "thickness," "thin," or derivatives thereof, may be used in place of "width" or "length" where indicated.

[0019] As used herein, terms such as "upper," "lower," "right," "left," "vertical," "horizontal," "top," "bottom," and their derivatives refer to the disclosed structures and methods oriented in the drawings. For example, as used herein, "vertical" refers to an orientation perpendicular to the top surface of a substrate in the drawings, and "horizontal" refers to an orientation parallel to the top surface of a substrate in the drawings.

[0020] As used herein, unless otherwise specified, terms such as "on," "overlapping," "atop," "on top," "located on," or "atopped" mean that a first element is on a second element, and that there may be intervening elements between the first and second elements. As used herein, unless otherwise specified, the terms "on," "overlapping," "atop," "on top," "located on," or "located on," or the term "directly" used in conjunction with the terms "contacting" or "directly contacting," mean that a first element and a second element are connected without an intervening element, such as an intermediate conductive, insulating, or semiconducting layer, present between the first and second elements.

[0021] It should be understood that these terms may be affected by the orientation of the device being described: for example, if the device is rotated upside down, the meaning of these descriptions may change, but the descriptions remain valid because they describe the relative relationships between features of the invention.

[0022] A structure, device, and method for the monolithic integration of vertical passive resistors and vertical bipolar junction transistors (VBJTs) is disclosed. The present invention substantially reduces the area consumption of passive resistors used in such circuits.

[0023] The resistance of a passive resistor is R L=ρL / A, where ρ is the resistivity of the passive resistor material, L is the length of the resistor in the direction of current flow, and A is the cross-sectional area of the resistor perpendicular to the direction of current flow. The vertical structure of the present invention allows L (the height of the resistor structure) to be arbitrarily large while A (the footprint of the resistor / transistor pair) to be small, and both a large L and a small A simultaneously favor a large R.

[0024] When used in large-scale circuits, the present invention offers significant space savings compared to planar (i.e., horizontal) resistors used in the prior art. Additionally, the length of the passive resistor can be designed, e.g., made taller or shorter, depending on the resistance needs without affecting the footprint of the device. In some embodiments, epitaxial growth of the resistor region allows multiple ways to tailor the resistor to the desired resistance, for example, by controlling the dopant species, codopants, doping level, and epitaxy thickness and size. Embodiments of the present invention include vertically oriented or stacked devices with four terminals.

[0025] FIG. 1 is a cross-sectional view of an intermediate multi-layer stack structure 100 used to form a passive resistor (e.g., a resistor) vertically stacked with a bipolar junction transistor (BJT) in a common-collector circuit.

[0026] The common collector circuit intermediate multi-layer stack structure embodiment 100 includes a support substrate 103 having a support substrate thickness 13, a punch-through stop (PTS) layer 104 (doped with an opposite dopant to the emitter region layer 105) having a PTS layer thickness 14 disposed on the support substrate 103, and a heavily doped emitter region layer 105 (connected to ground in some embodiments) having an emitter region layer thickness 15. The emitter region layer (or emitter layer) 105 is disposed on the PTS layer 104.

[0027] The material from which the support substrate 103 is made includes one or more semiconductor materials, such as bulk semiconductor materials. Non-limiting examples of suitable support substrate 103 materials include Si (silicon), strained Si, Si:C (carbon-doped silicon), Ge (germanium), SiGe (silicon germanium), SiGe:C (carbon-doped silicon germanium), Si alloys, Ge alloys, III-V semiconductor materials (e.g., GaAs (gallium arsenide), InAs (indium arsenide), InP (indium phosphide), or indium gallium arsenide (InGaAs)), or any combination thereof.

[0028] The support substrate 103 is 600 microns to 1000 microns of The support substrate has a thickness 13. Other thicknesses 13 are contemplated.

[0029] The PTS layer 104 can be formed on the upper surface of the support substrate 103 by ion implantation or by epitaxial growth in combination with "in situ" doping or ion implantation. The thickness 14 of the PTS layer 104 can be from 50 nanometers (nm) to 150 nm.

[0030] The emitter layer 105 is made of a semiconductor material. In some embodiments, the emitter layer 105 is formed by epitaxial growth combined with in situ doping. In some embodiments, the thickness 15 of the emitter layer 105 is from about 10 nm to about 100 nm.

[0031] In some embodiments, the emitter layer 105 is an epitaxially grown layer composed of a silicon material, such as n-type doped silicon. The emitter layer 105 is highly doped with an n-type dopant selected from the group of phosphorus (P), arsenic (As), and antimony (Sb). In a non-limiting example, the dopant concentration is 4×10 cm -3 ~2.5x1021cm -3 in be.

[0032] Figures 1, 15, and 20 disclose initial intermediate multi-layer stack structures 100 / 1500 / 2000, respectively. These related but different stack structures 100 / 1500 / 2000 are used to create three respective alternative structures / devices of the present invention.

[0033] Also, the disclosed structures 100 / 1500 / 2000 are based on Group IV semiconductors. In light of this disclosure, it is contemplated without loss of generality that similar structures can be made with III-V compound semiconductors using known MOCVD growth techniques not disclosed in detail herein.

[0034] Each of these structures 100 / 1500 / 2000 is formed on the just-described emitter substructure 103 / 104 / 105, i.e., support substrate 103, PTS layer 104, and emitter layer 105. Each of the alternative structures / devices has a different order and selection of layers disposed on the emitter substructure 103 / 104 / 105, as described below. Other embodiments are also contemplated.

[0035] We now continue with the description of the common collector circuit embodiment, beginning with structure 100 of FIG.

[0036] Continuing with the description of the common collector circuit intermediate multi-layer stack structure 100, an intermediate resistor substructure 132A / 135A / 137A layer is disposed on the emitter substructure. The intermediate resistor substructure 132A / 135A / 137A is comprised of a resistor lower spacer 132A with a resistor lower spacer thickness 131, a resistor dielectric layer 135A with a resistor dielectric layer thickness 136, and a resistor upper spacer 137A with a resistor upper spacer thickness 138.

[0037] In this embodiment, a resistor lower spacer 132A is disposed on the emitter layer 105, a resistor dielectric layer 135A is disposed on the resistor lower spacer 132A, and a resistor upper spacer 137A is disposed on the resistor dielectric layer 135A.

[0038] Each of the resistor lower spacer 132A, the resistor dielectric layer 135A, and the resistor upper spacer 137A may be made of an oxide (e.g., SiOx) or a nitride (e.g., silicon nitride, Si x N y ) or a dielectric oxynitride (e.g., SiOCN or SiBC). Other dielectric materials employed in semiconductor devices are also contemplated.

[0039] In some embodiments, the layers / spacers 132A / 135A / 137A are composed of silicon nitride or silicon oxynitride deposited by a process such as chemical vapor deposition (CVD) or physical vapor deposition (PVD) or plasma enhanced chemical vapor deposition (PECVD).

[0040] The composition of these dielectric layers 132A / 135A / 137A may be selected to provide selective etching between these layers 132A / 135A / 137A and / or adjacent and / or other layers in the initial intermediate multi-layer stack structure 100 / 1500 / 2000 ("selective etching" means that one material is removed by an etching step while another material is selectively and substantially not etched by the same etching step).

[0041] The thickness 131 of the resistor lower spacer 132A and the thickness 138 of the resistor upper spacer 137A are approximately 5 nm to 20 nm. in The thickness is preferably 6 to 2 nm.

[0042] The thickness 136 of the resistor dielectric layer 135A depends on the length of the resistor. Thus, for the same cross section of the resistor dielectric layer 135A, the resistance of the resistor is determined by the resistor length R, which is determined by the thickness 136 of the resistor dielectric layer 135A. L 136. In some alternative embodiments, the resistor length R L 136 is measured as the distance between the centerlines (not shown) of resistor bottom spacer 132A and resistor top spacer 137A.

[0043] In this embodiment of the common collector circuit middle multi-layer stack structure 100, a dummy contact layer 140 is deposited on the resistor top spacer 137A. The dummy contact layer 140 is composed of a sacrificial material that is selectively removed from the dummy layer 115, as described below.

[0044] The dummy contact layer 140 is deposited by known processes such as CVD, PVD, PECVD, atomic layer deposition (ALD), metalorganic chemical vapor deposition (MOCVD), room temperature chemical vapor deposition (RTCVD), high density plasma chemical vapor deposition (HDPCVD), and combinations thereof.

[0045] In some embodiments, the dummy contact layer 140 is made of a silicon material such as amorphous silicon, α-Si, or amorphous germanium, α-Ge, or amorphous silicon-germanium, α-SiGe, and has a thickness of approximately 10 nm to 60 nm. of The dummy contact layer has a thickness 141 .

[0046] In this embodiment of the common collector circuit intermediate multi-layer stack structure 100, a "three-layer dummy stack" 110 / 115 / 120 is deposited on the metal contact layer 140. The three-layer dummy stack 110 / 115 / 120 is comprised of a base bottom spacer 110 (thickness 111 of the base bottom spacer 110), a dummy layer 115 (thickness 116 of the dummy layer 115), and a base top spacer 120 (thickness 121 of the base top spacer 120).

[0047] The material making up the base lower spacer 110 and the base upper spacer 120 is selectively etchable from the material of the dummy layer 115. For example, the three-layer dummy stack 110 / 115 / 120 may be made of silicon nitride (Si x N y ) and then a base lower spacer 110 made of silicon dioxide (SiO x ) dummy layer 115 is laminated, and then silicon nitride (Si x N yIn an alternative embodiment, the base upper spacer 120 can be made of, for example, SiO x ), dummy layer 115 (Si x N y ), and a base upper spacer 120 (SiO x The dummy layer 115 is a sacrificial layer that can be selectively etched from the material that makes up the metal contact layer 140.

[0048] In some embodiments, the resistor bottom spacer 132A, the resistor top spacer 137A, the base bottom spacer 110, and the base top spacer 120 are made of the same material. Non-limiting examples of these materials include low-k materials, where the term "low-k" refers to a dielectric material having a dielectric constant equal to or less than that of silicon oxide (SiO2). Examples of low-k dielectric materials suitable for the spacers include diamond-like carbon (DLC), organosilicate glass (OSG), fluorine-doped silicon dioxide, carbon-doped silicon dioxide, carbon-doped silicon nitride, porous silicon dioxide, porous carbon-doped silicon dioxide, boron-doped silicon nitride (SiBN), carbon-boron-doped silicon nitride (SiBCN), SiOCN, SiCN, SiOC, spin-on organic polymer dielectrics (e.g., SILK), and the like. TM ), spin-on silicone-based polymer dielectrics (e.g., hydrogen silsesquioxane (HSQ) and methyl silsesquioxane (MSQ)), and combinations thereof.

[0049] The materials of the base lower spacer 110, the dummy layer 115, and the base upper spacer 120 are deposited by known deposition processes, including, by way of non-limiting example, CVD, PVD, ALD, MOCVD, RTCVD, HDPCVD, plasma enhanced chemical vapor deposition (PECVD), inductively coupled plasma chemical vapor deposition (ICP CVD), or any combination thereof.

[0050] The thickness 111 of the base lower layer spacer 110 and the thickness 121 of the base upper layer spacer 120 are approximately 5 nanometers (nm) to 20 nm, or 6 nm to 12 nm. in The dummy layer 115 has a thickness of 50 nm to 300 nm. of It has 116.

[0051] A cap dielectric layer 24 is formed on the base upper layer spacer 120. The cap dielectric layer 24 may be, by way of non-limiting example, silicon oxide (SiO x In some embodiments, the cap dielectric layer 24 is composed of an oxide such as tetraethylorthosilicate (TEOS) oxide, high aspect ratio plasma (HARP) oxide, high temperature oxide (HTO), and high density plasma (HDP) oxide. In some embodiments, the cap dielectric layer 24 is composed of a material that can be removed by an etching process that is selective to the base top layer spacers 120. The base top layer spacers 120 protect the sacrificial dummy layer 115 from being etched by the process step that removes the cap dielectric layer 24. Non-limiting examples of other materials that may be used to make the cap dielectric layer 24 include oxides such as tetraethylorthosilicate (TEOS) oxide, high aspect ratio plasma (HARP) oxide, high temperature oxide (HTO), and high density plasma (HDP) oxide.

[0052] FIG. 2 is a cross-sectional view of the middle multi-layer stack structure 200 of the common collector circuit embodiment of FIG. 1 after a trench has been etched up to / through the resistor bottom spacer 132A and a thin oxide layer 215 has been formed on the surface of the dummy layer 115 exposed in the trench opening 250.

[0053] In some embodiments, trench 250 is etched using a process that is selective to the layer(s) being etched away by the etch(s), such as reactive ion etching (RIE) or a series of RIE steps. Etching trench 250 is known.

[0054] The initial etch (or etching step) etches trench 250 down to and selectively to resistor bottom spacer 132A, i.e., the etch stops at the surface and does not remove the portion of resistor bottom spacer 132A within trench 250 (not shown).

[0055] As non-limiting examples of etching aspects of trench 250, a first etch (selective to the material of dummy layer 115) removes portions of the material of cap dielectric layer 24 and base upper layer spacer 120 within trench 250, a second etch (selective to the material of base lower layer spacer 110) removes portions of dummy layer 115 within trench 250, a third etch (selective to resistor upper spacer 137A) removes portions of metal layer 140 within trench 250, and a fourth etch (selective to resistor lower spacer 132A) removes portions of resistor dielectric layer 135A within trench 250.

[0056] Next, the surface 275 of the trench 250 is subjected to an oxidation process, such as, for example, plasma oxidation or other known oxidation methods. The oxidation step proceeds with parameters (e.g., time, temperature, etc.) to form a thin oxide layer 215 on the surface of the polysilicon layer 115 that is part of the surface 275 of the trench 250, and a thin oxide layer 240 on the surface of the dummy contact layer 140 that is also part of the surface of the trench 250. The thickness of the thin oxide layer 215 / 240 is between 2 nm and 3 nm. in No oxide layer is formed on the surface 275 of the dielectric layer 135A / 137A / 110 / 120 / 24 or on the resistor bottom spacer 132A.

[0057] After forming the thin oxide layer 215, etching continues to remove the portion of the resistor bottom spacer 132A in the trench 250 and expose the surface 225 of the emitter layer 105 in the trench 250. This etching step is selective to the material of the emitter layer 105, i.e., the etching stops on the exposed surface 225 of the emitter layer 105.

[0058] The width of the trench (trench width) 251 can be from about 6 nm to about 250 nm, or from about 6 nm to about 100 nm.

[0059] 3 is a cross-sectional view of the intermediate multi-layer stack structure 300 of a common-collector circuit embodiment after the resistor body 325 and transistor base 350 have been grown from the emitter layer surface 225 in trench 250. This growth is a step-wise epitaxial growth. There is no epitaxial growth from the dielectric surfaces, such as the sidewalls / surfaces 275 of trench 250, e.g., 132A / 135A / 137A / 240 / 110 / 215 / 120 / 24.

[0060] The terms "epitaxial growth and / or deposition" and "epitaxial formation and / or growth" refer to the growth of a semiconductor material (crystalline material) on a deposition surface of another semiconductor material (crystalline material), e.g., on the emitter layer 105, such that the growing semiconductor material (crystalline overlayer) has substantially the same crystalline properties as the semiconductor material (seed material) on the deposition surface. In an epitaxial deposition process, chemical reactants supplied by source gases are controlled and system parameters are set so that the deposited atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move across the surface in a manner that orients them in the crystalline arrangement of the atoms on the deposition surface. Thus, the epitaxially grown semiconductor material has substantially the same crystalline properties as the deposition surface on which the epitaxially grown material is formed. The epitaxial deposition process can use a deposition chamber in a chemical vapor deposition (PECVD) system or other chemical vapor deposition (CVD) system.

[0061] In some embodiments, the gas source for the deposition of epitaxially grown in situ doped n-type semiconductor material can include silicon (Si) deposited from silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, methylsilane, dimethylsilane, ethylsilane, methyldisilane, dimethyldisilane, hexamethyldisilane, and combinations thereof. In another example, when the semiconductor material includes germanium (Ge), the germanium gas source can be selected from the group consisting of germane, digermane, halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane, and combinations thereof. The temperature for epitaxial silicon germanium deposition typically ranges from 450°C to 900°C. Higher temperatures generally result in faster deposition, but faster deposition can also result in crystalline defects and film cracking. Epitaxial silicon germanium alloy layers can be formed using combinations of such gas sources. Carrier gases such as hydrogen, nitrogen, and helium can be used.

[0062] The passive resistor body 325 is epitaxially grown in the trench 250 on the emitter layer surface 225. The epitaxial resistor portion 325 can be composed of doped silicon, germanium, or silicon germanium. The doping type is the same as that of the emitter / collector.

[0063] The dimensions, material composition, dopant species, and dopant concentration of resistor 325 are selected to provide the resistance characteristics of resistor 325 according to the design parameters of the circuit. The cross-sectional area A of resistor 325 is determined by trench width 251. The resistor length R of resistor 325 L 320 is determined by the thickness 136 of the resistor dielectric layer 135A and, in some embodiments, the thickness 131 of the resistor bottom spacer 132A and the thickness 138 of the resistor top spacer 137A. Also, in situ carbon doping can be used in the tool to fine-tune the resistivity, independent of the polarity of the resistor structure.

[0064] The cross-sectional area A is perpendicular to the direction of current flow and is the length R of the resistor. L 320 is in the direction of current flow. The vertical structure 300 is the resistor length R L 320 can be arbitrarily large while allowing A (e.g., the footprint of the resistor / transistor pair) to be small. Both large L and small A values simultaneously favor a large resistance R. The resistor length R of passive resistor 325 L 320 can be made longer to increase the resistance of the passive resistor 325. L 320 can be a function of the length of time of the epitaxial growth process to form the passive resistor 325.

[0065] The cross-sectional area A of the resistor 325 affects the resistance of the resistor 325. The cross-sectional area A is, for example, 6 nm to 100 nm. in A certain trench width 215 and, for example, 20 nm to 100 nm in The resistor length R is a function of the length of the trench (not shown). L 320 is 10nm to 200nm in The resistors 325 have the same doping type as the respective emitter / collector and are 1x10 17 cm -3 ~1x10 19 cm -3 The resistors are made from the semiconductor materials mentioned above with a doping concentration of 1x10. Additionally, in situ carbon doping can be used in the tool to fine-tune the resistivity, regardless of the polarity of the resistor structure. When carbon doping is performed, the carbon doping concentration is 1x10. 16 cm -3 ~8x10 20 cm -3 in be.

[0066] The resistor typically has a resistor length R that extends from the top surface 225 of the emitter layer 105 to approximately the centerline (not shown) of the resistor bottom spacer 132A. L320. However, in some embodiments, the resistor 320 may extend slightly below or above the resistor lower spacer 132A. L 320 is also determined by the thickness 136 of the resistor dielectric layer 135A.

[0067] The resistor 325 must remain within the resistor spacers at the bottom 132A and top 137A. In some embodiments, the resistor length R L 320 is 5nm to 100nm in The resistor layer 325 may have a resistance between 10 ohms and 10 megaohms. 17 ~10 19 cm -3 The doping levels range from 0.1 to 1.0.

[0068] Resistor 325 has a resistor length R L After epitaxial growth to 320 (e.g., parameters such as growth time and temperature are typically determined experimentally), the epitaxial growth conditions are varied to form first doped epitaxy region 330, which will later serve as part of the external electrical connection to the voltage output generated across resistor 325.

[0069] The first doped epitaxial layer 330 has a doping polarity as the emitter / collector doping type and a doping concentration of 4x10 20 cm -3 ~2.5x10 21 cm -3 , preferably 4x10 20 cm -3 ~1.5x10 21 cm -3 inThe first doped epitaxial layer 330 is composed of a highly doped semiconductor material (e.g., silicon or silicon-germanium). Therefore, the first doped epitaxial layer 330 is highly conductive. In some embodiments, the doping concentration of the first doped epitaxial layer 330 is graded, with a doping concentration of 4×10 near the first resistive region 1625. 20 cm -3 ~1.5×10 21 cm -3 , and near the intrinsic base region 350, 19 cm -3 ~14×10 20 cm -3 (e.g., to reduce bandgap narrowing and Auger recombination in doped epitaxial layers near the intrinsic base region 350, as known in the art). Similarly, the doping concentration of the second doped epitaxial layer 2130 may be graded, ranging from 4×10 near the second resistor region 2125 to 4×10 near the second resistor region 2125. 20 cm -3 ~11.5×10 21 cm -3 , and near the intrinsic base region 350, 19 cm -3 ~14×10 20 cm -3 21 (see description of FIG. 21 below).

[0070] First doped epitaxy layer 330 continues to grow within trench 250 to fill the area approximately between resistor top spacer 137A and base bottom layer spacer 110. As a result, first doped epitaxy layer 330 has a thickness approximately equal to thickness 136 of resistor dielectric layer 135A. At this point in the process, first doped epitaxy layer 330 is in contact with thin oxide layer 240.

[0071] After the first doped epitaxy region 330 is grown, the epitaxial gas chemistry is modified in situ to grow an intrinsic base 350 that continues to grow within the trench 250. The intrinsic base material 350 grows, filling the remainder of the trench 250, until the intrinsic base material 350 forms a base cap 355 on top of the cap dielectric layer 24.

[0072] The intrinsic base 350 is made of a semiconductor material, such as silicon (Si), silicon-germanium (SiGe), or the like, and is lightly or moderately doped with a dopant type opposite to that of the emitter 105, the collector 1050, the first doped epitaxial layer 330, the second doped epitaxial layer 2130, the first resistor region 1625, and the resistor region 2125, and in some embodiments may be doped with a dopant type opposite to that of the emitter 105, the collector 1050, the first doped epitaxial layer 330, the second doped epitaxial layer 2130, the first resistor region 1625, and the resistor region 2125. 17 ~10 19 cm -3 of The doping concentration is as follows (see the description of Figures 16 and 21 below).

[0073] For example, in one embodiment where the bipolar junction transistor is an npn transistor, emitter 105, collector 1050, first doped epitaxy 330, second doped epitaxy 2130, first resistor region 1625, and resistor region 2125 are n-type doped, while intrinsic base 350 and extrinsic base 650 are p-type doped. In another embodiment where the bipolar junction transistor is a pnp transistor, emitter 105, collector 1050, first doped epitaxy 330, second doped epitaxy 2130, first resistor region 1625, and resistor region 2125 are p-type doped, while intrinsic base 350 and extrinsic base 650 are n-type doped. In a preferred embodiment, the intrinsic base 350 is composed of a material having a lower bandgap than the bandgap of the first or second or both doped epitaxy regions 330 and 2130. For example, the intrinsic base 350 may be composed of SiGe having a higher Ge content than the Ge content of the doped epitaxy regions 330 and 2130. As is known in the art, a relatively low bandgap for the intrinsic base is desirable for improved transistor gain, reduced switching voltage, or improved carrier collection, or a combination thereof.

[0074] In some embodiments, the intrinsic base material 350 is comprised of a material that is lattice-matched to the emitter layer 105. In some embodiments, the emitter layer 105 is comprised of silicon (Si), the collector 1050 is comprised of silicon (Si) (see description of FIG. 10), and the intrinsic base material 350 is comprised of silicon-germanium (SiGe).

[0075] As disclosed, the dopants and dopant concentrations used to create the epitaxial growth of resistor 325 may be selected to provide the resistive characteristics of passive resistor 325, then modified to form first doped epitaxy region 330, and then modified again to form intrinsic base 350 with appropriate semiconductor properties. The epitaxial growth parameters for each of these regions 325 / 330 / 350, e.g., growth time, temperature, etc., are determined by experimentation.

[0076] The passive resistor 325, the first doped epitaxy region 330, and the intrinsic base 350 can be epitaxially grown in the trench 250 using the same epitaxial growth chamber. The epitaxial growth in the trench 250 forms a monolithic structure 325 / 330 / 350, where the term "monolithic" denotes that the passive resistor 325, the first doped epitaxy region 330, and the intrinsic base 350 are composed of the same semiconductor material, albeit with different doping levels.

[0077] By growing in trench 250 , resistor 325 , first doped epitaxy region 330 , and intrinsic base 350 are vertically aligned, thereby minimizing the cross-sectional area A for each device on the surface of supporting substrate 103 .

[0078] FIG. 4 is a cross-sectional view of the middle multi-layer stack structure 400 of a common-collector circuit embodiment after removing the base cap 355 (e.g., by chemical-mechanical polishing (CMP)), adding a dielectric 424 to the cap dielectric layer 24 (forming a thicker cap dielectric layer), performing another CMP, and depositing a base mask 450.

[0079] CMP techniques are well known. The dielectric 424 applied on top of the cap dielectric layer 24 can be any dielectric. In some embodiments, the dielectric is the same dielectric 424 as the dielectric of the cap dielectric layer 24 deposited by the methods described above.

[0080] The base mask 450 is a hard mask that covers the trench 250 / true base 350 and extends to cover a portion of the dummy layer 115 around the trench 250 / true base 350.

[0081] The base mask 450 is composed of a protective dielectric material, such as a lithography-protective material, including, but not limited to, any one of silicon nitride (SiN), silicon borocarbonitride (SiBCN), silicon oxycarbonitride (SiOCN), and silicon oxynitride (SiON). The base mask 450 is deposited by standard techniques, including CVD, PVD, ALD, or other lithography processes, or combinations thereof.

[0082] FIG. 5 is a cross-sectional view of the middle multi-layer stack structure of the common collector circuit embodiment 500 after a directional etch has been performed to remove the dummy layer 115 and leave a void region 515 .

[0083] A directional etch, such as a first base directional etch, uses known chemistries to remove material not protected by the base mask 450 to form narrow cap dielectric layer 524 regions below the base mask 450 and narrow the base upper layer spacers 120. Material of the dummy layer 115 not protected by the base mask 450 may or may not be removed by the base directional etch, but the first base directional etch does not proceed beyond the base lower spacers 110.

[0084] In some embodiments, a dummy etch is then performed that removes the remaining material of the dummy layer 115 but is selective to (does not substantially remove) the cap dielectric layer 524, the base top layer spacers 120, the thin oxide layer 215, and the base bottom spacers 110. The second etch leaves voids 515 in place of the dummy layer 115.

[0085] The first base direction etching and the dummy etching may be performed in either order.

[0086] FIG. 6 is a cross-sectional view of the middle multi-layer stack structure of the common-collector circuit embodiment 600 after removing the thin oxide layer 215 and epitaxially growing the extrinsic base layer 650 .

[0087] The thin oxide liner 215 is removed by dry etching (e.g., SiCoNi TM The etched film can be removed using a short hydrofluoric acid (HF) etch, or any other suitable pre-cleaning process.

[0088] The extrinsic base layer 650 is epitaxially grown on the intrinsic base 350 , filling the void 515 left by the removal of the dummy layer 115 .

[0089] The shape of and access to the void 515 and the epitaxial growth along the surfaces of the plurality of spacers 110 / 120 allow: Epitaxy The epitaxial base of a BJT typically contains defects, including dislocations and stacking faults. Because the extrinsic base of a BJT is typically made of polycrystalline semiconductor material, defects will not degrade its function as an extrinsic base material. Defective epitaxial material grown resembles the properties of a polycrystalline material, but contains much larger grains (completely Epitaxy , forming a large grain polycrystalline material (LGP) extrinsic base layer 650. Thus, in some embodiments, extrinsic base layer 650 is a polycrystalline material 650 that may include defects, such as large grains, in polycrystalline structure 40, for example, forming a large grain polycrystalline material (LGP) extrinsic base layer 650.

[0090] In some embodiments, the extrinsic base 650 is in situ doped. Epitaxy The external base 650 is 10 19 cm -3 ~14×10 20 cm -3In a preferred embodiment, extrinsic base 650 is comprised of a material having a bandgap higher than that of intrinsic base 350. For example, if intrinsic base 350 is comprised of SiGe, extrinsic base 650 may be comprised of polysilicon. As is known in the art, a higher bandgap of extrinsic base 650 compared to that of intrinsic base 350 can be beneficial in some embodiments to reduce base current and improve transistor gain.

[0091] 7 is a cross-sectional view of the middle multi-layer stack structure of the common-collector circuit embodiment 700 after a second base directional etch is performed. The second base directional etch removes the portion of the material of the extrinsic base layer 650 that is not protected by the base mask 450. As a result, the cap dielectric layer 524, the base top layer spacers 120, and the sides of the extrinsic base layer 650 are coplanar surfaces defined by the shape of the base mask 450.

[0092] After the second base-directed etch, an interlayer dielectric (ILD) 750 material is deposited to fill any remaining spaces in the structure 700. The ILD 750 may be made of, for example, a low-k dielectric constant material (having k<4.0), including, but not limited to, silicon oxide, spin-on glass, flowable oxide, high-density plasma oxide, borophosphosilicate glass (BPSG), or any combination thereof. The ILD 750 may be deposited by a deposition process, including, but not limited to, CVD, PVD, PECVD, ALD, evaporation, or chemical solution deposition.

[0093] 8 is a cross-sectional view of the middle multi-layer stack structure of common-collector circuit embodiment 800 after removing base mask 450 (and a portion of the top surface of IDL 750) and depositing collector mask 850. Collector mask 850 has collector mask opening 851 approximately centered above true base 350.

[0094] The base mask 450 is removed by known techniques such as CMP or masked etching.

[0095] Collector mask 850 is a hard mask and can be made of the same materials as base mask 450 and deposited in the same manner.

[0096] FIG. 9 is a cross-sectional view of the middle multi-layer stack structure of a common-collector circuit embodiment 900 after the collector mask etch.

[0097] The collector masked etch creates the collector cavity 925 by removing material from the cap dielectric layer 524 and from a portion of the true base 350 in areas not protected by the collector mask 850. The shorter true base 950 results in exposing the base top surface 951 to the collector cavity 925. The collector masked etch is selective to the base top layer spacers 120.

[0098] FIG. 10 is a cross-sectional view of the middle multi-layer stack structure of the common-collector circuit embodiment 1000 after deposition of the collector 1050 .

[0099] Collector 1050 is epitaxially grown to fill collector cavity 925 and contact top base surface 951 of intrinsic base 950. Collector 1050 can be composed of any known collector material that is compatible with intrinsic base 950 and is deposited by known techniques, such as CVD and PVD, as described above.

[0100] In some embodiments, the collector 1050 is of the same dopant type as the emitter layer 105 and has a 4x10 20 cm -3 ~2.5x10 21 cm -3 of It is made of doped silicon doped with a dopant concentration.

[0101] FIG. 11 is a cross-sectional view of the middle multi-layer stack structure of a common-collector circuit embodiment 1100 after removal of the collector mask 850 by known methods such as CMP or mask etching.

[0102] FIG. 12 is a cross-sectional view of a common collector circuit embodiment of a vertical BJT with a stacked vertical resistor 1200 including external contacts 1225 / 1250 / 1275.

[0103] The external contacts 1225 / 1250 / 1275 are made by known methods, including, but not limited to, forming vias using a laser, patterning one or more trenches with a mask etch, etc.

[0104] The dummy contact layer 140 and thin oxide layer 240 are removed and replaced with a metal contact layer 340 .

[0105] In some embodiments, the dummy contact layer 140 is removed from between the resistor top spacers 137A and the base lower layer spacers 110 by a wet etch using hot ammonia. The etching material contacts the dummy contact layer 140 through one or more drilled holes, or by lateral access, or a combination thereof. The wet etch selectively removes the dummy contact layer 140 while leaving the resistor top spacers 137A, the base lower layer spacers 110, and the thin oxide layer 240 substantially intact. The thin oxide liner 240 is then removed by a dry etch (e.g., SiCoNi TM The SiCoNi is removed using a pre-cleaning process, a short hydrofluoric acid (HF) etch, or any other suitable pre-clean process. TM The etch is a plasma-based dry etching process that simultaneously exposes the substrate to hydrogen, NF3, and NH3 plasma by-products.

[0106] Thus, a cavity is formed between the resistor upper spacer 137A, the base lower layer spacer 110, and the first doped epitaxy region 330. After a silicide, typically 1240, is formed on the first doped epitaxy region 330, the cavity left by the removal of the dummy contact layer 140 is filled with a metal to create the metal contact layer 340. Non-limiting examples of metals that can be used to make the metal contact layer 340 include cobalt (Co) or tungsten (W), as well as other metals such as nickel (Ni), platinum (Pt), titanium (Ti), and molybdenum (Mo), deposited by known deposition techniques such as CVD, PVD, and ALD. The metal contact layer 340 is in direct contact with the silicide layer 1240, which is in direct contact with the surface of the first doped epitaxy region 330.

[0107] The vias / trenches are long enough to electrically connect the respective internal contacts of device 1200 to external circuitry. Removal of material from cap dielectric layer 524, base upper layer spacer 120, collector 1050, extrinsic base layer 650, base lower spacer 110, or metal contact layer 340, or a combination thereof, creates the respective vias / trench.

[0108] The base contact 1225 passes through the cap dielectric layer 524 and the base top layer spacer 120 to contact the extrinsic base layer 650 and the base 950. The collector contact 1250 directly contacts the collector 1050. The output contact 1275 contacts the metal contact layer 340. Note that an insulating layer 1280 is first deposited in the via containing the output contact 1275 to prevent the output contact 1275 from electrically shorting to the extrinsic base layer 650.

[0109] The vias / trenches are filled with a conductive material, such as a metal, or a combination of conductive materials. Non-limiting examples of conductive materials are conductive metals, aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), cobalt (Co), or any combination thereof. The conductive material can be deposited by a suitable deposition process, such as, for example, CVD, PECVD, PVD, plating, thermal or electron beam evaporation, or sputtering.

[0110] 13A is a cross-sectional view of a vertical BJT common collector circuit embodiment 1300 with stacked emitter resistor 325. Contacts 1225 / 1250 / 1275 are made as described above.

[0111] 13B is a top view of a common-collector circuit embodiment 1350 of a vertical BJT with stacked emitter resistor 1300 shown in FIG. 13A. In some embodiments, collector contact 1250 can be a single contact or multiple contacts 1250, as shown. In some embodiments, base contact 1225 is multiple contacts 1225 on one side of structure 1300 / 1350, as shown, and output contact 1275 is multiple contacts 1275 on another side of structure 1300 / 1350. In some embodiments, emitter contact 1305 is multiple contacts on the front or back surface or both of structure 1300 / 1350, as shown in top view 1350 but not visible in cross-sectional view 1300.

[0112] FIG. 14 is a circuit diagram of a common collector circuit embodiment of a vertical BJT with a stacked emitter resistor 1400.

[0113] The circuit input Vin is the external base connection 1225, and the circuit output Vout is the external connection 1275. In this circuit, the external emitter connection 1305 is connected to ground (or alternatively, the emitter supply voltage Vss). The external collector connection 1250 is connected to the collector supply voltage Vdd.

[0114] FIG. 15 is a cross-sectional view of an intermediate multi-layer stack structure used to form a bipolar junction transistor (BJT) and a vertically stacked resistor (eg, a resistor) in a common-emitter circuit embodiment 1500.

[0115] The layers in the common-emitter embodiment of the intermediate multi-layer stack structure 1500 are the same as those in the common-collector embodiment 100, but in a different order. Similar to the common-collector embodiment 100, the emitter substructures 103 / 104 / 105 are present. However, in the common-emitter embodiment 1500, the "three-layer dummy stack" 110 / 115 / 120 is deposited first on the emitter substructures. The dummy contact layer 140 is deposited on the three-layer dummy stack, e.g., on the base top spacer 120. The middle resistor substructures 132B / 135B / 137B are deposited on the dummy contact layer 140. The cap dielectric layer 24 is deposited on the middle resistor substructures 132B / 135B / 137B, e.g., on the resistor top spacer 137B. For the material compositions, thicknesses, and deposition methods of these layers, see the description of FIG. 1.

[0116] FIG. 16 is a cross-sectional view of an intermediate multi-layer stack structure used to form a passive resistor (e.g., resistor) vertically stacked with a bipolar junction transistor (BJT) in a common-emitter circuit embodiment 1600 after formation of the intrinsic base 350 and extrinsic base and resistor 1625.

[0117] This structure 1600 is formed by performing the steps of etching trench 250 and oxidizing thin oxide layer 215 / 240. The trench / opening 250 is then filled by epitaxial growth, with epitaxial growth time controlled, in this order to form intrinsic base 350, first doped epitaxial region 330, and collector resistor 1625. A base mask 450 is deposited.

[0118] A directional etch, for example a first base / collector directional etch, is performed using known chemistries to remove material not protected by the base mask 450. The first base / collector directional etch removes material below / selectively to the base bottom spacers 110.

[0119] In some embodiments, a dummy etch is then performed to remove remaining material of the dummy layer 115, but is selective to (does not substantially remove) the cap dielectric layer 524, the base top layer spacers 120, the thin oxide layer 215, and the base bottom spacers 110. A second etch leaves voids in place of the dummy layer 115. The thin oxide layer 215 is removed.

[0120] The extrinsic base layer 650 is epitaxially grown on the intrinsic base 350, filling the void left by the removal of the dummy layer 115. An ILD 750 is deposited.

[0121] For details regarding the materials used and process steps performed to create structure 1600, see the description of Figures 2-7.

[0122] FIG. 17 is a cross-sectional view of a common-emitter circuit embodiment of a vertical BJT with a stacked vertical collector resistor 1700 including external contacts.

[0123] Starting with structure 1600, base mask 450 is removed and collector mask 850 is deposited. Collector cavity 925 is formed and collector 1050 is epitaxially grown. Collector mask 850 is then removed. Dummy contact layer 1640B is removed and a silicide, typically 1740, is formed. Metal contact layer 1740B replaces the void left by the removed dummy contact layer 1640B, and external contacts 1725 / 1750 / 1775 / 1805 are formed.

[0124] The base contact 1725 passes through the cap dielectric layer 524, the resistor top spacer 137A, the resistor dielectric layer 135B, the resistor bottom spacer 132B, the metal contact layer 1740B, and the base top layer spacer 120 to contact the extrinsic base layer 650 and the base 350. Note that an insulating layer 1730 is first deposited in the via / trench containing the base contact 1725 to prevent the base contact 1725 from electrically shorting to the metal contact layer 1740B.

[0125] Collector contact 1750 directly contacts collector 1050. Output contact 1775 contacts metal contact layer 1740B.

[0126] For details of the materials and process steps used, please refer to the descriptions of Figures 8-12.

[0127] FIG. 18A is a cross-sectional view of a common-emitter circuit embodiment of a vertical BJT with a stacked collector resistor 1800.

[0128] Contacts 1725 / 1750 / 1775 are made as described above.

[0129] FIG. 18B is a top view of a common-emitter circuit embodiment of a vertical BJT with stacked emitter resistor 1850 shown in FIG. 18A.

[0130] In some embodiments, collector contact 1750 can be a single contact or multiple contacts 1750, as shown. In some embodiments, base contact 1725 is multiple contacts 1725 on one side of structure 1800 / 1850, as shown, and output contact 1775 is multiple contacts 1775 on another side of structure 1800 / 1850. In some embodiments, emitter contact 1805 is multiple contacts on the front or back side or both of structure 1800 / 1850, connecting to emitter layer 105, as shown in top view 1850 but not visible in cross-sectional view 1800.

[0131] FIG. 19 is a circuit diagram of a common-emitter circuit embodiment of a vertical BJT with a stacked collector resistor 1900.

[0132] The circuit input Vin is the external base connection 1725, and the circuit output Vout is the external connection 1775. In this circuit, the external emitter connection 1805 is connected to ground (or alternatively to an emitter supply voltage such as Vss). The collector resistor Rc 1625 is connected by 1750 to the collector supply voltage Vdd.

[0133] 20 is a cross-sectional view of an intermediate multi-layer stack structure 2000 used to form a bipolar junction transistor (BJT) and vertically stacked top / collector and bottom / emitter resistors in an emitter degeneration circuit embodiment. Adding emitter degeneration (i.e., R E Adding a rectifier (adding a rectifier) reduces the voltage gain but improves the linearity and stability of the circuit.

[0134] The layers in the emitter degeneration embodiment of the intermediate multi-layer stack structure 2000 are the same as those in the common-emitter embodiment 1500, except that a first / emitter resistor lower spacer 2032 and a first / emitter resistor dielectric layer 2035 are inserted between the emitter layer 105 and the three-layer dummy stack 110 / 115 / 120. The first / emitter resistor lower spacer 2032 is disposed on the emitter layer 105, and the first / emitter resistor dielectric layer 2035 is disposed on the first / emitter resistor layer spacer 2032. The first / emitter resistor dielectric layer 2035 becomes the emitter resistor Re.

[0135] The "three-layer dummy stack" 110 / 115 / 120 is deposited on the first resistor dielectric layer 2035. A dummy contact layer 140 is deposited on the three-layer dummy stack, e.g., on the base top spacer 120. The middle resistor substructure 132B / 135B / 137B is deposited on the dummy contact layer 140. A cap dielectric layer 24 is deposited on the middle resistor substructure 132B / 135B / 137B, e.g., on the resistor 1 for the material composition, thickness, and deposition method of these layers.

[0136] FIG. 21 is a cross-sectional view of the intermediate multi-layer stack structure used to form the bipolar junction transistor (BJT) and two vertically stacked resistors of the emitter degeneration circuit embodiment 2100 after the formation of the intrinsic base 350 and extrinsic base 650, the first / emitter resistor Re2 125, and the second / collector resistor Rc1 625.

[0137] The structure 2100 is formed by etching a trench 250 down to the base bottom spacer 110 and performing the steps of oxidizing the thin oxide layer 215 / 240. Etching of the trench 250 then continues until the emitter layer 105 is reached.

[0138] Next, trench 250 is filled with epitaxial growth in the following formation order: first / emitter resistor Re2 125, bottom doped epitaxy region 2130, intrinsic base 350, top doped epitaxy region 330, and second / collector resistor 1625. A base mask 450 is deposited.

[0139] A directional etch, for example a first base / collector directional etch, is performed using known chemistries to remove material not protected by the base mask 450. The first base / collector directional etch removes material below / selectively to the base bottom spacers 110.

[0140] In some embodiments, a dummy etch is then performed to remove remaining material of the dummy layer 115, but is selective to (does not substantially remove) the cap dielectric layer 524, the base top layer spacers 120, the thin oxide layer 215, and the base bottom spacers 110. A second etch leaves voids in place of the dummy layer 115. The thin oxide layer 215 is removed.

[0141] An extrinsic base layer 650 is epitaxially grown on the intrinsic base 350, filling the void left by the removal of the dummy layer 115. An ILD 750 is deposited.

[0142] For details of the materials used and process steps performed to create structure 2100, see the description of Figures 2-7.

[0143] In some embodiments, the materials and methods are the same for the first / emitter resistor Re2 125 and the second / collector resistor 1625. Furthermore, the materials and methods are the same for the bottom doped epitaxy region 2130 and the top doped epitaxy region 330. A silicide contact need not be formed on the bottom doped epitaxy region 2130.

[0144] FIG. 22A is a cross-sectional view of a vertical BJT emitter degeneration circuit embodiment 2200, complete with stacked first / emitter resistor Re2 125 and second / collector resistor Rc 1625, including external connections 1730 / 1750 / 1775 / 1805, metal contact layer 1740B, and silicide 1740.

[0145] Starting with structure 2100, base mask 450 is removed and collector mask 850 is deposited. Collector cavity 925 is formed and collector 1050 is deposited. Collector mask 850 is then removed, dummy contact layer 1640B is removed, and a silicide, typically 1740, is formed. Metal contact layer 1740B fills the void left by the removal of dummy contact layer 1640B, completing external contacts 1725 / 1750 / 1775 / 1805.

[0146] The base contact 1725 passes through the cap dielectric layer 524, the resistor upper spacer 137A, the resistor dielectric layer 135B, the resistor lower spacer 132B, the metal contact layer 1740B, and the base upper layer spacer 120 to contact the extrinsic base layer 650 and the base 350. Note that to prevent the base contact 1725 from electrically shorting to the metal contact layer 1740B, an insulating layer 1730 is first deposited in the via / trench containing the base contact 1725.

[0147] Collector contact 1750 directly contacts collector 1050. Output contact 1775 contacts metal contact layer 1740B.

[0148] For details of the materials used and method steps performed, see the descriptions of Figures 8-12.

[0149] FIG. 22B is a top view of a common-emitter circuit embodiment of a vertical BJT with stacked first / emitter resistor Re2 125 and second / collector resistor Rc1 625.

[0150] In some embodiments, collector contact 1750 can be a single contact or multiple contacts 1750, as shown. In some embodiments, base contact 1725 is multiple contacts 1725 on one side of structure 2200 / 2250, and output contact 1775 is multiple contacts 1775 on another side of structure 2200 / 2250, as shown. In some embodiments, emitter contact 1805 is multiple contacts on the front or back or both of structure 2200 / 2250 that connect to emitter layer 105, as shown in top view 2250 but not visible in cross-sectional view 2200.

[0151] FIG. 23 is a circuit diagram 2300 of a vertical BJT emitter degeneration circuit embodiment 2200 with stacked first / emitter resistor Re2 125 and second / collector resistor Rc1 625.

[0152] The circuit input Vin is the external base connection 1725 and the circuit output Vout is the external connection 1775. In this circuit, the external emitter connection 1805 is connected to ground (or the emitter supply voltage Vss). The collector resistor Rc 1625 is connected to the collector supply voltage Vdd by 1750.

[0153] FIG. 24 is a flow chart of a manufacturing process 2400 for a vertical BJT having one or more stacked resistors.

[0154] The process begins in step 2405 by creating an intermediate multi-layer stack 100 / 1500 / 2000 depending on the respective circuit embodiment being created, e.g., common collector, common emitter, or emitter degeneration circuit. See the descriptions of Figures 1, 15, and 20.

[0155] In step 2410, trench 250 is etched and epitaxial growth of layers within the trench forms first / emitter resistor Re2125, bottom doped epitaxy region 2130, intrinsic base 350, top doped epitaxy region 330, or second / collector resistor 1625, or a combination thereof. See the descriptions of Figures 2-3, 16, and 21, respectively.

[0156] In step 2415, dummy material is removed and replaced. For example, dummy contact layer 140 is removed and replaced with metal contact layer 340 / 1740B, and dummy layer 115 is removed and replaced with extrinsic base layer 650. See the descriptions of Figures 3A-7, 16, 21, and 22A.

[0157] Step 2420 grows extrinsic base 640 and deposits collector 1050. See descriptions of Figures 7-11, 17, and 22A.

[0158] In step 2425, external contacts are formed, see the descriptions of Figures 12, 13A, 13B, 17, 18A, 18B, 22A, and 22B.

[0159] The description of various embodiments of the present invention has been provided for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. For example, the semiconductor devices, structures, and methods disclosed in accordance with embodiments of the present invention can be employed in applications, hardware, or electronic systems, or combinations thereof. Hardware and systems suitable for implementing embodiments of the present invention may include, but are not limited to, personal computers, communication networks, e-commerce systems, portable communication devices (e.g., mobile phones and smartphones), solid-state media storage devices, expert and artificial intelligence systems, functional circuits, and the like. Systems and hardware incorporating semiconductor devices are contemplated embodiments of the present invention.

[0160] The terms used herein have been selected to explain the principles of embodiments and practical applications, or to describe technical improvements over technologies found in the marketplace, or to enable those skilled in the art to understand the embodiments disclosed herein. Devices, components, elements, features, apparatus, systems, structures, techniques, and methods described with different terms that perform substantially the same function, act in substantially the same way, have substantially the same application, or perform similar steps, or are combinations thereof, are contemplated as embodiments of the present invention.

Claims

1. A vertical bipolar junction transistor (VBJT), comprising: an emitter substructure having an emitter layer made of an emitter semiconductor; a collector made of a collector semiconductor; an intrinsic base made of either a lightly doped or a moderately doped semiconductor; one or more doped epitaxy regions made of a highly doped semiconductor; one or more resistors; Equipped with the intrinsic base, the doped epitaxy region, and the resistor are stacked together in a channel between the emitter layer and the collector; the emitter layer, the collector, the epitaxy region, and the resistor are of the same dopant type, while the intrinsic base is of a dopant type opposite to the dopant type; the doped epitaxy region is made of a highly doped semiconductor and the resistor is made of a lightly or moderately doped semiconductor; the doped epitaxy region is between the resistor and the intrinsic base; The vertical bipolar junction transistor (VBJT).

2. The doped epitaxy region is 4×10 ２０ cm －３ ~2.5 x 10 ２１ cm －３ 2. The VBJT of claim 1 having a doping concentration of

3. The emitter semiconductor is 4×10 ２０ cm －３ ~2.5 x 10 ２１ cm －３ 2. The VBJT of claim 1, wherein the VBJT is doped with an n-type dopant at an emitter dopant concentration of 0.1 to 0.

5.

4. 2. The VBJT of claim 1, wherein an extrinsic base made from an extrinsic base semiconductor surrounds the intrinsic base.

5. A VBJT as described in claim 1, further comprising one or more metal contact layers, each metal contact layer encompassing one or more of the doped epitaxy regions, and one or more of the metal contact layers connected to an external connection.

6. 2. The VBJT of claim 1, wherein a resistor dielectric thickness of said resistors determines a resistor length of each of said resistors.

7. 7. The VBJT of claim 6, wherein the resistor length is between 5 nm and 100 nm.

8. The resistor is 1x10 １７ cm －３ ~1x10 １９ cm －３ 2. The VBJT of claim 1, having a resistor dopant concentration of 9. The VBJT of claim 1, wherein the resistor has a resistor dopant having a resistor dopant concentration of 1×10 17 cm −3 to 1×10 19 cm −3 and is made from one of materials selected from silicon, germanium, and silicon-germanium.

10. The VBJT of claim 1 , wherein the resistor further comprises carbon doping.

11. The carbon doping is 1×10 １７ cm －３ ~8x10 ２０ cm －３ 11. The VBJT of claim 10, having a carbon doping concentration of

12. 2. The VBJT of claim 1, wherein the doped epitaxy region is a bottom doped epitaxy region, the resistor is an emitter resistor, the emitter resistor is disposed on the emitter layer, the bottom doped epitaxy region is disposed on the emitter resistor, and the intrinsic base is disposed on the emitter resistor, forming a common collector VBJT circuit.

13. 2. The VBJT of claim 1, wherein the doped epitaxy region is a top doped epitaxy region, the resistor is a collector resistor, the intrinsic base is disposed on the emitter layer, the top doped epitaxy region is disposed on the intrinsic base, and the collector resistor is disposed on the top doped epitaxy region, forming a common-emitter VBJT circuit.

14. 2. The VBJT of claim 1, wherein the one or more doped epitaxy regions include a bottom doped epitaxy region and a top doped epitaxy region, the one or more resistors include an emitter resistor and a collector resistor, the emitter resistor disposed on the emitter layer, the bottom doped epitaxy region disposed on an emitter resistor dielectric, the intrinsic base disposed on the bottom doped epitaxy region, the top doped epitaxy region disposed on the intrinsic base, and the collector resistor disposed on the top doped epitaxy region, forming an emitter degeneration circuit VBJT circuit.

15. A vertical bipolar junction transistor (VBJT) emitter degeneration circuit, comprising: an emitter substructure having an emitter layer made of an emitter semiconductor; an emitter resistor disposed on the emitter layer; a bottom doped epitaxy region disposed over the emitter resistor; an intrinsic base disposed on the bottom doped epitaxy region and made of either an undoped or lightly doped semiconductor; a top doped epitaxy region disposed on the intrinsic base; a collector resistor disposed on the top doped epitaxy region; a collector disposed on the collector resistor and made of a collector semiconductor; Equipped with the emitter resistor, the bottom doped epitaxy region, the intrinsic base, the top doped epitaxy region, and the collector resistor are stacked in a channel between the emitter layer and the collector; the emitter layer, the emitter resistor, the collector resistor, the collector, and the top and bottom doped epitaxy regions are of the same dopant type, while the intrinsic base is of a dopant type opposite to the dopant type; the bottom doped epitaxy region and the top doped epitaxy region are made of highly doped semiconductors, and the emitter resistor and the collector resistor are made of lightly or moderately doped semiconductors. The vertical bipolar junction transistor (VBJT) emitter degeneration circuit.

16. The VBJT emitter degeneration circuit of claim 15, wherein the emitter resistor and the collector resistor further comprise carbon doping.

17. A method for fabricating a vertical bipolar junction transistor (VBJT) circuit, comprising: creating an intermediate multi-layer stack comprising an emitter sub-structure, the emitter sub-structure having an emitter layer, and depositing one or more intermediate resistor sub-structures, a dummy contact layer, and a three-layer dummy stack on the emitter layer; etching a trench in the intermediate multi-layer stack down to a surface of the emitter layer; epitaxially growing in the trench one or more resistors, each resistor surrounded by one resistor dielectric layer of a respective intermediate resistor sub-structure, a doped epitaxy region surrounded by the dummy contact layer, and an intrinsic base surrounded by a dummy layer of the three-layer dummy stack; removing the dummy contact layer and replacing the dummy contact layer with depositing a metal contact layer; removing the dummy layer and replacing the dummy layer with an epitaxially grown extrinsic base layer; depositing a collector on the intrinsic base; Including, the emitter layer, the collector, the epitaxy region, and the resistor are of the same dopant type, while the intrinsic base is of a dopant type opposite to the dopant type; the doped epitaxy region is made of a highly doped semiconductor and the resistor is made of a lightly or moderately doped semiconductor; the doped epitaxy region is between the resistor and the intrinsic base; The method.

18. the middle resistor substructure being an emitter resistor substructure; the dummy contact layer; the three-layer dummy stack 18. The method of claim 17, wherein:

19. the three-layer dummy stack; the dummy contact layer; the middle resistor substructure being a collector resistor substructure; 18. The method of claim 17, wherein:

20. one of the intermediate resistor substructures being a first emitter resistor substructure; the three-layer dummy stack; the dummy contact layer; one of the intermediate resistor substructures being a second collector resistor substructure 18. The method of claim 17, wherein:

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