Substrate and manufacturing method thereof

Abstract

To provide a substrate that has entirely uniformly improved adhesive strength to a glass core and can transmit signals efficiently even when high-frequency power is applied and embodies an electrically conductive layer, and a method for manufacturing the same.SOLUTION: A substrate 100 includes a glass core 10 having an upper surface 11. The upper surface 11 of the glass core has a bonding roughness index Rq*k value which is in the range from 3.5 nm to 150 nm according to the following formula. Rq×k=Rq×Rku2. In the above formula, the Rq value is a root mean square deviation (nm in unit) and the Rku value is kurtosis. Such a substrate can embody an electrically conductive layer that has substantially uniformly improved bonding strength to a glass core and can efficiently transmit signals even when high frequency power is applied.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The embodiment relates to a substrate and a manufacturing method thereof. [Background technology]

[0002] In the production of electronic components, the process of creating circuits on semiconductor wafers is called the front-end process (FE), and the process of assembling the wafers so that they can be used in actual products is called the back-end process (BE), which includes the packaging process.

[0003] The four core technologies of the semiconductor industry that have enabled the rapid development of electronic products in recent years are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. Semiconductor technology has evolved into various forms, such as nano-level line widths below microns, more than 10 million cells, high-speed operation, and high heat dissipation, but the technology to perfectly package this has not been supported. As a result, the electrical performance of semiconductors is sometimes determined by packaging technology and the resulting electrical connections rather than the performance of the semiconductor technology itself.

[0004] Ceramic or resin is used as a material for the packaging substrate. Ceramic substrates have high resistance or high dielectric constant, making it difficult to mount high-performance, high-frequency semiconductor devices. Resin substrates can mount relatively high-performance, high-frequency semiconductor devices, but there is a limit to how much the wiring pitch can be reduced.

[0005] Recently, research has been conducted into the application of silicon and glass to high-end packaging substrates. By forming through-holes in silicon or glass substrates and filling these with conductive materials, the length of the wiring between the device and the motherboard can be shortened, resulting in excellent electrical characteristics. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent No. 5665988 [Patent Document 2] International Patent Publication No. 2018 / 221379 Summary of the Invention [Problem to be solved by the invention]

[0007] The purpose of the embodiment is to provide a substrate and a manufacturing method thereof that can realize an electrically conductive layer that has an improved adhesive strength that is uniform throughout the glass core and can efficiently transmit signals even when high-frequency power is applied. [Means for solving the problem]

[0008] A substrate according to one embodiment of the present disclosure includes a glass core having an upper surface.

[0009] The bonding roughness index R of the upper surface of the glass core is expressed by the following formula 1. q*k The value is 3.5 nm to 150 nm.

[0010] [Formula 1] JPEG0007725664000001.jpg732

[0011] In the above formula 1, the Rq value is the root mean square deviation (unit: nm), and the Rku value is the kurtosis.

[0012] The Rq value may be 0.25 nm to 5 nm.

[0013] The Rku value may be 3 or greater.

[0014] The upper surface of the glass core can include a total of three arbitrarily selected measurement areas.

[0015] The standard deviation of the Rq values of each measurement region may be 0.15 nm or less.

[0016] The standard deviation of the Rku values in each of the measurement regions may be 1 or less.

[0017] The substrate can include an electrically conductive layer disposed on the glass core.

[0018] The electrically conductive layer can include a seed layer and a conductive layer disposed on the seed layer.

[0019] The seed layer may have a thickness of 50 nm to 1500 nm.

[0020] The electrically conductive layer may have a patterned shape.

[0021] The width of the electrically conductive layer may be 1 μm to 5 μm.

[0022] The electrically conductive layer may have a thickness of 1 μm to 5 μm.

[0023] The electrically conductive layer may include a first electrically conductive layer formed in contact with a surface of the glass core.

[0024] When observed in cross section of the first electrically conductive layer, the Rz value, which is the maximum height roughness of the interface formed between the first electrically conductive layer and the glass core, may be 5 nm to 200 nm.

[0025] The bonding strength between the first electrically conductive layer and the glass core may be 0.25 kgf or more as measured by a 180° peel test.

[0026] The substrate may have a semiconductor packaging application.

[0027] A method for manufacturing a substrate according to another embodiment of the present specification includes a preparation step of providing a base glass plate, and a roughening step of providing a substrate including a glass core formed by roughening the top surface of the base glass plate.

[0028] The glass core has an upper surface.

[0029] The bonding roughness index R of the upper surface of the glass core is expressed by the following formula 1. q*k The value is 3.5 nm to 150 nm.

[0030] [Formula 1] JPEG0007725664000002.jpg732

[0031] In the above formula 1, the Rq value is the root mean square deviation (unit: nm), and the Rku value is the kurtosis.

[0032] The roughening step may include plasma treating the upper surface of the base glass plate to form a glass core. [Effects of the Invention]

[0033] In the case of the substrate of the embodiment, an electrically conductive layer having substantially uniformly improved adhesion strength to the glass core can be realized, and the electrically conductive layer can efficiently transmit signals even when high frequency power is applied. [Brief explanation of the drawings]

[0034] [Figure 1] FIG. 1 is a plan view illustrating a substrate according to an embodiment of the present specification. [Figure 2] FIG. 10 is a plan view illustrating a substrate according to another embodiment of the present specification. [Figure 3] FIG. 10 is a plan view illustrating a substrate according to still another embodiment of the present specification. [Figure 4] FIG. 10 is a plan view illustrating a substrate according to still another embodiment of the present specification. BEST MODE FOR CARRYING OUT THE INVENTION

[0035] The present invention will now be described in detail with reference to the accompanying drawings so that those skilled in the art can easily understand the present invention. However, the present invention may be embodied in various different forms and is not limited to the embodiments described herein. The same reference numerals are used throughout the specification to refer to similar parts.

[0036] Throughout this specification, the term "combinations thereof" contained in a Markush form phrase means a mixture or combination of one or more selected from the group of elements set forth in the Markush form phrase, and means including one or more selected from the group of elements.

[0037] Throughout this specification, terms such as "first," "second," or "A," "B" are used to distinguish between identical terms, and singular expressions include plural expressions unless the context clearly indicates otherwise.

[0038] In this specification, the term "-" may mean that the compound includes a compound corresponding to "-" or a derivative of "-".

[0039] In this specification, the term "B is located on A" means that B is located on A in direct contact with A, or that B is located on A with another layer located therebetween, and is not to be interpreted as being limited to B being located in contact with the surface of A.

[0040] In this specification, the expression "B is linked to A" means that A and B are directly linked or that A and B are linked via another component therebetween, and unless otherwise specified, it is not to be interpreted as being limited to A and B being directly linked.

[0041] In this specification, unless otherwise specified, the singular expression is to be construed as including the singular or plural as the context requires.

[0042] In this specification, the shape, relative size, angle, etc. of each component in the drawings are illustrative and may be exaggerated for the purpose of explanation, and the rights should not be interpreted as being limited to the drawings.

[0043] In this specification, "A and B are adjacent" means that A and B are adjacent to each other, or A and B are not adjacent to each other but are located close to each other. In this specification, the expression "A and B are adjacent to each other" is not interpreted as being limited to A and B being adjacent to each other unless otherwise specified.

[0044] In this specification, high frequency means a frequency of about 1 GHz to about 300 GHz. Specifically, it may mean a frequency of about 1 GHz to about 30 GHz, or may mean a frequency of about 1 GHz to about 15 GHz.

[0045] In this specification, unless otherwise specified, a fine line means a line having a width of 5 μm or less, and illustratively means a line having a width of 1 to 4 μm or less.

[0046] The inventors of the embodiment confirmed that by controlling the surface roughness characteristics of the glass core, it is possible to realize an electrically conductive layer that has an overall uniformly improved bonding strength to the surface of the glass core and can efficiently transmit signals by suppressing excessive increases in the resistance of the electrically conductive layer when high-frequency power is applied, and thus completed the embodiment.

[0047] The specific examples will be described below.

[0048] 1 is a plan view illustrating a substrate according to an embodiment of the present disclosure, and the substrate of the embodiment will be described with reference to FIG.

[0049] Glass Core Substrate 100 according to one embodiment of the present disclosure includes a glass core 10 having a top surface 11 .

[0050] The glass core 10 serves as a support for the substrate 100. The glass core 10 is separated from a core distribution layer (not shown) or bumps (not shown) disposed above or below the glass core 10.

[0051] In the embodiment, by using a core made of a glass material, it is possible to suppress the generation of parasitic elements and power loss in the core due to the application of high frequency power.

[0052] The material of the glass core 10 may be, for example, alkali borosilicate, non-alkali borosilicate, non-alkali alkaline earth borosilicate, or the like, and any sheet glass material suitable for electronic components may be used.

[0053] The thickness of the glass core 10 may be 50 μm or more. The thickness may be 100 μm or more. The thickness may be 250 μm or more. The thickness may be 400 μm or more. The thickness may be 500 μm or more. The thickness may be 3000 μm or less. The thickness may be 2000 μm or less. The thickness may be 1000 μm or less. When a glass core 10 having such a thickness is used, it can be highly usable as a core for semiconductor packaging.

[0054] The joint roughness index R of the upper surface 11 of the glass core is expressed by the following formula 1. q*k The value is 3.5 nm to 150 nm.

[0055] [Formula 1] JPEG0007725664000003.jpg732

[0056] In the above formula 1, the Rq value is the root mean square deviation (unit: nm), and the Rku value is the kurtosis.

[0057] To improve the bonding strength of the electrically conductive layer formed on the upper surface 11 of the glass core, it may be possible to simply increase the roughness of the upper surface 11 of the glass core. However, this may result in a problem in which the deviation in the roughness characteristics of the upper surface 11 of the glass core exceeds a certain level. If the electrically conductive layer is formed on such an upper surface 11, the electrically conductive layer may exhibit an overall non-uniform bonding strength. This may result in a decrease in the peel resistance of the electrically conductive layer and the electrical reliability of the substrate.

[0058] Furthermore, if an electrically conductive layer is formed on the upper surface 11 of the glass core having high roughness, the resistance of the electrically conductive layer formed on the core may become excessively high in an environment where high-frequency power is supplied. Specifically, when high-frequency power is applied to the substrate 100 to improve the signal transmission speed and amount, a skin effect may occur in the electrically conductive layer, and current may flow concentratedly in the surface portion of the electrically conductive layer.

[0059] When an electrically conductive layer is formed on the upper surface 11 of a glass core with excessively high roughness, at least a portion of the cross-sectional profile of the electrically conductive layer may have a rough and irregular shape. When a high-frequency current flows through an electrically conductive layer with such a shape, the area through which the current can actually flow within the electrically conductive layer is reduced, and the resistance of the electrically conductive layer may become significantly higher. The increase in the resistance of the electrically conductive layer due to the skin effect may become even more pronounced as the electrically conductive layer becomes thinner.

[0060] In the embodiment, the bonding roughness index R q*k In this case, the roughness of the upper surface 11 of the glass core 10 is not excessively increased, and a more stable interlocking structure can be formed between the glass core 10 and the electrically conductive layer over the entire upper surface 11 of the glass core. This effectively improves the bonding strength throughout the electrically conductive layer. In addition, the substrate 100 having the above characteristics allows the electrically conductive layer to exhibit stable resistance characteristics even when high-frequency power is applied.

[0061] R q*k The value is measured by the following method.

[0062] In three measurement areas (not shown), each 5 μm wide and 5 μm long, randomly selected on the top surface 11 of the glass core, the root mean square deviation (Rq) and the kurtosis (Rku) are measured in non-contact mode using an atomic force microscope according to the method specified in ISO 4287. The measurement areas are selected so that they do not overlap each other. For example, the atomic force microscope may be an XE-100 model manufactured by Park Systems.

[0063] The average values of the Rq and Rku values for each measurement area are taken as the Rq and Rku values for the upper surface of the glass core. q*k Calculate the value.

[0064] R of the top surface of the glass core 11 q*k The value can be 3.5 nm to 150 nm. q*k The value of R may be 6 nm or more. q*k The value of R may be 10 nm or more. q*k The value of R may be 15 nm or more. q*k The value of R may be 20 nm or more. q*k The value of R may be 30 nm or more. q*k The value may be 35 nm or more. q*k The value of R may be 120 nm or less. q*k The value of R may be 100 nm or less. q*k The value may be 70 nm or less. In this case, when forming a thinned electrically conductive layer on the glass core 10, the adhesive strength of the electrically conductive layer to the glass core 10 can be substantially uniformly improved over the entire upper surface 11 of the glass core, and the resistance of the electrically conductive layer can be prevented from becoming excessively high when high-frequency power is applied.

[0065] The Rq value of the upper surface 11 of the glass core may be 0.25 nm to 5 nm. The Rq value may be 0.3 nm or more. The Rq value may be 0.5 nm or more. The Rq value may be 1 nm or more. The Rq value may be 1.5 nm or more. The Rq value may be 3 nm or less. In this case, an electrically conductive layer that is stably fixed on the glass core 10 and whose resistance characteristics do not increase excessively even when high-frequency power is applied can be implemented on the glass core 10.

[0066] The Rku value of the top surface 11 of the glass core may be 3 or more. The Rku value may be 4 or more. The Rku value may be 5 or more. The Rku value may be 7 or more. The Rku value may be 15 or less.

[0067] In this case, a strong bond structure can be formed between the upper surface of the glass core and the electrically conductive layer, thereby effectively improving the bonding strength of the electrically conductive layer to the surface without excessively roughening the surface of the glass core.

[0068] The embodiment may help to ensure that the adhesive strength and resistance characteristics of the electrically conductive layer formed on the glass core 10 are uniform across the entire upper surface 11 of the glass core by controlling the deviation of the roughness characteristics of multiple different regions.

[0069] The upper surface 11 of the glass core can include a total of three arbitrarily selected measurement areas.

[0070] The measurement area is located within the upper surface of the glass core and is an area of 5 μm in width and 5 μm in length. A total of three measurement areas can be selected so that they do not overlap with each other.

[0071] The standard deviation of the Rq values of each measurement region may be 0.15 nm or less.

[0072] The standard deviation of the Rku values in each of the measurement regions may be 1 or less.

[0073] The standard deviation is the sample standard deviation.

[0074] The standard deviation of the Rq values in each measurement region may be 0.15 nm or less. The standard deviation may be 0.1 nm or less. The standard deviation may be 0.08 nm or less. The standard deviation may be 0.05 nm or less. The standard deviation may be 0.001 nm or more.

[0075] The standard deviation of the Rku values in each measurement region may be 1 or less. The standard deviation may be 0.8 or less. The standard deviation may be 0.6 or less. The standard deviation may be 0.4 or less. The standard deviation may be 0.1 or more.

[0076] In such a case, the roughness characteristics can be adjusted uniformly across the top surface 11 of the glass core.

[0077] The lower surface of the glass core may have the same roughness characteristics as the upper surface 11 of the glass core. In this case, an electrically conductive layer having a uniformly improved bonding strength may be formed on the lower surface of the glass core, and the electrically conductive layer may transmit signals efficiently by applying high frequency power.

[0078] The description of the roughness characteristics of the lower surface of the glass core is omitted here because it overlaps with the above description.

[0079] Core Distribution Layer 2 is a plan view illustrating a substrate according to another embodiment of the present disclosure, and the substrate of the embodiment will be described with reference to FIG.

[0080] The substrate 100 includes a glass core 10 having an upper surface 11. The specific configuration of the substrate 100 is the same as that described above with reference to Fig. 1. The following description will focus on the differences.

[0081] The substrate of the embodied example may include an electrically conductive layer 20 disposed on the glass core. The electrically conductive layer 20 may have a patterned shape. The electrically conductive layer 20 may be formed above and / or below the glass core 10 and may function to transmit signals.

[0082] The width of the electrically conductive layer 20 may be 1 μm to 5 μm. The width may be 4.5 μm or less. The width may be 4 μm or less.

[0083] The thickness of the electrically conductive layer 20 may be 1 μm to 5 μm. The thickness may be 4.5 μm or less. The thickness may be 4 μm or less.

[0084] In this case, a high density pattern of the electrically conductive layer 20 can be implemented on the substrate 100, which can help the electrically conductive layer 20 to have stable resistance characteristics at high frequency currents.

[0085] 3 is a plan view illustrating a substrate according to still another embodiment of the present disclosure, and the substrate of the embodiment will be described with reference to FIG.

[0086] The substrate 100 includes a glass core 10 having an upper surface 11. The specific configuration of the substrate 100 is the same as that described above with reference to Figures 1 and 2. The following description will focus on the differences.

[0087] The electrically conductive layer 20 may include a seed layer 21 and a conductive layer 22 disposed on the seed layer 21 .

[0088] The seed layer 21 can exhibit a certain level or more of bonding strength to the surface to be bonded (particularly, the upper surface 11 of the glass core). The conductive layer 22 can be stably bonded to the surface of the glass core 10 via the seed layer 21.

[0089] The seed layer 21 may include an element different from the metal element applied to the conductive layer. The seed layer 21 may further include the metal element applied to the conductive layer and a metal element different from the metal element applied to the conductive layer. The seed layer 21 may include a first seed layer (not shown) including an element different from the metal element applied to the conductive layer, and a second seed layer (not shown) disposed on the first seed layer and including the same element as the metal element applied to the conductive layer. For example, the first seed layer may include a material such as titanium, chromium, or nickel, and the second seed layer may include a material such as copper, nickel, aluminum, gold, or silver.

[0090] At least a portion of the seed layer 21 may be formed through a sputtering process. The seed layer 21 may help facilitate the formation of the conductive layer 22 on the glass core 10.

[0091] In the embodiment, by adjusting the thickness of the seed layer 21, a structure can be formed in which the upper surface 11 of the glass core with controlled roughness characteristics and the seed layer 21 are stably interlocked.

[0092] The thickness of the seed layer 21 may be 50 nm to 1500 nm. The thickness may be 80 nm or more. The thickness may be 100 nm or more. The thickness may be 150 nm or more. The thickness may be 200 nm or more. The thickness may be 250 nm or more. The thickness may be 300 nm or more. The thickness may be 1200 nm or less. The thickness may be 1000 nm or less.

[0093] In such a case, the seed layer 21 may help ensure that the electrically conductive layer 20 has good adhesion, allowing the electrically conductive layer 20 to be formed efficiently.

[0094] The conductive layer 22 may be formed on the seed layer 21 through a plating process. An electrically conductive material may be used as the material of the conductive layer 22. For example, the conductive layer 22 may include at least one of copper, nickel, aluminum, gold, and silver.

[0095] 4 is a plan view illustrating a substrate according to still another embodiment of the present disclosure. The substrate of the embodiment will be described with reference to FIG.

[0096] The substrate 100 includes a glass core 10 having an upper surface 11. The specific configuration of the substrate 100 is the same as that described above with reference to Figures 1 to 3. The following description will focus on the differences.

[0097] The substrate 100 can include a core distribution layer 50 disposed on the glass core 10. The core distribution layer 50 can include an electrically conductive layer 20 and an insulating layer 30 surrounding at least a portion of the electrically conductive layer 20.

[0098] The core distribution layer 50 may include a mixture of insulating layers 30 and electrically conductive layers 20. The core distribution layer 50 may be formed such that electrically conductive layers 20 having predetermined positions and shapes are embedded within the insulating layers 30. The electrically conductive layers 20 may be formed as thin wires on at least a portion of the core distribution layer 50.

[0099] The core distribution layer 50 may be formed by repeatedly forming and removing the insulating layer 30 and the electrically conductive layer 20 .

[0100] The insulating layer 30 may be any material that can be used as an insulating layer for semiconductor devices and packaging substrates. For example, an epoxy resin containing a filler may be used as the insulating layer 30. For example, the insulating layer 30 may be formed using a build-up layer material such as Ajinomoto Build-up Film (ABF) from Ajinomoto Co., Inc., or an undercoat material, but is not limited thereto.

[0101] The insulating layer 30 can be formed by laminating an uncured or semi-cured insulating film and then curing it.

[0102] Electrically conductive layer 20 can include a first electrically conductive layer 25 disposed in contact with the surface of glass core 10. Electrically conductive layer 20 can include a second electrically conductive layer 26 not in contact with the surface of glass core 10.

[0103] When observed in cross section, first electrically conductive layer 25 may have an Rz value, which is the maximum height roughness, of interface L formed between the first electrically conductive layer and the glass core, of 5 nm to 200 nm.

[0104] In this embodiment, the roughness characteristics of the interface L formed between the first electrically conductive layer and the glass core can be controlled, thereby stably controlling the resistance and heat generation characteristics of the first electrically conductive layer 25 due to the skin effect, and further improving the bonding strength of the first electrically conductive layer 25 to the glass core 10 due to the anchor effect.

[0105] The Rz value of the interface L is measured by the following method.

[0106] A cross section of the first electrically conductive layer 25 is photographed using a TEM (Transmission Electron Microscope). The cross section of the first electrically conductive layer 25 refers to a cross section in a direction perpendicular to the top surface 11 of the glass core. When the first electrically conductive layer 25 has a patterned shape, the cross section of the first electrically conductive layer 25 refers to a cross section in a direction perpendicular to the top surface 11 of the glass core and perpendicular to the longitudinal direction of the first electrically conductive layer 25. From the cross-sectional image of the first electrically conductive layer 25, a profile of the interface L formed between the first electrically conductive layer and the glass core is traced, and then the Rz value, which is the maximum height roughness of the interface L, is calculated from the traced profile.

[0107] The Rz value is measured according to the method specified in ISO 4287. Specifically, the Rz value is the sum of the height value of the highest peak and the depth value of the deepest valley in the tracing profile of the interface L.

[0108] The Rz value of the interface L formed between the first electrically conductive layer and the glass core may be 200 nm or less. The Rz value may be 180 nm or less. The Rz value may be 150 nm or less. The Rz value may be 100 nm or less. The Rz value may be 5 nm or more. The Rz value may be 10 nm or more. In this case, a first electrically conductive layer 25 having excellent peel resistance and suitable for application of high-frequency power can be realized on the surface of the glass core 10.

[0109] In the embodiment, the peel resistance of the first electrically conductive layer 25 can be improved by controlling the adhesive strength of the first electrically conductive layer 25 to the surface of the glass core to a certain level or more.

[0110] The adhesive strength between the first electrically conductive layer 25 and the glass core 10 measured by a 180° peel test is measured using a bond tester. When measuring the adhesive strength, the measurement speed (peel speed) is set to 10 mm / s and the measurement distance (peel distance) is set to 70 mm. For example, the adhesive strength can be measured using a Condor Sigma bond tester manufactured by XYZ TEC.

[0111] The bonding strength between the first electrically conductive layer 25 and the glass core 10 measured by a 180° peel test may be 0.25 kgf or more. The bonding strength may be 0.3 kgf or more. The bonding strength may be 0.4 kgf or more. The bonding strength may be 5 kgf or less. The bonding strength may be 3 kgf or less. In such cases, the electrically conductive layer 20 may be stably bonded to the surface of the glass core 10.

[0112] Other components in the packaging substrate The glass core 10 may include a core via (not shown) penetrating the glass core 10 in the thickness direction. The core distribution layer 50 may be formed on the upper surface 11 of the glass core and in the core via. The core distribution layer 50 may be formed on the upper surface 11 of the glass core, below the lower surface 12 of the glass core, and in the core via. In this case, the core distribution layer 50 can connect the upper surface 11 and the lower surface 12 of the glass core over a very short distance. In addition, electrical signals between elements disposed on the upper part of the substrate 100 and a motherboard disposed below the substrate 100 can be transmitted more quickly, and signal loss can be reduced.

[0113] The core via may include an internal space and a side surface surrounding the internal space. In the core via, the electrically conductive layer may be formed in contact with the side surface of the core via. The electrically conductive layer may be formed to fill the internal space of the core via.

[0114] The core via may be formed by processing a predetermined region in the glass core 10. Specifically, the core via may be formed by etching the glass core 10 using a physical and / or chemical method. For example, the core via may be formed by forming a defect in the surface of the glass core 10 using a laser or the like, followed by chemical etching, laser etching, or the like.

[0115] A cavity region (not shown) for accommodating an element may be disposed in the glass core 10. The cavity region may include a receiving portion, which is a space formed by recessing a portion of the glass core 10. The receiving portion may be formed by penetrating the glass core 10 from top to bottom. The receiving portion may be formed by recessing a portion of the upper or lower portion of the glass core 10.

[0116] An element can be placed in the housing. The element may be a semiconductor element such as a CPU, GPU, or memory chip, or may be a capacitor element, a transistor element, an impedance element, or other module. In other words, any semiconductor element that can be mounted on a semiconductor device can be used as the element without any restrictions.

[0117] The substrate 100 may further include a top layer (not shown) on the core distribution layer 50 disposed on the glass core 10 .

[0118] The upper layer may include an upper distribution layer and an upper connection layer disposed on the upper distribution layer. The elements disposed on the substrate 100 may be electrically connected to the substrate 100 through the upper connection layer.

[0119] The upper distribution layer may include an electrically conductive layer and an insulating layer surrounding at least a portion of the electrically conductive layer. The electrically conductive layer and insulating layer of the upper distribution layer may be made of the same materials as the electrically conductive layer and insulating layer of the core distribution layer, respectively. The upper distribution layer may electrically connect the element and the core distribution layer.

[0120] The substrate 100 may further include a bottom layer (not shown) below the core distribution layer (not shown) disposed on the lower surface 12 side of the glass core.

[0121] The lower layer may include a lower distribution layer and a board connection portion disposed below the lower distribution layer. A main board disposed below the substrate 100 may be electrically connected to the substrate 100 via the board connection portion. The core distribution layer may be electrically connected to the main board via the lower layer.

[0122] The lower distribution layer may include an electrically conductive layer and an insulating layer surrounding at least a portion of the electrically conductive layer, and the electrically conductive layer and insulating layer of the lower distribution layer may be made of the same materials as the electrically conductive layer and insulating layer of the core distribution layer, respectively.

[0123] The substrate 100 can be used for semiconductor packaging, for example, to mount a semiconductor element, protect the semiconductor, and provide electrical connection between the element and a main board.

[0124] Semiconductor Package A semiconductor package according to yet another embodiment of the present disclosure includes a substrate 100 and a main board (not shown) electrically connected to the substrate.

[0125] The substrate 100 can be mounted on a main board and electrically connected to the main board, and the main board is not limited as long as it is one that is commonly used in the field of semiconductor devices.

[0126] The description of the substrate 100 will be omitted as it overlaps with the above description.

[0127] Substrate manufacturing method A method for manufacturing a substrate according to yet another embodiment of the present specification includes a preparation step of providing a base glass plate, and a roughening step of providing a substrate including a glass core formed by roughening the top surface of the base glass plate.

[0128] The glass core has an upper surface, and the upper surface of the glass core has a bonding roughness index R q*k The value is 3.5 nm to 150 nm.

[0129] [Formula 1] JPEG0007725664000004.jpg732

[0130] In the above formula 1, the Rq value is the root mean square deviation (unit: nm), and the Rku value is the kurtosis.

[0131] In a preparation step, the elementary glass sheet can be processed to provide a glass core.

[0132] The base glass plate may be any plate glass material used for electronic components. For example, an alkali borosilicate glass plate, an alkali-free borosilicate glass plate, an alkali-free alkaline earth borosilicate glass plate, etc. Commercially available products manufactured by manufacturers such as Corning, Schott, and AGC may be used as the base glass plate.

[0133] In the embodiment, the roughening step may include a process of plasma-treating the upper surface of the base glass sheet to form a glass core. The roughening step may include a process of plasma-treating the upper surface of the base glass sheet using an inert gas to form a glass core. Through this, a glass core having an upper surface whose roughness characteristics are adjusted so that the roughness is not excessively high and has a degree of asymmetry within a predetermined range in the embodiment may be provided.

[0134] The inert gas may be any one selected from the group consisting of helium gas, argon gas, xenon gas, krypton gas, and combinations thereof. The inert gas may be argon gas. In this case, it may be useful to form a glass core having the desired surface roughness characteristics in the embodiment while suppressing chemical modification of the upper surface of the base glass sheet in the roughening step.

[0135] In the roughening step, the atmospheric pressure may be 100 mTorr or less. The atmospheric pressure may be 80 mTorr or less. The atmospheric pressure may be 50 mTorr or less. The atmospheric pressure may be 30 mTorr or less. The atmospheric pressure may be 1 mTorr or more. In such cases, in the roughening step, the ionized inert gas collides with the surface to be roughened without excessive interference, making it easy to adjust the roughness characteristics of the upper surface of the glass core.

[0136] In the roughening step, the flow rate of the introduced inert gas may be 100 sccm or more. The flow rate may be 150 sccm or more. The flow rate may be 200 sccm or more. The flow rate may be 1000 sccm or less. In such cases, a sufficient amount of ionized inert gas can impinge on the upper surface of the base glass plate at an appropriately adjusted speed.

[0137] In the roughening step, the source power may be 0.1 kW or more, 0.3 kW or more, 0.5 kW or more, or 5 kW or less.

[0138] In the roughening step, the bias power may be 0.1 kW or more. The bias power may be 0.3 kW or more. The bias power may be 0.5 kW or more. The bias power may be 1 kW or more. The bias power may be 8 kW or less. The bias power may be 5 kW or less.

[0139] In such cases, it may be useful to adjust the velocity of the ionized inert gas within an appropriate range to enable the formation of a glass core having the desired surface roughness characteristics in an embodiment.

[0140] The roughening step may be performed for 10 seconds or more. The roughening step may be performed for 15 seconds or more. The roughening step may be performed for 30 seconds or more. The roughening step may be performed for 1000 seconds or less. The roughening step may be performed for 500 seconds or less. The roughening step may be performed for 300 seconds or less. This may help form an upper surface of the glass core having roughness and asymmetry within a predetermined range in an embodiment.

[0141] The roughening step may be performed not only on the upper surface but also on the lower surface of the base glass plate, and the roughening step of the above-described type may be applied to the lower surface of the base glass plate.

[0142] If necessary, a core via can be formed in the glass core. Specifically, a defect can be formed at a predetermined position on the surface of the glass core. The defect can be subjected to physical or chemical etching to form the core via. The method for forming the core via will be omitted as it overlaps with the above description.

[0143] The method for manufacturing a substrate according to the embodiment may further include a core distribution layer forming step of forming a core distribution layer on the glass core.

[0144] The explanation of the core distribution layer will be omitted as it overlaps with the above content.

[0145] The core distribution layer forming step may include an electrically conductive layer forming process of forming an electrically conductive layer on the glass core, and an insulating layer forming process of forming an insulating layer surrounding at least a portion of the electrically conductive layer.

[0146] In the process of forming the electrically conductive layer, a seed layer is formed using preset ion beam deposition process conditions in accordance with the present embodiment, thereby preventing excessive variations in the roughness characteristics of the upper surface of the glass core due to the collision of sputtered particles with the upper surface of the glass core. Thus, the seed layer formed through sputtering forms a stable interlocking structure with the surface of the glass core over the entire upper surface of the glass core, thereby contributing to improved bonding strength of the electrically conductive layer. Additionally, this can help effectively prevent an increase in the resistance of the electrically conductive layer due to the skin effect.

[0147] The seed layer may include a first seed layer containing a different metal element from the metal element applied to the conductive layer, and a second seed layer disposed on the first seed layer containing the same metal element as the metal element applied to the conductive layer. For example, the first seed layer may include titanium, chromium, nickel, or the like, and the second seed layer may include copper, nickel, aluminum, gold, or silver, or the like.

[0148] The explanation of the seed layer is omitted here since it overlaps with the above-mentioned content.

[0149] In the ion beam deposition process for forming the seed layer, the atmospheric pressure may be 0.05 Pa or more. The pressure may be 0.1 Pa or more. The pressure may be 1 Pa or less. In such cases, the seed layer can be formed at a further improved deposition rate.

[0150] The sputtering power applied to the ion beam deposition process for forming the seed layer may be 10 kW or more. The sputtering power may be 15 kW or more. The sputtering power may be 20 kW or more. The sputtering power may be 100 kW or less. The sputtering power may be 50 kW or less. In this case, the sputtered particles may collide with the surface of the deposition target with controlled kinetic energy. This allows the seed layer to be formed more firmly on the glass core and prevents excessive fluctuations in the surface roughness characteristics of the glass core.

[0151] In the ion beam deposition process for the formation of the seed layer, an argon beam may be applied.

[0152] In the ion beam deposition process for forming the seed layer, the sputtering target may contain a metal element to be applied to the thin film to be deposited.

[0153] The ion beam deposition process for forming the first seed layer may be performed for 5 minutes or more, 10 minutes or more, 20 minutes or more, or 60 minutes or less.

[0154] The ion beam deposition process for forming the second seed layer may be performed for 5 minutes or more, 10 minutes or more, 20 minutes or more, or 60 minutes or less.

[0155] In this case, a seed layer having a structure that is stably bonded to the upper surface of the glass core can be formed.

[0156] After the formation of the seed layer is completed, portions of the seed layer where no electrically conductive layer is required can be removed. Plating activation / passivation treatment can be performed on both the portions of the seed layer where an electrically conductive layer is required and the portions where no electrically conductive layer is required. For example, the plating activation / passivation treatment can be performed using a light irradiation treatment using a laser of a specific wavelength, a chemical treatment, or the like. However, a conductive layer can be formed on the seed layer without performing the above treatment.

[0157] The structure and material of the seed layer will be explained below as they overlap with those described above.

[0158] The electrically conductive layer can be formed by forming a conductive layer on the seed layer through a plating process. The material of the conductive layer will not be described here as it is the same as the above. After the conductive layer is formed, the electrically conductive layer can be etched to have a pre-designed pattern shape.

[0159] After forming the electrically conductive layer, an insulating layer may be disposed to surround at least a portion of the electrically conductive layer to form a core distribution layer. The insulating layer may be formed, for example, using an epoxy resin containing a filler. For example, the insulating layer may be formed using a build-up layer material, such as Ajinomoto Build-up Film (ABF) from Ajinomoto Co., Inc., or an undercoat material, but is not limited thereto.

[0160] The insulating layer can be formed by laminating an uncured or semi-cured insulating film and then curing it.

[0161] The core distribution layer forming step may be a step of forming a core distribution layer on the glass core. The core distribution layer forming step may be a step of forming a core distribution layer above and below the glass core. The core distribution layer forming step may be a step of forming a core distribution layer above and below the glass core and in the core via. The description of the method of forming a core distribution layer below the glass core and in the core via is omitted as it is the same as the above description.

[0162] If necessary, the method for manufacturing a substrate according to an embodiment may further include forming an upper distribution layer on the core distribution layer disposed on the glass core, the upper distribution layer including an electrically conductive layer and an insulating layer surrounding at least a portion of the electrically conductive layer.

[0163] The method for manufacturing a substrate according to an embodiment may further include forming a lower distribution layer and / or bumps below the core distribution layer disposed below the glass core. The lower distribution layer may include an electrically conductive layer and an insulating layer surrounding at least a portion of the electrically conductive layer.

[0164] The electrically conductive and insulating layers applied to the upper and lower distribution layers may be made of the same materials and by the same manufacturing methods as the electrically conductive and insulating layers applied to the core distribution layer.

[0165] The following examples are provided for illustrative purposes only and are not intended to limit the scope of the present invention.

[0166] Manufacturing example: PCB manufacturing Manufacturing Example 1: The top surface of a 0.4T thick alkali-free glass substrate (base glass plate) was treated with argon plasma for 30 to 60 seconds to form a glass core with a root mean square deviation (Rq) value of 1.73 nm on the top surface. During the argon plasma treatment, the atmospheric pressure was 10 mTorr, the argon gas flow rate was 300 sccm, the source power was 1 kW, and the bias power was 1 kW.

[0167] Production Example 2: The top surface of a 0.55T thick soda lime glass substrate, which was a base glass plate, was subjected to argon plasma treatment for 30 to 60 seconds to form a glass core with a root mean square deviation Rq value of 0.45 nm on the top surface. The argon plasma process conditions were the same as those in Production Example 1.

[0168] Manufacturing Example 3: The top surface of a Corning SG7.8 glass substrate with a thickness of 0.5T was treated with argon plasma for 30 to 60 seconds to form a glass core with a root mean square deviation (Rq) value of 0.34 nm on the top surface. The argon plasma process conditions were the same as those in Manufacturing Example 1.

[0169] Production Example 4: The top surface of a 0.4T thick alkali-free glass substrate (base glass plate) was subjected to argon plasma treatment for 30 to 120 seconds to form a glass core with a root mean square deviation (Rq) value of 0.35 nm on the top surface. During the argon plasma treatment, the atmospheric pressure was 10 mTorr, the argon gas flow rate was 300 sccm, the source power was 1.5 kW, and the bias power was 2.5 kW.

[0170] Manufacturing Example 5: The upper surface of a 0.55T thick soda lime glass substrate was treated with argon plasma for 30 to 120 seconds to form a glass core with a root mean square deviation (Rq) value of 0.27 nm on the upper surface. The argon plasma process conditions were the same as those in Manufacturing Example 4.

[0171] Manufacturing Example 6: The top surface of a Corning SG7.8 glass substrate with a thickness of 0.5T was treated with argon plasma for 30 to 120 seconds to form a glass core with a root mean square deviation (Rq) value of 0.22 nm on the top surface. The argon plasma process conditions were the same as those in Manufacturing Example 4.

[0172] Manufacturing Example 7: The top surface of a Corning SG7.8 glass substrate with a thickness of 0.5T was treated with argon plasma for 30 to 120 seconds to form a glass core with a root mean square deviation (Rq) value of 0.26 nm on the top surface. The argon plasma process conditions were the same as those in Manufacturing Example 4.

[0173] Evaluation example: Measurement of roughness characteristics Three measurement areas, each 5 μm wide and 5 μm long, were arbitrarily selected on the top surface of the glass core of the manufacturing example. The measurement areas were specified so that they did not overlap each other. The Rq and Rku values of each measurement area were measured in non-contact mode using an atomic force microscope XE-100 manufactured by Park Systems in accordance with ISO 4287. The average Rq and Rku values for each measurement area were taken as the Rq and Rku values of the top surface of the glass core of the manufacturing example.

[0174] Thereafter, the standard deviation of the Rq values and the standard deviation of the Rku values for each production example were calculated from the Rq values and Rku values for each measurement region of the production examples.

[0175] Then, from the Rq value and Rku value calculated for each manufacturing example, R q*k The value was calculated.

[0176] The measurement and calculation results for each production example are shown in Tables 1 and 2 below.

[0177] Evaluation example: Evaluation of adhesive strength of electrically conductive layer A seed layer was formed on the upper surface of the glass core of the manufacturing example by forming a titanium layer having a thickness of 300 nm and a copper layer having a thickness of 300 nm on the titanium layer by ion beam deposition. The titanium layer and the copper layer were each formed by ion beam deposition for 30 minutes under conditions of an atmospheric pressure of 0.2 Pa and a sputtering power of 30 kW.

[0178] A conductive layer having a thickness of 20 μm was formed on the seed layer through a copper plating process to provide an electrical conductive layer.

[0179] The adhesive strength of the electrically conductive layer to the glass core was then measured by a 180° peel test using a bond tester, Condor Sigma, manufactured by XYZ TEC Corp. The measurement speed and distance were set to 10 mm / s and 70 mm, respectively.

[0180] The measurement results for each production example are shown in Table 1 below.

[0181] Evaluation example: Evaluation of the presence or absence of peeling of the electrically conductive layer 1 A seed layer was formed on the upper surface of the glass core of the manufacturing example by depositing a 300 nm thick titanium layer and a 300 nm thick copper layer on the titanium layer using an ion beam deposition process. The titanium layer and the copper layer were each deposited by performing a deposition process for 30 minutes under conditions of an atmospheric pressure of 0.2 Pa and a sputtering power of 30 kW. A 20 μm thick conductive layer was formed on the seed layer through a copper plating process to provide an electrically conductive layer.

[0182] The glass core on which the electrically conductive layer was formed was subjected to singulation. Specifically, energy was irradiated onto a dicing path on the upper surface of the glass core using a laser device, and the glass core was cut by applying physical force. Then, the edges of the cut glass core were ground.

[0183] The cross section of the singulated glass core was examined using an optical microscope to check for peeling of the electrically conductive layer. When no peeling of the electrically conductive layer was observed on the cross section, it was rated as P, and when peeling of the electrically conductive layer was observed, it was rated as F.

[0184] The measurement results for each production example are shown in Table 1 below.

[0185] Evaluation example: Evaluation of the presence or absence of peeling of the electrically conductive layer 2 A seed layer was formed on the upper surface of the glass core of the manufacturing example by depositing a 300 nm thick titanium layer and a 300 nm thick copper layer on the titanium layer using an ion beam deposition process. The titanium layer and the copper layer were each deposited by performing a deposition process for 30 minutes under conditions of an atmospheric pressure of 0.2 Pa and a sputtering power of 30 kW. A 20 μm thick conductive layer was formed on the seed layer through a copper plating process to provide an electrically conductive layer.

[0186] The glass core on which the electrically conductive layer was formed was left for 25 hours in an atmosphere at 125° C. Then, the glass core was left for 500 hours at 150° C.

[0187] After standing, the substrates of the different production examples were visually observed and rated as P if no peeling of the electrically conductive layer occurred, and as F if peeling of the electrically conductive layer occurred.

[0188] The measurement results for each production example are shown in Table 1 below.

[0189] JPEG0007725664000005.jpg50170

[0190] JPEG0007725664000006.jpg129166

[0191] In Table 1, R q*k In the case of Production Examples 1 to 5, in which the R value was controlled to be 3.5 nm or more and 150 nm or less, when the electrically conductive layer was formed on the glass core, the electrically conductive layer exhibited a bonding strength of 0.25 kgf or more, and no peeling of the electrically conductive layer was observed in two evaluations of the presence or absence of peeling. q*k In the case of Production Examples 6 and 7, where the value was less than 3.5 nm, when the electrically conductive layer was formed on the glass core, the adhesive strength of the electrically conductive layer was measured to be 0.4 kgf or less, and peeling of the electrically conductive layer occurred at least once in two evaluations of whether or not peeling occurred.

[0192] In Table 2, the standard deviation of the Rq values in each measurement region of the manufacturing example was calculated to be 0.1 nm or less, and the standard deviation of the Rku values in each measurement region was calculated to be 1 or less. This means that the roughness characteristics of the top surface of the glass core of the manufacturing example were uniform overall.

[0193] Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements made by those skilled in the art using the basic concept of the present invention defined in the appended claims also fall within the scope of the present invention. [Explanation of symbols]

[0194] 100 boards 10 Glass Core 11 Top surface of glass core 12 Underside of glass core 20 Electrically Conductive Layer 21 Seed layer 22 Conductive Layer 25 First electrically conductive layer 26 Second electrically conductive layer 30 insulating layer 50 Core Distribution Layer L: Interface formed between the first electrically conductive layer and the glass core

Claims

1. a glass core having an upper surface; The bonding roughness index R of the upper surface of the glass core is expressed by the following formula 1. ｑ＊ｋ The substrate has a value of 3.5 nm to 150 nm. [Formula 1] In the above formula 1, the Rq value is the root mean square deviation (unit: nm), and the Rku value is the kurtosis.

2. The substrate of claim 1, wherein the Rq value is between 0.25 nm and 5 nm.

3. The substrate of claim 1 , wherein the Rku value is 3 or greater.

4. The upper surface of the glass core includes a total of three arbitrarily selected measurement areas, The substrate according to claim 1 , wherein the standard deviation of the Rq values of the respective measurement regions is 0.15 nm or less.

5. The upper surface of the glass core includes a total of three arbitrarily selected measurement areas, The substrate according to claim 1 , wherein the standard deviation of the Rku values of the measurement areas is 1 or less.

6. The substrate of claim 1 , comprising an electrically conductive layer disposed on the glass core.

7. the electrically conductive layer includes a seed layer and a conductive layer disposed on the seed layer; The substrate of claim 6, wherein the seed layer has a thickness of 50 nm to 1500 nm.

8. the electrically conductive layer has a patterned shape; the width of the electrically conductive layer is 1 μm to 5 μm; The substrate of claim 6, wherein the electrically conductive layer has a thickness of 1 μm to 5 μm.

9. the electrically conductive layer includes a first electrically conductive layer formed in contact with a surface of the glass core; 7. The substrate according to claim 6, wherein, when observed in a cross section of the first electrically conductive layer, the Rz value, which is the maximum height roughness of the interface formed between the first electrically conductive layer and the glass core, is 5 nm to 200 nm.

10. the electrically conductive layer includes a first electrically conductive layer formed in contact with a surface of the glass core; 7. The substrate of claim 6, wherein the bonding strength between the first electrically conductive layer and the glass core measured by a 180° peel test is 0.25 kgf or more.

11. The substrate of claim 1 , wherein the substrate has a semiconductor packaging application.

12. a preparation step of providing a base glass plate; a roughening step of roughening the upper surface of the base glass plate to provide a substrate including a glass core; the glass core has an upper surface; The bonding roughness index R of the upper surface of the glass core is expressed by the following formula 1. ｑ＊ｋ The method for manufacturing a substrate, wherein the value is 3.5 nm to 150 nm. [Formula 1] In the above formula 1, the Rq value is the root mean square deviation (unit: nm), and the Rku value is the kurtosis.

13. The method for manufacturing a substrate according to claim 12 , wherein the roughening step includes a process of plasma treating the upper surface of the base glass plate to form a glass core.

Images