Display device

Abstract

To provide a semiconductor device with high reliability, including a transistor using an oxide semiconductor.SOLUTION: In a semiconductor device including a transistor with a bottom-gate structure including an oxide semiconductor layer, a first insulating layer is formed in contact with the oxide semiconductor layer, and an oxygen doping process is performed so that the first insulating layer containing excess oxygen compared to the stoichiometric composition is obtained. By forming a second insulating layer on the first insulating layer, the excess oxygen contained in the first insulating layer can be supplied efficiently to the oxide semiconductor layer. Accordingly, the semiconductor device with high reliability and a stable electric characteristic can be provided.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The disclosed invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to a general category of semiconductor devices, including electro-optical devices, light-emitting displays, semiconductor circuits, and electronic equipment. be. [Background technology]

[0003] A technology for constructing transistors using semiconductor thin films formed on substrates with insulating surfaces is The transistor is used in integrated circuits (ICs) and image display devices (also known simply as display devices). It is widely applied to semiconductor electronic devices such as transistors. Silicon-based semiconductor materials are widely known as suitable semiconductor thin films, but other materials include oxides. Compound semiconductors are attracting attention.

[0004] For example, zinc oxide or In-Ga-Zn oxide is used as the oxide semiconductor to produce a transistor. Techniques for producing a transistor have been disclosed (see Patent Documents 1 and 2).

[0005] In oxide semiconductors, hydrogen is contained, which causes a level close to the conduction band (shallow It has been pointed out that donors are generated at the junction level (level) and the resistance becomes low (n-type). Therefore, it is necessary to take measures to prevent hydrogen from being mixed in when forming the oxide semiconductor. In addition, hydrogen in the oxide semiconductor and the gate insulating film in contact with the oxide semiconductor can be reduced. A technique for reducing the fluctuation of the threshold voltage has been disclosed (see Patent Document 3). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 [Patent Document 3] Japanese Patent Application Laid-Open No. 2009-224479 Summary of the Invention [Problem to be solved by the invention]

[0007] In addition, oxygen vacancies in oxide semiconductors generate electrons, which are carriers, in the oxide semiconductor. When many oxygen vacancies exist in the oxide semiconductor including the channel formation region of the transistor, This generates electrons in the channel formation region, causing the threshold voltage of the transistor to decrease. This causes fluctuations in the direction.

[0008] In view of the above problems, one embodiment of the present invention provides a semiconductor device including an oxide semiconductor, The present invention aims to provide a semiconductor device having stable electrical characteristics and high reliability, and a method for manufacturing the same. It is considered one of the targets. [Means for solving the problem]

[0009] In a semiconductor device having a bottom-gate transistor including an oxide semiconductor layer, an insulating layer is formed in contact with the oxide semiconductor layer, and the insulating layer and the oxide semiconductor layer in contact with the insulating layer The insulating layer and the oxide semiconductor in contact with the insulating layer are doped with oxygen. The conductor layer can be in an oxygen-excess state, containing more oxygen than the stoichiometric composition. By making the insulating layer in contact with the oxide semiconductor layer an insulating layer containing excess oxygen, it is possible to prevent oxygen from being released from the insulating layer. Since it becomes easier to supply oxygen to the oxide semiconductor layer, oxygen is easily released from the oxide semiconductor layer. This makes it possible to prevent the oxygen vacancies in the oxide semiconductor layer and to compensate for the oxygen vacancies in the oxide semiconductor layer.

[0010] Further, a first insulating layer doped with oxygen is formed on the oxide semiconductor layer, and A second insulating layer may be further formed on the oxygen-doped first insulating layer. By forming this insulating layer, the excess oxygen contained in the first insulating layer can be efficiently converted into oxide semiconductor. The body layer can be supplied with the

[0011] The second insulating layer may be formed of the same material as the first insulating layer, but may contain impurities such as hydrogen and moisture. A metal oxide with high barrier properties that blocks both carbon and oxygen. It is preferable to use a material such as aluminum oxide.

[0012] In addition, the second insulating layer is formed of the same material as the first insulating layer, and the third insulating layer is formed on the second insulating layer. A metal oxide layer made of a metal oxide material having barrier properties may be formed as the layer.

[0013] The metal oxide layer is formed by forming a metal layer on the first insulating layer or the second insulating layer, and adding oxygen to the metal layer. The metal layer can be formed by oxidizing it through doping.

[0014] An insulating layer containing oxygen is sandwiched between an oxide semiconductor layer and a metal oxide layer having a barrier property. This reduces hydrogen, which is a factor in fluctuations in the electrical characteristics during and after the manufacturing process of a transistor. , impurities such as moisture are mixed into the oxide semiconductor layer, and the main component material constituting the oxide semiconductor Therefore, the release (desorption) of oxygen from the oxide semiconductor layer can be prevented. The electrical characteristics and reliability of the transistor can be improved.

[0015] The metal oxide layer formed by oxygen doping is 1×10 10 Ω m or more 1×10 1 9 Ω·m or less, preferably 1×10 10 Ω m or more 1×10 18 Ω·m or less, more preferable 1×10 11 Ω m or more 1×10 15 It is preferable to have a resistivity ρ of Ω·m or less The metal oxide layer having a resistivity in the above range prevents electrostatic breakdown of the transistor. It is possible.

[0016] In addition, an insulating layer (for example, an interlayer insulating layer or a gate insulating layer) in contact with the oxide semiconductor layer may be formed as follows. It is preferable that impurities such as water and hydrogen are not contained in the insulating layer in contact with the oxide semiconductor layer. If hydrogen is contained in the oxide semiconductor layer, the hydrogen may penetrate into the oxide semiconductor layer or may be oxidized. This is because there is a risk of extracting oxygen from the oxide semiconductor layer. The insulating layer is preferably a layer that has been subjected to heat treatment for the purpose of dehydration or dehydrogenation. .

[0017] The above-mentioned "oxygen doping treatment" refers to a treatment in which oxygen (at least oxygen radicals, oxygen atoms, and oxygen Ozone, oxygen ions (oxygen molecular ions), and / or oxygen cluster ions. The term "bulk" refers to the addition of oxygen to the The term "acid" is used to clarify that the thin film is not only added to the surface but also to the inside of the thin film. "Primary doping process" involves adding plasma oxygen to the bulk, called "oxygen plasma doping process." The oxygen doping process includes ion implantation, ion doping, plasma immersion, and This is done using methods such as ion implantation and plasma treatment in an oxygen atmosphere. It is also possible to use a gas cluster ion beam as the ion implantation method. .

[0018] The oxygen doping treatment can be performed using a gas containing oxygen. Oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide, etc. can be used. In the oxygen doping treatment, a rare gas may be added to the oxygen-containing gas.

[0019] One aspect of the present invention is a gate electrode, a gate insulating layer formed on the gate electrode, and a gate electrode. an oxide semiconductor layer formed over the gate insulating layer and overlapping with the electrode; a source electrode and a drain electrode formed on the source electrode and the drain electrode; a first insulating layer in contact with a portion of the semiconductor layer; and a second insulating layer formed on the first insulating layer; The first insulating layer is characterized by containing more oxygen than in the stoichiometric composition.

[0020] The first insulating layer is preferably thicker than 10 nm and thinner than 100 nm.

[0021] One embodiment of the present invention is a method for forming a gate electrode, forming a gate insulating layer on the gate electrode, and forming a gate insulating layer on the gate electrode. An oxide semiconductor layer is formed in a region overlapping with the gate electrode over the insulating layer, and A source electrode and a drain electrode are formed, and an oxide semiconductor is formed on the source electrode and the drain electrode. forming a first insulating layer in contact with a portion of the first insulating layer and containing more oxygen than the stoichiometric composition; A second insulating layer is formed on the edge layer.

[0022] A third insulating layer may be further formed on the second insulating layer. The border layer is preferably a metal oxide layer having barrier properties. [Effects of the Invention]

[0023] According to one embodiment of the present invention, an oxide film that can impart stable electrical characteristics and achieve high reliability can be obtained. It is possible to provide a semiconductor device using a compound semiconductor. [Brief explanation of the drawings]

[0024] [Figure 1] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 2] 1A to 1C are cross-sectional views illustrating one embodiment of a method for manufacturing a semiconductor device. [Figure 3] 1A to 1C are cross-sectional views illustrating one embodiment of a method for manufacturing a semiconductor device. [Figure 4] 1A to 1C are cross-sectional views illustrating one embodiment of a method for manufacturing a semiconductor device. [Figure 5] 1A and 1B are cross-sectional views illustrating one embodiment of a semiconductor device. [Figure 6] FIG. 1 is a plan view illustrating one embodiment of a semiconductor device. [Figure 7] FIG. 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 8] 1A and 1B are a circuit diagram and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 9] 1A and 1B are diagrams illustrating electronic devices. [Figure 10] 1A and 1B are diagrams showing an electronic device and a block diagram illustrating a charge / discharge control circuit. [Figure 11] 1A and 1B are cross-sectional views illustrating one embodiment of a semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0025] Hereinafter, embodiments of the invention disclosed in this specification will be described in detail with reference to the accompanying drawings. However, the invention disclosed in this specification is not limited to the following description, and the modes and details may be variously modified. It will be readily understood by those skilled in the art that the invention disclosed in this specification can be modified as follows. The present invention is not limited to the following description of the embodiments. In the configuration of the present invention, the same parts or parts having similar functions are denoted by the same reference numerals. The same functions are used in common between the drawings, and the repeated explanations thereof will be omitted. When referring to a part, the hatch pattern may be the same and no particular reference numeral may be given.

[0026] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components. It should be noted that the number is not a numerical limit.

[0027] (Embodiment 1) In this embodiment, a structure and a manufacturing method of a transistor, which is one embodiment of a semiconductor device, will be described. The transistor disclosed in this embodiment has an oxide film formed in a semiconductor layer where a channel is formed. It is a transistor that uses a compound semiconductor.

[0028] FIG. 1A shows a transistor 15 using an oxide semiconductor for a semiconductor layer in which a channel is formed. 1(B) is a top view showing the planar configuration of the 10th embodiment, and FIG. 1(B) is a top view showing the planar configuration of the 10th embodiment shown in FIG. 1(A) by the chain line A1-A2. FIG. 1(C) is a cross-sectional view showing the cross-sectional structure of the B1-B2 chain in FIG. 1(A). 1 is a cross-sectional view showing the cross-sectional configuration of a portion indicated by a line. In 1(A), some components are omitted.

[0029] The transistor 150 shown in FIG. 1 has a bottom gate structure called a channel etched type. It is one of the transistor structures known as the inverted staggered type. do.

[0030] In FIG. 1, an insulating layer 102 is formed on a substrate 101, and a gate electrode 1 is formed on the insulating layer 102. 1, a gate insulating layer 104 is formed on the gate electrode 103. In the example, the gate insulating layer 104 is a stack of the gate insulating layer 104a and the gate insulating layer 104b. As shown, the gate insulating layer 104 may be a single layer or a stack of multiple layers.

[0031] In addition, an oxide semiconductor layer 105 is formed on the gate insulating layer 104. A source electrode 106a and a drain electrode 106b are formed on the oxide semiconductor layer. An insulating layer 10 is in contact with a part of the dielectric layer 105 and is formed on the source electrode 106a and the drain electrode 106b. 7 is formed on the insulating layer 107, and an insulating layer 108 is formed on the insulating layer 107.

[0032] The oxide semiconductor used for the oxide semiconductor layer 105 is at least indium (In). It is preferable that the material contains In or zinc (Zn). It is particularly preferable that the material contains In and Zn. and a stabilization method for reducing variations in electrical characteristics of a transistor using the oxide semiconductor. It is preferable to have gallium (Ga) as a stabilizer in addition to the above. It is preferable to use tin (Sn) as the stabilizer. It is preferable that the alloy contains aluminum (Al) as a stabilizer. ) is preferred.

[0033] Other stabilizers include lanthanides such as lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Mium (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb), Ru It may contain one or more of tetraethion (Te) and tetraethion (Tb).

[0034] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and oxides of binary metals. In-Zn oxides, Sn-Zn oxides, Al-Zn oxides, Zn-Mg oxides Oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, ternary metal oxides In-Ga-Zn oxide (also written as IGZO), In-Al-Zn oxide Oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides , In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, I n-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In -Lu-Zn oxides, In-Sn-Ga-Zn oxides, which are oxides of quaternary metals, I n-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al- Zn-based oxide, In-Sn-Hf-Zn-based oxide, In-Hf-Al-Zn-based oxide are used. The oxide semiconductor may contain SiO2.

[0035] Here, for example, the In-Ga-Zn oxide is a compound containing indium (In), gallium (Ga ), zinc (Zn), and the ratio of In, Ga, and Zn does not matter. In addition, metal elements other than In, Ga, and Zn may be contained. It is preferable to use an excess amount of oxygen relative to the stoichiometric ratio. This can suppress the generation of carriers caused by oxygen vacancies.

[0036] The oxide semiconductor layer has the chemical formula InMO3(ZnO) m A thin film expressed as (m>0) Here, M is selected from Sn, Zn, Ga, Al, Mn and Co. In addition, the oxide semiconductor is In2SnO 5(ZnO) n Materials expressed as (n>0) may also be used.

[0037] For example, In:Ga:Zn=1:1:1 (=1 / 3:1 / 3:1 / 3) or In:G In-Ga-Zn system oxide with an atomic ratio of a:Zn=2:2:1 (=2 / 5:2 / 5:1 / 5) In:Sn:Zn=1 :1:1(=1 / 3:1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3:1 / 6:1 / 2) or In:Sn:Zn=2:1:5(=1 / 4:1 / 8:5 / 8) It is advisable to use an In-Sn-Zn oxide having an atomic ratio or an oxide having a composition close to that.

[0038] However, it is not limited to these, and the required semiconductor characteristics (mobility, threshold, variation, etc.) In addition, in order to obtain the required semiconductor characteristics, Carrier concentration, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density, etc. It is preferable to use an appropriate one.

[0039] For example, high mobility can be obtained relatively easily with In-Sn-Zn oxides. Therefore, even in In-Ga-Zn oxides, the mobility can be increased by reducing the defect density in the bulk. It can be done.

[0040] For example, when the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c(a+b+ and oxides with an atomic ratio of In:Ga:Zn=A:B:C (A+B+C=1). The oxide compositions are close to each other when a, b, and c are (a―A) 2 +(b-B) 2 +(c-C) 2 ≦r 2 The value of r can be set to, for example, 0.05. The same applies to other oxides. .

[0041] The oxide semiconductor film may have, for example, a non-single crystal structure. Axis Aligned Crystal), polycrystalline, microcrystalline, and amorphous parts. The amorphous part has a higher defect level density than the microcrystals and CAAC. The oxide semiconductor having CAAC is called CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor It is called a uctor.

[0042] It is relatively easy to obtain a flat surface for an amorphous oxide semiconductor film. This allows for the reduction of interface scattering when fabricating a transistor, and is relatively easy. In addition, a relatively high mobility can be obtained.

[0043] In addition, in a crystalline oxide semiconductor film, defects in the bulk can be further reduced, and By improving the flatness of the surface, it is possible to obtain a mobility higher than that of an oxide semiconductor film in an amorphous state. In order to improve the flatness of the surface, it is preferable to form an oxide semiconductor film on a flat surface. More specifically, the average surface roughness (Ra) is preferably 1 nm or less, more preferably 0.3 nm or less, and even more preferably 10 nm or less. It is more preferable to form it on a surface of 0.1 nm or less. This can be evaluated using an AFM (Atomic Force Microscope).

[0044] In addition, when an In-Zn oxide material is used as the oxide semiconductor film, the atomic ratio is In / Zn=0.5 or more and 50 or less, preferably In / Zn=1 or more and 20 or less, more preferably The atomic ratio of In to Zn is preferably in the above range. The field effect mobility of the transistor can be improved by the above. When the numerical ratio is In:Zn:O=X:Y:Z, Z>1.5X+Y.

[0045] The oxide semiconductor film may include, for example, a CAAC-OS. The c-axis is oriented, and the a-axis and / or b-axis are not aligned macroscopically.

[0046] The oxide semiconductor film may have, for example, microcrystals. The microcrystalline oxide semiconductor film has a thickness of, for example, 1 nm to 10 nm. The film contains microcrystals (also called nanocrystals) of about 1000 nm in size. Alternatively, the film contains microcrystalline oxide semiconductors. The film is, for example, an oxide having a crystalline-amorphous mixed phase structure with a crystalline portion of 1 nm or more and less than 10 nm. It has a semiconductor.

[0047] The oxide semiconductor film may have, for example, an amorphous portion. The amorphous oxide semiconductor film is a semiconductor in which the atomic arrangement is disordered. The amorphous oxide semiconductor film has no crystalline component. Alternatively, the amorphous oxide semiconductor film has a completely amorphous structure, for example. and has no crystalline parts.

[0048] Note that the oxide semiconductor film may be a CAAC-OS film, a microcrystalline oxide semiconductor film, or an amorphous oxide semiconductor film. The mixed film may be a film containing, for example, an amorphous oxide semiconductor region and a microcrystalline oxide region. The mixed film has a semiconductor region and a CAAC-OS region. A stack of an oxide semiconductor region, a microcrystalline oxide semiconductor region, and a CAAC-OS region It may have a structure.

[0049] Note that the oxide semiconductor film may be, for example, single-crystal.

[0050] The oxide semiconductor film has a plurality of crystal parts, and the c-axes of the crystal parts are aligned along a normal vector of a surface where the crystal parts are formed. It is preferable that the crystal orientations are aligned in a direction parallel to the normal vector of the surface. The directions of the a-axis and the b-axis may be different between the oxide semiconductor films. An example is a CAAC-OS film.

[0051] The CAAC-OS film is not completely amorphous. For example, the CAAC-OS film has crystalline and amorphous portions. The oxide semiconductor has a crystalline-amorphous mixed phase structure having an amorphous portion and an amorphous portion. The part is often small enough to fit inside a cube with a side of less than 100 nm. Transmission Electron Microscope (TEM) In the observation image by pe), the boundary between the amorphous and crystalline parts in the CAAC-OS film, the crystalline The boundary between the grain and crystalline regions is not clear. Therefore, the CAAC-OS film has no grain boundaries. The decrease in electron mobility caused by the magnetic field is suppressed.

[0052] The crystal part included in the CAAC-OS film has a c-axis that is the normal vector of the surface on which the CAAC-OS film is formed. The triangle is aligned parallel to the normal vector of the hole or surface and perpendicular to the ab plane. The metal atoms are arranged in a layered or hexagonal shape when viewed perpendicular to the c-axis. Metal atoms and oxygen atoms are arranged in layers. The orientation of the a and b axes may be different. The range is from 0° to 100°, preferably from 85° to 95°. In addition, when simply describing it as parallel, it means that the angle is between -10° and 10°, preferably between -5° and 5°. The following ranges are included:

[0053] In the CAAC-OS film, the distribution of the crystal parts may not be uniform. In the process of forming the C-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, The proportion of crystalline parts may be higher near the surface than near the growth surface. By adding impurities to the AC-OS film, the crystalline part in the impurity-doped region becomes amorphous. It may also be pawned.

[0054] The c-axis of the crystalline part in the CAAC-OS film is the normal vector of the surface on which the CAAC-OS film is formed. The CAAC-OS film shape (on which the film is formed) is Depending on the cross-sectional shape of the surface, the directions may be different from each other. The crystalline portion is formed when the film is formed or when a crystallization process such as a heat treatment is performed after the film is formed. Therefore, the c-axis direction of the crystalline part is determined by the shape of the CAAC-OS film when it is formed. The vectors are aligned to be parallel to the normal vector of the resulting surface or the normal vector of the surface.

[0055] The electrical characteristics of a transistor using a CAAC-OS film change when irradiated with visible or ultraviolet light. Therefore, the transistor has high reliability.

[0056] Note that part of oxygen contained in the oxide semiconductor may be substituted with nitrogen.

[0057] In addition, in oxide semiconductors with crystalline parts such as CAAC-OS, defects in the bulk can be further reduced. By improving the surface flatness, the movement can be reduced more than that of an amorphous oxide semiconductor. To improve the flatness of the surface, it is necessary to deposit an oxide semiconductor on a flat surface. Specifically, it is preferable to form a surface having an average surface roughness (Ra) of 1 nm or less, preferably 0 It is preferable to form the surface on a surface with an interatomic thickness of 0.3 nm or less, more preferably 0.1 nm or less. It can be evaluated using an atomic force microscope (AFM). be.

[0058] However, since the transistor 150 described in this embodiment is a bottom-gate transistor, Below the nitride semiconductor film, a gate electrode 103 and a gate insulating layer 104 are present. In order to obtain the above-mentioned flat surface, a gate electrode 103 and a gate insulating layer 104 are formed on the substrate. After the formation, at least the surface of the gate insulating layer 104 overlapping with the gate electrode 103 is oxidized. Chemical Mechanical Polishing (CMP) ) treatment may be performed.

[0059] The thickness of the oxide semiconductor layer 105 is 1 nm or more and 30 nm or less (preferably 5 nm or more and 10 nm or less). m or less), and sputtering method, MBE (Molecular Beam Epita xy) method, CVD method, pulsed laser deposition method, ALD (Atomic Layer Deposition The oxide semiconductor layer 105 can be formed by a sputtering method or the like. Film deposition is performed with multiple substrate surfaces set approximately perpendicular to the target surface. Alternatively, the film may be formed using a sputtering apparatus that performs the above steps.

[0060] Next, an example of a method for manufacturing the transistor 150 will be described with reference to FIGS.

[0061] First, an insulating layer 102 is formed on a substrate 101, and a gate electrode 103 is formed on the insulating layer 102. (See FIG. 2(A)). There is no particular limitation on the substrate that can be used for the substrate 101. At least, it is necessary to have heat resistance to the extent that it can withstand the subsequent heat treatment. For example, glass substrates, ceramic substrates, single crystal semiconductor substrates such as silicon and silicon carbide, In addition to polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, and SOI substrates, Use a plastic substrate or the like that is heat-resistant enough to withstand the processing temperature of this manufacturing process. In addition, a substrate having a semiconductor element formed thereon can be used as the substrate 101. It's fine.

[0062] The glass substrate may be, for example, barium borosilicate glass, aluminoborosilicate glass, or Alternatively, a non-alkali glass substrate such as an aluminosilicate glass substrate may be used. A sapphire substrate or the like can be used. In addition, the substrate 101 can be a flexible substrate (flexible substrate). When a flexible substrate is used, a transistor is formed on the flexible substrate. The transistor 150 may be directly fabricated, or may be fabricated on another fabrication substrate. After the formation, the film may be peeled off and transferred to a flexible substrate. To avoid this, a separation layer is preferably provided between the formation substrate and the transistor. The substrate 101 is made of aluminoborosilicate glass.

[0063] The insulating layer 102 functions as an underlayer to prevent or reduce the diffusion of impurity elements from the substrate 101. The insulating layer 102 may be made of aluminum nitride, aluminum oxide, or nitride oxide. Aluminum, aluminum oxide nitride, gallium oxide, silicon nitride, silicon oxide, nitride A material selected from silicon oxide or silicon oxynitride is formed in a single layer or a laminated layer. In this specification, oxynitride refers to a material whose composition contains more nitrogen than oxygen. Oxynitride is a material that contains more oxygen than nitrogen. The content of each element is measured by, for example, Rutherford backscattering spectroscopy (RBS). utherford Backscattering Spectrometry) etc. The insulating layer 102 can be formed by a sputtering method, a CVD method, a coating method, or It can be formed by using a printing method or the like.

[0064] Furthermore, by making the insulating layer 102 contain halogen elements such as chlorine and fluorine, the substrate 101 The insulating layer can further enhance the function of preventing or reducing the diffusion of impurity elements from the insulating layer. The concentration of halogen elements contained in 102 was measured by secondary ion mass spectrometry (SIMS). obtained by analysis using Daily Ion Mass Spectrometry At the concentration peak, 1 x 10 15 / cm 3 More than 1×10 20 / cm 3 The following should do: .

[0065] In this embodiment, a 2 mm thick insulating layer 102 is formed on a substrate 101 using a plasma CVD method. The insulating layer 102 is formed at a temperature of 1000 nm. For example, the substrate 101 is heated to 350° C. or higher. The insulating layer 102 is formed while heating at a temperature of 450° C. or less. For example, the insulating layer 102 is formed by heating the substrate at 350°C. This is done by heating.

[0066] After the insulating layer 102 is formed, the insulating layer 102 may be heated under reduced pressure, a nitrogen atmosphere, a rare gas atmosphere, or an ultra-dry atmosphere. Heat treatment may be performed under a nitrogen atmosphere. The concentration of hydrogen, moisture, hydrides, hydroxides, etc. can be reduced by the heat treatment. The treatment temperature is preferably higher than the temperature that the substrate 101 can withstand. In practice, it is preferable to perform the heating at a temperature equal to or higher than the temperature at which the insulating layer 102 is formed and lower than the strain point of the substrate 101 .

[0067] After the insulating layer 102 is formed, the insulating layer 102 is subjected to oxygen doping treatment. Note that the oxygen doping treatment to the insulating layer 102 may be performed after the heat treatment. It is preferable to do this in the following order.

[0068] Next, a gate electrode 103 is formed by sputtering, vacuum deposition, or plating. The conductive layer that becomes the gate electrode 103 is made of aluminum (Al), chromium (Cr), and silicon (Si). Aluminum (Cr), Copper (Cu), Tantalum (Ta), Titanium (Ti), Molybdenum (Mo), Metal elements selected from tungsten (W), neodymium (Nd), and scandium (Sc), Alloys containing the above metal elements, alloys combining the above metal elements, and alloys containing the above metal elements. It can be formed using nitrides of elements such as manganese (Mn), magnesium (Mg), etc. Select one or more of magnesium (Mg), zirconium (Zr), and beryllium (Be). Materials containing selected metal elements may also be used. Semiconductors such as crystalline silicon, and silicides such as nickel silicide may also be used.

[0069] The conductive layer to be the gate electrode 103 may have a single layer structure or a stacked structure of two or more layers. For example, a single layer structure using aluminum containing silicon, titanium on aluminum, Two-layer structure with titanium on titanium nitride, two-layer structure with tungsten on titanium nitride Two-layer structure with tungsten laminated on tantalum nitride, two-layer structure with tungsten laminated on tantalum nitride, Cu-M Two-layer structure with Cu layered on g-Al alloy, copper layered on titanium nitride, and There are three-layer structures that form tungsten.

[0070] The conductive layer to be the gate electrode 103 contains indium tin oxide and tungsten oxide. Indium oxide, indium zinc oxide with tungsten oxide, indium zinc oxide with titanium oxide Indium oxide, indium tin oxide with titanium oxide, indium zinc oxide, ketone oxide It is also possible to use a conductive material with light transmission, such as indium tin oxide doped with indium. In addition, the light-transmitting conductive material and the material containing the metal element may be laminated. It is also possible to do so.

[0071] Furthermore, a metal oxide containing nitrogen, specifically, a nitrogen-containing metal oxide, is used as a conductive layer to be the gate electrode 103. In-Ga-Zn oxides containing nitrogen, In-Sn oxides containing nitrogen, and In -Ga-based oxides, In-Zn-based oxides containing nitrogen, Sn-based oxides containing nitrogen, and nitrogen In-based oxides containing InN or metal nitride films (InN, SnN, etc.) can be used.

[0072] These materials have a work function of 5 eV (electron volts) or more, and when used as a gate electrode, In this case, the threshold voltage of the transistor can be made positive, and it is a so-called normally-off n-type A transistor can be realized.

[0073] In this embodiment, a conductive layer to be the gate electrode 103 is formed by sputtering. Form 100 nm of tungsten.

[0074] Next, a portion of the conductive layer that will become the gate electrode 103 is selectively etched to form the gate electrode 10 3 (including wiring formed in the same layer). Part of the conductive layer is selectively etched. In the case of etching, a resist mask is formed over the conductive layer, and a dry etching method or a wet etching method is used. The unnecessary portion of the conductive layer can be removed by etching. The etching may be performed by a combination of dry etching and wet etching. The resist mask formed on the conductive layer is formed by photolithography, printing, inkjet, etc. When the resist mask is formed by the ink-jet method, a photomask Since no wiring is used, manufacturing costs can be reduced.

[0075] When etching the conductive layer by dry etching, halogen is used as the etching gas. A gas containing a halogen element can be used. An example of a gas containing a halogen element is chlorine ( Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4) or carbon tetrachloride (C Chlorine gases such as chlorine (Cl4), carbon tetrafluoride (CF4), sulfur hexafluoride (SF6 ), nitrogen trifluoride (NF3) or trifluoromethane (CHF3) are typical examples. Fluorine-based gas, hydrogen bromide (HBr) or oxygen can be used as appropriate. An inert gas may be added to the etching gas. Reactive ion etching (RIE) method was used. It is possible.

[0076] In addition, a capacitively coupled plasma (CCP) was used as the plasma source. Inductively Coupled Plasma (ICP) Coupled Plasma), Electron Cyclotron Resonance (ECR) Cyclotron Resonance plasma, Helicon wave excited plasma (HW P: Helicon Wave Plasma, Microwave Excited Surface Wave Plasma (SW P: Surface Wave Plasma) can be used. In particular, IC P, ECR, HWP, and SWP can generate high density plasma. Etching by the etching method (hereinafter also referred to as "dry etching process") is carried out by The etching conditions (power applied to the coil-type electrode) were adjusted so that the processed shape could be etched. The amount of heat generated, the amount of power applied to the electrode on the substrate side, the temperature of the electrode on the substrate side, etc. are adjusted appropriately.

[0077] Note that a resist mask of any shape can be formed on the conductive layer or the insulating layer by photolithography. The process of forming the resist mask is called the photolithography process. In many cases, a chipping process and a resist mask stripping process are performed. Unless otherwise specified, the photolithography process in this specification includes a resist mask forming process, The process includes etching a conductive or insulating layer and removing a resist mask. Let's say.

[0078] In addition, the cross-sectional shape of the gate electrode 103, specifically the cross-sectional shape of the end portion (taper angle, film thickness, etc.) ) to improve the coverage of the layer formed on the gate electrode 103. can be done.

[0079] Specifically, the gate electrode 103 is formed so that its cross section has a trapezoidal or triangular shape. The end of the electrode 103 is tapered. Here, the taper angle θ of the end of the gate electrode 103 is , 60° or less, preferably 45° or less, and more preferably 30° or less. By setting the angle range, when a high gate voltage is applied to the gate electrode 103, the source voltage This reduces the electric field concentration that may occur near the end of the drain electrode 106a or the drain electrode 106b. The taper angle θ is the angle at which a layer having a tapered shape is formed when viewed from the cross section (of the substrate). When observed from the direction perpendicular to the surface, the angle between the side and bottom of the layer is In addition, a taper angle of less than 90° is called a forward taper, and a taper angle of 90° is called a forward taper. The edge of each layer, not limited to the gate electrode 103, is called a reverse taper. The forward tapered shape prevents the layer that is coated on top from being interrupted (step discontinuity). This makes it possible to improve the covering properties.

[0080] Next, a gate insulating layer 104 is formed over the gate electrode 103 (see FIG. 2B).

[0081] In order to improve the coverage of the gate insulating layer 104, a planarization process is performed on the surface of the gate electrode 103. In particular, when a thin insulating layer is used as the gate insulating layer 104, It is preferable that the surface of the port electrode 103 has good flatness.

[0082] The gate insulating layer 104 can be formed by a sputtering method, an MBE method, a CVD method, a pulsed laser deposition method, or the like. It can be formed by appropriately using an ALD method or the like. z) can be applied. 104 is a plate on which a plurality of substrate surfaces are set approximately perpendicular to the surface of the sputtering target. Alternatively, the film may be formed using a sputtering device that forms a film in a heated state.

[0083] The material of the gate insulating layer 104 is aluminum nitride, aluminum oxide, aluminum nitride oxide, or the like. Aluminum, aluminum oxide nitride, gallium oxide, silicon nitride, silicon oxide, nitride A material selected from silicon oxide or silicon oxynitride is formed in a single layer or a laminated layer. In this embodiment, the gate insulating layer 104 is a gate insulating layer 104a. and the gate insulating layer 104b are stacked.

[0084] Generally, a capacitance element has a structure in which a dielectric is sandwiched between two opposing electrodes. The thinner the thickness (the shorter the distance between the two opposing electrodes), and the higher the dielectric constant of the dielectric However, the thinner the dielectric, the larger the capacitance value. When the capacitance is increased, the leakage current between the two electrodes increases, and the dielectric strength of the capacitance element also decreases. It becomes easier to decrease.

[0085] The overlapping portion of the gate electrode, gate insulating layer, and semiconductor layer of the transistor is the capacitance element described above. The gate insulating layer of the semiconductor layer functions as a capacitor (hereinafter also referred to as "gate capacitance"). A channel is formed in the region overlapping the gate electrode via the gate electrode. The channel forming region functions as two electrodes of the capacitor element, and the gate insulating layer functions as the dielectric of the capacitor element. It is preferable that the gate capacitance is large, but in order to increase the capacitance, Furthermore, if the gate insulating layer is made thinner, problems such as an increase in leakage current and a decrease in dielectric strength voltage will occur. is likely to occur.

[0086] Therefore, the gate insulating layer 104 is made of hafnium silicate (HfSi x O y (x>0, y>0), nitrogen-doped hafnium silicate (HfSi x O y N z (x>0, y >0, z>0), nitrogen-doped hafnium aluminate (HfAlx O y N z (x >0, y>0, z>0), high-k materials such as hafnium oxide and yttrium oxide When the gate insulating layer 104 is thick, the gate electrode 103 and the oxide semiconductor layer 10 It is possible to ensure a sufficient capacitance value between the capacitors 5.

[0087] For example, if a high-k material with a large dielectric constant is used as the gate insulating layer 104, Even if the insulating layer 104 is made thick, the capacitance is the same as when silicon oxide is used for the gate insulating layer 104. Since the amount of leakage current between the gate electrode 103 and the oxide semiconductor layer 105 can be reduced, In addition, the wiring formed using the same layer as the gate electrode 103 and the wiring overlapping the wiring can be reduced. The leakage current generated between the gate insulating layer 104 and other interconnects can be reduced. A laminated structure of an igh-k material and the above material may also be used.

[0088] The gate insulating layer 104 is formed to have an oxygen-containing layer at a portion in contact with the oxide semiconductor layer 105 to be formed later. In this embodiment, the gate electrode in contact with the oxide semiconductor layer 105 preferably includes The insulating layer 104b has a film (bulk) containing oxygen in an amount exceeding the stoichiometric ratio. For example, when a silicon oxide film is used as the gate insulating layer 104b, SiO 2+α (where α>0). This silicon oxide film is used as the gate insulating layer 10 By using the oxide semiconductor layer 4b, oxygen can be supplied to the oxide semiconductor layer 105, and the characteristics can be improved. It can be done well.

[0089] The gate insulating layer 104a is made of silicon nitride or aluminum oxide, which is resistant to hydrogen, moisture, and hydrogenated materials. It is possible to use materials that have barrier properties against impurities such as hydroxides and oxygen. It is preferable that the gate insulating layer 104a is formed of a material having a barrier property. The intrusion of the impurities from the gate insulating layer 104b is prevented, and the oxygen contained in the gate insulating layer 104b is prevented from penetrating the substrate side. It is to be noted that the gate insulating layer 104 can be formed of a material having a barrier property. By using the insulating layer 102, the formation of the insulating layer 102 which functions as a base layer can be omitted.

[0090] Furthermore, before forming the gate insulating layer 104, oxygen, nitrous oxide, or a rare gas (typically The plasma treatment using gas such as argon removes moisture and other substances from the surface of the substrate. It is preferable to remove impurities such as inorganic materials.

[0091] After the gate insulating layer 104 is formed, the gate insulating layer 104 is annealed under reduced pressure, a nitrogen atmosphere, a rare gas atmosphere, or a superheated atmosphere. Heat treatment may be performed in a dry air nitrogen atmosphere. The concentration of hydrogen, moisture, hydrides, hydroxides, etc. contained in 104 can be reduced. The heat treatment is preferably performed at a temperature higher than the temperature that the substrate 101 can withstand. Specifically, the temperature should be equal to or higher than the temperature at which the gate insulating layer 104 is formed and lower than the strain point of the substrate 101. It is preferable that:

[0092] After the gate insulating layer 104 is formed, the gate insulating layer 104 is subjected to oxygen doping treatment. The insulating layer 104 may be in an oxygen-excess state. Doping method, plasma immersion ion implantation method, under oxygen atmosphere The oxygen doping to the gate insulating layer 104 can be performed by plasma treatment or the like. The lapping treatment is preferably carried out after the heat treatment.

[0093] The gate insulating layer 104 containing a large amount (excessive amount) of oxygen, which serves as an oxygen supply source, is formed on the oxide semiconductor layer 10 5, the oxide film is removed from the gate insulating layer 104 by a subsequent heat treatment. Oxygen can be supplied to the semiconductor layer 105 .

[0094] By supplying oxygen to the oxide semiconductor layer 105, oxygen vacancies in the oxide semiconductor layer 105 are reduced. Furthermore, the gate insulating layer 104 can compensate for the size of the transistor to be manufactured. It is preferable to form the insulating film 101 in consideration of the step coverage to the gate electrode 103 and the size of the insulating film 101 .

[0095] Next, a layer (later called an oxide semiconductor layer 105) is formed on the gate insulating layer 104 (gate insulating layer 104b). An oxide semiconductor layer 115 (not shown) made of the above-mentioned SiO 2 is formed by a sputtering method.

[0096] Furthermore, prior to the formation of the oxide semiconductor layer 115, the oxide semiconductor layer 10 of the gate insulating layer 104 The area where the film 5 is in contact with the film 5 may be subjected to a flattening treatment. Although not limited, polishing processes (e.g., CMP processes), dry etching processes, plasma processes can be used.

[0097] The plasma treatment may be, for example, a reverse plasma treatment in which argon gas is introduced to generate plasma. Reverse sputtering is a process in which RF is applied to the substrate side in an argon atmosphere. This method involves applying voltage using a power supply to generate plasma near the substrate, thereby modifying the surface. Instead of the argon atmosphere, nitrogen, helium, oxygen, etc. may be used. When the cleaning is performed, powdery substances (particles, dust, etc.) adhering to the surface of the gate insulating layer 104 are removed. (also called) can be removed.

[0098] In addition, polishing, dry etching, and plasma treatment are performed multiple times as planarization processes. In addition, when the steps are combined, the order of the steps may be There are no particular limitations on the thickness, and it may be set appropriately according to the unevenness of the surface of the gate insulating layer 104.

[0099] Note that a sputtering gas for forming the oxide semiconductor layer 115 is a rare gas (typically, An atmosphere of argon, an oxygen gas atmosphere, or a mixed gas of rare gas and oxygen is used as appropriate. The sputtering gas is a high-purity gas from which impurities such as hydrogen, water, hydroxyl groups, or hydrides have been removed. It is preferable to use a pure gas.

[0100] Note that the oxide semiconductor layer 115 is grown under conditions where a large amount of oxygen is contained (for example, 100% oxygen). The film is formed by sputtering under an atmosphere containing a large amount of oxygen. The oxygen is supersaturated (preferably, the oxide semiconductor has a stoichiometric composition in a crystalline state). It is preferable that the oxygen content is in a state where the oxygen content is excessive.

[0101] For example, when an oxide semiconductor layer is formed by a sputtering method, a sputtering gas It is preferable to carry out the sputtering under conditions where the proportion of oxygen is high, and the sputtering gas is oxygen gas 1 It is preferable to perform the sputtering at 00%. The proportion of oxygen gas in the sputtering gas is high. When the film is formed under certain conditions, especially when the film is formed using 100% oxygen gas, even if the film formation temperature is 300°C or higher, the film is not formed using oxygen. This suppresses the release of Zn from the oxide semiconductor layer.

[0102] The oxide semiconductor layer 115 contains almost no impurities such as copper, aluminum, or chlorine. It is desirable that the material be highly purified so that it is not easily broken down. It is necessary to appropriately select a process that does not involve the risk of these impurities being mixed in or adhering to the surface of the oxide semiconductor layer. Specifically, the copper concentration in the oxide semiconductor layer is preferably 1×10 18 atoms / cm 3 Less than 1 × 10 17 atoms / cm 3 The oxide semiconductor layer The aluminum concentration in 18 atoms / cm 3 The following applies. In addition, oxide semiconductors The chlorine concentration in the body layer is 2 x 10 18 atoms / cm 3 The following applies.

[0103] In addition, sodium (Na), lithium (Li), and potassium (K ) and other alkali metals, Na is 5 × 10 16 cm -3 Less than 1 × 10 16 cm -3 or less, more preferably 1 × 10 15 cm -3 Below, Li is 5 × 10 15 c m -3 Less than 1 × 10 15 cm -3 In the following, K is 5×10 15 cm -3 Below is good Preferably 1 x 10 15 cm -3 The following applies.

[0104] In this embodiment, the oxide semiconductor layer 115 is formed by sputtering using an AC power supply. A 35 nm thick In-Ga-Zn oxide was deposited by sputtering using a ring system. The target for fabricating it by sputtering is A metal oxide target with an atomic ratio of In:Ga:Zn=1:1:1 is used.

[0105] The relative density (filling rate) of the metal oxide target is preferably 90% or more and 100% or less. The relative density is 95% or more and 99.9% or less. Use a metal oxide target with a high relative density. As a result, the formed oxide semiconductor layer can be a dense layer.

[0106] First, the substrate 101 is held in a film-forming chamber that is maintained in a reduced pressure state. While removing moisture, a sputtering gas from which hydrogen and moisture have been removed is introduced, and the target is used. The oxide semiconductor layer 115 is formed over the gate insulating layer 104. To remove the particles, an adsorption type vacuum pump, such as a cryopump, ion pump, or titanium It is preferable to use a sublimation pump. A pump with a cold trap may be used. The film formation chamber contains, for example, hydrogen atoms, compounds containing hydrogen atoms such as water (H2O) (more preferably Since the oxide semiconductor layer formed in the deposition chamber is exhausted, The concentration of impurities contained in 115 can be reduced.

[0107] In addition, the gate insulating layer 104 and the oxide semiconductor layer 115 are successively formed without exposure to the air. The gate insulating layer 104 and the oxide semiconductor layer 115 may be successively formed without exposure to the air. This prevents impurities such as hydrogen and moisture from adhering to the surface of the gate insulating layer 104. This can be done.

[0108] Next, a part of the oxide semiconductor layer 115 is selectively etched by a photolithography process. The island-shaped oxide semiconductor layer 105 is formed by etching (see FIG. 2C). A resist mask for forming the dielectric layer 105 may be formed by an inkjet method. When a photomask is formed by the inkjet method, no photomask is used, reducing manufacturing costs. can be reduced.

[0109] Note that the oxide semiconductor layer 115 can be etched by either dry etching or wet etching. The oxide semiconductor layer 11 may be removed by wet etching, or both may be used. When etching step 5, the etching solution is a mixture of phosphoric acid, acetic acid, and nitric acid, A solution containing oxalic acid can also be used. ITO-07N (manufactured by Kanto Chemical Co., Ltd.) Alternatively, the oxide semiconductor layer 115 may be etched by a dry etching method. For example, ECR (Electron Cyclotron Resonance) ) or high density plasma such as ICP (Inductively Coupled Plasma) A dry etching method using a high-temperature plasma source can be used. As a dry etching method that can easily obtain uniform discharge, ECCP (Enhanced Electrochemical Process) Dry etching using the Capacitively Coupled Plasma mode This dry etching method can be used to fabricate a substrate such as a 10th generation 3D silicon wafer. It is also possible to use a substrate with a size exceeding m.

[0110] After the oxide semiconductor layer 105 is formed, excess hydrogen (water or hydroxide) in the oxide semiconductor layer 105 is removed. A heat treatment may be carried out to remove (dehydrate or dehydrogenate) the hydroxyl groups (including the hydroxyl groups). The temperature of the heat treatment should be between 300°C and 700°C, or below the distortion point of the substrate. The heating can be carried out under pressure or in a nitrogen atmosphere. The substrate is placed in a furnace, and the oxide semiconductor layer 105 is heated in a nitrogen atmosphere at 450° C. for 1 hour. The heat treatment is carried out.

[0111] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heat source such as a resistance heating element. A device that heats the object to be treated by radiation may be used. For example, a GRTA (Gas Reactor Tank Apparatus) apid Thermal Anneal) equipment, LRTA (Lamp Rapid T RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, high-pressure mercury lamp It is a device that heats the object to be treated by radiating light (electromagnetic waves) emitted from a lamp or other lamp. The GRTA device is a device that uses high-temperature gas to perform heat treatment. Inert gases such as argon or nitrogen that do not react with the material to be treated by heat treatment An active gas is used.

[0112] For example, as a heat treatment, the substrate is placed in an inert gas heated to a high temperature of 650 to 700°C. After heating for several minutes, GRTA may be performed in which the substrate is taken out of the inert gas.

[0113] In the heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen or hydrogen introduced into the heat treatment device is not contained. The purity of rare gases such as sodium, neon, and argon is preferably 6N (99.9999%) or higher. is 7N (99.99999%) or more (i.e., impurity concentration is 1 ppm or less, preferably 0.1 It is preferable to set the concentration to less than 1 ppm.

[0114] After the oxide semiconductor layer 105 was heated by heat treatment, high-purity oxygen gas, High purity nitrous oxide gas or ultra-dry air (Cavity Ring-Down Spectroscopy (CRDS) A dew point meter using Cavity Ring-Down Spectroscopy (CRA) was used. The moisture content measured at this temperature is 20 ppm or less (-55°C in terms of dew point), preferably 1 ppm m or less, more preferably 10 ppb or less of air) may be introduced. It is preferable that the dinitrogen chloride gas does not contain water, hydrogen, etc. The purity of the oxygen gas or nitrous oxide gas to be used is 6N or more, preferably 7N or more (i.e., the purity of the oxygen gas or nitrous oxide gas to be used is 6N or more, preferably 7N or more). The impurity concentration in nitrogen gas or dinitrogen monoxide gas is 1 ppm or less, preferably 0.1 ppm. It is preferable to dehydrate or The oxide semiconductor was reduced during the dehydrogenation process to remove impurities. By supplying oxygen, which is the main constituent material, oxygen vacancies in the oxide semiconductor are reduced. The conductivity is reduced, and the oxide semiconductor layer 105 can be made i-type (intrinsic) or substantially i-type. In this respect, unlike silicon, which is made i-type by adding impurity elements, it is an oxide semiconductor. The i-shape of the body can be said to involve a technological concept that has never been seen before.

[0115] If the heat treatment for dehydration or dehydrogenation is performed after the formation of the oxide semiconductor layer, the island-shaped oxide This may be carried out before or after the formation of the compound semiconductor layer 105. The heat treatment for hydrogenation may be carried out multiple times, or may be carried out in combination with other heat treatments.

[0116] Furthermore, the dehydration or dehydrogenation treatment can remove oxygen, which is a main component material of the oxide semiconductor. When oxygen is released from the oxide semiconductor layer, Oxygen vacancies exist at these locations, and these oxygen vacancies cause fluctuations in the electrical characteristics of the transistor. This results in a lower level.

[0117] Therefore, the oxide semiconductor layer 105 that has been subjected to dehydration or dehydrogenation treatment is subjected to oxygen doping treatment. In this case, oxygen may be supplied to the oxide semiconductor layer 105.

[0118] Oxygen is introduced into the oxide semiconductor layer 105 that has been subjected to dehydration or dehydrogenation treatment, and the oxide semiconductor By supplying oxygen into the layer 105, impurities can be removed by dehydration or dehydrogenation treatment. The oxygen vacancies in the oxide semiconductor layer 105 caused by the removal process are reduced, and the oxide semiconductor layer 105 is made into an i-type The transistor having the oxide semiconductor layer 105 that has been made into an i-type (intrinsic) oxide semiconductor layer 105 can be formed. The transistor has suppressed fluctuations in electrical characteristics and is electrically stable.

[0119] When oxygen is introduced into the oxide semiconductor layer 105, oxygen doping treatment is performed directly on the oxide semiconductor layer 105. The bonding may be performed directly or via another layer.

[0120] Furthermore, the introduction of oxygen can enhance the bonding between hydrogen and elements constituting the oxide semiconductor layer 105, or breaks the bond between the element and the hydroxyl group, and these hydrogens or hydroxyl groups react with oxygen. Therefore, if heat treatment is performed after oxygen is introduced, the impurity hydrogen is also generated. Therefore, oxygen is introduced into the oxide semiconductor layer 105. After that, oxygen may be further introduced into the oxide semiconductor layer 105. Alternatively, the oxide semiconductor layer 105 may be in an oxygen-excess state. The introduction of oxygen into the film and the heat treatment may be carried out alternately multiple times. Oxygen may be introduced at the same time.

[0121] In this manner, the oxide semiconductor layer 105 has high conductivity because impurities such as hydrogen are sufficiently removed. The oxide semiconductor layer 105 is purified and a sufficient amount of oxygen is supplied, so that oxygen vacancies in the oxide semiconductor layer 105 are reduced. It is desirable that the material be i-type (intrinsic) or substantially i-type (intrinsic) by the above-mentioned method. I wish.

[0122] Highly purified acid with reduced impurities such as water or hydrogen, which act as electron donors The oxide semiconductor (purified OS) then supplies oxygen to the oxide semiconductor, By reducing oxygen vacancies in the oxide semiconductor, it is possible to obtain an i-type (intrinsic) oxide semiconductor or an i-type The oxide semiconductor can be made to be substantially i-type. A transistor using an i-type or substantially i-type oxide semiconductor for a semiconductor layer to be formed is It has the characteristic of having a very low off-state current.

[0123] Specifically, the hydrogen concentration in the highly purified oxide semiconductor layer was measured by SIMS. The value is preferably 5 x 10 19 atoms / cm 3 Less than or equal to 5 × 10 18 a toms / cm 3 or less, and even more preferably 5 x 10 17 atoms / cm 3 The following In addition, in order to supply a sufficient amount of oxygen to the oxide semiconductor layer 105 so that the oxide semiconductor layer 105 is supersaturated with oxygen, Therefore, insulating layers containing a large amount of oxygen (such as silicon oxide) are bonded to sandwich the oxide semiconductor layer 105. It is preferable to provide it as follows.

[0124] The hydrogen concentration in the insulating layer, which contains a lot of oxygen, is also important because it affects the characteristics of the transistor. The hydrogen concentration in the oxygen-rich insulating layer is 7.2 × 10 20 atoms / cm 3 That's all In some cases, the variation in the initial characteristics of the transistor increases, the L length dependency increases, and the B The hydrogen concentration of the insulating layer containing a large amount of oxygen is not preferred because it deteriorates significantly in the T stress test. Or 7.2 x 10 20 atoms / cm 3 That is, the hydrogen concentration of the oxide semiconductor layer is less than Degrees are 5 x 10 19 atoms / cm 3 The hydrogen concentration of the insulating layer containing a large amount of oxygen is as follows: 7.2×10 20 atoms / cm 3 It is preferable that it is less than 1000 kJ / s.

[0125] Here, we will discuss SIMS analysis of hydrogen concentration. It is difficult to obtain accurate data near the surface of the material or near the interface between layers of different materials. Therefore, the distribution of hydrogen concentration in the layer in the thickness direction was analyzed by SIMS. When doing so, the value should not fluctuate dramatically and should be approximately constant within the range where the target layer exists. The average value in the region where the hydrogen concentration is obtained is adopted as the hydrogen concentration. When the thickness of is small, it is affected by the hydrogen concentration in the adjacent film and a nearly constant value is obtained. In this case, the hydrogen concentration in the region where the layer exists may not be found. The maximum or minimum value is adopted as the hydrogen concentration in the layer. In the region, there is no mountain-shaped peak having a maximum value or a valley-shaped peak having a minimum value. In this case, the value at the inflection point is adopted as the hydrogen concentration.

[0126] Next, a conductive layer 117 (not shown) is formed over the oxide semiconductor layer 105, and then a photolithography A portion of the conductive layer 117 is selectively etched by a etching process to form the source electrode 106a and The drain electrode 106b is formed (see FIG. 2(D)).

[0127] The conductive layer 117 to be the source electrode 106a and the drain electrode 106b is resistant to subsequent heat treatment. The conductive layer 117 is formed using a material that can be obtained. Metals containing elements selected from a, Ti, Mo, and W, or metals containing the above elements as components Nitrides (titanium nitride, molybdenum nitride, tungsten nitride) and the like can be used. In addition, a high-temperature metal such as Ti, Mo, or W may be applied to either or both of the upper and lower sides of a metal layer such as Al or Cu. Melting point metals or their metal nitrides (titanium nitride, molybdenum nitride, tungsten nitride) The conductive layer 117 may be formed using a conductive metal oxide. Conductive metal oxides include indium oxide (In2O3), tin oxide (SnO2), and zinc oxide (ZnO), indium oxide tin oxide (In2O3-SnO2, abbreviated as ITO) ), indium oxide zinc oxide (In2O3-ZnO) or these metal oxide materials with acid It is possible to use a material containing silicon dioxide.

[0128] In this embodiment, the conductive layer 117 is formed by sputtering titanium to a thickness of 200 nm. The conductive layer 117 is etched in the same manner as in the formation of the gate electrode 103. For example, etching gas (BCl3:Cl2 = 750 sccm: 150 s ccm), the bias power was 1500 W, the ICP power was 0 W, and the pressure was 2 This can be done by ICP etching at 0.0 Pa.

[0129] The oxide semiconductor exposed by forming the source electrode 106a and the drain electrode 106b The surface of the layer 105 contains elements that make up the source electrode 106a and the drain electrode 106b, The elements present in the processing chamber and the elements that make up the etching gas used for etching are impurities. This may cause adhesion.

[0130] When impurities are attached, the off-state current of the transistor increases or the electrical characteristics of the transistor deteriorate. Furthermore, a parasitic channel is likely to occur in the oxide semiconductor layer 105. Therefore, the electrodes that should be electrically isolated from each other are easily electrically connected via the oxide semiconductor layer 105. become.

[0131] In addition, some impurities may be mixed in the vicinity of the surface or the side surface of the oxide semiconductor layer 105, and may cause oxidation. The oxygen in the oxide semiconductor layer 105 is extracted, and the surface and side surfaces of the oxide semiconductor layer 105 are For example, the salts contained in the etching gas may cause oxygen vacancies in the vicinity of the etching gas. The silicon, boron, and aluminum, which are the constituent materials of the processing chamber, are used to convert the oxide semiconductor layer 105 into an n-type. This could be one of the factors that lead to this.

[0132] Therefore, in one embodiment of the present invention, the source electrode 106a and the drain electrode 106b are formed. After the etching for the oxide semiconductor layer 105 and the source electrode 106a and the drain electrode 106b are completed, A cleaning process (impurity removal) is performed to remove impurities adhering to the surface and side surfaces of the inner electrode 106b. processing).

[0133] The impurity removal treatment can be performed by plasma treatment or treatment with a solution. As the plasma treatment, oxygen plasma treatment or nitrous oxide plasma treatment may be used. Alternatively, a rare gas (typically, argon) may be used for the plasma treatment.

[0134] In addition, cleaning with solutions includes alkaline solutions such as TMAH solution, water, and diluted fluorine solution. This can be done using an acidic solution such as an acid. For example, when using dilute hydrofluoric acid, 50 w t% hydrofluoric acid, 1 / 10 with water 2 ~1 / 10 5 About 1 / 10, preferably 3 ~1 / 10 5 Dilute hydrofluoric acid diluted to about 0.5 wt % to 5×10 -4 % by weight of diluted hydrofluoric acid, preferably 5×10 -2 Weight% to 5×10 -4 % by weight of diluted hydrofluoric acid The cleaning treatment is preferably used for cleaning the exposed surface of the oxide semiconductor layer 105. The above-mentioned impurities adhering to the surface can be removed.

[0135] Furthermore, when impurity removal treatment is performed using a dilute hydrofluoric acid solution, the exposed oxide semiconductor layer 105 That is, the surface of the exposed oxide semiconductor layer 105 can be etched. The impurities adhering to the oxide semiconductor layer 105 and the impurities mixed in the vicinity of the surface of the oxide semiconductor layer 105 are removed by the oxide semiconductor. This allows the oxide semiconductor layer 105 to be removed together with a portion of the oxide semiconductor layer 105. In this case, the thickness of the region overlapping with the source electrode 106a and the drain electrode 106b is The thickness is greater than the thickness of the region that does not overlap with the electrode 106a and the drain electrode 106b.

[0136] By performing impurity removal treatment, the concentration peak obtained by SIMS analysis , the chlorine concentration on the surface of the oxide semiconductor layer is 1×10 19 / cm 3 Less than or equal to (preferably 5 x 1 0 18 / cm 3 or less, more preferably 1 × 10 18 / cm 3 (below) In addition, the boron concentration is set to 1×10 19 / cm 3 or less (preferably 5 × 10 18 / cm 3 below , and more preferably 1 × 10 18 / cm 3 (See below). The concentration of 19 / cm 3 or less (preferably 5 × 10 18 / cm 3 Below are some more preferred Or 1 x 10 18 / cm 3 (See below).

[0137] By performing impurity removal processing, we can create highly reliable transistors with stable electrical characteristics. 0 can be achieved.

[0138] Next, a source electrode 106a and a drain electrode 106b are formed in contact with a part of the oxide semiconductor layer 105. An insulating layer 111 is formed on the oxide semiconductor layer 6b to a thickness of 20 nm to 50 nm. The insulating layer 111 is formed on the insulating layer 102 or the gate insulating layer 104. For example, silicon oxide or silicon oxynitride can be used. The insulating layer 107 may be formed by sputtering or CVD. do.

[0139] In this embodiment, the insulating layer 111 is a 30 nm thick nitride oxide film formed by plasma CVD. The insulating layer 111 is formed by, for example, forming a silicon oxide film by using a gas flow rate ratio of SiH4 and N2O. SiH4:N2O=20sccm:3000sccm, pressure 40Pa, RF The power supply power (power supply output) is set to 100 W and the substrate temperature is set to 350°C.

[0140] Next, oxygen 121 is introduced into the insulating layer 111, and the insulating layer 111 is treated as an insulating layer 111 containing excess oxygen. 07 (see Figure 3(B)). Oxygen 121 contains at least oxygen radicals, ozone , oxygen atoms, or oxygen ions (including molecular ions and cluster ions) The introduction of oxygen 121 can be carried out by oxygen doping treatment.

[0141] The oxygen 121 may be introduced to the entire surface of the insulating layer 111 at once. When a linear ion beam is used, the substrate 101 or By relatively moving (scanning) the ion beam, oxygen 1 is deposited on the entire surface of the insulating layer 111. 21 can be introduced.

[0142] The supply gas for oxygen 121 may be a gas containing oxygen atoms, for example, O2 Gas, N2O gas, CO2 gas, CO gas, NO2 gas, etc. can be used. The oxygen supply gas may contain a rare gas (for example, Ar).

[0143] Also, for example, when oxygen is introduced by ion implantation, the dose of oxygen 121 is 1×10 13 ions / cm 2 5x10 or more 16 ions / cm 2 It is preferable that the following is true: The oxygen content of the layer 107 is preferably greater than the stoichiometric composition. Such a region containing excess oxygen compared to the stoichiometric composition exists in a part of the insulating layer 107. The oxygen implantation depth may be appropriately controlled by adjusting the implantation conditions.

[0144] In this embodiment, the oxygen 121 is introduced by plasma treatment performed in an oxygen atmosphere. Since the insulating layer 107 is an insulating layer in contact with the oxide semiconductor layer 105, water and water Therefore, before the introduction of oxygen 121, it is preferable that the insulating layer is free of impurities such as oxygen. It is preferable to perform a heat treatment to reduce hydrogen (including water and hydroxyl groups) in the insulating layer 111. The temperature for heat treatment for the purpose of dehydration or dehydrogenation treatment should be between 300°C and 700°C. The heat treatment for the purpose of dehydration or dehydrogenation should be performed at a temperature of 1000 K or less than the strain point of the substrate. The heat treatment can be carried out in the same manner as described above.

[0145] The plasma treatment for introducing oxygen 121 (oxygen plasma treatment) was carried out with an oxygen flow rate of 250 sc cm, the ICP power supply power was 0 W, the bias power was 4500 W, and the pressure was 15 Pa At this time, part of the oxygen introduced into the insulating layer 111 by the oxygen plasma treatment is The oxide semiconductor layer 105 is introduced through the insulating layer 111. Since oxygen is introduced through the insulating layer 111, the surface of the oxide semiconductor layer 105 is exposed to the plasma. The insulating layer 111 is less susceptible to damage caused by the heat treatment, and the reliability of the semiconductor device can be improved. The thickness of the insulating layer 111 is preferably set to be thicker than 10 nm and thinner than 100 nm. When the thickness is 10 nm or less, the oxide semiconductor layer 105 is less susceptible to damage during oxygen plasma treatment. Furthermore, if the thickness of the insulating layer 111 is set to 100 nm or more, the oxygen plasma treatment There is a possibility that the introduced oxygen may not be sufficiently supplied to the oxide semiconductor layer 105. Heat treatment and / or introduction of oxygen 121 for the purpose of dehydration or dehydrogenation of the edge layer 111 By introducing oxygen into the insulating layer 111, the insulating layer 107 is oxidized. It can function as an element supply layer.

[0146] Next, an insulating layer 108 is formed on the insulating layer 107 to a thickness of 200 nm to 500 nm (FIG. 3(C)). The insulating layer 108 is made of the same material as the insulating layer 102 or the gate insulating layer 104. For example, silicon oxide or silicon oxynitride can be used as a spatula. It can be formed by a tarpaulin method or a CVD method and used as the insulating layer 108.

[0147] In this embodiment, the insulating layer 108 is formed by a 370 nm thick oxide film formed by plasma CVD. The insulating layer 108 is formed by, for example, using a gas flow rate of SiH4 and N2O. The ratio was SiH4:N2O=30sccm:4000sccm, and the pressure was 200Pa. The RF power supply power (power supply output) is set to 150 W and the substrate temperature is set to 220°C.

[0148] After the insulating layer 108 is formed, the insulating layer 108 is heated in an inert gas atmosphere, an oxygen atmosphere, or an inert gas atmosphere. In an oxygen mixed atmosphere, 250°C to 650°C, preferably 300°C to 600°C The heat treatment may be performed at a temperature of 1000 to 2000° C. ... oxygen contained in the insulating layer 107 is removed by the heat treatment. to the oxide semiconductor layer 105 to compensate for oxygen vacancies in the oxide semiconductor layer 105. By forming the insulating layer 108 on the insulating layer 107, the oxygen contained in the insulating layer 107 can be can be efficiently supplied to the oxide semiconductor layer 105.

[0149] In addition, oxygen doping treatment is performed on the insulating layer 108 to introduce oxygen 121 into the insulating layer 108. The introduction of oxygen 121 into the insulating layer 108 is performed in a state where the amount of oxygen 121 is excessive. After the introduction of oxygen 121 into the insulating layer 108, the inactive 250℃ or higher in an inert gas atmosphere, oxygen atmosphere, or a mixed atmosphere of inert gas and oxygen The heat treatment may be carried out at a temperature of 650°C or less, preferably 300°C or more and 600°C or less.

[0150] FIG. 11(A) is an enlarged view of the portion 201 shown in FIG. 1(B), and FIG. 11(B) is an enlarged view of the portion 201 shown in FIG. 11(A) and 11(B) are enlarged views of the portion 202 shown in FIG. 1 shows how oxygen 122 contained in the layer 107 is supplied to the oxide semiconductor layer 105. The oxygen 122 contained in the insulating layer 107 is present in the region where the oxide semiconductor layer 105 and the insulating layer 107 are in contact with each other. In addition to being supplied directly to the oxide semiconductor layer 105 in the region, The oxide semiconductor layer 105 is also indirectly supplied with the insulating layer 108 or the gate insulating layer 109. When the insulating layer 104b is in an oxygen-excess state, the insulating layer 108 or the gate insulating layer 104b The oxygen contained in the oxide semiconductor layer 105 can also be supplied to the oxide semiconductor layer 105.

[0151] The transistor 150 of this embodiment is formed by the above steps. An insulating layer may be further formed on the transistor 150. 3D, an example in which a planarization insulating layer 110 is formed on the planarization insulating layer 150 is shown. Examples of the polymers include polyimide, acrylic resin, polyimide amide, and benzocyclobutene resin. Heat-resistant organic materials such as grease, polyamide, and epoxy resin can be used. In addition to the above organic materials, low-k materials, siloxane resins, PSG ( Phosphorus glass, BPSG (borophosphorus glass), etc. can be used. The planarization insulating layer 110 may be formed by stacking a plurality of insulating layers made of the same material.

[0152] A transistor using an oxide semiconductor for a semiconductor layer in which a channel is formed has a By supplying oxygen to the oxide semiconductor layer, the interface state density between the oxide semiconductor layer and the insulating layer can be reduced. As a result, carriers are generated at the interface between the oxide semiconductor layer and the insulating layer due to the operation of the transistor. This can prevent the trapping of electrons, resulting in a highly reliable transistor. do.

[0153] Furthermore, carriers may be generated due to oxygen vacancies in the oxide semiconductor layer. Oxygen vacancies in the oxide semiconductor layer are one of the causes of the generation of electrons, which are carriers, in the oxide semiconductor layer. As a result, the threshold voltage of the transistor shifts in the negative direction. The oxide semiconductor layer is preferably supplied with oxygen in sufficient amount, and the oxide semiconductor layer preferably contains excess oxygen. By including the oxygen vacancy, the density of oxygen vacancies in the oxide semiconductor layer can be reduced.

[0154] Note that the oxide semiconductor layer 105 may have a structure in which a plurality of oxide semiconductor layers are stacked. For example, the oxide semiconductor layer 105 may be formed by stacking a first oxide semiconductor layer and a second oxide semiconductor layer. As a result, metal oxides having different compositions are used for the first oxide semiconductor layer and the second oxide semiconductor layer. For example, a ternary metal oxide may be used for the first oxide semiconductor layer, and a ternary metal oxide may be used for the second oxide semiconductor layer. The conductor layer may be made of a binary metal oxide. The two oxide semiconductor layers may both be oxides of ternary metals.

[0155] In addition, the first oxide semiconductor layer and the second oxide semiconductor layer are made of the same constituent elements, and the composition of both layers is For example, the atomic ratio of the first oxide semiconductor layer may be set to In:Ga:Zn=1. :1:1, and the atomic ratio of the second oxide semiconductor layer is In:Ga:Zn=3:1:2. The atomic ratio of the first oxide semiconductor layer may be In:Ga:Zn=1:3:2, The atomic ratio of the second oxide semiconductor layer may be In:Ga:Zn=2:1:3.

[0156] At this time, the first oxide semiconductor layer and the second oxide semiconductor layer that are closer to the gate electrode (thickness The In and Ga contents of the oxide semiconductor layer on the channel side are preferably In>Ga. The In and Ga contents of the oxide semiconductor layer on the side farther from the back electrode (back channel side) are set to In≦ It is best to call it Ga.

[0157] In oxide semiconductors, the s orbitals of heavy metals mainly contribute to carrier conduction, and the In content Increasing the number of s orbitals tends to increase the overlap, so In>Ga The oxide with this composition has a higher mobility than the oxide with a composition of In≦Ga. , Ga has a higher oxygen vacancy formation energy than In, so oxygen vacancies are less likely to occur. Oxides with a composition of In≦Ga have more stable characteristics than oxides with a composition of In>Ga. Equipped with.

[0158] An oxide semiconductor with a composition of In>Ga is applied to the channel side, and In≦ By using an oxide semiconductor containing Ga, the mobility and reliability of the transistor can be improved. It will be possible to further increase

[0159] In addition, the first oxide semiconductor layer and the second oxide semiconductor layer may be formed using oxide semiconductors with different crystallinity. That is, a single crystal oxide semiconductor, a polycrystalline oxide semiconductor, an amorphous oxide semiconductor, The first oxide may be a conductor or a CAAC-OS. An amorphous oxide semiconductor is used for at least one of the semiconductor layer and the second oxide semiconductor layer. Then, the internal stress and the external stress of the oxide semiconductor layer 105 are alleviated, and the characteristics of the transistor are improved. This reduces variations in characteristics and also makes it possible to further improve the reliability of the transistor.

[0160] On the other hand, amorphous oxide semiconductors are prone to absorbing impurities that act as donors, such as hydrogen, and are also prone to oxidation. Therefore, the oxide semiconductor layer on the channel side is easily made n-type. It is preferable to use a crystalline oxide semiconductor such as CAAC-OS.

[0161] In addition, a bottom-gate channel-etched transistor is used as the transistor. In this case, if an amorphous oxide semiconductor is used on the back channel side, the source electrode and the drain electrode The etching process during electrode formation causes oxygen deficiency, making the material prone to becoming n-type. When a channel-etched transistor is used, the oxide semiconductor layer on the back channel side is It is preferable to use a crystalline oxide semiconductor.

[0162] In addition, the oxide semiconductor layer 105 has a stacked structure of three or more layers, and the oxide semiconductor layer 105 has a crystalline structure. A structure in which an amorphous oxide semiconductor layer is sandwiched between semiconductor layers may be used. A structure in which semiconductor layers and amorphous oxide semiconductor layers are alternately stacked may also be used.

[0163] In the case where the oxide semiconductor layer 105 has a stacked structure of a plurality of layers, the above structure can be formed by appropriately combining the layers. They can be used in combination.

[0164] In addition, the oxide semiconductor layer 105 has a stacked structure of multiple layers, and after each oxide semiconductor layer is formed, oxygen is added. Doping treatment may be performed. By performing oxygen doping treatment every time an oxide semiconductor layer is formed, This can enhance the effect of reducing oxygen vacancies in the oxide semiconductor.

[0165] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0166] (Embodiment 2) In this embodiment, a transistor 160 and a transistor 161 each having a different structure from the transistor 150 are used. The transistor 170 will now be described.

[0167] The transistor 160 shown in FIG. 4C has a structure in which the insulating layer 108 in the transistor 150 is replaced with a The difference is that an insulating layer 109 is formed instead. The transistor 160 is formed as follows. First, the insulating layer 107 is formed in the same manner as in the transistor 150. After introducing oxygen 121 into the insulating layer 107, a metal layer 119 is formed on the insulating layer 107 (FIG. 4(A)). ) In this embodiment, aluminum is used as the metal layer 119.

[0168] The metal layer 119 is preferably formed by a sputtering method, a vapor deposition method, a CVD method, or the like. The thickness of the metal layer 119 is preferably 3 nm or more and 10 nm or less. In this embodiment, aluminum is formed to a thickness of 5 nm.

[0169] The metal layer 119 formed on the insulating layer 107 will be formed by introducing oxygen later. The metal oxide layer (insulating layer 109) is made of a material that functions as a barrier layer of a transistor. The metal oxide layer is formed to remove impurities such as hydrogen and moisture, and oxygen from the transistor. A material with high barrier properties that blocks both The metal oxide layer can be formed using aluminum. In addition to aluminum, there are aluminum with magnesium addition, aluminum with titanium addition, and insulating a laminate of aluminum on layer 107 and magnesium on the aluminum, or A laminate of aluminum in contact with the insulating layer 107 and titanium in contact with the aluminum may be used. It is possible.

[0170] Next, oxygen 121 is introduced into the metal layer 119. The introduction of oxygen 121 is carried out by oxygen doping. In this embodiment, the oxygen 121 is introduced under an oxygen atmosphere. This is done by plasma treatment at 1000 K. This removes the oxide of the metal layer 119 from the insulating layer 109 is formed (see Figure 4(B)).

[0171] The insulating layer 109 formed by the oxygen doping treatment is an oxide layer having a stoichiometric composition. It is not necessary for the composition to contain AlO, and it may have some conductivity. x In the case of aluminum oxide represented by the formula: x is preferably 1 or more and 3.5 or less. If aluminum oxide is conductive, its resistivity ρ is 1×10 10 Ω m or more 1 x10 19 Ω·m or less, preferably 1×10 10 Ω m or more 1×10 18 Less than Ω m More preferably 1×10 11 Ω m or more 1×10 15 It is preferable to keep it at Ω·m or less. When the aluminum nitride has a resistivity in the above range, electrostatic breakdown of the transistor is prevented. This makes it possible to

[0172] After the insulating layer 109 is formed, heat treatment may be performed. The temperature for the heat treatment is, for example, 250° C. or higher. The heating temperature can be set to 600°C or lower, preferably 300°C or higher and 600°C or lower.

[0173] The transistor 160 is formed by the above steps. In this embodiment, a flat insulating layer is formed on the transistor 160. An example of forming an insulating film 110 is shown (see FIG. 4(D)).

[0174] The transistor 170 shown in FIG. 5 has an insulating layer 108 on the insulating layer 108 of the transistor 150. The insulating layer 109 is formed on the insulating layer 109 of the transistor 160. It can be formed in the same manner as 109.

[0175] Depending on the metal element that constitutes the insulating layer 109 (or the metal layer 119), an oxide semiconductor The insulating layer 109 becomes an impurity element that makes the oxide semiconductor layer 105 n-type. As shown in the transistor 170, the insulating layer 10 It is preferable that the insulating film 9 be formed as far away from the oxide semiconductor layer 105 as possible.

[0176] In addition, the insulating layer 102 or the gate insulating layer 104a and the insulating layer 108 or the insulating layer 109 are Has barrier properties against impurities such as hydrogen, moisture, hydrides, and hydroxides, as well as oxygen. It is preferable to form the insulating layer using a material having a barrier property. By sandwiching or wrapping the compound semiconductor layer 105 between layers having a barrier property, and prevents the intrusion of impurities from the oxide semiconductor layer 105, the insulating layer 107, and the gate insulating layer 1 This can prevent oxygen from being released from O4b.

[0177] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0178] (Embodiment 3) A semiconductor device having a display function (display) using the transistors exemplified in the above embodiments In addition, it is possible to manufacture a part of a driver circuit including a transistor. The entire display can be formed on the same substrate as the pixel section, forming a system-on-panel. In this embodiment, a display device including the transistors exemplified in the above embodiment will be described. An example will be described with reference to Figs. 6 and 7. Figs. 7(A) and 7(B) are the same as Fig. 6. FIG. 10 is a cross-sectional view showing the cross-sectional configuration of the portion indicated by the chain line MN in (B).

[0179] In FIG. 6A, a pixel portion 4002 provided on a first substrate 4001 is surrounded by a A sealant 4005 is provided and the substrate is sealed with a second substrate 4006. In A), the area surrounded by the sealant 4005 on the first substrate 4001 and In the different regions, a signal is formed of a single crystal semiconductor or a polycrystalline semiconductor on a separately prepared substrate. A signal line driver circuit 4003 and a scanning line driver circuit 4004 are mounted. Various signals are given to the driving circuit 4003, the scanning line driving circuit 4004, or the pixel portion 4002. and potential is FPC (Flexible printed circuit) 4018a , supplied by FPC4018b.

[0180] In FIG. 6B and FIG. 6C, a pixel portion 4002 provided on a first substrate 4001 A sealant 4005 is provided so as to surround the scanning line driver circuit 4004 . A second substrate 4006 is provided on the pixel portion 4002 and the scanning line driver circuit 4004. Therefore, the pixel portion 4002 and the scanning line driver circuit 4004 are connected to the first substrate 4001. The display element is sealed by a sealing material 4005 and a second substrate 4006. In (B) and (C) of FIG. 6, the first substrate 4001 is surrounded by a sealing material 4005. In a region different from the region where the semiconductor is embedded, a single-crystal semiconductor or polycrystalline semiconductor is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a semiconductor device is mounted on the semiconductor device. In the signal line driver circuit 4003, the scanning line driver circuit 4004, or the pixel portion 4002, The various signals and potentials are supplied from the FPC4018.

[0181] In addition, in FIG. 6B and FIG. 6C, a signal line driver circuit 4003 is separately formed. However, the present invention is not limited to this configuration. A circuit may be formed separately and mounted, or a part of a signal line driver circuit or a part of a scanning line driver circuit may be mounted. Alternatively, only the part may be formed separately and mounted.

[0182] The method of connecting the separately formed drive circuit is not particularly limited, and may be ip On Glass) method, wire bonding method, or TAB (Tape A The C This is an example in which a signal line driver circuit 4003 and a scanning line driver circuit 4004 are implemented by the OG method. FIG. 6(B) shows an example in which a signal line driver circuit 4003 is mounted by the COG method, and FIG. 6(C) shows an example in which a signal line driver circuit 4003 is mounted by the COG method. ) is an example in which the signal line driver circuit 4003 is mounted by the TAB method.

[0183] The display device also includes a panel in which a display element is sealed, and a controller for the panel. and modules in which ICs, etc., including the above are mounted.

[0184] In this specification, the term "display device" refers to an image display device, a display device, or an optical device. Also refers to connectors, such as FPC or TAB tape. Modules with TCP attached, TAB tape or TCP with a printed wiring board attached The IC (integrated circuit) is directly mounted on the module or display element using the COG method. All such modules are also included in the display device.

[0185] The pixel portion and the scanning line driver circuit provided on the first substrate have a plurality of transistors. The transistor described in the above embodiment can be applied to this semiconductor device.

[0186] The display element provided in the display device may be a liquid crystal element (also called a liquid crystal display element), a light-emitting element ( The light-emitting element emits light by applying a current or a voltage. This category includes elements whose brightness can be controlled, specifically inorganic EL (Electroluminescent) Luminescence, organic electroluminescence, etc. Also, electronic ink, etc. A display medium whose contrast changes depending on use can also be applied.

[0187] As shown in FIGS. 7A and 7B, the semiconductor device has a connection terminal electrode 4015 and a terminal electrode 4016. The connection terminal electrode 4015 and the terminal electrode 4016 are connected to an FPC 4018 The anisotropic conductive layer 4019 is electrically connected to a terminal of the semiconductor device.

[0188] The connection terminal electrode 4015 is formed from the same conductive layer as the first electrode layer 4030, and the terminal electrode 4 016 is a conductive layer that is the same as the source and drain electrodes of the transistors 4010 and 4011. It is formed by

[0189] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. 7A and 7B, the pixel portion 4002 includes a plurality of transistors. a transistor 4010 included in the scanning line driver circuit 4004; In FIG. 7A, the transistor 4010 and the transistor 4011 are 7B, an insulating layer 4020 is provided on the insulating layer 4024. An insulating layer 4021 is provided. Note that the insulating layer 4023 is an insulating layer that functions as a base layer.

[0190] In this embodiment, the transistors 4010 and 4011 are the same as those in the above embodiment. The transistor shown in FIG.

[0191] The transistor described in the above embodiment has suppressed fluctuations in electrical characteristics and is electrically stable. Therefore, the semiconductor device of this embodiment shown in FIGS. 7A and 7B is reliable. Therefore, a highly reliable semiconductor device can be provided.

[0192] In addition, in FIG. 7B, the transistor 4011 for the driver circuit is formed over the insulating layer 4024. 10 is an example in which a conductive layer 4017 is provided in a position overlapping with a channel formation region of the oxide semiconductor layer. In this embodiment, the conductive layer 4017 is formed using the same conductive layer as the first electrode layer 4030. The conductive layer 4017 is provided so as to overlap with a channel formation region of the oxide semiconductor layer. By doing so, the amount of change in the threshold voltage of the transistor 4011 before and after the BT test can be further reduced. In addition, the potential of the conductive layer 4017 can be further reduced. The conductive layer may be the same as or different from the gate electrode, and may function as a second gate electrode. The potential of the conductive layer 4017 can be set to GND, 0 V, or a floating state. It may be in a locking state.

[0193] The conductive layer 4017 also has a function of blocking an external electric field. (especially the function of preventing static electricity) The shielding function of the conductive layer 4017 prevents the influence of external electric fields such as static electricity. The conductive layer 4 can prevent the electrical characteristics of the transistor from fluctuating due to the influence of the conductive layer 4. 017 can be applied to any of the transistors described in the above embodiment modes.

[0194] The transistor 4010 provided in the pixel portion 4002 is electrically connected to a display element. The display element is not particularly limited as long as it can display, and various display elements can be used. can be used.

[0195] FIG. 7A shows an example of a liquid crystal display device using a liquid crystal element as a display element. The liquid crystal element 4013, which is a display element, has a first electrode layer 4030 and a second electrode layer 403 1 and a liquid crystal layer 4008. The liquid crystal layer 4008 is sandwiched between two layers that function as alignment films. The second electrode layer 4031 is provided with an insulating layer 4032 and an insulating layer 4033. The first electrode layer 4030 and the second electrode layer 4031 are disposed on the side of the liquid crystal layer 4006. The signal is superimposed via 4008.

[0196] The spacers 4035 are columnar spacers obtained by selectively etching the insulating layer. and the distance (cell gap) between the first electrode layer 4030 and the second electrode layer 4031 is controlled. A spherical spacer may also be used.

[0197] When liquid crystal elements are used as display elements, thermotropic liquid crystals, low molecular weight liquid crystals, polymer liquid crystals, etc. The liquid crystals that can be used include polymer dispersed liquid crystals, ferroelectric liquid crystals, and antiferroelectric liquid crystals. Depending on the conditions, the liquid crystal material can be in a cholesteric phase, a smectic phase, a cubic phase, or a chiral phase. It shows nematic phase, isotropic phase, etc.

[0198] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so the temperature range needs to be improved. To achieve this, a liquid crystal composition containing 5% by weight or more of a chiral agent is used in the liquid crystal layer. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent has a short response time of 1 msec or less. Since the liquid crystal display is optically isotropic, no alignment treatment is required and the viewing angle dependency is small. Since there is no need to provide a rubbing treatment, the This can prevent electrostatic breakdown, which may occur during the manufacturing process, thereby reducing defects and damage to the liquid crystal display device. Therefore, it is possible to improve the productivity of the liquid crystal display device. The electrical characteristics of a transistor that uses a conductor layer are significantly affected by static electricity. Therefore, the transistor using an oxide semiconductor layer may fluctuate and deviate from the design range. It is more effective to use a blue phase liquid crystal material in a liquid crystal display device having the above structure.

[0199] The specific resistance of the liquid crystal material is 1×10 9 Ω·cm or more, preferably 1×10 11 Ω·cm or more, and more preferably 1×10 12 Ω·cm or more. The resistivity values in this document are those measured at 20°C.

[0200] The transistor including the highly purified oxide semiconductor layer used in this embodiment has an off state. Therefore, the current value (off-state current value) at the time of the image signal or the like can be reduced. The data retention time can be extended, and the write interval can also be set longer when the power is on. This reduces the frequency of refresh operations, which has the effect of reducing power consumption. It plays a key role.

[0201] The size of the storage capacitor provided in the liquid crystal display device is determined by the lead of the transistor arranged in the pixel portion. It is set so that the charge can be held for a predetermined period, taking into consideration the current and other factors. The size of the high-purity oxide semiconductor layer can be set in consideration of the off-state current of the transistor and the like. By using a transistor having It is sufficient to provide a storage capacitor having a capacity preferably 1 / 5 or less of the capacity of the storage capacitor.

[0202] Furthermore, the above-described transistor using an oxide semiconductor has a relatively high field-effect mobility. Therefore, the above transistors can be used in the pixel portion of a semiconductor device having a display function. By using transistors, high quality images can be provided. Since it is possible to separately manufacture the driver circuit section and the pixel section, The number of points can be reduced.

[0203] There are two types of LCD displays: TN (Twisted Nematic) mode, IPS (In-P lane-Switching) mode, FFS (Fringe Field Switching) mode ching) mode, ASM(Axially Symmetric aligned) Micro-cell mode, OCB (Optical Compensated B) refrigeration mode, FLC (Ferroelectric Liquid d Crystal) mode, AFLC (AntiFerroelectric Liq. uid Crystal) mode can be used.

[0204] Furthermore, normally black type liquid crystal display devices, for example, those employing vertical alignment (VA) mode The liquid crystal display device may be a transmission type liquid crystal display device. This is a method of controlling the arrangement of crystal molecules, and when no voltage is applied, In this method, the liquid crystal molecules are aligned vertically. There are several types of vertical alignment modes: However, for example, MVA (Multi-Domain Vertical Alignment) nt) mode, PVA (Patterned Vertical Alignment) mode, ASV (Advanced Super View) mode, etc. It is also possible to divide a pixel into several regions (subpixels) and display each region separately. Multi-domain or multi-domain design that is designed to tilt the molecule in the direction of The method mentioned can be used.

[0205] In addition, in display devices, black matrices (light-shielding layers), polarizing members, phase difference members, reflecting members, Optical members (optical substrates) such as a protection member are provided as appropriate. For example, a polarizing substrate and a retardation substrate are provided as appropriate. Alternatively, a backlight or a sidelight may be used as the light source. It's fine.

[0206] In addition, the display method in the pixel section uses the progressive method, interlace method, etc. In addition, the color elements controlled by pixels when displaying colors are RGB (R is It is not limited to the three colors (red, green, and blue). For example, RGBW (W stands for white). , or RGB plus one or more colors such as yellow, cyan, magenta, etc. The size of the display area may differ for each dot of the color element. The present invention is not limited to display devices with a monochromatic display, but can also be applied to display devices with a monochrome display. can.

[0207] Furthermore, a light-emitting element that utilizes electroluminescence is used as a display element included in the display device. The light-emitting element using electroluminescence can be applied to a light-emitting material They are distinguished by whether they are organic or inorganic compounds, and generally, the former are organic E The latter is called an inorganic EL element.

[0208] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into the layers containing the light-emitting organic compounds, causing a current to flow. The recombination of the electrons and holes creates an excited state in the light-emitting organic compound. The excited state is then converted to the ground state, at which point light is emitted. Such a light-emitting element is called a current-excited light-emitting element.

[0209] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor interaction that utilizes the donor and acceptor levels. Thin-film inorganic EL devices sandwich the light-emitting layer between dielectric layers. Furthermore, this structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0210] The light emitting element only needs to have at least one of the pair of electrodes transparent in order to extract light. Then, a transistor and a light emitting element are formed on the substrate, and light is extracted from the surface opposite the substrate. Top emission, bottom emission where light is extracted from the surface on the substrate side, and surface on the substrate side and the opposite side of the substrate There are light emitting devices with a double-sided emission structure that extracts light from the It is possible.

[0211] FIG. 7B shows an example of a light-emitting device using a light-emitting element as a display element. The element 4513 is electrically connected to the transistor 4010 provided in the pixel portion 4002. The light-emitting element 4513 includes a first electrode layer 4030, an electroluminescent layer 4511, a second electrode layer 4032, a third electrode layer 4033, a fourth electrode layer 4034, a fourth electrode layer 4035, a fourth electrode layer 4036, a fourth electrode layer 4037, a fifth electrode layer 4038, a sixth electrode layer 4039 ... The light-emitting element 4513 has a stacked structure of two electrode layers 4031, but is not limited to the structure shown. The configuration of the light emitting element 4513 can be changed as needed to suit the direction of the light to be extracted. do.

[0212] The partition wall 4510 is formed using an organic insulating material or an inorganic insulating material, particularly a photosensitive resin. An opening is formed on the first electrode layer 4030 using a material, and the sidewall of the opening has a continuous curved surface. It is preferable to form the inclined surface so as to have a certain slope.

[0213] The electroluminescent layer 4511 may be composed of a single layer or a plurality of layers stacked. It doesn't matter whether it's done or not.

[0214] The second electrode layer is formed to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4513. A protective layer may be formed on the insulating film 4031 and the partition wall 4510. The protective layer may be made of silicon nitride. , silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxide nitride, nitride The first substrate 4001 can be formed with aluminum oxide, DLC film, etc. A filler 4514 is filled in the space sealed by the second substrate 4006 and the sealant 4005. In this way, the container is airtight and does not get exposed to the outside air. Use less protective film (laminating film, UV curing resin film, etc.) and cover material. Packaging (encapsulation) is preferred.

[0215] Filler 4514 can be an inert gas such as nitrogen or argon, or an ultraviolet curing resin or Thermosetting resins can be used, such as PVC (polyvinyl chloride), acrylic resin, Imide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. For example, nitrogen can be used as a filler. That's fine.

[0216] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, an anti-reflection film may be provided on the polarizing plate or the circular polarizing plate. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0217] A first electrode layer and a second electrode layer (a pixel electrode layer, a common electrode layer, a pair of electrodes) that apply a voltage to the display element In the case of a light-emitting diode (also called a counter electrode layer), the direction of the light to be extracted, the location of the electrode layer, and The light transmission property or reflectivity can be selected depending on the pattern structure of the electrode layer.

[0218] The first electrode layer 4030 and the second electrode layer 4031 are made of an indium oxide containing tungsten oxide. oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide (hereinafter referred to as ITO) ), indium zinc oxide, indium tin oxide with silicon oxide added, etc. A conductive material that can be used can be used.

[0219] The first electrode layer 4030 and the second electrode layer 4031 are made of tungsten (W) and molybdenum. (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (N b), Tantalum (Ta), Chromium (Cr), Cobalt (Co), Nickel (Ni), Titanium Metals such as titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), and silver (Ag), It can be formed by using one or more of the metals, alloys thereof, or metal nitrides thereof. Cut.

[0220] The first electrode layer 4030 and the second electrode layer 4031 are made of a conductive polymer (conductive polymer). The conductive polymer can be formed using a conductive composition containing a conductive polymer. For example, a so-called π-electron conjugated conductive polymer can be used. or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or or a copolymer consisting of two or more of aniline, pyrrole and thiophene, or a derivative thereof Examples include conductors.

[0221] In addition, since transistors are easily damaged by static electricity, a protection circuit for protecting the drive circuit is required. It is preferable that the protection circuit is configured using a non-linear element.

[0222] As described above, by using the transistor described in the above embodiment, a display function A highly reliable semiconductor device can be provided.

[0223] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0224] (Fourth embodiment) An image sensor that reads information about an object using the transistor described in the above embodiment A functional semiconductor device can be manufactured.

[0225] FIG. 8A shows an example of a semiconductor device having an image sensor function. 8(A) is an equivalent circuit of the photosensor, and FIG. 8(B) is a cross-sectional view showing a part of the photosensor.

[0226] The photodiode 602 has one electrode connected to a photodiode reset signal line 658 and the other One electrode is electrically connected to the gate of transistor 640. One of the source and drain is connected to the photosensor reference signal line 672, and the other of the source and drain is connected to the photosensor reference signal line 673. The other terminal is electrically connected to one of the source and drain terminals of the transistor 656. The transistor 656 has a gate connected to a gate signal line 659 and a source or drain connected to a photodiode. The signal line 671 is electrically connected to the sensor output signal line 671.

[0227] Note that in the circuit diagrams in this specification, a transistor including an oxide semiconductor layer is not clearly shown. To make it easier to distinguish, the symbol for a transistor using an oxide semiconductor layer is written as “OS.” In FIG. 8A, the transistor 640 and the transistor 656 are the same as those in the above embodiment. The transistor shown in FIG. 1 can be applied to a semiconductor device using an oxide semiconductor for a semiconductor layer where a channel is formed. In this embodiment, the transistor 150 described in Embodiment 1 is An example of applying a transistor having a similar structure is shown. The transistor 640 is an oxide semiconductor. A bottom-gate inverted switch with an insulating layer functioning as a channel protection layer on a conductor layer. It is a tag-type transistor.

[0228] FIG. 8B shows the photodiode 602 and the transistor 640 in the photosensor. 6 is a cross-sectional view showing a configuration example, in which a sensor and a TFT substrate are provided on a substrate 601 (TFT substrate) having an insulating surface. A photodiode 602 and a transistor 640 are provided to function as a photodiode. A substrate 613 is provided on the diode 602 and the transistor 640 using an adhesive layer 608. It is being done.

[0229] An insulating layer 633 and an insulating layer 634 are provided over the transistor 640. The electrode 602 is provided on an insulating layer 633, and an electrode 641a and an electrode 641b are formed on the insulating layer 633. Between the electrode 641b and the electrode layer 642 provided on the insulating layer 634, from the insulating layer 633 side A first semiconductor layer 606a, a second semiconductor layer 606b, and a third semiconductor layer 606c are stacked in this order. It has a structure.

[0230] The electrode 641b is electrically connected to the conductive layer 643 formed on the insulating layer 634, and the electrode layer 641b is electrically connected to the conductive layer 643 formed on the insulating layer 634. 42 is electrically connected to the conductive layer 645 via the electrode 641a. The photodiode 602 is electrically connected to the gate electrode of the transistor 640. It is electrically connected to the transistor 640 .

[0231] Here, the first semiconductor layer 606a is a semiconductor layer having a p-type conductivity, and the second semiconductor layer 606b is a high resistance semiconductor layer (i-type semiconductor layer), and the third semiconductor layer 606c is an n-type A pin-type photodiode in which semiconductor layers having different conductivity types are stacked is shown as an example.

[0232] The first semiconductor layer 606a is a p-type semiconductor layer, and is made of amorphous silicon containing an impurity element that imparts p-type conductivity. The first semiconductor layer 606a can be formed of silicon. Using semiconductor material gas containing pure elements (e.g., boron (B)), the plasma CVD method is used. Silane (SiH4) can be used as the semiconductor material gas. 2H6, SiH2Cl2, SiHCl3, SiCl4, SiF4, etc. may also be used. After forming amorphous silicon that does not contain impurity elements, the diffusion method or ion implantation method is used. Impurity elements may be introduced into the amorphous silicon by ion implantation or the like. After the pure element is introduced, the impurity element may be diffused by heating or the like. The amorphous silicon can be formed by LPCVD, vapor phase growth, or spat. The thickness of the first semiconductor layer 606a is 10 nm to 50 nm. It is preferable to form it so that it faces downward.

[0233] The second semiconductor layer 606b is an i-type semiconductor layer (intrinsic semiconductor layer) and is made of amorphous silicon. The second semiconductor layer 606b is formed by using a semiconductor material gas. The semiconductor material gas is silane (S Alternatively, Si2H6, SiH2Cl2, SiHCl3, SiC The second semiconductor layer 606b may be formed by LPCVD, vapor phase The second semiconductor layer 606b may be grown by a growth method, a sputtering method, or the like. It is preferable to form the film so that the thickness is between 1000 nm and 1000 nm.

[0234] The third semiconductor layer 606c is an n-type semiconductor layer and is an amorphous layer containing an impurity element that imparts n-type conductivity. The third semiconductor layer 606c is formed of silicon. It is formed by plasma CVD using semiconductor material gas containing (e.g., phosphorus (P)). Silane (SiH4) can be used as the semiconductor material gas. Alternatively, Si2H6, S iH2Cl2, SiHCl3, SiCl4, SiF4, etc. may also be used. After forming amorphous silicon that does not contain silicon, the amorphous silicon is Impurity elements may be introduced into amorphous silicon by ion implantation or the like. After the introduction, the impurity element is preferably diffused by heating or the like. The method for forming the base silicon is LPCVD, vapor phase growth, or sputtering. The thickness of the third semiconductor layer 606c is 20 nm or more and 200 nm or less. It is preferable to form it as follows.

[0235] The first semiconductor layer 606a, the second semiconductor layer 606b, and the third semiconductor layer 606c are Instead of an amorphous semiconductor, a polycrystalline semiconductor may be used. Semi-amorphous semiconductor (SAS) ctor) may be used.

[0236] In addition, the mobility of holes generated by the photoelectric effect is smaller than that of electrons, so the pin-type Photodiodes exhibit better characteristics when the p-type semiconductor layer side is used as the light receiving surface. From the surface of the substrate 601 on which the in-type photodiode is formed to the photodiode 602 The example shows how the light 622 received by the semiconductor layer is converted into an electrical signal. Since light from the semiconductor layer side having the conductivity type of the It is also possible to use the n-type semiconductor layer side as the light receiving surface.

[0237] The insulating layers 633 and 634 function as planarizing layers to reduce surface irregularities. The insulating layer 633 and the insulating layer 634 are preferably made of, for example, polyimide or acrylic. Heat-resistant organic insulating materials such as resin, benzocyclobutene resin, polyamide, and epoxy resin In addition to the organic insulating materials, low-k materials can also be used. materials), siloxane resin, PSG (phosphor glass), BPSG (borophosphor glass), etc. A single layer or a laminate can be used.

[0238] By detecting the light incident on the photodiode 602, information on the detected object is read. It is possible to read the information of the detected object using a light source such as a backlight. It is possible.

[0239] The transistor described in the above embodiment has suppressed fluctuations in electrical characteristics and is electrically stable. Therefore, a highly reliable semiconductor device including the transistor 640 having stable electrical characteristics can be obtained. Furthermore, highly reliable semiconductor devices can be manufactured with a high yield. High productivity can be achieved.

[0240] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0241] (Embodiment 5) The semiconductor device disclosed in this specification can be applied to various electronic devices (including gaming machines). As electronic equipment, television equipment (also known as television or television receiver) (hereinafter referred to as "computer monitors"), digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, portable information terminals, sound players, gaming machines (Pachinko machines, slot machines, etc.) and game cabinets. Examples are shown in Figures 9 and 10.

[0242] FIG. 9A shows a table 9000 having a display unit. A display unit 9003 is built into the body 9001, and images are displayed on the display unit 9003. It is possible to support the housing 9001 with four legs 9002. The housing 9001 also has a power cord 9005 for power supply.

[0243] The semiconductor device described in any of Embodiments 1 to 4 can be used for the display portion 9003. This makes it possible to provide high reliability to electronic devices.

[0244] The display unit 9003 has a touch input function, and the display unit 9003 of the table 9000 By touching the displayed display button 9004 with a finger or the like, the screen can be operated or information can be input. It can also communicate with other home appliances or control them, making it possible to It may also be a control device that controls other home appliances by operation. If a semiconductor device having an image sensor function as shown in FIG. 3 is used, the display portion 9003 can be touched. It can have input functionality.

[0245] In addition, the screen of the display unit 9003 can be vertically fixed to the floor by a hinge provided in the housing 9001. It can also be set upright and used as a television set. If you install a large screen television, the free space will be narrow, but it is possible to install it on a table. If the display unit is built in, the space in the room can be used more effectively.

[0246] 9B shows a television device 9100. The television device 9100 includes: A display unit 9103 is incorporated in the housing 9101, and images are displayed on the display unit 9103. In this example, the housing 9101 is supported by a stand 9105. This shows the progress.

[0247] The television device 9100 can be operated using an operation switch provided on the housing 9101 or a separate remote control. This can be done by the remote control operation device 9110. The channel and volume can be controlled by the 9109, and the information displayed on the display 9103 is In addition, the remote control unit 9110 can be used to operate the video. A display unit 9107 for displaying information output from 9110 may be provided.

[0248] The television device 9100 shown in FIG. 9(B) includes a receiver, a modem, and the like. The vision device 9100 can receive general television broadcasts using a receiver, and By connecting to a wired or wireless communication network via a modem, Information from sender to receiver) or two-way (between sender and receiver, or between receivers) It is also possible to carry out communication.

[0249] The semiconductor device described in any of Embodiments 1 to 4 is used for the display portions 9103 and 9107. This makes it possible to provide high reliability to the television device and the remote control. can be done.

[0250] FIG. 9C shows a computer, which includes a main body 9201, a housing 9202, a display unit 9203, and a keyboard. It includes a board 9204, an external connection port 9205, a pointing device 9206, and the like. The computer displays a semiconductor device manufactured using one embodiment of the present invention on the display portion 9203. By using the semiconductor device described in the above embodiment, reliability can be improved. It is possible to make it a high-performance computer.

[0251] Figures 10(A) and 10(B) show a foldable tablet terminal. 9 shows the tablet terminal in an open state, and the tablet terminal includes a housing 9630, a display unit 9631a, and a display unit A display unit 9631 having a display mode changeover switch 9626, a power switch Switch 9627, power saving mode switch 9625, fastener 9629, operation switch 9 628, has.

[0252] The semiconductor device described in any of Embodiments 1 to 4 includes a display portion 9631a, a display portion 9631b, a display portion 9631c, a display portion 9631d, a display portion 9631e, a display portion 9631f, a display portion 9631g, a display portion 9631h, a display portion 9631i, a display portion 9631j ... b), making it possible to create a highly reliable tablet-type terminal.

[0253] A part of the display unit 9631a can be used as a touch panel area 9632a. By touching the operation keys 9638, data can be input. In 1a, for example, half of the area has a display function only, and the other half The display unit 963 has a touch panel function, but is not limited to this. The entire area of the display unit 96 may have a touch panel function. The entire surface of 31a is displayed as a keyboard button to serve as a touch panel, and the display part 9631b is displayed. It can be used as a screen.

[0254] In addition, in the display unit 9631b, as in the display unit 9631a, a part of the display unit 9631b The area 9632b of the touch panel can be used as the keyboard of the touch panel. By touching the area where the display switch button 9639 is displayed with your finger or a stylus, A keyboard can be displayed on the display portion 9631b.

[0255] In addition, touch panel area 9632a and touch panel area 9632b can be touched simultaneously. You can also input characters using the touchpad.

[0256] A display mode changeover switch 9626 changes the display orientation between portrait and landscape. You can select between black and white and color display. The 9625 uses a built-in light sensor in the tablet device to detect external light during use. The display brightness can be optimized according to the amount of light. In addition, other detection devices such as gyro, acceleration sensor, etc. that detect tilt are also included. It may be stored.

[0257] FIG. 10A shows an example in which the display area of the display portion 9631b is the same as that of the display portion 9631a. However, there is no particular limitation, and one size may be different from the other, and the display For example, one display panel may be capable of displaying images with higher resolution than the other. It may also be possible to use the following.

[0258] FIG. 10B shows the tablet terminal in a closed state, and the tablet terminal includes a housing 9630 and a solar cell 96 33, a charge / discharge control circuit 9634, a battery 9635, and a DC / DC converter 9636 10B, a battery 9635 is used as an example of the charge / discharge control circuit 9634. , a configuration having a DC-DC converter 9636 is shown.

[0259] In addition, since the tablet device can be folded in half, the housing 9630 can be folded when not in use. Therefore, the display portions 9631a and 9631b can be protected, and thus the display portions 9631a and 9631b can be withstood. This makes it possible to provide a tablet terminal that is highly durable and reliable even from the perspective of long-term use.

[0260] In addition, the tablet terminals shown in Figs. 10(A) and 10(B) can also store various information. Functions that display information (still images, videos, text images, etc.), calendars, dates, or times, etc. The function to display the information on the display unit, and the function to operate or edit the information displayed on the display unit by touch input. It has the function of controlling the processing by various software (programs), etc. This can be done.

[0261] The solar cell 9633 attached to the surface of the tablet terminal supplies power to the touch panel, The solar cell 9633 can be supplied to a display unit, a video signal processor, or the like. The battery 9635 can be efficiently charged by the battery 9630. The battery 9635 is preferably a lithium The use of ion batteries has advantages such as miniaturization.

[0262] The configuration and operation of the charge / discharge control circuit 9634 shown in FIG. 10(B) will be described with reference to FIG. ) shows a block diagram and explains. In FIG. 10(C), a solar cell 9633, a battery 96 35, DC-DC converter 9636, converter 9637, switches SW1 to SW3, The display unit 9631 is shown, along with the battery 9635 and the DC-DC converter 9636. The converter 9637 and the switches SW1 to SW3 constitute the charge / discharge control circuit shown in FIG. This corresponds to road 9634.

[0263] First, an example of operation when power is generated by the solar cell 9633 using external light will be described. The power generated by the solar cell is converted to a voltage to charge the Battery 9635. The voltage is increased or decreased by a C converter 9636. When power is being used from the battery 9633, the switch SW1 is turned on and the converter 96 37 increases or decreases the voltage to the voltage required for the display unit 9631. When not displaying in 31, turn SW1 off and SW2 on to charge the battery. 35 charging configuration.

[0264] The solar cell 9633 is shown as an example of a power generating means, but is not particularly limited thereto. Other power generation methods such as piezoelectric elements (piezoelectric elements) and thermoelectric elements (Peltier elements) For example, it may be configured to transmit and receive power wirelessly (contactlessly). A wireless power transmission module that charges by transmitting power, or a configuration that combines other charging methods It may also be possible to use the following.

[0265] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is. [Explanation of symbols]

[0266] 101 Substrate 102 Insulating layer 103 gate electrode 104 Gate insulating layer 105 Oxide semiconductor layer 107 Insulating layer 108 Insulating layer 109 Insulating Layer 110 Planarizing insulating layer 111 Insulating layer 115 Oxide semiconductor layer 117 Conductive Layer 119 Metal layer 121 Oxygen 122 Oxygen 150 transistors 160 transistors 170 transistors 201 parts 202 parts 601 Substrate 602 Photodiode 608 Adhesive layer 613 Substrate 622 light 633 Insulation Layer 634 Insulating layer 640 transistors 642 Electrode layer 643 Conductive Layer 645 Conductive Layer 656 Transistor 658 Photodiode reset signal line 659 Gate signal line 671 Photo sensor output signal line 672 Photo sensor reference signal line 4001 board 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 board 4008 Liquid crystal layer 4010 transistor 4011 transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4017 Conductive layer 4018 FPC 4019 Anisotropic conductive layer 4020 Insulation layer 4021 Planarization layer 4023 Insulation layer 4024 Insulation layer 4030 Electrode layer 4031 Electrode layer 4032 Insulation layer 4033 Insulation layer 4035 Spacer 4510 Bulkhead 4511 Electroluminescent layer 4513 Light-emitting element 4514 Filling material 9000 tables 9001 Case 9002 Legs 9003 Display section 9004 Display button 9005 Power Cord 9100 Television equipment 9101 Housing 9103 Display section 9105 Stand 9107 Display section 9109 Operation key 9110 Remote control device 9201 Main Unit 9202 Housing 9203 Display section 9204 keyboard 9205 External connection port 9206 Pointing Device 9625 Switch 9626 Switch 9627 Power Switch 9628 Operation Switch 9629 Fasteners 9630 chassis 9631 Display section 9633 Solar Cells 9634 Charge / Discharge Control Circuit 9635 Battery 9636 DC / DC Converter 9637 Converter 9638 Operation key 9639 Button 104a Gate insulating layer 104b Gate insulating layer 106a Source electrode 106b Drain electrode 4018a FPC 4018b FPC 606a Semiconductor layer 606b Semiconductor layer 606c Semiconductor layer 641a electrode 641b Electrode 9631a Display section 9631b Display section 9632a area 9632b area

Claims

1. a first conductive film; a silicon nitride film having a region located above the first conductive film; a silicon oxide film having a region located above the silicon nitride film; a first oxide semiconductor film having a region located above the silicon oxide film; a second oxide semiconductor film having a region located above the first oxide semiconductor film; a second conductive film having a region located above the second oxide semiconductor film; a first insulating film having a region located above the second oxide semiconductor film; a second insulating film having a region located above the first insulating film; a pixel electrode having a region located above the second conductive film, a region of the second conductive film that overlaps with the first oxide semiconductor film has a region that does not overlap with the first conductive film; a region of the second conductive film that does not overlap with the first oxide semiconductor film includes a region that is in contact with the pixel electrode; the first oxide semiconductor film and the second oxide semiconductor film contain In, Ga, and Zn; a ratio of In in an atomic ratio of In to Ga in the first oxide semiconductor film is larger than a ratio of In in an atomic ratio of In to Ga in the second oxide semiconductor film; the crystallinity of the first oxide semiconductor film is different from the crystallinity of the second oxide semiconductor film; the second oxide semiconductor film has a plurality of crystals whose c-axes are aligned in parallel to each other.

2. a first conductive film; a silicon nitride film having a region located above the first conductive film; a silicon oxide film having a region located above the silicon nitride film; a first oxide semiconductor film having a region located above the silicon oxide film; a second oxide semiconductor film having a region located above the first oxide semiconductor film; a second conductive film having a region located above the second oxide semiconductor film; a first insulating film having a region located above the second oxide semiconductor film; a second insulating film having a region located above the first insulating film; a pixel electrode having a region located above the second conductive film, the first oxide semiconductor film has an end portion in contact with the second conductive film in a region where the first oxide semiconductor film does not overlap with the first conductive film in a cross-sectional view in a channel length direction; a region of the second conductive film that does not overlap with the first oxide semiconductor film includes a region that is in contact with the pixel electrode; the first oxide semiconductor film and the second oxide semiconductor film contain In, Ga, and Zn; a ratio of In in an atomic ratio of In to Ga in the first oxide semiconductor film is larger than a ratio of In in an atomic ratio of In to Ga in the second oxide semiconductor film; the crystallinity of the first oxide semiconductor film is different from the crystallinity of the second oxide semiconductor film; the second oxide semiconductor film has a plurality of crystals whose c-axes are aligned in parallel to each other.

3. A display device according to claim 1 or 2, wherein the first oxide semiconductor film has an amorphous oxide semiconductor.

Images