Semiconductor Devices

Abstract

To provide a technology for manufacturing a semiconductor device that facilitates etching control when a contact hole is formed.SOLUTION: A semiconductor device comprises: a semiconductor layer formed on at least an insulation surface; a first insulating layer formed on the semiconductor layer; a gate electrode formed on the first insulating layer; and a second insulating layer formed on the gate electrode. An opening is formed at least on the semiconductor layer and the second insulating layer to partially expose the insulation surface. The semiconductor device comprises a conductive layer formed on the second insulating layer via the opening. Here, the conductive layer is electrically connected with the semiconductor layer on a lateral face of the opening formed on the semiconductor layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof. This refers to any device that can function by utilizing the properties of semiconductors. [Background technology]

[0002] In recent years, thin film transistors (TFTs) have been formed on substrates with insulating surfaces such as glass. The production of semiconductor devices that use thin film transistors as switching elements etc. is becoming more and more popular. The thin film transistor is formed on a substrate having an insulating surface by a CVD method, a photolithography method, etc. An island-shaped semiconductor film is formed by a film forming process or the like, and a part of the island-shaped semiconductor film is formed as a transistor. The region is provided to be used as a channel forming region (for example, Patent Document 1).

[0003] A schematic cross-sectional view of a thin film transistor is shown in Figure 21. As shown in Figure 21, The substrate 30 has an insulating layer 31 formed thereon, which functions as a base film. a channel forming region 32a, an impurity region 32b functioning as a source region and a drain region, A semiconductor layer 32 having a gate insulating layer 32c is formed on the semiconductor layer 32 and the insulating layer 31. An insulating layer 33 functioning as a gate electrode is formed on the insulating layer 33. An insulating layer 203 is formed on the conductive layer 34, and an impurity region is formed on the insulating layer 203. Wiring 204 is formed to electrically connect 32b and 32c. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 08-018055 Summary of the Invention [Problem to be solved by the invention]

[0005] In the structure of FIG. 21, in order to electrically connect the wiring to the surface of the source region or the drain region, It is considered necessary to form a semiconductor layer that will become a source region or a drain region at the bottom of the opening. This made it difficult to control the etching when forming openings in the insulating layer. This is a particularly significant problem when the semiconductor layer is formed as a thin film of 50 nm or less.

[0006] The present invention is a technology to solve such problems, and A technique for manufacturing a semiconductor device that can easily control switching is proposed. [Means for solving the problem]

[0007] The semiconductor device of the present invention comprises at least a semiconductor layer formed on an insulating surface and a metal oxide film formed on the semiconductor layer. a first insulating layer formed on the first insulating layer, a gate electrode formed on the first insulating layer, and a gate electrode formed on the gate electrode. and a second insulating layer formed on the semiconductor layer, and an opening is formed in at least the semiconductor layer and the second insulating layer. The insulating surface is partially exposed through the opening, and a metal oxide film is formed on the second insulating layer. and a conductive layer. Here, the conductive layer is formed on the side of a contact hole formed in the semiconductor layer. The surface of the semiconductor layer is electrically connected to the semiconductor layer. In other words, the upper area of the opening formed in the semiconductor layer is The upper surface area of the opening formed in the second insulating layer is smaller than the upper surface area of the conductive layer and the semiconductor The layer is electrically connected to the side surface of the contact hole formed in the semiconductor layer and the surface of the semiconductor layer. The power supply may be electrically connected.

[0008] The semiconductor device of the present invention includes a semiconductor layer formed on an insulating surface, and a first insulating layer formed on the semiconductor layer. forming a gate electrode on the first insulating layer; forming a second insulating layer on the gate electrode; an opening in at least the semiconductor layer and the second insulating layer that partially exposes the insulating surface; and forming a conductive layer on the insulating surface and the second insulating layer through the opening. It can be made by

[0009] The semiconductor device of the present invention further comprises a first insulating layer formed on a substrate, and a second insulating layer formed on the first insulating layer. forming an insulating layer, forming a semiconductor layer on the second insulating layer, and forming a third insulating layer on the semiconductor layer; Then, a gate electrode is formed on the third insulating layer, a fourth insulating layer is formed on the gate electrode, and The surface of the first insulating layer is partially exposed to at least the second insulating layer, the semiconductor layer and the fourth insulating layer. and forming an opening through which a conductive layer is formed on the surface of the first insulating layer and the fourth insulating layer. It can be produced by forming

[0010] The semiconductor device of the present invention further comprises a first insulating layer formed on a substrate, and a second insulating layer formed on the first insulating layer. forming an insulating layer, forming a semiconductor layer on the second insulating layer, and forming a third insulating layer on the semiconductor layer; a gate electrode formed on the third insulating layer; a fourth insulating layer formed on the gate electrode; A resist is formed on the insulating layer, and a semiconductor is formed on at least the fourth insulating layer using the resist as a mask. A first opening is formed to partially expose the surface of the conductor layer, and at least The second insulating layer, the semiconductor layer and the fourth insulating layer are also etched to form the first insulating layer surface and and forming a second opening that partially exposes the surface of the semiconductor layer, and The conductive layer is formed on the insulating layer surface, the semiconductor layer surface, and the fourth insulating layer. The first opening can be formed by wet etching, and the second opening can be formed by wet etching. can be formed by dry etching.

[0011] The semiconductor device of the present invention further comprises a first insulating layer formed on a substrate, and a second insulating layer formed on the first insulating layer. forming an insulating layer, forming a semiconductor layer on the second insulating layer, and forming a third insulating layer on the semiconductor layer; a gate electrode formed on the third insulating layer; a fourth insulating layer formed on the gate electrode; A resist is formed on the insulating layer, and a semiconductor is formed on at least the fourth insulating layer using the resist as a mask. A first opening is formed to partially expose the surface of the conductor layer, and the resist is etched to expose the first opening. The resist is then receded, and at least the second insulating layer, the semiconductor layer, and the fourth insulating layer are formed using the resist as a mask. a second insulating layer that partially exposes the first insulating layer surface and the semiconductor layer surface; and forming an opening, and exposing the first insulating layer surface, the semiconductor layer surface, and the fourth insulating layer surface through the second opening. The first opening and the second opening can be formed by forming a conductive layer on an insulating layer. The second opening can be formed by dry etching. [Effects of the Invention]

[0012] In the present invention, since it is not necessary to stop etching at the surface of the semiconductor film, the contact hole The etching process during the formation of the semiconductor layer can be easily controlled. The side of the contact hole can be electrically connected to the source electrode or the drain electrode. Therefore, a semiconductor device in which deterioration of characteristics is suppressed can be easily manufactured. [Brief explanation of the drawings]

[0013] [Figure 1] 1A and 1B are a top view and a cross-sectional view illustrating a structure of a semiconductor device of the present invention. [Figure 2] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device of the present invention. [Figure 3] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device of the present invention. [Figure 4] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device of the present invention. [Figure 5] 1A and 1B are a top view and a cross-sectional view illustrating a structure of a semiconductor device of the present invention. [Figure 6] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device of the present invention. [Figure 7] 1A and 1B are a top view and a cross-sectional view illustrating a structure of a semiconductor device of the present invention. [Figure 8] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device of the present invention. [Figure 9] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device of the present invention. [Figure 10] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device of the present invention. [Figure 11] 1A and 1B are a top view and a cross-sectional view illustrating a structure of a semiconductor device of the present invention. [Figure 12] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device of the present invention. [Figure 13] 1 is a cross-sectional view illustrating a structure of a semiconductor device according to the present invention. [Figure 14] 1 is a cross-sectional view illustrating a structure of a semiconductor device according to the present invention. [Figure 15] 1 is a cross-sectional view illustrating a structure of a semiconductor device according to the present invention. [Figure 16] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device of the present invention. [Figure 17] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device of the present invention. [Figure 18] 1 is a cross-sectional view illustrating a structure of a semiconductor device according to the present invention. [Figure 19] 1 is a cross-sectional view illustrating a structure of a semiconductor device according to the present invention. [Figure 20] 1A and 1B are a top view and a cross-sectional view illustrating a structure of a semiconductor device of the present invention. [Figure 21] FIG. 1 is a cross-sectional view illustrating a configuration of a conventional semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0014] The present invention will be described below with reference to the accompanying drawings. The present invention is not limited to the above, and various modifications and variations in form and detail are possible without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that the present invention can be modified in the following manner. It should be noted that the present invention is not limited to the following description. In the configuration, the same reference numerals may be used in common between different drawings.

[0015] (Embodiment 1) In this embodiment, etching can be easily controlled when forming contact holes. The structure and manufacturing method of the semiconductor device will be described.

[0016] FIG. 1 is a top view and a cross-sectional view for explaining the main configuration of a semiconductor device according to the present invention. FIG. 1(A) shows a top view of a thin film transistor in particular, and FIG. 1(B) shows the A and B of FIG. 1(A). 1(A) and 1(B) are cross-sectional views taken along the dashed line connecting C and D in FIG. 1(A), and FIG. 1(C) is a cross-sectional view taken along the dashed line connecting C and D in FIG. 1(A). 1 shows a cross-sectional view of the

[0017] The semiconductor device shown in this embodiment is a semiconductor device having an island-shaped structure on a substrate 30 with an insulating layer 31 interposed therebetween. A conductor layer 32, a gate insulating layer 33 formed on the semiconductor layer 32, and a gate insulating layer 34 formed above the semiconductor layer 32. a conductive layer 34 that functions as a gate electrode and is provided via a gate insulating layer 33; The insulating layer 2 is provided over the film transistor 205, the gate insulating layer 33, and the conductive layer 34. 03, and a conductive layer serving as a source electrode or a drain electrode provided over the insulating layer 203. 204 (FIGS. 1(A) to 1(C)). The semiconductor layer 32 has a channel forming region. and impurity regions 32b and 32c which function as a source region and a drain region. In addition, the semiconductor layer 32 is in contact with the end portion thereof, that is, the channel forming region 32a below the conductive layer 34. and an insulating layer 36 formed on the portion.

[0018] The semiconductor device shown in this embodiment includes the insulating layer 203, the impurity region 32b of the semiconductor layer 32, 32c is etched to form a contact hole (also called an opening) that reaches the insulating layer 31b. Then, a conductive layer 204 is formed so as to fill the contact hole. In the embodiment, the conductive layer 204 and the impurity regions 32b and 32c are , 32c are electrically connected to the side surface of a contact hole formed in the first and second electrodes.

[0019] In this embodiment, since it is not necessary to stop etching at the surface of the semiconductor layer, This makes it easy to control the etching when forming holes. The side of the contact hole is electrically connected to the source electrode or the drain electrode. Therefore, a semiconductor device in which deterioration of characteristics is suppressed can be easily manufactured.

[0020] Here, the insulating layer 36 formed on the edge of the semiconductor layer is not necessarily formed, but it is possible to form the insulating layer 36 on the edge of the semiconductor layer. The end of the conductive layer 32 and the conductive layer 34 functioning as the gate electrode are short-circuited, causing a leakage current to flow. Therefore, when the insulating layer 36 is provided, it is preferable to provide at least If it is formed on the side surface (exposed portion) of the channel forming region 32a of the semiconductor layer 32, However, it is of course acceptable to form it in other parts. In this embodiment, the insulating layer 36 is formed in the region below the gate insulating layer 33 (on the substrate side). It is formed in contact with

[0021] Next, an example of a method for manufacturing the semiconductor device shown in FIG. The fabrication process in the cross section taken along the dashed line connecting A and B in FIG. 1(A) is shown in FIGS. 2(A) to 2(D). 3(A)-(C), and Fig. 4(A)-(B), the dashed line connecting C and D in Fig. 1(A) The cross-sectional fabrication process is shown in Figures 2(E)-(H), 3(D)-(F), and 4(C)-(D). This will be explained using:

[0022] First, an insulating layer 31 is formed on a substrate 30 (FIGS. 2(A) and 2(E)). The insulating layer 31 includes a first insulating layer 31a formed on the substrate 30 and a second insulating layer 31b formed on the first insulating layer 31a. The formed second insulating layer 31b forms a two-layer structure.

[0023] The substrate 30 may be a glass substrate, a quartz substrate, a metal substrate (e.g., a ceramic substrate or a stainless steel substrate). Substrates, etc., and semiconductor substrates such as Si substrates can also be used. As the backing material, polyethylene terephthalate (PET), polyethylene naphthalate ( Substrates such as PEN, polyethersulfone (PES), and acrylic can also be selected. Cut.

[0024] The insulating layer 31 is formed by depositing silicon oxide or silicon nitride using, for example, a CVD method or a sputtering method. Silicon, silicon oxynitride (SiOxNy) (x>y>0), silicon oxynitride (SiN For example, the first insulating material may be an insulating material such as 0xOy (x>y>0). A silicon nitride oxide film is formed as the insulating layer 31a, and a silicon oxynitride film is formed as the second insulating layer 31b. Alternatively, a silicon nitride film may be formed as the first insulating layer 31a, and a silicon nitride film may be formed as the second insulating layer 31b. Alternatively, a silicon oxide film may be formed as the second insulating layer 31b. This prevents impurities such as alkali metals from diffusing from the substrate 30 and contaminating the elements formed thereon. It is possible.

[0025] Subsequently, a semiconductor film 201 is formed on the insulating layer 31. The semiconductor film 201 is an amorphous semiconductor film. Alternatively, the insulating layer 31 may be formed of a crystalline semiconductor film. The amorphous semiconductor film is crystallized by heat treatment or laser light irradiation. As the semiconductor material, silicon is preferable, and other silicon A germanium semiconductor or the like can also be used.

[0026] The semiconductor film 201 has a thickness of 10 nm to 200 nm, preferably 10 nm to 50 nm, and more preferably Preferably, the film thickness is about 10 nm to 30 nm. When forming a semiconductor film, after forming a semiconductor film with a thickness of 50 nm or more, the surface of the semiconductor film is Dry etching is performed to form a semiconductor film with a thickness of approximately 10 nm to 50 nm. The etching gas used in this etching is Cl2, BCl3, Si Chlorine gases such as Cl4, fluorine gases such as CF4, NF3, SF6, CHF3, or is a mixed gas made by adding an appropriate amount of inert gases such as O2 gas, H2 gas, He, or Ar to a fluorine-based gas. Before dry etching, the surface of the semiconductor film is treated with diluted hydrofluoric acid. The natural oxide film formed on the semiconductor surface is then removed by rinsing the semiconductor surface with ozone water or the like. An oxide film may be formed on the surface of the semiconductor film by processing.

[0027] By forming the semiconductor film 201 as a thin film of about 50 nm or less, In addition, the semiconductor film can be formed as a thin film. This allows the TFT to be made smaller. Even if the amount of impurity element doped into the channel formation region is increased to achieve this, the semiconductor film By forming a thin film, it becomes easier to fabricate a fully depleted TFT, resulting in a good S value. In this state, it is possible to fabricate a TFT with a controlled threshold voltage.

[0028] In addition, a film obtained by crystallizing or recrystallizing an amorphous semiconductor film by irradiating it with laser light is called a semiconductor. When used as the membrane 201, a laser diode pumped continuous wave (CW) laser is used as the laser light source. The second harmonic (wavelength 532 nm) can be used. Although it is not necessary to limit it to the second harmonic, the second harmonic is more energy efficient than the higher harmonics. When a semiconductor film is irradiated with a CW laser, energy is continuously transferred to the semiconductor film. Therefore, once the semiconductor film is melted, it can remain melted. Furthermore, the solid-liquid interface of the semiconductor film is moved by scanning the CW laser. It is possible to form long crystal grains along the direction of the laser beam. The reason is that compared to gas lasers, etc., the output is highly stable and stable processing is expected. This is because, not only CW lasers but also pulse lasers with repetition rates of 10 MHz or more can be used. It is also possible to use a pulsed laser with a high repetition rate. If the laser pulse interval is shorter than the time it takes for the film to melt and solidify, the semiconductor The film can be kept in a molten state, and the movement of the solid-liquid interface creates a structure consisting of long crystal grains in one direction. It is possible to form a semiconductor film that is similar to the CW laser and the repetition rate is 1 Pulsed lasers of 100 MHz or higher can also be used. For example, gas lasers include: There are Ar lasers, Kr lasers, CO2 lasers, etc. As for solid-state lasers, YAG lasers Laser, YLF laser, YAlO3 laser, GdVO4 laser, KGW laser, KYW laser, Alexandrite laser, Ti:sapphire laser, Y2O3 laser Lasers include YAG lasers, Y2O3 lasers, and GdV lasers. There are ceramic lasers such as O4 lasers and YVO4 lasers. Metal vapor lasers and Examples include helium cadmium lasers. When laser light is emitted in TEM00 (single transverse mode), the This is preferable because it can improve the energy uniformity of the linear beam spot that is generated. Alternatively, a pulsed excimer laser may be used.

[0029] Next, a resist 202 is selectively formed on the semiconductor film 201 (FIGS. 2(A) and 2(E)). Then, the semiconductor film 201 is dry-etched using the resist 202 as a mask to form island-like The semiconductor layer 32 is formed (FIGS. 2B and 2F). The resist 202 is removed by etching. It is used as a mask when The above-mentioned materials can be appropriately selected and used.

[0030] The etching gases used in dry etching are CF4, NF3, SF6, C Fluorine-based gas such as HF3, or the fluorine-based gas plus O2 gas, H2 gas, He, Ar, etc. A mixed gas containing an inert gas can be used. Preferably, CF4 and O2 are used. mixed gas of SF6 and O2, mixed gas of CHF3 and He, or mixed gas of CF4 and H It is advisable to use a mixed gas of 2. Also, etching is not limited to dry etching, and wet etching is also possible. In this case, the semiconductor film 201 may be etched with TMAH (tetrahydrofuran). methylanmmonium hydroxide, tetramethylammonium hydroxide Wet etching using an organic alkaline aqueous solution, typically alkoxide, is performed. It is possible to form an island-shaped semiconductor layer 32. Note that the etching solution is TMAH or the like. When using the above method, only the semiconductor film 201 is selectively etched, and the underlying insulating layer 31 In this way, the insulating surface can be etched without damaging the By forming the semiconductor layer in an island shape, multiple thin-film transistors and peripheral circuits can be formed on the same substrate. When the above-mentioned elements are formed, the elements can be isolated from each other.

[0031] The semiconductor layer 32 may be formed so that the end portion is vertical, or so that the end portion is tapered. The shape of the end of the semiconductor layer 32 can be changed by changing the etching conditions, etc. Preferably, the end of the semiconductor layer 32 is tapered. The taper angle is preferably 45° or more and less than 95°, and more preferably 60° or more and less than 95°. By forming the end of the semiconductor layer 32 in a nearly vertical shape, a parasitic channel can be formed. can be reduced.

[0032] Subsequently, the resist 202 formed on the semiconductor layer 32 is removed.

[0033] Next, an insulating layer 107 (hereinafter also referred to as a third insulating layer 107) is formed to cover the semiconductor layer 32. The third insulating layer 107 is formed by a CVD method or a sputtering method (FIGS. 2(C) and 2(G)). Silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, SiO It can be formed using materials such as F, SiOC, DLC, and porous silica.

[0034] The third insulating layer 107 is formed to a thickness that can sufficiently cover the end portions of the semiconductor layer 32 . The thickness of the third insulating layer 107 is 1.5 to 3 times the thickness of the semiconductor layer 32 formed thereunder. It is preferable to form the film with a thickness in the range of .

[0035] Next, the third insulating layer 107 is anisotropically etched mainly in the vertical direction. The insulating layer 36 (hereinafter referred to as the fourth insulating layer 3) in contact with the side surface of the semiconductor layer 32 is selectively etched. 6) (Figures 2(D) and (H)).

[0036] When the third insulating layer 107 is anisotropically etched mainly in the vertical direction, the semiconductor The third insulating layer 107 formed on one surface of the insulating layer 32 and on the insulating layer 31b is gradually The surface of the semiconductor layer 32 and the insulating layer 31b are etched away. A third insulating layer 107 having the same thickness is formed. Therefore, one surface of the semiconductor layer 106 is exposed. By stopping the etching at the point where the semiconductor layer 32 is exposed, the region in contact with the side surface of the semiconductor layer 32 and The third insulating layer 107 can be left only on and around the area. corresponds to the fourth insulating layer 36. The end of the semiconductor layer 32 is formed in a shape close to a vertical shape. By doing so, the third insulating layer 107 is formed only in the region in contact with the side surface of the semiconductor layer 32 and in the vicinity thereof. In other words, the fourth insulating layer 36 can be easily formed.

[0037] The third insulating layer 107 is etched by anisotropic etching mainly in the vertical direction. There is no particular limitation as long as it is a material that can be used. For example, reactive ion etching (RIE) can be used. Reactive Ion Etching can also be used. The plasma generation method is parallel plate type, magnetron type, dual frequency type, EC type. They are classified into R type, helicon type, ICP type, etc. The etching gas used in this case is The etching selectivity between the third insulating layer 107 and the other layer (semiconductor layer 32) can be obtained. When selectively etching an insulating film, for example, CHF3, C Fluorine-based gases such as F4, C4F8, C2F6, and NF3 can be used. Inert gases such as helium (He), argon (Ar), xenon (Xe), or O2 gas Gas, H2 gas may be added as needed.

[0038] The shape of the fourth insulating layer 36 can be determined by appropriately selecting the material for forming the thin film, etching conditions, etc. In this embodiment, the fourth insulating layer 36 has a bottom surface (insulating layer 3 1b) is formed so that the height in the vertical direction from the surface in contact with the semiconductor layer 32 is approximately the same as that of the semiconductor layer 32. The fourth insulating layer 36 has a curved surface that does not contact the side surface of the semiconductor layer. Specifically, the surface has an arbitrary curvature and is curved in a convex shape relative to the side surface of the semiconductor layer 32 that is in contact with the surface. Of course, the present invention is not particularly limited, and the fourth insulating layer 36 may be formed in a rounded shape. The corner portion of the fourth insulating layer 36 may be formed as a square shape. By making the shape of the insulating layer 33 gentle, the covering property of the layer laminated on the upper layer (here, the insulating layer 33) can be improved. The etching conditions are the type of etching gas, the flow rate ratio of each gas, etc. In addition, the amount of power applied to the electrode on which the substrate is placed, the electrode temperature of the electrode on which the substrate is placed, Indicates the pressure inside the bar, etc.

[0039] Next, an insulating layer 33 (hereinafter also referred to as the fifth insulating layer 33) is formed on the semiconductor layer 32 and the fourth insulating layer 36. The fifth insulating layer 33 is formed by a CVD method or a sputtering method (FIGS. 3A and 3D). Silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, and nitride are produced by the etching method. The fifth insulating layer 33 is formed of a material such as aluminum nitride. The fifth insulating layer 33 is formed as a single layer structure or a laminated structure using one or more of these. The thickness is 1 nm to 50 nm, preferably 1 nm to 20 nm, more preferably 1 nm to It is formed in the range of 10 nm.

[0040] The method for forming the insulating layer 36 is not limited to that shown in this embodiment. Formed by wet oxidation or plasma treatment of the edge of layer 32 in an oxygen-containing atmosphere. In this case, after forming the insulating layer 33 on the semiconductor layer 32, the edge of the semiconductor layer 32 may be The insulating layer 33 covering the semiconductor layer 32 is removed, and the exposed portion of the semiconductor layer 32 is treated with plasma or wet acid. Preferably, the insulating layer 36 is formed by curing.

[0041] In the case of wet oxidation, aqueous solutions containing ozone, hydrogen peroxide, sulfuric acid, etc. The surface of the semiconductor layer 32 is treated with an aqueous solution, an aqueous solution containing iodic acid, or an aqueous solution containing nitric acid. By this treatment, the oxide film formed on the exposed portion of the semiconductor layer 32 is converted into the insulating layer 36. The aqueous solution containing ozone, the aqueous solution containing hydrogen peroxide, the aqueous solution containing sulfuric acid, The aqueous solution containing iodic acid, the aqueous solution containing nitric acid, or the aqueous solution containing acetic acid or oxalic acid may also include:

[0042] In addition, an oxygen-containing atmosphere may be, for example, a mixture of oxygen (O2) and rare gases (He, Ne, Ar, K In a mixed gas atmosphere of oxygen, hydrogen (H2) and rare gas (r, Xe), In a mixed gas atmosphere of nitrous oxide and rare gas, or in a mixed gas atmosphere of nitrous oxide and rare gas The reaction can be carried out under a mixed gas atmosphere of oxygen, hydrogen, and rare gases. A mixed gas of hydrogen (H2) and argon (Ar) can be used. In this case, the flow rate is Oxygen 0.1 to 100 sccm, hydrogen 0.1 to 100 sccm, argon 100 to 5 000sccm. The oxygen:hydrogen:argon mixture is 1:1:100. It is preferable to introduce a mixed gas. For example, oxygen at 5 sccm, hydrogen at 5 sccm, and arsenic at 5 sccm. Just introduce 500sccm of Gon.

[0043] In addition, the nitrogen-containing atmosphere is, for example, a mixture of nitrogen (N2) and rare gases (He, Ne, Ar, K In a mixed gas atmosphere of nitrogen, hydrogen and rare gases (containing at least one of r and Xe), It can be performed under a gas atmosphere or a mixture of ammonia (NH3) and rare gases. can.

[0044] The plasma treatment was carried out in an atmosphere of the above gas with an electron density of 1×1011 cm-3. The electron temperature is 1.5 eV or less. The electron density is between 1×1011 cm-3 and 1×1013 cm-3, and the electron temperature is 0.5 eV. The plasma has a high electron density and is 1.5 eV or less. As a result, the electron temperature in the vicinity of the object to be processed (here, the semiconductor layer 32) formed on the substrate 30 is low. Therefore, damage to the object to be treated by the plasma can be prevented. Since the electron density of the surface is high at 1×1011 cm-3 or more, the surface can be treated by plasma processing. The oxide or nitride film formed by oxidizing or nitriding the irradiated object can be formed by CVD or Compared to films formed by sputtering, the film thickness is more uniform and denser. In addition, since the electron temperature of the plasma is low at 1.5 eV or less, it is possible to Compared with the Zuma process and thermal oxidation method, the oxidation or nitriding process can be performed at a lower temperature. For example, plasma treatment at a temperature 100 degrees or more lower than the distortion point of the glass substrate will not result in sufficient oxidation. In addition, the frequency used to generate plasma is microwave (2 High frequencies such as 0.45GHz can be used.

[0045] Next, a conductive layer 34 that functions as a gate electrode is formed on the gate insulating layer 33 (FIG. 3(B) ) and (E)). Here, the conductive layer 34 is shown as a single layer. The structure may be a laminate of two or three or more layers of the conductive material. However, the conductive layer 34 is formed by selectively etching the conductive layer formed on the gate insulating layer 33. The film can be formed by:

[0046] The conductive layer 34 may be made of tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), or the like. Mo, aluminum (Al), copper (Cu), chromium (Cr), niobium (Nb), etc. The elements selected from the above or alloy materials or compound materials whose main components are these elements are In addition, it is possible to form a silicon nitride film, which is typified by polycrystalline silicon doped with impurity elements such as phosphorus. For example, the conductive layer 34 may be formed of a first conductive film and a second conductive film. When a laminated structure with a conductive film is formed, tantalum nitride is used as the first conductive film and tantalum nitride is used as the second conductive film. It is preferable to use tungsten as the conductive layer. When the layer 34 is formed by laminating, the above materials can be freely combined.

[0047] Next, the impurity element 121 is introduced into the semiconductor layer 32 using the conductive layer 34 as a mask. Therefore, the semiconductor layer 32 has the impurity regions 32b and 32c and the region in which the impurity element 121 is not introduced. A channel forming region 32a is formed (FIGS. 3(B) and 3(E)). After forming the conductive layer 32 across the island-shaped semiconductor layer 32, the impurity element is introduced. Impurities are introduced into the regions of the semiconductor layer 32 that are not covered by the impurity regions 32b and 32c. The impurity element 121 is introduced into the region of the semiconductor layer 32 covered with the conductive layer 34. A channel forming region 32a is formed in which the SiO 2 is not etched.

[0048] Here, the impurity element 121 is an impurity element that imparts n-type conductivity or an impurity element that imparts p-type conductivity. Impurity elements that exhibit n-type conductivity include phosphorus (P) and arsenic (As). As impurity elements that exhibit p-type, boron (B) and aluminum can be used. For example, the impurity element 121 may be aluminum (Al), gallium (Ga), or the like. The semiconductor layer is then doped with phosphorus (P) at a concentration of 1×1018 to 1×1021 / cm3. 32 to form n-type impurity regions 32b and 32c. Between the formation region 32a and the impurity regions 32b and 32c which are the source region and the drain region, The impurity is added at a lower concentration than the impurity regions 32b and 32c which are the source and drain regions. A low concentration impurity region (LDD region) may be formed by adding a low concentration impurity region. This reduces the electric field at the drain end, suppressing deterioration due to repeated writing and erasing. It can be controlled.

[0049] In addition, the channel forming region 32a contains impurities opposite to those added to the impurity regions 32b and 32c. An impurity element having a conductivity type other than that of the n-type TFT (for example, boron for an n-type TFT) may be added. By adding impurities of the opposite conductivity type to the channel forming region 32a, the threshold voltage of the TFT The voltage can be controlled. The impurity element can be doped through the gate electrode. Alternatively, the dopant may be added in advance before the gate electrode is formed.

[0050] Next, an insulating layer 203 is formed so as to cover the conductive layer 34 and the gate insulating layer 33 (FIG. 3(C) , (F)). Subsequently, a resist 207 is selectively formed on the insulating layer 203.

[0051] Then, the insulating layer 203, the gate insulating layer 33, and the semiconductor layer 32 are dry-etched. Contact holes are formed (FIGS. 4A and 4C). Next, a source electrode is formed on the insulating layer 203. A conductive layer 204 that functions as a gate or drain electrode is selectively formed (FIGS. 4(B), 4(D)). Here, the conductive layer 204 is connected to the insulating layer 203, the gate insulating layer 33, and the semiconductor layer 32. The conductive layer 204 is formed so as to fill the contact hole. The impurity regions 32b and 32c functioning as a source region or a drain region are impurity regions The contact holes 32b and 32c are electrically connected to each other at the side surfaces thereof. It is provided.

[0052] Here, the insulating layer 203 is made of silicon oxide, oxide, or the like, formed by a CVD method, a sputtering method, or the like. Silicon nitride (SiOxNy) (x>y>0), silicon oxide nitride (SiNxOy) ( x>y>0) can be used. Also, polyimide, polyamide, polyvinyl fluoride, etc. Organic materials such as phenol, benzocyclobutene, acrylic, and epoxy, or siloxane resins It can be made of a single layer or laminated structure made of siloxane materials such as grease, oxazole resin, etc. It should be noted that siloxane materials correspond to materials containing Si-O-Si bonds. The skeleton of hexane is made up of bonds between silicon (Si) and oxygen (O). For this purpose, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group can also be used as a substituent. Photosensitive polybenzoxazole has a low dielectric constant (normally It has a dielectric constant of 2.9 at 1MHz and high heat resistance (differential thermal analysis / thermogravimetry simultaneous analysis (TG / DTA) hermogravimetry-Differential Thermal Ana Decomposition temperature: 550℃ at 5℃ / min. Low water absorption (24 hours at room temperature) Oxazole resin is a material with a relative dielectric constant (3.2 to 3.3%) similar to polyimide. Compared to silicon dioxide (approximately 4), the dielectric constant is low (approximately 2.9), which suppresses the occurrence of parasitic capacitance. Here, the insulating layer 203 is an oxide film formed by the CVD method. Silicon, silicon oxynitride (SiOxNy) (x>y>0) or silicon oxynitride (S iNxOy) (x>y>0) is formed as a single layer or a laminate. Organic materials such as polyamide, polyvinylphenol, benzocyclobutene, acrylic, and epoxy The material may be formed by laminating a siloxane material such as a siloxane resin or an oxazole resin. good.

[0053] The conductive layer 204 may be made of aluminum, tungsten, titanium, tantalum, molybdenum, A single layer made of an element selected from nickel and neodymium or an alloy containing multiple of these elements For example, a conductive layer made of an alloy containing a plurality of the elements can be used. Titanium-containing aluminum alloys and neodymium-containing aluminum alloys are used as conductive films. In addition, when the insulating film is provided in a laminated structure, for example, an aluminum layer or Alternatively, a laminated structure in which the aluminum alloy layer is sandwiched between titanium layers may be used. good.

[0054] Through the above steps, a semiconductor device including the thin film transistor 205 can be manufactured.

[0055] In this embodiment, since it is not necessary to stop etching at the surface of the semiconductor film, This makes it easy to control the etching when forming holes. The side of the contact hole is electrically connected to the source electrode or the drain electrode. Therefore, a semiconductor device in which deterioration of characteristics is suppressed can be easily manufactured.

[0056] Alternatively, a thick insulating layer may be selectively provided at the end of the channel forming region of the semiconductor layer. By doing so, it is possible to alleviate the electric field concentration at the end of the channel formation region of the semiconductor layer. Therefore, it is possible to reduce gate leakage defects and improve the breakdown voltage of the gate electrode. .

[0057] (Embodiment 2) In this embodiment mode, a structure and a manufacturing method of a semiconductor device different from that shown in FIG. 1 will be described.

[0058] FIG. 5 is a top view and a cross-sectional view for explaining the configuration of the semiconductor device according to the present embodiment. FIG. 5(A) shows a top view of a thin film transistor, and FIG. 5(B) shows a top view of A and B in FIG. 5(A). 5(A) and 5(B) are cross-sectional views taken along the dashed line connecting C and D in FIG. 5(A). A cross-sectional view is shown.

[0059] The semiconductor device shown in this embodiment is a semiconductor device having an island-shaped structure on a substrate 30 with an insulating layer 31 interposed therebetween. A conductor layer 32, a gate insulating layer 33 formed on the semiconductor layer 32, and a gate insulating layer 34 formed above the semiconductor layer 32. a conductive layer 34 that functions as a gate electrode and is provided via a gate insulating layer 33; The insulating layer 2 is provided over the film transistor 205, the gate insulating layer 33, and the conductive layer 34. 03, and a conductive layer serving as a source electrode or a drain electrode provided over the insulating layer 203. 204 (FIGS. 5(A) to 5(C)). The semiconductor layer 32 has a channel forming region. and impurity regions 32b and 32c which function as a source region and a drain region. In addition, the semiconductor layer 32 is in contact with the end portion thereof, that is, the channel forming region 32a below the conductive layer 34. The channel forming region 32a has an insulating layer 36 formed in the portion where the insulating layer 36 is formed. Impurities of the opposite conductivity type to the impurities added to the pure regions 32b and 32c may be added. stomach.

[0060] The semiconductor device shown in this embodiment includes the insulating layer 203, the impurity region 32b of the semiconductor layer 32, 32c, the insulating layer 31b is etched to form a contact hole reaching the insulating layer 31a. Then, a conductive layer 204 is formed so as to fill the contact hole. In this embodiment, the conductive layer 204 and the impurity regions 32b and 32c are They are electrically connected to the side surface of a contact hole formed in 2c.

[0061] Next, the manufacturing process in the cross section taken along the dashed line connecting A and B in FIG. 5(A) is shown in FIGS. 6(A) to 6(B). 6(C) to 6(D) are the fabrication steps for the cross section taken along the dashed line connecting C and D in FIG. 5(A). D) is used to explain.

[0062] First, similarly to the first embodiment, insulating layers 31a and 31b are formed on a substrate 30, and insulating layer 31 a semiconductor layer 32, an insulating layer 36, and a gate insulating layer 33 are formed on the surface of the gate insulating layer 33; A conductive layer 34 that functions as a gate electrode is formed, and an insulating layer 203 is formed over the conductive layer 34. (FIGS. 6(A) and 6(C)). Here, a resist 207 is formed on the insulating layer 203. .

[0063] Next, the insulating layer 203, the gate insulating layer 33, and the semiconductor layer 32 are formed using the resist 207 as a mask. The insulating layer 31b is etched to form a contact hole reaching the insulating layer 31a. (Figure 6(B) and (D)).

[0064] Subsequently, the resist 207 is removed. The subsequent steps are the same as in the first embodiment except for the contact hole. A conductive layer 204 is formed to fill the holes, thereby fabricating the semiconductor device shown in FIG. It is possible.

[0065] In this embodiment, since it is not necessary to stop etching at the surface of the semiconductor film, This makes it easy to control the etching when forming holes. The side of the contact hole is electrically connected to the source electrode or the drain electrode. Therefore, a semiconductor device in which deterioration of characteristics is suppressed can be easily manufactured.

[0066] Alternatively, a thick insulating layer may be selectively provided at the end of the channel forming region of the semiconductor layer. By doing so, it is possible to alleviate the electric field concentration at the end of the channel formation region of the semiconductor layer. Therefore, it is possible to reduce gate leakage defects and improve the breakdown voltage of the gate electrode. .

[0067] (Embodiment 3) In this embodiment mode, a structure and a manufacturing method of a semiconductor device different from those shown in FIGS. do.

[0068] FIG. 7 is a top view and a cross-sectional view for explaining the configuration of the semiconductor device according to this embodiment. FIG. 7(A) shows a top view of a thin film transistor, and FIG. 7(B) shows a top view of A and B in FIG. 7(A). 7(A) and 7(B) are cross-sectional views taken along the dashed line connecting C and D in FIG. 7(A). A cross-sectional view is shown.

[0069] As shown in FIG. 7, the semiconductor device of this embodiment has the structure shown in FIG. 5 and a conductive layer 204 filled therein. In other words, the semiconductor device shown in this embodiment has a different shape from the contact hole. In this step, the insulating layer 203, the impurity regions 32b and 32c of the semiconductor layer 32, and the insulating layer 31b are etched. The contact hole reaching the insulating layer 31a formed by the etching is formed on the surface of the semiconductor layer 32. The impurity regions 32b and 32c are also formed so as to be exposed. In this embodiment, the conductive layer 204 and the impurity regions 32b and 32c are The side surface of the contact hole formed in the region c and the surfaces of the impurity regions 32b and 32c are electrically connected. In this embodiment, the insulating layer 31b is also electrically connected to the contact hole. However, no contact holes are formed in the insulating layer 31b. A contact hole may be formed so that the surface is exposed.

[0070] Next, the manufacturing process in the cross section taken along the dashed line connecting A and B in FIG. 7(A) is shown in FIGS. 8(A) to 8(C). 9(A)-(B), the cross section taken along the dashed line connecting C and D in FIG. 7(A) was fabricated. The process will be explained with reference to FIGS. 8(D) to 8(F) and FIGS. 9(C) to 9(D).

[0071] First, similarly to the first embodiment, insulating layers 31a and 31b are formed on a substrate 30, and insulating layer 31 a semiconductor layer 32, an insulating layer 36, and a gate insulating layer 33 are formed on the surface of the gate insulating layer 33; A conductive layer 34 that functions as a gate electrode is formed, and an insulating layer 203 is formed over the conductive layer 34. (FIGS. 8(A) and 8(D)). Here, a resist 207 is formed on the insulating layer 203. .

[0072] Next, the insulating layer 203 and the gate insulating layer 33 are dry etched using the resist 207 as a mask. Then, contact holes reaching the semiconductor layer 32 are formed (FIGS. 8(B) and 8(E)).

[0073] Next, the insulating layer 203 and the gate insulating layer 33 are removed by wet etching using the resist 207 as a mask. By this etching, the insulating layer 203 and the gate insulating layer 33 are recessed outward.

[0074] Next, the semiconductor layer 32 and the insulating layer 31b are dry etched using the resist 207 as a mask. Then, a contact hole is formed that reaches the insulating layer 31a. The contact holes expose the side surfaces of the impurity regions 32b and 32c and a part of the surfaces of the impurity regions 32b and 32c. It is possible to form a

[0075] The subsequent steps are carried out in the same manner as in the first or second embodiment to fill the contact holes. By forming a conductive layer 204 on the insulating film 201, the semiconductor device shown in FIG. 7 can be manufactured.

[0076] Next, a manufacturing method different from the method shown in FIGS. 8 and 9 will be described with reference to FIG. The fabrication process for the cross section taken along the dashed line connecting A and B in (A) is shown in Figures 10(A) to 10(C). The fabrication process in the cross section taken along the dashed line connecting C and D in FIG. 7(A) is shown in FIGS. 10(D) to 10(F). This will be used to explain.

[0077] First, similarly to FIGS. 8B and 8E, insulating layers 31a and 31b are formed on a substrate 30, and insulating layers 31a and 31b are formed on a substrate 30. A semiconductor layer 32, an insulating layer 36, and a gate insulating layer 33 are formed on the layer 31b. A conductive layer 34 that functions as a gate electrode is formed on the insulating layer 203. The resist 207 formed on the insulating layer 203 is used as a mask to form the insulating layer 203 and the gate electrode. The contact insulating layer 33 is dry-etched to form contact holes (FIGS. 10(A) and 10(D)). )).

[0078] Next, the resist 207 is dry-etched to recede outward (FIG. 1 0(B), (E)). Next, using the resist 207 as a mask, the insulating layer 203 and the gate insulating layer The layer 33, the semiconductor layer 32, and the insulating layer 31b are dry-etched to expose the insulating layer 31a. A contact hole is formed through the impurity region 32 (FIGS. 10(C) and 10(F)). The contact holes expose the side surfaces of the impurity regions 32b and 32c and a part of the surfaces of the impurity regions 32b and 32c. It is possible to form a

[0079] In the subsequent steps, the conductive layer 204 is formed so as to fill the contact holes in the same manner as in the first embodiment. By forming the above, the semiconductor device shown in FIG. 7 can be manufactured.

[0080] In this embodiment, since it is not necessary to stop etching at the surface of the semiconductor film, The etching can be easily controlled when forming the holes. Since a step is formed between the conductive layer 32 and the conductive layer 2 on the side surface of the contact hole, The coating property of the conductive layer 204 is improved, and the variation in the film thickness of the conductive layer 204 and the disconnection of the conductive layer 204 are prevented. This makes it possible to suppress variations in contact resistance. The side of the contact hole is electrically connected to the source electrode or the drain electrode. Therefore, it is possible to easily manufacture a semiconductor device in which deterioration of characteristics is suppressed. do.

[0081] Alternatively, a thick insulating layer may be selectively provided at the end of the channel forming region of the semiconductor layer. By doing so, it is possible to alleviate the electric field concentration at the end of the channel formation region of the semiconductor layer. Therefore, it is possible to reduce gate leakage defects and improve the breakdown voltage of the gate electrode. .

[0082] (Fourth embodiment) The semiconductor device according to the present invention is not limited to the configurations shown in the first to third embodiments and may take various forms. In this embodiment, a thin film transistor in which the semiconductor layer is partially silicided can be used. The structure and manufacturing method of the semiconductor device of this embodiment mode are described below. Figure 11(A) is a top view, and Figure 11(B) is a cross-sectional view taken along the dashed line AB in Figure 11(A). 11(C) shows a cross-sectional view taken along dashed line CD in FIG. 11(A).

[0083] As shown in FIG. 11, the semiconductor device of this embodiment includes a semiconductor layer 32 in addition to the configuration shown in FIG. A silicide region 1102 is formed on a part of the surface of the gate electrode. The conductive layer 34 is formed of a laminated structure of a first conductive layer 34a and a second conductive layer 34b. An insulating layer (also called a sidewall insulating layer) 1101 is formed on the side wall of the conductive layer 34. Furthermore, impurity regions (high concentration impurities) that function as source regions or drain regions are formed. impurity regions 32b, 32c between the channel forming region 32a and the impurity regions 32b, 32c; Regions 32d and 32c are doped with impurities at lower concentrations (also called low-concentration impurity regions). 2e is formed.

[0084] Next, a method for manufacturing the semiconductor device shown in FIG. 11 will be described.

[0085] First, similarly to the first embodiment, insulating layers 31a and 31b are formed on a substrate 30, and insulating layer 31 a semiconductor layer 32, an insulating layer 36, and a gate insulating layer 33 are formed on the surface of the gate insulating layer 33; A first conductive layer 34a and a second conductive layer 34b that function as gate electrodes are formed (FIG. 12). Next, using the conductive layer 34b as a mask, a first concentration impurity source that imparts one conductivity type is implanted. After the addition of the impurity element, the conductive layer 34a and the conductive layer 34b are used as a mask to perform the second concentration of the impurity element. The doping is performed to form a pair of high concentration impurity regions 32b and 32c in a self-aligned manner, and a pair of low concentration The impurity regions 32d and 32e and the channel forming region 32a are formed. The impurity element of the first concentration and the impurity element of the second concentration are doped with impurity elements of the same conductivity type, for example. Boron (B), aluminum (Al), and gallium (Ga) are impurity elements that give p-type conductivity. ), and impurity elements such as phosphorus (P) and arsenic (As) that give n-type conductivity can be added. do.

[0086] The channel forming region 32a is given one conductivity type for controlling the threshold voltage of the transistor. The channel forming region 32a may be doped with an impurity element. This can be done before forming the conductive layer 34. Also, the impurity element that imparts one conductivity type After the addition, a heat treatment may be carried out to activate the added impurity element. This can be done using a laser beam, or an RTA or furnace annealing oven. The heating may be carried out at a temperature ranging from 00°C to 700°C, preferably from 500°C to 650°C. The heat treatment is preferably carried out in a nitrogen atmosphere.

[0087] Next, a sidewall insulating layer 1101 is formed to contact the side surfaces of the conductive layer 34a and the conductive layer 34b. (Figure 12(B)).

[0088] The sidewall insulating layer 1101 forms an insulating layer on the conductive layer 34a and the conductive layer 34b. The insulating layer is selectively etched by anisotropic etching mainly in the vertical direction. For example, silicon oxide can be formed by CVD or sputtering. Inorganic materials such as silicon nitride, silicon oxynitride, silicon nitride oxide, etc., and organic resins An insulating layer having a single layer structure or a laminated structure is formed using an organic material, and the insulating layer is selectively etched. The sidewall insulating layer 1101 can be formed by etching the silicide region. This is used as a silicide mask when forming the sidewall insulating layer. The layer 1101 has a curved surface that does not contact the side surfaces of the conductive layers 34a and 34b. The sidewall insulating layer 1101 is formed between the conductive layer 34a and the conductive layer 34b which form the gate electrode. It is formed so as to completely cover the side of b.

[0089] In this embodiment, the etching for forming the sidewall insulating layer 1101 is The underlying insulating layer 33 is also etched by this process, and a part of the semiconductor layer 32 is selectively exposed. Specifically, the high concentration impurity region 32 in the region not overlapping with the sidewall insulating layer 1101 Depending on the etching conditions, the high concentration impurity regions 32b and 32c are exposed. The upper layer of 2c may also be etched, resulting in a decrease in film thickness (called film loss).

[0090] Next, a metal layer 1103 is formed on the exposed surface of the semiconductor layer 32 (FIG. 12(C)).

[0091] The metal layer 1103 may be formed at least on the exposed semiconductor layer 32. The sidewall insulating layer 1101 is formed in a region of the conductor layer 32 that does not overlap with the sidewall insulating layer 1101. In this embodiment, the metal layer 1103 covers not only the exposed surface of the semiconductor layer 32 but also the sidewall insulation. The metal layer 1103 is formed so as to cover the insulating layer 1101 and the conductive layer 34. The metal layer 1103 does not react with the semiconductor layer. The material is formed by using a material that forms silicide. For example, nickel (Ni), titanium (T i) Metal elements such as cobalt (Co) or platinum (Pt), or alloys containing such metal elements The metal layer 1103 can be formed by sputtering using these materials. The metal layer 1103 is formed by a method such as vapor deposition or plating. It is necessary to select the thickness appropriately depending on the film thickness of the side region. A nickel layer having a thickness of 10 nm is formed by the above process. If a natural oxide film is formed on the exposed semiconductor layer 32, the natural oxide film is removed. Then, a metal layer 1103 may be formed.

[0092] Next, a silicide region 1102 is formed in a part of the semiconductor layer 32 (FIG. 12(D)).

[0093] The silicide region 1102 is formed by heat treatment to remove the semiconductor layer 32 and the metal layer 1103. The silicide region 1102 is formed by a reaction between the metal layer 1103 and the silicide layer 1102. A part of the semiconductor layer 32 in the region where the semiconductor layer 32 is in contact with the semiconductor layer 32 is silicided. The high concentration impurity regions 32b and 32c formed in the substrate 32 are partially silicided. It can be said that a silicide region is formed in part of the high-concentration impurity region. For example, when nickel is formed as the metal layer 1103, the silicide region 1102 is Similarly, titanium, cobalt, When platinum is formed, titanium silicide is formed as the silicide region 1102, and platinum is formed as the silicide region 1102. Cobalt silicide and platinum silicide are formed.

[0094] The heat treatment can be performed using an RTA or an annealing furnace. The temperature ranges from 00°C to 700°C, and the time ranges from 10 seconds to 1 hour, preferably from 20 seconds to 30 minutes. In this embodiment, the heat treatment is performed at 550° C. for 30 seconds to form nickel silicide. A silicide region 1102 made of silicon dioxide is formed.

[0095] In FIG. 12(D), the silicide region 1102 is formed in the channel forming region of the semiconductor layer 32. The thickness of the sidewall 32a is smaller than the thickness of the region where the sidewall 32a is formed. In the semiconductor layer 32 in the region that does not overlap with the insulating layer 1101, High concentration impurities 32b and 32c are formed on the side of the insulating layer 31b. A silicide region 1102 is formed in contact with the upper layer of 32b and 32c.

[0096] The shape, thickness, etc. of the silicide region 1102 depend on the thickness of the metal layer 1103 to be reacted, the thermal The selection can be made by appropriately controlling the treatment temperature, heat treatment time, etc. As shown in FIG. 13B, the semiconductor in the region not overlapping with the sidewall insulating layer 1101 In the layer 32, a part or the whole of the semiconductor layer 32 in the region is The upper surface may be a silicide region 1102 formed by silicidizing the semiconductor. The surface of the insulating layer 32 on which a metal layer for silicidation is formed is referred to as the bottom surface. When the entire surface from the top to the bottom is silicided, A high concentration impurity region is formed under the wall insulating layer 1101. The present invention is not particularly limited, and a part of the silicide region is formed on the half under the sidewall insulating layer 1101. The conductor layer 32 (excluding the channel forming region 32a) may also be formed.

[0097] In addition, if an unreacted metal layer remains after the reaction between the semiconductor layer 32 and the metal layer 1103, The unreacted metal layer is removed. Although not shown, the insulating layer 36 and the sidewall insulating layer are also removed. The metal layer 1103 formed on the layer 1101, the conductive layer 34b and the insulating layer 31b is removed. If an unreacted metal layer remains on the formed silicide region 1102, the residue is removed. The remaining metal layer is also removed. The unreacted metal layer is removed by wet etching or dry etching. In this case, the etching gas or etching solution is unreacted. The metal layer and other layers (e.g., insulating layer 36, sidewall insulating layer 1101, conductive layer 34) b, insulating layer 31b and silicide region 1102) can be sufficiently etched. In other words, the etching rate for the metal layer is high and the etching rate for other layers is low. For example, a metal layer 1103 made of nickel may be used. When the sample was prepared, a mixed solution of hydrochloric acid (HCl), nitric acid (HNO3) and pure water (H2O) was used. It can be removed by wet etching. For example, the mixture ratio of the solution is HCl:H The ratio can be NO3:H2O=3:2:1.

[0098] In this embodiment, the insulating layer 36 is formed in contact with the side surface of the end of the semiconductor layer 32. Therefore, when the unreacted metal layer is etched away, the side surface of the semiconductor layer 32 is etched away. This can prevent it from being

[0099] When forming a silicide region, the silicide region and the gate electrode are formed by the conductive layer. This is because the silicide region and the gate electrode must not come into contact with each other. If this happens, the gate electrode and the source or drain region will be shorted, resulting in poor switching characteristics. This is because the device will no longer function as a semiconductor device. Therefore, in this embodiment, the width of the conductive layers 34a and 34b forming the gate electrode is The sidewall insulating layer 1101 is narrower than the insulating layer 33 that functions as a gate insulating layer. The end of the insulating layer 33 is made to substantially coincide with the end of the insulating layer 33 .

[0100] Next, an insulating layer 203 is formed so as to cover the insulating layer, conductive layer, etc. provided on the substrate 30 ( Figure 13(A)).

[0101] The subsequent steps are the same as in the first embodiment, with the insulating layer 203 and the semiconductor layer 32, and the insulating layer 31b. A contact hole is formed to reach the substrate, and a conductive layer 204 is formed to fill the contact hole. By forming the semiconductor device shown in FIG. 11 or FIG. 13A, the semiconductor device shown in FIG. 11 or FIG. 13A can be manufactured.

[0102] The semiconductor device of this embodiment is not limited to those shown in FIGS. 11 to 13, but may be any of those shown in FIGS. 14 to 15. The shape shown in the figure may also be used.

[0103] The semiconductor device shown in FIG. 14A has the structure shown in FIG. 13A and a conductive layer 204 filled therein. The shape of the contact hole is different. That is, in the semiconductor device shown in FIG. Therefore, the contact holes filled with the conductive layer 204 are free from impurities in the insulating layer 203 and the semiconductor layer 32. The insulating layer 31b is etched to form the insulating layer 31a. Therefore, in this embodiment, the conductive layer 204 and the impurity region 32 b and 32c are the contact holes formed in the impurity regions 32b and 32c. The contact holes shown in FIG. 14(A) are electrically connected to each other. It should be noted that the method is not limited to that shown in FIG. As shown in FIG. 14(B), the semiconductor layer 32 is partially or entirely shielded from the upper surface to the lower surface. Residified silicide regions 1102 may be formed.

[0104] 15A is a semiconductor device having the same structure as that shown in FIG. 13A except that a conductive layer 204 is filled in. In other words, the semiconductor device shown in this embodiment has a different shape from the semiconductor device shown in this embodiment. In this case, the insulating layer 203, the impurity regions 32b and 32c of the semiconductor layer 32, and the insulating layer 31b are The contact hole formed by etching and reaching the insulating layer 31a is formed on the surface of the semiconductor layer 32. Therefore, in this embodiment, the impurity regions 32b and 31c are also exposed. In this embodiment, the conductive layer 204 and the impurity regions 32b and 32c are On the side surface of the contact hole formed in 2c and on the surfaces of the impurity regions 32b and 32c In this embodiment, the insulating layer 31b is also electrically connected to the contact hole. However, no contact holes are formed in the insulating layer 31b. A contact hole may be formed so that the surface is exposed. The hole can be formed in the same manner as in the third embodiment. 15(A), it may be applied to a part or the whole of the semiconductor layer 32 as shown in FIG. 15(B). Alternatively, a silicide region 1102 may be formed by silicidizing the entire surface from the top surface to the bottom surface. .

[0105] In this embodiment, since it is not necessary to stop etching at the surface of the semiconductor film, This makes it easy to control the etching when forming holes. The side of the contact hole is electrically connected to the source electrode or the drain electrode. Therefore, a semiconductor device in which deterioration of characteristics is suppressed can be easily manufactured.

[0106] (Embodiment 5) The semiconductor device described in the first to fourth embodiments is a semiconductor device made of silicon oxide on a single crystal silicon substrate. An oxide film is formed, and the single-crystal semiconductor thin film formed on the oxide film can be used as the active layer. In this embodiment, a semiconductor device using SOI technology called SIMOX is explain.

[0107] First, a single crystal silicon substrate 601 is prepared as a material for forming the single crystal silicon layer (see FIG. 16). (A)) Here, we will explain the case where a P-type single crystal silicon substrate is used, but if an N-type single crystal silicon substrate is used, Of course, a single crystal silicon germanium substrate can also be used. can.

[0108] Next, oxygen ions are added to the single crystal silicon substrate 601 to form an oxygen-containing film at a predetermined depth. The oxygen ions are, for example, 1×10 atoms / It is sufficient to add the oxygen-containing layer 602 at a dose of about cm2. The distance between the main surface of the crystalline silicon substrate 601 and the oxygen-containing layer 602 is This is the thickness of the single crystal silicon layer that functions as the active layer of the TFT.

[0109] Next, a heat treatment is performed at a temperature of 800 to 1200° C. to bury the oxygen-containing layer 602 and form the insulating layer 6 The width of the oxygen-containing layer 602 in the depth direction is changed to 03 by the distribution of oxygen ions when ions are added. The concentration of oxygen ions is determined by the fabric. 603. Therefore, the interface between the single crystal silicon substrate 601 and the buried insulating layer 603 Although the surface is unclear, this heat treatment process allows the single crystal silicon substrate 601 and the buried insulating layer The interface with 603 becomes clear (FIGS. 16(B) and (C)).

[0110] The thickness of the buried insulating layer 603 is set to 10 to 500 nm (typically 20 to 50 nm). In this embodiment, the interface between the single crystal silicon substrate 601 and the buried insulating layer 603 is stable. Because the material is bonded to the substrate, a thin buried insulating layer of 20 to 50 nm can be formed. Cut.

[0111] When the buried insulating layer 603 is formed in this manner, the buried insulating layer 603 is partially covered with a thin film. A portion of the single crystal silicon substrate remains, forming a single crystal silicon layer 604. The thickness of the crystalline silicon layer 604 is 10 to 200 nm (preferably 10 to 50 nm, more preferably The depth at which the oxygen-containing layer 602 is formed is adjusted so that the thickness is approximately 10 nm to 30 nm. good.

[0112] Next, a resist is selectively formed on the single crystal silicon layer 604, and the single crystal silicon layer 60 By selectively etching 4, island-shaped single layers that will become the active layers of the TFTs to be formed later are formed. A crystalline silicon layer 605 is formed. In this embodiment, a single island-shaped single crystalline silicon layer is formed. Although only one layer is shown, multiple layers may be formed on the same substrate. (See FIG. 16(D) )

[0113] The subsequent steps are carried out in the same manner as in the first to fourth embodiments to manufacture the semiconductor device according to the present invention. It can be manufactured.

[0114] In the semiconductor device according to this embodiment, it is not necessary to stop etching at the surface of the semiconductor film. This makes it easy to control etching when forming contact holes. The side of the contact hole formed in the layer is electrically connected to the source electrode or the drain electrode. Since the connection can be made, a semiconductor device in which deterioration of characteristics is suppressed can be easily manufactured. In addition, the semiconductor device according to this embodiment uses a single crystal semiconductor layer as an active layer. Therefore, the characteristics can be further improved.

[0115] (Sixth embodiment) In this embodiment, an oxide film made of silicon oxide is formed on a single crystal silicon substrate. A semiconductor device using a single crystal semiconductor thin film formed on a substrate as an active layer will be described. In the embodiment, a semiconductor device using an SOI substrate formed by using the Smart-Cut method is This section explains the location.

[0116] First, a single crystal silicon substrate 801 is prepared as a material for forming the single crystal silicon layer. The case where a P-type single crystal silicon substrate is used will be explained, but an N-type single crystal silicon substrate will also be used. Of course, a single crystal silicon germanium substrate can also be used.

[0117] Next, a thermal oxidation treatment is performed to form a silicon oxide film 802 on the main surface (corresponding to the element formation surface). The thickness of the film can be determined by the practitioner, but it is preferably 10 to 500 nm (typically 20 This silicon oxide film 802 will later be used as a buried insulating film for the SOI substrate. It functions as part of the layer (Figure 17(A)).

[0118] Next, hydrogen ions are introduced from the main surface side of the single crystal silicon substrate 801 through the silicon oxide film 802. The hydrogen-containing layer 803 is formed by adding hydrogen (FIG. 17(B)). Depth to be formed (distance between the main surface of the single-crystal silicon substrate 801 and the hydrogen-containing layer 803) is the thickness of the single crystal silicon layer that will later function as the active layer of the TFT. A 50 nm thick single crystal silicon layer is formed between the main surface of the silicon substrate 801 and the hydrogen-containing layer 803. The hydrogen ions are implanted at 1×1016 to 1×1 It can be doped at a dose of 0.17 atoms / cm.

[0119] Next, the single crystal silicon substrate 801 and a support substrate are bonded together. A single crystal silicon substrate 804 is used as the plate, and a silicon oxide film for bonding is applied to the surface. 17C). Instead of the single crystal silicon substrate 804, F A silicon substrate formed by the Z method, a polycrystalline silicon substrate, or the like may also be used. Also, a quartz substrate Alternatively, a highly heat-resistant substrate such as a ceramic substrate or a crystallized glass substrate may be used.

[0120] At this time, the bonding interface becomes a highly hydrophilic silicon oxide film, so the The adhesive is formed by the reaction of the water.

[0121] Next, a heat treatment (first heat treatment) is performed at 400 to 600°C (for example, 500°C). This causes a change in the volume of the micropores in the hydrogen-containing layer 803, and fractures occur along the hydrogen-containing layer 803. As a result, the single crystal silicon substrate 801 is divided, and the oxide film is left on the support substrate. The silicon nitride film 802 and the single crystal silicon layer 806 are left behind (FIG. 17(D)).

[0122] Next, as the second heat treatment step, the film is heated at a temperature in the range of 1050 to 1150°C (for example, 1100°C). A furnace annealing process is performed. In this process, Si-O-Si bonds are formed at the bonding interface. In other words, the single crystal silicon layer 806 is This is the process to completely adhere the film to the supporting substrate. This stabilizes the bonding interface. In this way, a buried insulating layer 807 is formed (FIG. 17(E)). A hydrogen-containing layer 803 is formed, and a fracture surface is generated along the hydrogen-containing layer 803 to form a thin film single crystal. Although the silicon layer 806 is formed, it is not limited to this. The hydrogen-containing layer 803 may be formed. By polishing the single crystal silicon substrate 801 without providing a thin single crystal silicon layer 806 may be formed.

[0123] Next, a process for planarizing the surface of the single crystal silicon layer 806 may be performed. P (chemical mechanical polishing) and high temperature (90 The furnace annealing process can be performed at a temperature of approximately 0 to 1200°C.

[0124] The final thickness of the single crystal silicon layer 806 is 10 to 200 nm (preferably 10 to 50 nm). , and more preferably 10 nm to 30 nm).

[0125] Next, a resist is selectively formed on the single crystal silicon layer 806, and the single crystal silicon layer 80 By selectively etching 6, island-shaped single layers that will become the active layers of the TFTs to be formed later are formed. A crystalline silicon layer 808 is formed. In this embodiment, a single island of single crystalline silicon is formed. Although only one layer is described, multiple island-shaped single-crystal silicon layers are formed on the same substrate. (Fig. 17(F))

[0126] The subsequent steps are carried out in the same manner as in the first to fourth embodiments to manufacture the semiconductor device according to the present invention. It can be manufactured.

[0127] In the semiconductor device according to this embodiment, it is not necessary to stop etching at the surface of the semiconductor film. This makes it easy to control etching when forming contact holes. The side of the contact hole formed in the layer is electrically connected to the source electrode or the drain electrode. Since the connection can be made, a semiconductor device in which deterioration of characteristics is suppressed can be easily manufactured. In addition, the semiconductor device according to this embodiment uses a single crystal semiconductor layer as an active layer. Therefore, the characteristics can be further improved.

[0128] (Embodiment 7) In this embodiment, the semiconductor device and the electroluminescence element described in the first embodiment are (hereinafter also referred to as "EL element") The semiconductor device that can be used in this embodiment mode is The semiconductor device is not limited to that shown in the first embodiment, and may be any of the semiconductor devices described in the second to sixth embodiments.

[0129] In this embodiment, light from the electroluminescent element is taken from the first electrode 110 side. In order to form a structure in which the first electrode 110 is exposed, the first electrode 110 is formed using a film having light-transmitting properties. In this embodiment, indium tin oxide containing silicon oxide (ITSO) is used as the first electrode 110. Use.

[0130] First, as shown in FIG. 18, TFTs 1701 to 1703 and TFT An insulating layer 1710 covering the TFTs 1701 to 1703 and the source regions or Next, wirings 1704 to 1709 are formed to electrically connect to the drain region. An insulating layer 109 is formed to cover the wiring 1709 to 1709. The first electrode 110 is then electrically connected to the insulating layer 110. An insulating film 111 (also called a bank, partition wall, barrier, embankment, etc.) is formed to cover the 109. Complete.

[0131] The insulating film 111 may be made of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or aluminum nitride. Aluminum, aluminum oxynitride and other inorganic insulating materials, or acrylic acid, methacrylic acid Acids and their derivatives, or polyimides, aromatic polyamides, poly Heat-resistant polymers such as polybenzimidazole, is an inorganic siloxane containing Si-O-Si bonds among compounds consisting of silicon, oxygen, and hydrogen, Organosiloxanes in which hydrogen atoms bonded to the siloxane are replaced with organic groups such as methyl or phenyl. Insulating materials such as acrylic and polyimide can be used. In this embodiment, a photosensitive polyimide is used to form a flat area. The insulating film 111 is formed to a thickness of 1.5 μm.

[0132] The insulating film 111 preferably has a shape in which the radius of curvature changes continuously. The electroluminescent layer 112 (layer containing an organic compound) and the second electrode 113 are formed on the substrate 111 so as to improve coverage. It can be done.

[0133] In order to further improve reliability, the first electrode 112 is formed before the electroluminescent layer 112 is formed. The insulating film 10 and the insulating film 111 are subjected to nitriding or oxidation treatment using a high density plasma device. The first electrode 110 may be nitrided or oxidized using a high-density plasma device. The plasma damage during surface modification is minimal, resulting in a surface with fewer defects. Therefore, the display by the light-emitting element of this embodiment mode is high-definition and has little display unevenness. When the film 111 is nitrided, the surface of the insulating film 111 is modified, and the absorption of moisture into the insulating film is prevented. Furthermore, when the insulating film 111 is oxidized, the film becomes stronger, and the amount of organic gas can be reduced. In this embodiment, the high density plasma device is used to suppress the emission of plasma. It is possible to perform a process with less smear damage. Whether to perform oxidation treatment or nitriding treatment can be appropriately selected in consideration of the material and effect of the insulating film. good.

[0134] Next, an electroluminescent layer 112 is formed on the first electrode 110. Note that in FIG. 18, only one pixel is shown. Although not shown, in this embodiment, there are electric signals corresponding to the colors red (R), green (G), and blue (B). In this embodiment, red (R), green ( G) and blue (B) luminescent materials were selected by evaporation using an evaporation mask. The red (R), green (G), and blue (B) luminescent materials are formed by using a deposition mask. The method of selectively forming the layers by a vapor deposition method or a droplet discharge method is also applicable. In the case of the droplet ejection method, it is possible to paint RGB colors without using a mask. In this embodiment, materials that emit red (R), green (G), and blue (B) light are used. Each is formed by vapor deposition.

[0135] Before the deposition of EL, the gas was heated in an atmosphere containing an inert gas as the main component, with an oxygen concentration of 5% or less and a water concentration of It is preferable to perform the heat treatment in an atmosphere with a temperature of 1% or less to remove moisture and the like. In the form, heat treatment is carried out at 300°C for 1 hour.

[0136] Next, a second electrode 113 made of a conductive film is formed on the electroluminescent layer 112. 113, materials with low work functions (Al, Ag, Li, Ca, or alloys thereof) MgAg, MgIn, AlLi, CaF2, or calcium nitride) can be used. In this way, a light emitting element consisting of the first electrode 110, the electroluminescent layer 112 and the second electrode 113 is formed. It is done.

[0137] In the display device shown in FIG. 18, light emitted from the light emitting element is transmitted between the substrate 101 and the first electrode 11. 0 and is emitted from the first electrode 110 side in the direction of the arrow.

[0138] It is also effective to provide a passivation film so as to cover the second electrode 113. Passivation films include silicon nitride, silicon oxide, silicon oxynitride (SiON), and nitride. Silicon oxide (SiNO), aluminum nitride (AlN), aluminum oxynitride (AlON) ), aluminum oxide nitride (AlNO) or aluminum oxide, which has a nitrogen content higher than the oxygen content. Insulators including aluminum, diamond-like carbon (DLC), and nitrogen-containing carbon (CN) films The insulating film may be a single layer or a laminated layer of a combination of insulating films. Siloxane, whose skeletal structure is formed by bonding silicon (Si) and oxygen (O), may also be used. Siloxanes are substituted with organic groups (e.g., alkyl groups, aromatic groups) containing at least hydrogen. Aromatic hydrocarbons are used. In addition, fluoro groups or groups containing at least hydrogen as substituents are used. An organic group and a fluoro group may also be used.

[0139] In this case, it is preferable to use a film with good coverage as the passivation film, and a carbon film The use of DLC film is particularly effective. DLC film can be used in the temperature range from room temperature to 100°C or less. Therefore, it is possible to easily form a film above the electroluminescent layer 112, which has low heat resistance. In addition, the DLC film has a high blocking effect against oxygen, and the oxygen in the electroluminescent layer 112 can be blocked. Therefore, the electroluminescent layer can be prevented from being oxidized during the subsequent sealing step. This can prevent problems such as oxidation of 112.

[0140] Next, the substrate 101 on which the light emitting element is formed is fixed to the sealing substrate with a sealing material, and the light emitting element is The element is sealed. The sealant prevents moisture from entering through the cross section, Deterioration can be prevented, and the reliability of the display device is improved. The container may be filled with a material, or nitrogen or the like may be enclosed by sealing it under a nitrogen atmosphere. The filler may also be dropped in a liquid state to fill the display device. Since it is a bottom injection type, it is not necessary to use a filler with light transmission. In the case of a structure in which light is extracted by the insulating film, the filler must be formed using a light-transmitting material. Examples of fillers include visible light curing, UV curing, or heat curing epoxy resins. Through the above steps, a display device having a light-emitting element is completed.

[0141] It is also preferable to place a desiccant inside the EL display panel to prevent deterioration of the element due to moisture. In this embodiment, a dried liquid is applied to a recess formed in the sealing substrate so as to surround the pixel region. The area corresponding to the gate wiring layer is also coated with a drying agent. By installing the agent, the water absorption area can be made larger, and the water absorption effect is high. Since the desiccant is formed on the gate wiring layer, it does not reduce the light extraction efficiency. None.

[0142] The process of sealing the light-emitting element is a process for protecting the light-emitting element from moisture. Methods of mechanically sealing with bar material, sealing with thermosetting resin or ultraviolet light curing resin, The method of sealing is to use a thin film with high barrier properties such as metal oxide or nitride. The substrate or cover material is glass, ceramic, plastic or metal. However, if light is to be emitted to the cover material side, it must be translucent. The cover material and the substrate on which the light emitting element is formed are made of a thermosetting resin, an ultraviolet light curing resin, or the like. The parts are attached using a sealant, and the resin is hardened by heat treatment or ultraviolet light irradiation. A sealed space is formed. A moisture absorbent material, typically barium oxide, is placed in this sealed space. This moisture absorbent material may be provided on the sealing material in contact with the sealing material, or may be provided on the sealing material in contact with the light from the light emitting element. The cover material may be provided on or around the partition wall so as not to interfere with the light emitting element. It is also possible to fill the space between the substrate and the substrate with thermosetting resin or ultraviolet light curing resin. In this case, a material such as barium oxide is added to a thermosetting resin or an ultraviolet light curing resin. It is effective to add a moisture absorbent.

[0143] The TFTs 1701 to 1703 shown in this embodiment are fabricated by any one of the methods of the first to sixth embodiments. There is no need to stop etching at the surface of the semiconductor film, so the contact hole The etching process can be easily controlled during the formation of the semiconductor layer. The side of the contact hole can be electrically connected to the source electrode or the drain electrode. Therefore, a semiconductor device with reduced deterioration in characteristics can be easily manufactured. An EL display device with good characteristics can be easily fabricated.

[0144] (Embodiment 8) In this embodiment mode, a transmission type liquid crystal display device is manufactured using the semiconductor device manufactured in Embodiment Mode 1. A method for manufacturing the semiconductor device will be described. You can also be there.

[0145] First, as in the first embodiment, TFTs 1701 to 1703 and TFTs 1701 to 1703 are The insulating layer 1710 covers the source region or drain region of the TFTs 1701 to 1703. Next, wirings 1704 to 1709 are formed to connect the wirings 1704 to 1709 to each other (FIG. 19). An insulating layer 109 is formed to cover the insulating layer 109, and the insulating layer 109 is electrically connected to the wiring 1709. In this embodiment, the first electrode 110 is formed using the following material: Indium tin oxide containing silicon oxide (ITSO) is used. Next, as shown in Figure 19, An alignment film 1801 is formed over the insulating layer 109 and the first electrode 110. In this embodiment, Polyimide is used for the alignment film 1801. Next, the opposing substrate 1802 is prepared. 02 is a glass substrate 1803, a counter electrode 1804 made of a transparent conductive film, an alignment film 1805, and It consists of:

[0146] Next, the TFT substrate 1806 obtained in the above process and the opposing substrate 1802 are bonded together via a sealing material. Here, in order to keep the gap between the two substrates constant, the alignment film 1801 and the alignment film 18 A spacer may be provided between the substrates 1805. After that, liquid crystal 1807 is injected between the two substrates and sealed. By sealing with a sealing material, a transmission type liquid crystal display device as shown in FIG. 19 is completed.

[0147] Although the present embodiment has been described as a transmission type liquid crystal display device, the liquid crystal display device of the present invention The display device is not limited to this. By providing a reflective film on the upper or lower surface of the first electrode 110, it is possible to use the liquid crystal display device as a reflective liquid crystal display device. It may also be used in a semi-transmissive liquid crystal display device.

[0148] The TFTs 1701 to 1703 shown in this embodiment are fabricated by any one of the methods of the first to sixth embodiments. There is no need to stop etching at the surface of the semiconductor film, so the contact hole The etching process can be easily controlled during the formation of the semiconductor layer. The side of the contact hole can be electrically connected to the source electrode or the drain electrode. Therefore, a semiconductor device with reduced deterioration in characteristics can be easily manufactured. A liquid crystal display device with good characteristics can be easily manufactured.

[0149] (Embodiment 9) In this embodiment, the thin film transistor, memory element, and amplifier described in the first to sixth embodiments are A method for manufacturing a semiconductor device including a tena according to the present invention will be described with reference to the drawings.

[0150] The semiconductor device described in this embodiment mode is shown in FIG. 20. Note that FIG. 20(A) shows the semiconductor device described in this embodiment mode. 20(A) shows an example of the top surface structure of a semiconductor device, and FIG. 20(B) shows a part of the cross-sectional structure of FIG. It shows.

[0151] In this embodiment, a semiconductor device 1200 includes an integrated circuit portion 1201, a memory portion 1202, It has an antenna 1203 (FIG. 20(A)). In FIG. 20(B), 204 corresponds to a part of the cross-sectional structure of the integrated circuit portion 1201 in FIG. 20(A), and the region 1205 is The region 1206 corresponds to a part of the cross-sectional structure of the memory section 1202 in FIG. ) corresponds to a part of the cross-sectional structure of antenna 1203.

[0152] As shown in FIG. 20(B), the semiconductor device of this embodiment has an insulating layer 775 formed on a first substrate 775. Thin film transistors (TFTs) 744 to 748 are provided through the thin film transistors 03. An insulating film 750 is provided on the substrates 744 to 748, and a source is provided on the insulating film 750. The insulating film 752 has conductive films 752 to 761 that function as source electrodes or drain electrodes. An insulating film 762 is provided on the conductive films 750 and 752 to 761. The conductive films 763 to 765 and the insulating film 762 are formed by a thin film so as to cover parts of the conductive films 763 to 764. The insulating film 766 is provided as shown in FIG. 1, and the memory element portions 789 and 790 are provided on the insulating film 766. a conductive layer 786 functioning as an antenna provided over the conductive film 765; An insulating film provided to cover the conductive film 771 and the conductive layer 786 functioning as an antenna The first substrate 772 is a first insulating film, and the second substrate 776 is provided on the insulating film 772. The substrate 775 and the second substrate 776 form an integrated circuit portion 1201 and a memory portion of the semiconductor device. 1202 and antenna 1203 are sealed.

[0153] The thin film transistors 744 to 748 shown in this embodiment are the same as those in any one of Embodiments 1 to 6. It is not necessary to stop the etching at the surface of the semiconductor film, so the contact The etching process for forming the holes can be easily controlled. The side surface of the contact hole is electrically connected to the source electrode or the drain electrode. Therefore, a semiconductor device in which deterioration of characteristics is suppressed can be easily manufactured. Therefore, a semiconductor device capable of wireless communication and having good characteristics can be easily manufactured. [Explanation of symbols]

[0154] 30 boards 31 Insulating layer 32 Semiconductor layer 33 Gate insulating layer 34 Conductive layer 36 Insulating layer 203 Insulating layer 204 Conductive layer 205 Thin-film transistor 32a Channel formation region 32b Impurity region 32c impurity region

Claims

1. a first insulating layer having a region overlying the substrate and comprising silicon nitride; a second insulating layer having a region located above the first insulating layer and comprising silicon oxide; a semiconductor layer having a region located above the second insulating layer and having a channel formation region of a transistor; a third insulating layer having a region in contact with an upper surface of the semiconductor layer and including silicon oxide; a first conductive layer having a region located above the third insulating layer and functioning as a gate electrode of the transistor; a fourth insulating layer having a region located above the first conductive layer; a second conductive layer having a region located above the fourth insulating layer and functioning as one of a source electrode and a drain electrode of the transistor; the fourth insulating layer has a first opening; the third insulating layer has a second opening in a region overlapping with the first opening; the semiconductor layer has a third opening in a region overlapping the first opening and the second opening, the second conductive layer has a region in contact with the semiconductor layer inside the third opening, the second conductive layer has a portion located closer to the substrate than an upper surface of the second insulating layer in a region overlapping with the first opening to the third opening in a cross-sectional view; In a cross-sectional view, a diameter of the third opening on the upper surface of the semiconductor layer is larger than a diameter of the third opening on the lower surface of the semiconductor layer; an inner periphery of the third opening has a region in contact with the second insulating layer in a cross-sectional view; In a plan view, the semiconductor layer entirely overlaps with the first insulating layer, an inner wall of the second opening has a region that forms a first angle with the substrate in a cross-sectional view; In a cross-sectional view, an inner wall of the third opening has a region that forms the first angle with the substrate.

2. a first insulating layer having a region located above the substrate and comprising silicon nitride; a second insulating layer having a region located above the first insulating layer and comprising silicon oxide; a semiconductor layer having a region located above the second insulating layer and having a channel formation region of a transistor; a third insulating layer having a region in contact with an upper surface of the semiconductor layer and including silicon oxide; a first conductive layer having a region located above the third insulating layer and functioning as a gate electrode of the transistor; a fourth insulating layer having a region located above the first conductive layer; a second conductive layer having a region located above the fourth insulating layer and functioning as one of a source electrode and a drain electrode of the transistor; the fourth insulating layer has a first opening; the third insulating layer has a second opening in a region overlapping with the first opening; the semiconductor layer has a third opening in a region overlapping the first opening and the second opening, the second conductive layer has a region in contact with the semiconductor layer inside the third opening, the second conductive layer has a portion located closer to the substrate than an upper surface of the second insulating layer in a region overlapping with the first opening to the third opening in a cross-sectional view; In a cross-sectional view, a diameter of the third opening on the upper surface of the semiconductor layer is larger than a diameter of the third opening on the lower surface of the semiconductor layer; an inner periphery of the third opening has a region in contact with the second insulating layer in a cross-sectional view; In a plan view, the semiconductor layer entirely overlaps with the first insulating layer, the first insulating layer has a first portion overlapping with the semiconductor layer, and a second portion overlapping with the second conductive layer in regions overlapping with the first opening to the third opening and having the same film thickness as the first portion; an inner wall of the second opening has a region that forms a first angle with the substrate in a cross-sectional view; In a cross-sectional view, an inner wall of the third opening has a region that forms the first angle with the substrate.

3. a first insulating layer having a region overlying the substrate and comprising silicon nitride; a second insulating layer having a region located above the first insulating layer and comprising silicon oxide; a semiconductor layer having a region located above the second insulating layer and having a channel formation region of a transistor; a third insulating layer having a region in contact with an upper surface of the semiconductor layer and including silicon oxide; a first conductive layer having a region located above the third insulating layer and functioning as a gate electrode of the transistor; a fourth insulating layer having a region located above the first conductive layer; a second conductive layer having a region located above the fourth insulating layer and functioning as one of a source electrode and a drain electrode of the transistor; the fourth insulating layer has a first opening; the third insulating layer has a second opening in a region overlapping with the first opening; the semiconductor layer has a third opening in a region overlapping the first opening and the second opening, the second conductive layer has a region in contact with the semiconductor layer inside the third opening, the second conductive layer has a portion located closer to the substrate than an upper surface of the second insulating layer in a region overlapping with the first opening to the third opening in a cross-sectional view; In a cross-sectional view, a diameter of the third opening on the upper surface of the semiconductor layer is larger than a diameter of the third opening on the lower surface of the semiconductor layer; an inner periphery of the third opening has a region in contact with the second insulating layer in a cross-sectional view; In a plan view, the semiconductor layer entirely overlaps with the first insulating layer, the second conductive layer has a laminated structure in which an aluminum layer is sandwiched between titanium layers, an inner wall of the second opening has a region that forms a first angle with the substrate in a cross-sectional view; In a cross-sectional view, an inner wall of the third opening has a region that forms the first angle with the substrate.

4. a first insulating layer having a region located above the substrate and comprising silicon nitride; a second insulating layer having a region located above the first insulating layer and comprising silicon oxide; a semiconductor layer having a region located above the second insulating layer and having a channel formation region of a transistor; a third insulating layer having a region in contact with an upper surface of the semiconductor layer and including silicon oxide; a first conductive layer having a region located above the third insulating layer and functioning as a gate electrode of the transistor; a fourth insulating layer having a region located above the first conductive layer; a second conductive layer having a region located above the fourth insulating layer and functioning as one of a source electrode and a drain electrode of the transistor; the fourth insulating layer has a first opening; the third insulating layer has a second opening in a region overlapping with the first opening; the semiconductor layer has a third opening in a region overlapping the first opening and the second opening, the second conductive layer has a region in contact with the semiconductor layer inside the third opening, the second conductive layer has a portion located closer to the substrate than an upper surface of the second insulating layer in a region overlapping with the first opening to the third opening in a cross-sectional view; In a cross-sectional view, a diameter of the third opening on the upper surface of the semiconductor layer is larger than a diameter of the third opening on the lower surface of the semiconductor layer; an inner periphery of the third opening has a region in contact with the second insulating layer in a cross-sectional view; In a plan view, the semiconductor layer entirely overlaps with the first insulating layer, the second conductive layer has a laminated structure in which an aluminum layer is sandwiched between titanium layers, the first insulating layer has a first portion overlapping with the semiconductor layer, and a second portion overlapping with the second conductive layer in regions overlapping with the first opening to the third opening and having the same film thickness as the first portion; an inner wall of the second opening has a region that forms a first angle with the substrate in a cross-sectional view; In a cross-sectional view, an inner wall of the third opening has a region that forms the first angle with the substrate.

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