Silicon carbide semiconductor device and manufacturing method thereof

Abstract

To provide an SiC semiconductor device capable of suppressing generation of a crack on a side surface of an SiC semiconductor layer, and a method for manufacturing the same.SOLUTION: A method for manufacturing an SiC semiconductor device includes the steps of: forming a groove 110 for a rear surface 2b of an SiC semiconductor layer 2 of an SiC wafer 100 along a cutting schedule line to generate a crack; forming a metal film on a wall surface constituting the groove 110; forming a silicide layer 4 by reaction of Si in the SiC semiconductor layer 2 and a metal element in the metal film by heat treatment; and applying a stress to the SiC wafer 100 and dividing the SiC wafer 100 into a plurality of chips by developing the crack. This causes the silicide layer 4 to cover a modified layer generated by formation of the groove 110 on the side surface side of the SiC semiconductor layer 2. For this reason, generation of a crack on the side surface of the SiC semiconductor layer 2 can be suppressed.SELECTED DRAWING: Figure 5D

Description

[Technical Field]

[0001] The present invention relates to a silicon carbide (hereinafter referred to as "SiC") semiconductor device and a method for manufacturing the same. [Background technology]

[0002] Patent Document 1 discloses a stealth dicing method, which is one of the methods for dicing SiC wafers. In the stealth dicing method, a modified layer is formed inside the SiC wafer by irradiating the SiC wafer with laser light along the intended cutting line. When an external force is applied to the SiC wafer, cracks propagate from the modified layer in the thickness direction of the SiC wafer. This separates the SiC wafer into multiple chips. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-27855 Summary of the Invention [Problem to be solved by the invention]

[0004] The present inventors have investigated the use of a scribe-and-break method as a method for dicing SiC wafers. In this method, grooves are formed along dicing lines on the back surface of the SiC wafer, causing cracks. An external force is then applied to the SiC wafer, causing the cracks to propagate in the thickness direction of the SiC wafer. This divides the SiC wafer into multiple chips (i.e., SiC semiconductor devices).

[0005] In this method, when a groove is formed in the SiC wafer, a modified layer is generated around the groove. After the SiC wafer is cut, the modified layer is exposed on the back side of the side surface of the SiC semiconductor layer. That is, the modified layer constitutes a part of the back side of the side surface of the SiC semiconductor layer. For this reason, the present inventors have discovered a problem in that, in a device in which an SiC semiconductor device is mounted, when stress such as thermal stress is applied to the SiC semiconductor device, cracks occur in the modified layer on the side surface of the SiC semiconductor layer, and the cracks progress into the SiC semiconductor layer.

[0006] In view of the above, an object of the present invention is to provide a SiC semiconductor device capable of suppressing the occurrence of cracks on the side surfaces of a SiC semiconductor layer, and a method for manufacturing the same. [Means for solving the problem]

[0007] In order to achieve the above object, according to the invention described in claim 1, SiC semiconductor devices are The substrate includes a SiC single crystal, has a main surface (2a), a back surface (2b) opposite to the main surface, and a side surface (2c) connecting the main surface and the back surface and being formed by a cleavage plane, and a part of the side surface on the back surface side a wall surface (112) located inside the main surface side of the side surface in a direction (DR1) parallel to the main surface; a SiC semiconductor layer (2) having a modified layer (21) which is an atomic arrangement structure of SiC different from that of SiC single crystal; a metal silicide, which is a compound of a metal element and silicon, provided on a side surface of the SiC semiconductor layer; Outside the direction parallel to the main surface (DR1) and a side silicide layer (42) covering the modified layer.

[0008] According to this, the side silicide layer covers the modified layer on the side surface of the SiC semiconductor layer. Therefore, when stress is applied to the SiC semiconductor device, stress on the modified layer is alleviated. Therefore, compared to a case where the SiC semiconductor device does not have the side silicide layer, the occurrence of cracks on the side surface of the SiC semiconductor layer can be suppressed.

[0009] According to the invention described in claim 2, SiC semiconductor devices are The substrate includes a SiC single crystal, has a main surface (2a), a back surface (2b) opposite to the main surface, and a side surface (2c) connecting the main surface and the back surface and being formed by a cleavage plane, and a part of the side surface on the back surface side a wall surface (112) located inside the main surface side of the side surface in a direction (DR1) parallel to the main surface; a SiC semiconductor layer (2) having a modified layer (21) which is an atomic arrangement structure of SiC different from that of SiC single crystal; The metal silicide is a compound of a metal element and silicon, and is provided on the side surface of the SiC semiconductor layer, adjacent to the rear surface side of the modified layer, and in a direction parallel to the main surface. Without the interposition of a modified layer The part of the SiC semiconductor layer that is made up of single crystal SiC Connect with and a side silicide layer (42) that supports the silicide layer.

[0010] According to this, since the side surface silicide layer is formed on the side surface of the SiC semiconductor layer, the modified layer present on the side surface of the SiC semiconductor layer is reduced compared to when the side surface silicide layer is not formed, and thus it is possible to suppress the occurrence of cracks on the side surface of the SiC semiconductor layer compared to when the silicide layer is not provided.

[0011] Also, claims 7 According to the invention described in The method for manufacturing a SiC semiconductor device includes: Providing a SiC wafer (100) including a SiC semiconductor layer (2) containing a SiC single crystal and having a main surface (2a) and a back surface (2b) opposite to the main surface; forming a groove (110) on the back surface along a line to be cut to generate a crack (111); forming a metal film (114) on a wall surface (112) that forms the groove; forming a silicide layer (4) containing a metal silicide on a wall surface side of the SiC semiconductor layer by reacting silicon contained in the SiC semiconductor layer with a metal element contained in the metal film through heat treatment; and applying stress to the SiC wafer to cause cracks to propagate along a direction perpendicular to the main surface, thereby cutting the SiC wafer into a plurality of chips.

[0012] This makes it possible to manufacture the SiC semiconductor device according to claim 1 or claim 2. Therefore, the same effects as those of the SiC semiconductor device according to claim 1 or claim 2 can be obtained.

[0013] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and the specific components described in the embodiments described below. [Brief explanation of the drawings]

[0014] [Figure 1] 1 is a perspective view of a SiC semiconductor device according to a first embodiment. [Figure 2A] 1 is a cross-sectional view of a SiC semiconductor device according to a first embodiment. [Figure 2B] FIG. 2B is an enlarged view of region IIB of FIG. 2A. [Figure 3] 1 is a top view of a SiC semiconductor layer included in the SiC semiconductor device of the first embodiment. FIG. [Figure 4] 2 is a cross-sectional view showing a specific element structure of the SiC semiconductor device of the first embodiment. FIG. [Figure 5A] 2A to 2C are cross-sectional views illustrating a manufacturing process of the SiC semiconductor device according to the first embodiment. [Figure 5B] 5B is a cross-sectional view showing the manufacturing process of the SiC semiconductor device subsequent to FIG. 5A. [Figure 5C] FIG. 5C is a cross-sectional view showing the manufacturing process of the SiC semiconductor device subsequent to FIG. 5B. [Figure 5D] 5D is a cross-sectional view showing the manufacturing process of the SiC semiconductor device subsequent to FIG. 5C. [Figure 5E] FIG. 5E is a cross-sectional view showing the manufacturing process of the SiC semiconductor device subsequent to FIG. 5D. [Figure 5F] FIG. 5B is a cross-sectional view showing the manufacturing process of the SiC semiconductor device subsequent to FIG. 5E. [Figure 5G] FIG. 5C is a cross-sectional view showing the manufacturing process of the SiC semiconductor device subsequent to FIG. 5F. [Figure 5H] FIG. 5C is a cross-sectional view showing the manufacturing process of the SiC semiconductor device subsequent to FIG. 5G. [Figure 6]FIG. 5C is an enlarged view of a portion of the SiC wafer of FIG. 5B. [Figure 7] FIG. 5D is an enlarged view of a portion of the SiC wafer of FIG. 5C. [Figure 8] FIG. 5E is an enlarged view of a portion of the SiC wafer of FIG. 5D. [Figure 9] FIG. 5F is an enlarged view of a portion of the SiC wafer of FIG. 5G. [Figure 10A] 4A to 4C are cross-sectional views showing the manufacturing process of the SiC semiconductor device of Comparative Example 1. [Figure 10B] 10B is a cross-sectional view showing the manufacturing process of the SiC semiconductor device subsequent to FIG. 10A. [Figure 10C] 10C is a cross-sectional view showing the manufacturing process of the SiC semiconductor device subsequent to FIG. 10B. [Figure 10D] 10D is a cross-sectional view showing the manufacturing process of the SiC semiconductor device subsequent to FIG. 10C. [Figure 10E] FIG. 10E is a cross-sectional view showing the manufacturing process of the SiC semiconductor device subsequent to FIG. 10D. [Figure 10F] 10F is a cross-sectional view showing the manufacturing process of the SiC semiconductor device subsequent to FIG. 10E. [Figure 10G] 10F is a cross-sectional view showing the manufacturing process of the SiC semiconductor device subsequent to FIG. 10F. [Figure 10H] 10B is a cross-sectional view showing the manufacturing process of the SiC semiconductor device subsequent to FIG. 10G. [Figure 11] FIG. 2 is a perspective view of a SiC semiconductor device of Comparative Example 1. [Figure 12] FIG. 2 is a cross-sectional view of a SiC semiconductor device of Comparative Example 1. [Figure 13] 1 is a cross-sectional view of a portion of a power card on which the SiC semiconductor device of Comparative Example 1 is mounted. [Figure 14] FIG. 6 is an enlarged cross-sectional view of a portion of the SiC semiconductor device according to the second embodiment. [Figure 15] FIG. 10 is a top view of a SiC semiconductor layer included in a SiC semiconductor device according to another embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0015] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following embodiments, parts that are identical or equivalent to each other will be denoted by the same reference numerals.

[0016] (First embodiment) [SiC semiconductor device] 1 and 2A, the SiC semiconductor device 1 of this embodiment is a single semiconductor chip formed by dividing a SiC wafer into multiple chips. The SiC semiconductor device 1 has the following basic configuration: the SiC semiconductor layer 2, the front electrode 3, the silicide layer 4, and the back electrode 5.

[0017] The SiC semiconductor layer 2 includes SiC single crystal. The SiC semiconductor layer 2 has a main surface 2a, a back surface 2b, and multiple side surfaces 2c. The main surface 2a is the surface on which the main components of the element are formed and is called the element formation surface. The main surface 2a is quadrangular. The back surface 2b is the surface opposite the main surface. Each of the multiple side surfaces 2c connects the main surface 2a and the back surface 2b. Each of the multiple side surfaces 2c constitutes a part of the side surface of the SiC semiconductor device 1.

[0018] The SiC semiconductor layer 2 is mainly composed of 4H—SiC single crystal, which is a hexagonal SiC single crystal. Alternatively, the SiC semiconductor layer 2 may be mainly composed of 2H—SiC single crystal or 6H—SiC single crystal, which is a hexagonal SiC single crystal.

[0019] The main surface 2a faces the c-plane of the SiC single crystal. The c-plane is a hexagonal (0001) plane. The main surface 2a has an off-angle inclined at an angle greater than 0° and equal to or less than 10° with respect to the c-plane of the SiC single crystal.

[0020] Each of the multiple side surfaces 2c is a cleavage plane. A cleavage plane is a flat surface formed by cleavage and has a predetermined crystal orientation. As shown in FIG. 3, when the SiC semiconductor layer 2 is made of a 4H—SiC single crystal, the predetermined crystal orientation planes are the (−1-120) plane, the (11-20) plane, the (−1100) plane, and the (1-100) plane. When indicating a crystal orientation, a bar (-) is normally placed above the desired number. However, due to limitations on expression based on electronic filing, a bar is placed before the desired number in this specification.

[0021] The SiC semiconductor layer 2 has a modified layer 21. The modified layer 21 is formed by forming grooves 110 in a scribing process described below. The modified layer 21 has an atomic arrangement structure of SiC that is different from that of SiC single crystal. Examples of atomic arrangement structures of SiC that are different from that of SiC single crystal include polycrystalline and amorphous structures. The modified layer 21 constitutes a portion of the back surface 2b side of each of the multiple side surfaces 2c.

[0022] The surface electrode 3 is formed on the main surface 2a of the SiC semiconductor layer 2. The surface electrode 3 is made of a conductive film.

[0023] The silicide layer 4 is a layer containing a metal silicide, which is a compound of a metal element and silicon. As shown in FIG. 2B , the silicide layer 4 includes a back-side silicide layer 41 and a side-side silicide layer 42. The back-side silicide layer 41 is a portion of the silicide layer 4 provided on the back surface 2b of the SiC semiconductor layer 2.

[0024] The side surface-side silicide layer 42 is provided on each side surface 2c of the SiC semiconductor layer 2 in the silicide layer 4. The side surface-side silicide layer 42 covers the modified layer 21 on the side surface side of the SiC semiconductor device 1. In other words, the side surface-side silicide layer 42 is adjacent to the modified layer 21 on the outer side in the direction DR1 parallel to the main surface 2a. The side surface-side silicide layer 42 forms part of the side surface of the SiC semiconductor device 1. The side surface-side silicide layer 42 is arranged continuously over all of the multiple side surfaces 2c. In other words, the side surface-side silicide layer 42 is arranged in a ring shape. The side surface-side silicide layer 42 is continuous with the back surface-side silicide layer 41.

[0025] In this embodiment, the metal silicide is NiSi (nickel silicide), which contains Ni as a metal element. The entire silicide layer 4 is composed of NiSi. The width W1 of the side silicide layer 42 in a direction perpendicular to the main surface 2a is 10 μm or less. This is because the depth of the groove 110, which will be described later, is 10 μm or less.

[0026] The back electrode 5 is formed on the back surface 2b side of the SiC semiconductor layer 2. The back electrode 5 is in contact with the back surface-side silicide layer 41. The back surface electrode 5 is made of a conductive film.

[0027] The above is the basic configuration of the SiC semiconductor device 1. Next, we will explain the semiconductor element included in the SiC semiconductor device 1. As shown in Fig. 4, the SiC semiconductor device 1 can include a vertical power MOSFET as the semiconductor element.

[0028] In this case, the SiC semiconductor layer 2 is n + a SiC substrate 11 and an n-type - The SiC substrate 11 is made of a single crystal of SiC. The SiC substrate 11 has an impurity concentration of 1×10 18 cm -3The epitaxial layer 12 is made of a single crystal of SiC having a dopant concentration lower than that of the SiC substrate 11. The epitaxial layer 12 is a layer formed on the main surface of the SiC substrate 11 by epitaxial growth.

[0029] In a predetermined region in the surface layer of the epitaxial layer 12, p - The base regions 13a and 13b are formed apart from each other. These base regions 13a and 13b are p + The base regions 13a and 13b are provided with p-type deep base layers 15a and 15b. The deep base layers 15a and 15b are formed in portions that do not overlap with the source regions 14a and 14b, which will be described later. The thicker portions of the base regions 13a and 13b where the deep base layers 15a and 15b are formed have a higher p-type impurity concentration than the thinner portions where the deep base layers 15a and 15b are not formed. By forming such deep base layers 15a and 15b, the electric field strength between the SiC substrate 11 and the deep base layers 15a and 15b can be increased, making avalanche breakdown more likely to occur at these positions.

[0030] In a predetermined region in the surface layer of the base region 13a, an n + A source region 14a of the n-type is formed in a predetermined region in the surface layer of the base region 13b. + A source region 14b of a MOSFET is formed in the base region 13a, 13b and the source region 14a, 14b. Recesses 16a, 16b are formed in the surfaces of the base regions 13a, 13b and the source regions 14a, 14b. Deep base layers 15a, 15b are exposed at the bottoms of the recesses 16a, 16b.

[0031] Furthermore, the surface portions of the base regions 13a and 13b between the epitaxial layer 12 and the source regions 14a and 14b are used as channel regions, and a gate insulating film 17 made of a silicon oxide film or the like is formed at least on these channel regions. The gate insulating film 17 is formed on the upper surfaces of the epitaxial layer 12 and the source regions 14a and 14b, including the channel regions. A gate electrode 18 is formed on the gate insulating film 17 as the surface electrode 3. The gate electrode 18 is covered with an insulating film 19 made of a silicon oxide film or the like.

[0032] A source electrode 20 serving as a front surface electrode 3 is formed on the main surface 2a side of the SiC semiconductor layer 2 so as to cover the insulating film 19. The source electrode 20 is connected to the source regions 14a, 14b and the base regions 13a, 13b. A drain electrode serving as a back surface electrode 5 is stacked on the silicide layer 4 on the back surface 2b side of the SiC semiconductor layer 2.

[0033] [Method for manufacturing SiC semiconductor device] Next, a method for manufacturing SiC semiconductor device 1 of this embodiment will be described with reference to Figures 5A to 5H and Figures 6 to 8. In this embodiment, a scribe-and-break method is used as a method for dicing the SiC wafer.

[0034] As shown in FIG. 5A, a SiC wafer 100 is prepared, and a portion of the back surface side of the SiC wafer 100 is removed. The prepared SiC wafer 100 includes a SiC semiconductor layer 2 having a main surface 2a and a back surface 2b. The SiC semiconductor layer 2 includes a SiC substrate 11 and an epitaxial layer 12. A semiconductor region (not shown) is formed on the surface layer of the SiC semiconductor layer 2. The semiconductor region is the base regions 13a, 13b, the source regions 14a, 14b, etc. in FIG. 4. The prepared SiC wafer 100 includes a front surface electrode 3 formed on the main surface 2a of the SiC semiconductor layer 2. The back surface side of the SiC wafer 100, i.e., the portion on the back surface 2b side of the SiC semiconductor layer 2, is ground.

[0035] Next, as shown in FIG. 5B, grooves 110 are formed in the rear surface 2b of the SiC semiconductor layer 2, and cracks 111 are generated as shown in FIG. 6. This is the scribing process. The grooves 110 are formed along the intended cutting line using a scribing tool such as a pen, roller, or laser. The cracks 111 extend from the bottom of the grooves 110 in the thickness direction of the SiC semiconductor layer 2. The thickness direction is perpendicular to the main surface 2a and the rear surface 2b. The grooves 110 are formed by wall surfaces 112. The wall surfaces 112 form part of the side surfaces 2c of the SiC semiconductor layer 2 after dicing.

[0036] At this time, the formation of the grooves 110 on the back surface 2b of the SiC semiconductor layer 2 causes a disturbance in the crystal structure of the SiC semiconductor layer 2 in the periphery of the grooves 110. As a result, the periphery of the grooves 110 becomes a modified layer 21. The periphery of the grooves 110 is a region of the SiC semiconductor layer 2 on the side of the wall surfaces 112, including the wall surfaces 112. In other words, the periphery of the grooves 110 is a region of the SiC semiconductor layer 2 that forms the wall surfaces 112.

[0037] 5C and 7, a metal film 114 is formed from the rear surface 2b of the SiC semiconductor layer 2 to the wall surfaces 112 that define the grooves 110. The metal film 114 is in contact with the rear surface 2b and the wall surfaces 112. The metal film 114 is a Ni film made of Ni.

[0038] Next, as shown in FIGS. 5D and 8, the back surface 2b side of the SiC semiconductor layer 2 is heat-treated to react silicon contained in the SiC semiconductor layer 2 with metal elements contained in the metal film 114, thereby forming a silicide layer 4. This reaction is a silicide reaction. Laser annealing is used as the heat treatment method. The silicide layer 4 is formed from the back surface 2b side to the wall surface 112 side. The silicide layer 4 contains NiSi as a metal silicide.

[0039] The portion of the silicide layer 4 provided on the back surface 2b is the back surface-side silicide layer 41 shown in Fig. 2B. The portion of the silicide layer 4 provided on the wall surface 112 is the side surface-side silicide layer 42 shown in Fig. 2B. In this manner, the side surface-side silicide layer 42 is formed on the back surface of the SiC wafer 100 by utilizing the process of forming the silicide layer 4 by laser annealing.

[0040] 5E, a metal film is formed on the back surface 2b side of the SiC semiconductor layer 2 to form the back surface electrode 5. At this time, a stacked film of Ti, Ni, and Au is formed as the metal film.

[0041] Subsequently, as shown in FIG. 5F, a dicing tape 116 is attached to the rear surface 2b side of the SiC semiconductor layer 2.

[0042] 5G, a breaking device is used to apply stress to the SiC wafer 100, thereby cutting the SiC wafer 100 into a plurality of chips. This is the breaking step.

[0043] The breaking device includes a support table 118 that supports the SiC wafer 100, and a blade 119 that applies stress to the SiC wafer 100. The support table 118 has a space 118a. The SiC wafer 100 is placed on the support table 118. In this state, the blade 119 applies stress to the main surface 2a side of the SiC wafer 100. As a result, the SiC wafer 100 is three-point bent by the blade 119 and walls 118b, 118b that form the space of the support table 118.

[0044] In the breaking process, this three-point bending causes crack 111 shown in FIG. 8 to propagate along a direction perpendicular to main surface 2a. As a result, SiC semiconductor layer 2 of SiC wafer 100 is cleaved as shown in FIG. 9. Silicide layer 4 and back surface electrode 5 are also cleaved starting from the grooves formed therein. As a result, SiC wafer 100 is cut into a plurality of chips.

[0045] Next, as shown in Fig. 5H, the dicing tape 116 is irradiated with UV light and die-picked. That is, each cut chip is extracted. In this manner, the SiC semiconductor device 1 of this embodiment is manufactured.

[0046] Next, the effects of this embodiment will be described in comparison with Comparative Example 1. In the method for manufacturing a SiC semiconductor device of Comparative Example 1, the steps shown in Figures 10A to 10H are carried out.

[0047] 10A, similar to the step shown in FIG. 5A, a portion of the back surface side of the SiC wafer 100 is removed. Subsequently, in the step shown in FIG. 10B, a metal film 114 is formed on the back surface 2b of the SiC semiconductor layer 2. Subsequently, in the step shown in FIG. 10C, a silicide layer 4 is formed on the back surface 2b by heat treatment of the back surface 2b of the SiC semiconductor layer 2. Subsequently, in the step shown in FIG. 10D, a back surface electrode 5 is formed on the back surface 2b of the SiC semiconductor layer 2.

[0048] 10E, grooves 110A are formed on the back surface 2b side of the SiC semiconductor layer 2. The grooves 110A are formed to a depth that penetrates the back surface electrode 5 and the silicide layer 4 and reaches a part of the SiC semiconductor layer 2. Although not shown, the formation of the grooves 110A forms cracks that extend from the bottoms of the grooves 110A in the thickness direction of the SiC semiconductor layer 2. Furthermore, although not shown, the formation of the grooves 110A causes the peripheral portions of the grooves 110A to become modified layers.

[0049] 10F, a dicing tape 116 is attached to the back surface 2b of the SiC semiconductor layer 2. Next, in a step shown in FIG. 10G, a breaking device is used to apply stress to the SiC wafer 100, thereby cutting the SiC wafer 100 into a plurality of chips. Next, in a step shown in FIG. 10H, the dicing tape 116 is irradiated with UV light and subjected to die picking. In this manner, the SiC semiconductor device 1A of Comparative Example 1 is manufactured.

[0050] 11 and 12, in the SiC semiconductor device 1A of Comparative Example 1, the modified layer 21 is exposed on the back surface 2b side of the side surface 2c of the SiC semiconductor layer 2. Therefore, as shown in FIG. 13, when thermal stress F1 is applied to the SiC semiconductor device 1A in a power card 30 on which the SiC semiconductor device 1A is mounted, a crack C1 occurs in the modified layer 21 exposed on the side surface 2c of the SiC semiconductor layer 2. The present inventors have discovered a problem in which the crack C1 progresses into the SiC semiconductor layer 2. In FIG. 13, the SiC semiconductor device 1A is sealed with a resin member 31.

[0051] In contrast, the manufacturing method of the SiC semiconductor device 1 of this embodiment includes, as described above, preparing a SiC wafer 100 having a SiC semiconductor layer 2 having a main surface 2a and a back surface 2b, forming a groove 110 in the back surface 2b to generate a crack 111, forming a metal film 114 on a wall surface 112 that constitutes the groove 110, forming a side silicide layer 42 on the wall surface 112 side of the SiC semiconductor layer 2 by heat treatment, and applying stress to the SiC wafer 100 to cut the SiC wafer 100 into a plurality of chips.

[0052] This allows the manufacture of the SiC semiconductor device 1 of this embodiment. The SiC semiconductor device 1 includes a SiC semiconductor layer 2 that includes a SiC single crystal, has a main surface 2a, a back surface 2b, and a side surface 2c, and includes a modified layer 21 that forms a part of the side surface 2c on the back surface 2b side. The SiC semiconductor device 1 further includes a side-side silicide layer 42 that is provided on the side surface 2c of the SiC semiconductor layer 2 and covers the modified layer 21.

[0053] According to this, the side surface silicide layer 42 covers the modified layer 21 on the side surface 2c side of the SiC semiconductor layer 2. Therefore, compared to the SiC semiconductor device 1 of Comparative Example 1 in which the SiC semiconductor device 1 does not have the side surface silicide layer 42, stress on the modified layer 21 when thermal stress F1 is applied to the SiC semiconductor device 1 mounted on the power card 30 is alleviated. Therefore, compared to the SiC semiconductor device 1 of Comparative Example 1, it is possible to suppress the occurrence of cracks on the side surface 2c of the SiC semiconductor layer 2.

[0054] The same effect can be obtained not only when the SiC semiconductor device 1 is mounted on the power card 30 but also when the SiC semiconductor device 1 is mounted on another device. That is, when stress is applied to the SiC semiconductor device 1, the stress on the modified layer 21 can be alleviated.

[0055] (Second embodiment) In the first embodiment, the side surface silicide layer 42 is adjacent to the modified layer 21 on the outside in the direction DR1 parallel to the main surface 2a.

[0056] 14, in this embodiment, the side-side silicide layer 42 faces and contacts the portion of the SiC semiconductor layer 2 made of SiC single crystal in the direction DR1 parallel to the main surface 2a. That is, no modified layer 21 exists between the portion of the SiC semiconductor layer 2 made of SiC single crystal and the side-side silicide layer 42 in the direction DR1 parallel to the main surface 2a.

[0057] In this embodiment as well, the side surface silicide layer 42 forms part of the side surface of the SiC semiconductor device 1. The side surface silicide layer 42 is adjacent to the rear surface 2b of the SiC semiconductor layer 2 with respect to the modified layer 21 exposed at the side surface 2c of the SiC semiconductor layer 2.

[0058] This structure is formed by the fact that, in the formation of the silicide layer 4 in the steps shown in FIGS. 5D and 8 described in the first embodiment, the silicide reaction in the portion of the modified layer 21 that contacts the metal film 114 in FIG. 7 occurs largely in the direction DR1 parallel to the main surface 2a. Even in this case, the silicide reaction does not occur in the portion of the modified layer 21 that does not contact the metal film 114 shown in FIG. 7. For this reason, as shown in FIG. 14, part of the modified layer 21 that was formed in the scribing step remains.

[0059] Other configurations of the SiC semiconductor device 1 and other configurations of the method for manufacturing the SiC semiconductor device 1 are the same as those of the first embodiment.

[0060] According to the present embodiment, the side surface silicide layer 42 is formed on the side surface 2c of the SiC semiconductor layer 2, thereby reducing the modified layer 21 compared to the SiC semiconductor device 1A of Comparative Example 1 in which the side surface silicide layer 42 is not formed. As a result, the occurrence of cracks on the side surface 2c of the SiC semiconductor layer 2 can be suppressed compared to the SiC semiconductor device 1A of Comparative Example 1.

[0061] (Other embodiments) (1) In the SiC semiconductor device 1 of the first embodiment, the silicide layer 4, including the backside silicide layer 41 and the sideside silicide layer 42, is composed only of NiSi as a metal silicide. However, the silicide layer 4 may contain a compound other than a metal silicide. Examples of the compound other than a metal silicide include metal carbides such as MoC and TiC.

[0062] The silicide layer 4 may also contain a metal silicide other than NiSi. Examples of metal silicides other than NiSi include TiSi, MoSi, TaSi, PtSi, and CoSi. The metal silicide may also contain multiple metal elements. As such, the metal silicide contained in the silicide layer 4 only needs to contain at least one of Ni, Ti, Mo, Ta, Pt, and Co as the metal element.

[0063] (2) In the SiC semiconductor device 1 of the first embodiment, the SiC semiconductor layer 2 is a hexagonal SiC single crystal. However, the SiC semiconductor layer 2 may be a cubic SiC single crystal. In this case, the crystal orientation plane of the cleavage planes constituting the multiple side surfaces 2c is the (011) plane, as shown in FIG. 15. The (0-1-1) plane, the (011) plane, the (01-1) plane, and the (0-11) plane all have the same structure.

[0064] (3) In the method for manufacturing the SiC semiconductor device 1 of the first embodiment, the side surface silicide layer 42 and the back surface silicide layer 41 are formed simultaneously. Therefore, the side surface silicide layer 42 is continuous with the back surface silicide layer 41. However, the side surface silicide layer 42 and the back surface silicide layer 41 may be formed separately. In this case, the side surface silicide layer 42 may be separated from the back surface silicide layer 41.

[0065] (4) In the SiC semiconductor device 1 of the first embodiment, the side surface silicide layer 42 is disposed continuously over all of the multiple side surfaces 2c. However, the side surface silicide layer 42 does not have to be disposed continuously. The side surface silicide layer 42 may be disposed only on some of the four side surfaces. Even in these cases, the occurrence of cracks on the side surfaces 2c of the SiC semiconductor layer 2 can be suppressed in the portions where the side surface silicide layer 42 is formed.

[0066] (5) The semiconductor element included in the SiC semiconductor device 1 of the first embodiment is a planar vertical power MOSFET. However, the semiconductor element may be a trench gate vertical power MOSFET. The semiconductor element may also be another vertical semiconductor element.

[0067] (6) The present invention is not limited to the above-described embodiments and can be modified as appropriate within the scope of the claims, including various modifications and modifications within the scope of equivalents. Furthermore, the above-described embodiments are not unrelated to each other and can be combined as appropriate unless the combination is clearly impossible. It goes without saying that the elements constituting the embodiments are not necessarily essential unless specifically stated as essential or clearly considered essential in principle. Furthermore, when the numbers, values, amounts, ranges, etc. of the components of the embodiments are mentioned in the above-described embodiments, they are not limited to the specific numbers unless specifically stated as essential or clearly limited to a specific number in principle. Furthermore, when the materials, shapes, positional relationships, etc. of the components are mentioned in the above-described embodiments, they are not limited to the specific materials, shapes, positional relationships, etc., unless specifically stated or clearly limited to a specific material, shape, positional relationship, etc. in principle. [Explanation of symbols]

[0068] 2 SiC semiconductor layer 21 Modified layer 4 Silicide layer 41 Backside silicide layer 42 Side silicide layer

Claims

1. A silicon carbide semiconductor device, a silicon carbide semiconductor layer (2) including a silicon carbide single crystal, having a main surface (2a), a back surface (2b) opposite to the main surface, and a side surface (2c) connecting the main surface and the back surface and constituted by a cleavage plane, constituting a wall surface (112) that is a part of the back surface side of the side surface and is located inside the main surface side of the side surface in a direction (DR1) parallel to the main surface, and in which a modified layer (21) having an atomic arrangement structure of silicon carbide different from that of the silicon carbide single crystal is present; a side-side silicide layer (42) including a metal silicide that is a compound of a metal element and silicon, the side-side silicide layer (42) being provided on the side of the silicon carbide semiconductor layer and covering the modified layer outside a direction (DR1) parallel to the main surface.

2. A silicon carbide semiconductor device, a silicon carbide semiconductor layer (2) including a silicon carbide single crystal, having a main surface (2a), a back surface (2b) opposite to the main surface, and a side surface (2c) connecting the main surface and the back surface and constituted by a cleavage plane, constituting a wall surface (112) that is a part of the back surface side of the side surface and is located inside the main surface side of the side surface in a direction (DR1) parallel to the main surface, and in which a modified layer (21) having an atomic arrangement structure of silicon carbide different from that of the silicon carbide single crystal is present; a side-side silicide layer (42) including a metal silicide which is a compound of a metal element and silicon, the side-side silicide layer (42) being provided on the side of the silicon carbide semiconductor layer, adjacent to the back surface side of the modified layer, and in contact with a portion of the silicon carbide semiconductor layer made of silicon carbide single crystal in a direction parallel to the main surface, without the modified layer being interposed therebetween.

3. A silicon carbide semiconductor device, a silicon carbide semiconductor layer (2) including a silicon carbide single crystal, having a main surface (2a), a back surface (2b) opposite to the main surface, and a side surface (2c) connecting the main surface and the back surface and constituted by a cleavage plane, and constituting a part of the back surface side of the side surface, and having a modified layer (21) which is an atomic arrangement structure of silicon carbide different from that of the silicon carbide single crystal; a side silicide layer (42) including a metal silicide which is a compound of a metal element and silicon, and provided on the side surface of the silicon carbide semiconductor layer and covering the modified layer; the silicon carbide semiconductor layer has a plurality of side surfaces including the side surface, the modified layer constitutes a part of the back surface side of each of the plurality of side surfaces, the side surface silicide layer is disposed continuously over all of the plurality of side surfaces.

4. A silicon carbide semiconductor device, a silicon carbide semiconductor layer (2) including a silicon carbide single crystal, having a main surface (2a), a back surface (2b) opposite to the main surface, and a side surface (2c) connecting the main surface and the back surface and constituted by a cleavage plane, and constituting a part of the back surface side of the side surface, and having a modified layer (21) which is an atomic arrangement structure of silicon carbide different from that of the silicon carbide single crystal; a side-side silicide layer (42) including a metal silicide which is a compound of a metal element and silicon, provided on the side surface of the silicon carbide semiconductor layer, adjacent to the rear surface side of the modified layer, and facing and in contact with a portion of the silicon carbide semiconductor layer made of silicon carbide single crystal in a direction parallel to the main surface, the silicon carbide semiconductor layer has a plurality of side surfaces including the side surface, the modified layer constitutes a part of the back surface side of each of the plurality of side surfaces, the side surface silicide layer is disposed continuously over all of the plurality of side surfaces.

5. The silicon carbide semiconductor device includes a back-side silicide layer (41) provided on the back surface of the silicon carbide semiconductor layer and containing a metal silicide which is a compound of a metal element and silicon, The silicon carbide semiconductor device according to claim 3 , wherein said side silicide layer is continuous with said back surface silicide layer.

6. 6. The silicon carbide semiconductor device according to claim 3, wherein said metal silicide contains at least one of Ni, Ti, Mo, Ta, Pt, and Co as said metal element.

7. A method for manufacturing a silicon carbide semiconductor device, comprising: A silicon carbide wafer (100) is provided with a silicon carbide semiconductor layer (2) including a silicon carbide single crystal and having a main surface (2a) and a back surface (2b) opposite to the main surface; forming a groove (110) on the back surface along a line to be cut to generate a crack (111); forming a metal film (114) on a wall surface (112) that constitutes the groove; reacting silicon contained in the silicon carbide semiconductor layer with a metal element contained in the metal film by heat treatment to form a silicide layer (4) containing a metal silicide on the wall surface side of the silicon carbide semiconductor layer; applying stress to the silicon carbide wafer to cause the crack to propagate along a direction perpendicular to the main surface, and dicing the silicon carbide wafer into a plurality of chips.

8. In forming the metal film, the metal film is formed from the back surface to the wall surface; 8. The method for manufacturing a silicon carbide semiconductor device according to claim 7, wherein, in forming said silicide layer, said silicide layer is formed from said back surface side to said wall surface side of said silicon carbide semiconductor layer.

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