NAND cell structure with charge trap cut

Abstract

A memory device is described that includes a plurality of memory cells formed around a memory hole that extends through a memory stack on a substrate. Each of the plurality of memory cells includes a discontinuous blocking oxide layer, a charge trapping layer, and a tunnel oxide layer. The blocking oxide layer is discontinuous between each of the plurality of memory cells. The tunnel oxide layer is continuous between each of the plurality of memory cells, and the charge trapping layer is discontinuous between each of the plurality of memory cells. The charge trapping layer has a first thickness at a top portion and a second thickness at a center portion, the first thickness being different from the second thickness.

Description

[Technical Field]

[0001]

[0001] Embodiments of the present disclosure relate to the field of electronic devices and methods and apparatus for manufacturing electronic devices. More particularly, embodiments of the present disclosure provide 3D-NAND with a discontinuous charge trapping layer and methods of formation. [Background technology]

[0002]

[0002] Semiconductor technology is advancing at a rapid pace, and device dimensions are shrinking as technology advances to achieve faster processing and storage speeds per unit space. In NAND devices, the string current must be high enough to obtain enough current to distinguish between ON and OFF cells. The string current depends on carrier mobility, which is improved by increasing the grain size of the silicon channel.

[0003]

[0003] Current 3D-NAND stacks based on charge traps as the storage layer contain a continuous charge trapping layer. The continuous charge trapping layer causes two major problems that hinder scaling down from word line (WL) to WL insulator: cell-to-cell interference and lateral charge diffusion. To suppress these problems, the charge trapping layer under the source and drain (S / D) of each cell needs to be eliminated by a trap-cut structure or confinement structure. However, problems arise in the trap-cut structure due to partial use of the gate area and variations in the shape and thickness of the trapping layer caused by the deposition and removal processes.

[0004]

[0004] Therefore, there is a need in the art for a 3D-NAND device with an improved charge trapping layer and a method for fabricating a 3D-NAND device. Summary of the Invention

[0005] One or more embodiments of the present disclosure are directed to a semiconductor memory device including: a plurality of memory cells formed around a memory hole extending through a memory stack on a substrate, the memory stack including alternating word lines and a dielectric material, each of the plurality of memory cells including a discontinuous blocking oxide layer, a charge trapping layer, and a tunnel oxide layer, the blocking oxide layer being discontinuous between each of the plurality of memory cells, the tunnel oxide layer being continuous between each of the plurality of memory cells, and the charge trapping layer being discontinuous between each of the plurality of memory cells; and a filled slit extending through the memory stack adjacent to the memory hole.

[0006]

[0006] Further embodiments of the present disclosure are directed to a method for forming a semiconductor memory device. In one or more embodiments, the method for forming the semiconductor device includes forming a memory hole in a memory stack including alternating layers of a first material and a second material on a substrate, recessing the second material through the memory hole to form a first recessed region, oxidizing a portion of the second material adjacent to the memory hole to form a blocking oxide layer, depositing a charge trapping layer on the blocking oxide layer, conformally depositing a sacrificial layer on the charge trapping layer, selectively removing the charge trapping layer from the sacrificial layer, removing the sacrificial layer, forming a bit line in the memory hole, patterning a slit, forming a plurality of word lines, and filling the slit.

[0007]

[0007] Further embodiments of the present disclosure are directed to a non-transitory computer-readable medium. In one or more embodiments, the non-transitory computer-readable medium includes instructions that, when executed by a controller of a processing chamber, cause the processing chamber to perform steps of forming a memory hole in a memory stack including alternating layers of a first material and a second material on a substrate, recessing the second material through the memory hole to form a first recessed region, oxidizing a portion of the second material adjacent to the memory hole to form a blocking oxide layer, depositing a charge trapping layer on the blocking oxide layer, conformally depositing a sacrificial layer on the charge trapping layer, selectively removing the charge trapping layer from the sacrificial layer, removing the sacrificial layer, forming a bit line in the memory hole, patterning a slit, forming a plurality of word lines, and filling the slit.

[0008]

[0008] In order that the features of the present disclosure described above may be understood in detail, the present disclosure summarized above will now be more particularly described with reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings depict only typical embodiments of the present disclosure and therefore should not be considered as limiting the scope of the present disclosure, which may also admit of other equally effective embodiments. The embodiments described herein are presented by way of example and not by way of limitation to the figures of the accompanying drawings, in which like references indicate similar elements. [Brief explanation of the drawings]

[0009] [Figure 1-1] FIG. 1 is a process flow diagram of a method for forming a memory device according to embodiments described herein. [Figure 1-2] FIG. 1 is a process flow diagram of a method for forming a memory device according to embodiments described herein. [Figure 2] 1 is a cross-sectional view of an electronic device including a memory stack according to one or more embodiments. [Figure 3] 1A and 1B are cross-sectional views of an electronic device after forming a stepped pattern of a memory stack according to one or more embodiments. [Figure 4]1 is a cross-sectional view illustrating an electronic device according to one or more embodiments. [Figure 5A] 1 is a cross-sectional view illustrating an electronic device according to one or more embodiments. [Figure 5B] 1 is an enlarged view of region 120 according to one or more embodiments. [Figure 6A] 1 is an enlarged view of region 120 according to one or more embodiments. [Figure 6B] 1 is a cross-sectional view illustrating an electronic device according to one or more embodiments. [Figure 7A] 1 is a cross-sectional view illustrating an electronic device according to one or more embodiments. [Figure 7B] 1 is an enlarged view of region 120 according to one or more embodiments. [Figure 8A] 1 is a cross-sectional view illustrating an electronic device according to one or more embodiments. [Figure 8B] 1 is an enlarged view of region 120 according to one or more embodiments. [Figure 9A] 1 is a cross-sectional view illustrating an electronic device according to one or more embodiments. [Figure 9B] 1 is an enlarged view of region 120 according to one or more embodiments. [Figure 10A] 1 is a cross-sectional view illustrating an electronic device according to one or more embodiments. [Figure 10B] 1 is an enlarged view of region 120 according to one or more embodiments. [Figure 11A] 1 is a cross-sectional view illustrating an electronic device according to one or more embodiments. [Figure 11B] 1 is an enlarged view of region 120 according to one or more embodiments. [Figure 11C] 1 is an enlarged view of region 120 according to one or more alternative embodiments. [Figure 12A] 1 is a cross-sectional view illustrating an electronic device according to one or more embodiments. [Figure 12B] 1 is an enlarged view of region 120 according to one or more embodiments. [Figure 13]1 is a cross-sectional view illustrating an electronic device according to one or more embodiments. [Figure 14] 1 is a cross-sectional view illustrating an electronic device according to one or more embodiments. [Figure 15] 1 is a cross-sectional view illustrating an electronic device according to one or more embodiments. [Figure 16] 1 is a cross-sectional view illustrating an electronic device according to one or more embodiments. [Figure 17] 1 is a cross-sectional view illustrating an electronic device according to one or more embodiments. [Figure 18] 1 is a cross-sectional view illustrating an electronic device according to one or more embodiments. [Figure 19] 1 is a cross-sectional view illustrating an electronic device according to one or more embodiments. [Figure 20] 1 is a cross-sectional view illustrating an electronic device according to one or more embodiments. [Figure 21A] 1 is a cross-sectional view illustrating an electronic device according to one or more embodiments. [Figure 21B] FIG. 1 is an enlarged view of region 170 according to one or more embodiments. [Figure 22-1] FIG. 1 is a process flow diagram illustrating a method of forming a memory device according to embodiments described herein. [Figure 22-2] FIG. 1 is a process flow diagram illustrating a method of forming a memory device according to embodiments described herein. [Figure 23A] FIG. 1 is a perspective view illustrating an electronic device according to one or more embodiments. [Figure 23B] 1 is an enlarged view of region 180 according to one or more embodiments. [Figure 24A] FIG. 1 is a perspective view illustrating an electronic device according to one or more embodiments. [Figure 24B] 1 is an enlarged view of region 180 according to one or more embodiments. [Figure 25A] FIG. 1 is a perspective view illustrating an electronic device according to one or more embodiments. [Figure 25B] 1 is an enlarged view of region 180 according to one or more embodiments. [Figure 26A] FIG. 1 is a perspective view illustrating an electronic device according to one or more embodiments. [Figure 26B] 1 is an enlarged view of region 180 according to one or more embodiments. [Figure 27] FIG. 1 illustrates a cluster tool according to one or more embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0010]

[0050] Before describing several example embodiments of the present disclosure, it is to be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description. The present disclosure is capable of other embodiments and of being practiced or being carried out in various ways.

[0011]

[0051] As used herein and in the appended claims, the terms "precursor," "reactant," "reactive gas," and the like are used interchangeably to refer to any gas species capable of reacting with the substrate surface.

[0012]

[0052] As used herein, "atomic layer deposition" or "cyclic deposition" refers to the sequential exposure of two or more reactive compounds to deposit layers of material on a substrate surface. As used herein and in the appended claims, the terms "reactive compound," "reactive gas," "reactive species," "precursor," "process gas," and the like are used interchangeably to refer to substances having species capable of reacting with the substrate surface or materials on the substrate surface in a surface reaction (e.g., chemisorption, oxidation, reduction). The substrate or a portion of the substrate is exposed to the precursors (or reactive gases) sequentially or substantially sequentially. As used throughout this specification, "substantially sequential" means that the majority of the duration of precursor exposure does not overlap with exposure to a co-reagent, although some overlap is possible.

[0013]

[0053] As used herein, the term "over" does not refer to the physical orientation of one surface over another, but rather to the relationship of the thermodynamic or kinetic properties of the relative chemical reactions between one surface and another. For example, selectively depositing a film on a damaged dielectric material over an oxide material means that the film deposits on the damaged dielectric material and less or not at all on the oxide material, or that the formation of a film on the damaged dielectric material is thermodynamically or kinetically favored relative to the formation of a film on the oxide material.

[0014]

[0054] In the following description, numerous specific details are set forth, such as particular materials, chemicals, dimensions of elements, etc., to provide a thorough understanding of one or more embodiments of the present disclosure. However, it will be apparent to one skilled in the art that one or more embodiments of the present disclosure may be practiced without these specific details. In other instances, semiconductor manufacturing processes, techniques, materials, equipment, etc. have not been described in detail to avoid unnecessarily obscuring the specification. One skilled in the art will be able, given the description contained herein, to achieve the appropriate functionality without undue experimentation.

[0015]

[0055] While certain exemplary embodiments of the present disclosure have been described and illustrated in the accompanying drawings, it is to be understood that the above embodiments are illustrative only and do not limit the present disclosure, and that the present disclosure is not limited to the specific constructions and arrangements shown and described, as modifications may be made by those skilled in the art.

[0016]

[0056] In existing 3D NAND devices based on a memory stack of alternating layers of oxide and nitride materials and with charge traps as the storage layer, the charge traps are a continuous layer. This continuous charge trap layer causes cell-to-cell interference and lateral charge diffusion, preventing scaling down from the word line (WL) to the WL insulator. To address cell-to-cell interference and lateral charge diffusion, trap cuts or confinement structures must be used to eliminate the trap layer under the source and drain (S / D) of each cell. However, trap cuts cannot use the gate region, and the trap layer must have a consistent shape and thickness. Therefore, one or more embodiments provide a 3D NAND structure and a method for fabricating a charge trap layer using trap cuts.

[0017]

[0057] One or more embodiments provide structures and methods for fabricating 3-NAND devices using atomic layer deposited silicon nitride for the formation of a discontinuous charge trapping layer. The charge trapping layer of one or more embodiments is confined only between the tunnel oxide and the word line, so that cell-to-cell interference and lateral diffusion are not inhibited. In one or more embodiments, non-selective silicon nitride (SiN) can be used as the charge trapping layer.

[0018]

[0058] In one or more embodiments, metal deposition and other processes can be performed in an isolated environment (e.g., a cluster processing tool). Accordingly, some embodiments of the present disclosure provide an integrated tool system with associated process modules for performing the methods.

[0019]

[0059] FIG. 1 is a flow diagram illustrating an exemplary method 10 for forming a memory device. Those skilled in the art will recognize that method 10 can include any or all of the illustrated processes. Furthermore, the order of the individual processes may vary in some respects. Method 10 can begin with any of the listed processes without departing from this disclosure. Referring to FIG. 1 , in step 12, a memory stack is formed. In step 14, word line steps are formed in the memory stack. In step 16, a memory hole is patterned. In step 18, a nitride layer is recessed. In step 20, a blocking oxide is formed in the recess. In step 22, a charge trapping layer is deposited, followed by a sacrificial layer. In step 24, the sacrificial layer is partially removed. In step 26, the charge trapping layer is unmasked and the sacrificial layer is removed. In step 28, a transistor layer is deposited in the memory hole. In step 30, bit line pads are formed. In step 32, a slit pattern is formed in the device. In step 34, the common source line sacrificial layer is removed and replaced. In step 36, the nitride layer of the memory stack is removed (mold pullback). In step 38, word lines are formed. In step 40, the slits are filled. In step 42, bit line pad studs are formed. In step 44, back-end (BEOL) contacts are formed.

[0020]

[0060] 2-21 are diagrams illustrating a portion of a memory device 100 following the process flow illustrated in method 10 of FIG.

[0021]

[0061] Figure 2 is a diagram illustrating an initial or starting memory stack of an electronic device 100 according to one or more embodiments of the present disclosure. In some embodiments, the electronic device 100 shown in Figure 2 is formed as layers on a bare substrate 102, as shown. The electronic device of Figure 2 is comprised of the substrate 102, a common source line 103, and a memory stack 130.

[0022]

[0062] The substrate 102 can be any suitable material known to those skilled in the art. As used herein and in the appended claims, the term "substrate" refers to a surface, or a portion of a surface, upon which a process acts. Those skilled in the art will also understand that a reference to a substrate may refer to only a portion of a substrate, unless the context clearly dictates otherwise. Furthermore, a reference to depositing on a substrate can refer to both a bare substrate and a substrate having one or more films or features deposited or formed thereon.

[0023]

[0063] As used herein, "substrate" refers to any substrate or material surface formed on a substrate on which film processing is performed during a manufacturing process. For example, substrate surfaces on which processing may be performed include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, but are not limited to, semiconductor wafers. Substrates may be exposed to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to performing film processing directly on the surface of the substrate itself, in the present disclosure, any of the disclosed film processing steps may be performed on an underlying layer formed on the substrate, as disclosed in more detail below, and the term "substrate surface" is intended to include such underlying layers as the context indicates. Thus, for example, when a film / layer or partial film / layer is deposited on a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0024]

[0064] In one or more embodiments, a common source line 103 is on the substrate 102. The common source line 103 may also be referred to as a semiconductor layer. The common source line 103 may be formed by any suitable technique known to those skilled in the art and may be made of any suitable material, including, but not limited to, polysilicon (poly-Si). In some embodiments, the common source line 103 comprises multiple different conductive or semiconductor materials. For example, in one or more embodiments, as shown in FIG. 2 , the common source line 103 includes a polysilicon layer 104 on the substrate 102, a common source sacrificial layer 106 on the polysilicon layer, and a second polysilicon layer 104 on the common source sacrificial layer 106.

[0025]

[0065] In one or more embodiments, the sacrificial layer 106 may be formed on the polysilicon layer 104 and may be made of any suitable material. In some embodiments, the sacrificial layer 106 is removed and replaced in a later process. In some embodiments, the sacrificial layer 106 is not removed but remains in the memory device 100. In this case, the term "sacrificial" has an expanded meaning to include a permanent layer, which may be referred to as a conductive layer. In the illustrated embodiment, the sacrificial layer 106 is removed in step 34, as described further below. In one or more embodiments, the sacrificial layer 106 comprises a material that can be selectively removed relative to the adjacent polysilicon layer 104. In one or more embodiments, the sacrificial layer is a nitride material, such as silicon nitride (SiN), or an oxide material, such as silicon oxide (SiO x ) is included.

[0026]

[0066] In one or more embodiments, a memory stack 130 is formed over the common source line 103. The memory stack 130 in the illustrated embodiment includes a plurality of alternating first layers 108 and second layers 110. While the memory stack 130 illustrated in FIG. 2 includes five pairs of alternating first layers 108 and second layers 110, those skilled in the art will recognize that this is for illustrative purposes only. The memory stack 130 may include any number of alternating first layers 108 and second layers 110. For example, in some embodiments, the memory stack 130 includes 192 pairs of alternating first layers 108 and second layers 110. In other embodiments, the memory stack 130 includes more than 50 pairs of alternating first layers 108 and second layers 110, or more than 100 pairs of alternating first layers 108 and second layers 110, or more than 300 pairs of alternating first layers 108 and second layers 110.

[0027]

[0067] In one or more embodiments, the first layer 108 and the second layer 110 independently comprise a dielectric material. In one or more embodiments, the dielectric material may comprise any suitable dielectric material known to those skilled in the art. As used herein, the term "dielectric material" refers to an electrical insulator that can be polarized in an electric field. In some embodiments, the dielectric material comprises one or more of an oxide, a carbon-doped oxide, porous silicon dioxide (SiO), silicon nitride (SiN), silicon dioxide / silicon nitride, a carbide, an oxycarbide, a nitride, an oxynitride, an oxycarbonitride, a polymer, a phosphosilicate glass, a fluorosilicate (SiOF) glass, or an organosilicate glass (SiOCH).

[0028]

[0068] In one or more embodiments, the first layer 108 comprises an oxide layer and the second layer 110 comprises a nitride layer. In one or more embodiments, the second layer 110 comprises a material that has etch selectivity with respect to the first layer 108 such that the second layer 110 can be removed without substantially affecting the first layer 108. In one or more embodiments, the first layer 108 comprises silicon oxide (SiO xIn one or more embodiments, the second layer 110 comprises silicon nitride (SiN). In one or more embodiments, the first layer 108 and the second layer 110 are deposited by chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0029]

[0069] The individual alternating layers may be formed to any suitable thickness. In some embodiments, the thickness of each second layer 110 is approximately equal. In one or more embodiments, each second layer 110 has the thickness of the second layer. In some embodiments, the thickness of each first layer 108 is approximately equal. As used in this regard, approximately equal thicknesses are within ±5% of each other. In some embodiments, a silicon layer (not shown) is formed between the second layer 110 and the first layer 108. The thickness of the silicon layer may be relatively thin compared to the thickness of either the second layer 110 or the first layer 108. In one or more embodiments, the first layer 108 has a thickness ranging from about 0.5 nm to about 30 nm, including about 1 nm, about 3 nm, about 5 nm, about 7 nm, about 10 nm, about 12 nm, about 15 nm, about 17 nm, about 20 nm, about 22 nm, about 25 nm, about 27 nm, and about 30 nm. In one or more embodiments, the first layer 108 has a thickness in the range of about 0.5 to about 40 nm. In one or more embodiments, the second layer 110 has a thickness in the range of about 0.5 to about 30 nm, including about 1 nm, about 3 nm, about 5 nm, about 7 nm, about 10 nm, about 12 nm, about 15 nm, about 17 nm, about 20 nm, about 22 nm, about 25 nm, about 27 nm, and about 30 nm. In one or more embodiments, the second layer 110 has a thickness in the range of about 0.5 to about 40 nm.

[0030]

[0070] In one or more embodiments, the first layer 108 and the second layer 110 are deposited by chemical vapor deposition (CVD) or physical vapor deposition (PVD). The individual alternating layers may be formed to any suitable thickness. In some embodiments, the thickness of each second layer 112 is approximately equal. In one or more embodiments, each second layer 112 has the thickness of the first second layer. In some embodiments, the thickness of each first layer 110 is approximately equal. As used in this regard, approximately equal thicknesses are within ±5% of each other. In one or more embodiments, the first layer 108 has a thickness in the range of about 0.5 nm to about 30 nm, including about 1 nm, about 3 nm, about 5 nm, about 7 nm, about 10 nm, about 12 nm, about 15 nm, about 17 nm, about 20 nm, about 22 nm, about 25 nm, about 27 nm, and about 30 nm. In one or more embodiments, the second layer 110 has a thickness in the range of about 0.5 nm to about 30 nm, including about 1 nm, about 3 nm, about 5 nm, about 7 nm, about 10 nm, about 12 nm, about 15 nm, about 17 nm, about 20 nm, about 22 nm, about 25 nm, about 27 nm, and about 30 nm.

[0031]

[0071] Referring to FIG. 3 , in step 14 of method 10, staircase structure 131 is fabricated. In one or more embodiments, staircase structure 131 exposes a top surface 134 of first layer 108. Top surface 134 can be used to provide space for forming word line contacts, as described below. A suitable filler material 135 can be deposited to fill the space outside staircase structure 131. A suitable filler material 135 can be any material that prevents electrical shorting between adjacent word lines, as will be understood by those skilled in the art. Staircase structure 131 has a width (shown from left to right in the figure) in which each word line is smaller than the word line below it. The use of relative terms such as “top” and “bottom” should not be construed as limiting the scope of the present disclosure to physical orientations in space.

[0032]

[0072] 4, in step 16, the memory hole channel 116 is opened / patterned through the memory stack 130. In some embodiments, opening the memory hole channel 116 includes etching through the mask layer 137, the memory stack 130, the common source line 103, and the substrate 102. The memory hole channel 116 has sidewalls that extend through the memory stack 130, exposing the surface 111 of the second layer 110 and the surface 109 of the first layer 108.

[0033]

[0073] The memory hole channel 116 extends a distance into the substrate 102 such that sidewall surfaces 109, 111, 113 and a bottom surface 115 of the memory hole channel 116 are formed within the substrate 102. The bottom 114 of the memory hole channel 116 can be formed at any point within the thickness of the substrate 102. In some embodiments, the memory hole channel 116 extends into the substrate 102 a thickness in the range of about 1% to about 90%, or about 5% to about 90%, or about 20% to about 80%, or about 30% to about 70%, or about 40% to about 60% of the thickness of the substrate 102. In some embodiments, the memory hole channel 116 extends into the substrate 102 a distance of 10 nm or more.

[0034]

[0074] 5A and 5B illustrate step 18, in which second layer 110 is recessed partially through memory hole 116 to form recessed region 118. In one or more embodiments, second layer 110 is recessed by a recess distance r1 ranging from 1 nm to 30 nm, or from 5 nm to 20 nm. Accordingly, in one or more embodiments, recessed region 118 has a size ranging from 1 nm to 30 nm, or from 5 nm to 20 nm. Second layer 110 can be recessed by any method known to those skilled in the art. In one or more embodiments, a portion of second layer 110 is recessed through memory hole 116 by selective removal with reactive species formed via a remote plasma from a process gas including oxygen (O) and nitrogen trifluoride (NF). In other embodiments, a portion of second layer 110 is recessed through memory hole 116 by selective removal with hot phosphorus (HP).

[0035]

[0075] 6A and 6B illustrate step 20 in which a blocking oxide layer 122 is formed in recessed region 118 adjacent second layer 110. In one or more embodiments, blocking oxide layer 122 is formed by oxidizing a portion of second layer 110. Thus, in one or more embodiments, blocking oxide layer 122 comprises silicon oxynitride (SiON). Blocking oxide layer 122 may have any suitable thickness. In some embodiments, blocking oxide layer 122 has a thickness in the range of 1 nm to 15 nm, or in the range of 3 nm to 10 nm.

[0036]

[0076] 7A and 7B illustrate step 22, in which a charge trapping layer 124 is formed adjacent to the blocking oxide layer 122. In some embodiments, the sides of the charge trapping layer 124 are exposed to the memory hole channel 116. The charge trapping layer 124 may comprise any suitable material known to those skilled in the art. In one or more embodiments, the charge trapping layer 124 comprises a nitride, such as silicon nitride (SiN). The charge trapping layer 124 may be formed by any suitable means known to those skilled in the art. In one or more embodiments, the charge trapping layer 124 is deposited by atomic layer deposition (ALD). In some embodiments, the charge trapping layer 124 has a thickness in the range of 1 nm to 15 nm, or in the range of 3 nm to 10 nm.

[0037]

[0077] 8A and 8B illustrate step 22 in which a sacrificial layer 128 is formed adjacent to the charge trapping layer 124 and through the memory hole channel 116 in the recessed region 118. The sacrificial layer 128 may comprise any suitable material known to those skilled in the art. In one or more embodiments, the sacrificial layer 128 is an oxide layer, such as silicon oxide (SiO x ). The sacrificial layer 128 can be formed by any suitable means known to those skilled in the art. In one or more embodiments, the sacrificial layer is formed by atomic layer deposition (ALD). In one or more embodiments, the sacrificial layer 128 is a conformal layer. In other embodiments, the sacrificial layer 128 is a conformal layer, where the sacrificial layer 128 substantially conforms to the underlying charge trapping layer 124. As used herein, a "substantially conformal" layer refers to a layer that has about the same thickness throughout (e.g., over the charge trapping layer 124). A substantially conformal layer has a thickness variation of about 5% or less, 2% or less, 1% or less, or 0.5% or less.

[0038]

[0078] 8B, the sacrificial layer 128 is thicker in the center of the recessed region 118 compared to the top and bottom of the recessed region 118. In one or more embodiments, the center of the sacrificial layer 128 has a thickness in the range of 1 nm to 50 nm or in the range of 5 nm to 30 nm, and the top / bottom of the sacrificial layer 128 has a thickness in the range of >0% to 50% of the thickness of the center of the sacrificial layer 128.

[0039]

[0079] 9A and 9B, in step 24, a portion of the sacrificial layer 128 is removed. In one or more embodiments, the sacrificial layer 128 is removed from the sidewalls of the memory hole channel 116, while leaving portions 129 of the sacrificial layer 128 within the recessed region 118. The sacrificial layer 128 can be removed by any suitable means known to those skilled in the art. In one or more embodiments, the portion of the sacrificial layer 128 is removed by selective etching, for example, with a dilute hydrofluoric acid (HF) solution or HF gas.

[0040]

[0080] 10A and 10B, in step 26, the portions 130 of the sacrificial layer 128 are unmasked, e.g., trap cut, by selectively removing the charge trapping layer 124 around the portions 130 of the sacrificial layer 128. The portions 130 of the sacrificial layer 128 may be unmasked by any suitable means. In one or more embodiments, the charge trapping layer 124 is selectively removed from the portions 130 of the sacrificial layer 128 using a wet or dry process with phosphoric acid solution or gas.

[0041]

[0081] 11A and 11B, after the trap cut of step 26, the remaining portions 130 of the sacrificial layer 128 are removed to form openings 132. The remaining portions 130 of the sacrificial layer 128 may be removed by any suitable means. In one or more embodiments, the remaining portions 130 of the sacrificial layer 128 are removed by selective etching. In some specific embodiments, the remaining portions 130 of the sacrificial layer 128 are removed using a dilute hydrofluoric acid (HF) solution or gas.

[0042]

[0082] In one or more embodiments, the charge trapping layer 124 has a first thickness t t and a second thickness t c In one or more embodiments, the first thickness t t and the second thickness t c In one or more embodiments, the top (and bottom) first thickness t t is the second thickness t c In one or more embodiments, the first thickness t t is the second thickness t c In one or more embodiments, the first thickness t t is the second thickness t c In other embodiments, the first thickness t of the top (and bottom) of the charge trapping layer 124 is in the range of 1% to 50% thicker. t is the second thickness t c In one or more embodiments, the first thickness t t is the second thickness t c In one or more embodiments, the first thickness t t is the second thickness t c It ranges from 1% to 50% thinner.

[0043]

[0083] 12A and 12B, at step 28, a transistor layer 136 is formed in the memory hole channel 116. The transistor layer 136 may be formed by any suitable technique known to those skilled in the art. In some embodiments, the transistor layer is formed by a conformal deposition process. In some embodiments, the transistor layer is formed by one or more of atomic layer deposition or chemical vapor deposition.

[0044]

[0084] In one or more embodiments, the deposition of the transistor layer 136 is substantially conformal. As used herein, a "substantially conformal" layer refers to a layer that has approximately the same thickness throughout (e.g., the top, middle, and bottom of the sidewalls and the bottom of the memory hole channel 116). The thickness variation of a substantially conformal layer is about 5% or less, 2% or less, 1% or less, or 0.5% or less. The transistor layer 136 in the memory hole may include one or more of an aluminum oxide (AlO) layer, a blocking oxide layer, a trap layer, a tunnel oxide layer, and a channel layer.

[0045]

[0085] 12B, which is an expanded view of region 120 of FIG. 12A, in one or more embodiments, transistor layers 136 include a blocking oxide layer 122, a nitride trapping layer 124, a tunnel oxide layer 136a, a channel material 136b, and a core oxide material 136c in the memory hole channel 116. In one or more embodiments, the channel material 136b includes polysilicon.

[0046]

[0086] The transistor layer 136 can have any suitable thickness, depending on, for example, the dimensions of the memory hole channel 116. In some embodiments, the transistor layer 136 has a thickness in the range of about 0.5 nm to about 50 nm, or in the range of about 0.75 nm to about 35 nm, or in the range of about 1 nm to about 20 nm.

[0047]

[0087] 13 illustrates step 30 of method 10 in which bit line pad 138 is formed on the top surface of transistor layer 136 and mask layer 137. In one or more embodiments, core oxide 136c is recessed and then the recessed area is filled with doped polysilicon to form bit line pad 138. Bit line pad 138 may be any suitable material known to those skilled in the art, including, but not limited to, polysilicon.

[0048]

[0088] Referring to FIG. 14, in step 32 of method 10, memory stack 130 is slit patterned to form slit pattern openings 142 extending from the top surface of layer 140 to sacrificial layer 106 of common source line 103.

[0049]

[0089] 15 and 16, in step 34 of method 10, sacrificial layer 106 of common source line 103 is removed and replaced with polysilicon layer 146 to form opening 144. Sacrificial layer 106 may be removed by any suitable technique known to those skilled in the art, including, but not limited to, selective etching, hot phosphoric acid, etc. Polysilicon layer 146 may be doped or undoped.

[0050]

[0090] 17 illustrates step 36, mold pullback, in which second layer 110 is removed to form opening 148. Second layer 110 can be removed by any suitable means known to those skilled in the art. In one or more embodiments, second layer 110 is removed by selective etching, for example, selective wet etching or selective dry etching. Removal of second layer 110 forms opening 148.

[0051]

[0091] 18 illustrates step 38 of method 10 in which word lines 150 are formed. Word lines 150 include one or more of an oxide layer 150a, a barrier layer 150b, and a word line metal 150c. Oxide layer 150a may include any suitable material known to those skilled in the art. In one or more embodiments, oxide layer 150a is an aluminum oxide layer. Barrier layer 150b may include any suitable material known to those skilled in the art. In one or more embodiments, barrier layer 150b includes one or more of titanium nitride (TiN), tantalum nitride (TaN), etc. In one or more embodiments, word line metal 150c includes a bulk metal including one or more of copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt), tantalum (Ta), titanium (Ti), or rhodium (Rh). In one or more embodiments, the wordline metal 150c includes tungsten (W). In other embodiments, the wordline metal 150c includes ruthenium (Ru). In one or more embodiments, the wordline 150 includes one or more of a metal, a metal nitride, a conductive metal compound, and a semiconductor material. The metal may be selected from one or more of tungsten (W), molybdenum (Mo), tantalum (Ta), niobium (Nb), osmium (Os), zirconium (Zr), iridium (Ir), rhenium (Re), or titanium (Ti). The metal nitride may be selected from one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), and zirconium nitride (ZrN). The conductive metal compound may be selected from one or more of tungsten oxide (WOx), ruthenium oxide (RuOx), and iridium oxide (IrOx). The semiconductor material may be selected from one or more of silicon (Si), silicon germanium (SiGe), and germanium (Ge).

[0052]

[0092] 19 illustrates step 40 of method 10, in which slits 142 are filled with one or more of spacer material 152 and filler material 154. Spacer material 152 may comprise any suitable material known to those skilled in the art. In one or more embodiments, spacer material 152 is silicon oxide (SiO x Insulator material 154 may be any suitable material known to those skilled in the art. In one or more embodiments, fill material 154 includes polysilicon. The polysilicon may be doped or undoped. In one or more embodiments, the polysilicon may be N + It is doped polysilicon.

[0053]

[0093] 20 illustrates a cap formed on top of the filled slit. In one or more embodiments, the cap includes a barrier layer 156 and a metal layer 158. Barrier layer 156 may include any suitable material known to those of skill in the art. In one or more embodiments, barrier layer 156 includes titanium nitride (TiN). Metal layer 158 may include any suitable metal known to those of skill in the art. In some embodiments, metal 158 includes tungsten (W).

[0054]

[0094] 21A and 21B illustrate steps 42 and 44 in which bit line pad studs 162 and word line (W / L) contacts 160 are formed. Bit line studs 162 can be formed by any suitable means known to those skilled in the art.

[0055]

[0095] The word line contact 160 extends a sufficient distance through the memory stack 130 to terminate at one of the word lines 150. In one or more embodiments, the word line contact 160 may comprise any suitable material known to those skilled in the art. In one or more embodiments, the word line contact 160 comprises one or more of a metal, a metal suicide, polysilicon, amorphous silicon, or epitaxial silicon. In one or more embodiments, the word line contact 160 is doped with either an N-type dopant or a P-type dopant to reduce contact resistance. In one or more embodiments, the metal of the word line contact 160 is selected from one or more of copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), or platinum (Pt).

[0056]

[0096] FIG. 22 is a flow diagram illustrating an exemplary alternative method 11 for forming a memory device. Those skilled in the art will recognize that method 11 can include any or all of the illustrated processes. Furthermore, the order of the individual processes may vary in some respects. Method 11 can begin with any of the listed processes without departing from this disclosure. Referring to FIG. 22, in step 12, a memory stack is formed. In step 14, word line steps are formed in the memory stack. In step 16, a memory hole is patterned. In step 18, a nitride layer is recessed. In step 20, a blocking oxide is formed in the recess. In step 22, a charge trapping layer is deposited, followed by a sacrificial layer. In step 24, the sacrificial layer is partially removed. In step 26, the charge trapping layer is unmasked and the sacrificial layer is removed. In step 28, a transistor layer is deposited in the memory hole. In step 30, bit line pads are formed. In step 32, a slit pattern is formed in the device. In step 34, the sacrificial layer of the common source line is removed and replaced. In step 36, the nitride layer of the memory stack is removed (mold pullback). In step 37A, the blocking oxide is removed. In step 37B, a portion of the charge trapping layer is oxidized. Method 11 then continues in the same manner as method 10 of FIG. 1. In step 38, word lines are formed. In step 40, the slits are filled with a dielectric material. In step 42, bit line pad studs are formed. In step 44, back-end (BEOL) contacts are formed.

[0057]

[0097] Figures 23A to 26B illustrate alternative method 11. Referring to Figure 22, steps 12 to 36 are identical to those of method 10 described above.

[0058]

[0098] 23A and 23B show device 100 after mold pullback process 36, in which second layer 110 is removed to form opening 148. Second layer 110 can be removed by any suitable means known to those skilled in the art. In one or more embodiments, second layer 110 is removed by selective etching, for example, selective wet etching or selective dry etching. Removal of second layer 110 forms opening 148.

[0059]

[0099] 24A and 24B, in step 37A, blocking oxide 122 is removed through opening 148. Blocking oxide 122 can be removed by any suitable means known to those skilled in the art.

[0060]

[0100] 25A and 25B illustrate step 37B of method 11, in which a portion of charge trapping layer 124 is oxidized to form oxide layer 182. Charge trapping layer 124 can be partially oxidized by any means known to those skilled in the art. In one or more embodiments, oxide layer 182 is silicon oxynitride (SiON) or silicon oxide (SiO x ) includes one or more of the following.

[0061]

[0101] 26A and 26B illustrate step 38 of method 11 in which word lines 150 are formed. Word lines 150 include one or more of an oxide layer 150a, a barrier layer 150b, and a word line metal 150c. Oxide layer 150a may include any suitable material known to those skilled in the art. In one or more embodiments, oxide layer 150a is an aluminum oxide layer. Barrier layer 150b may include any suitable material known to those skilled in the art. In one or more embodiments, barrier layer 150b includes one or more of titanium nitride (TiN), tantalum nitride (TaN), etc. In one or more embodiments, the wordline metal 150c comprises a bulk metal including one or more of copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt), tantalum (Ta), titanium (Ti), or rhodium (Rh). In one or more embodiments, the wordline metal 150c comprises tungsten (W). In other embodiments, the wordline metal 150c comprises ruthenium (Ru). In one or more embodiments, the wordline 150 comprises one or more of a metal, a metal nitride, a conductive metal compound, and a semiconductor material. The metal may be selected from one or more of tungsten (W), molybdenum (Mo), tantalum (Ta), niobium (Nb), osmium (Os), zirconium (Zr), iridium (Ir), rhenium (Re), or titanium (Ti). The metal nitride may be selected from one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), and zirconium nitride (ZrN). The conductive metal compound may be selected from one or more of tungsten oxide (WOx), ruthenium oxide (RuOx), and iridium oxide (IrOx). The semiconductor material may be selected from one or more of silicon (Si), silicon germanium (SiGe), and germanium (Ge).

[0062]

[0102] Method 11 then proceeds in the same manner as described above with respect to method 10 of Figures 1 and 19-21B. In step 40, slits 142 are filled. In step 42, bit line pad studs are formed. In step 44, back-end (BEOL) contacts are formed.

[0063]

[0103] In another embodiment, a method for forming a semiconductor device is provided. The method may include forming a memory hole in a memory stack including alternating layers of a first material and a second material on a substrate. The second material is recessed through the memory hole to form a recessed region. A portion of the second material adjacent to the memory hole is oxidized to form a blocking oxide layer. A charge trapping layer is deposited on the blocking oxide layer. A sacrificial layer is conformally deposited on the charge trapping layer. The charge trapping layer is selectively removed from the sacrificial layer, which is then removed. Bit lines are formed in the memory hole. A slit pattern is then formed in the memory device to form a plurality of word lines. The slits are then filled.

[0064]

[0104] An additional embodiment of the present disclosure is directed to a processing tool 900 for forming the described memory devices and methods, as shown in FIG.

[0065]

[0105] The cluster tool 900 includes at least one central transfer station 921, 931 having multiple sides. Robots 925, 935 are positioned within the central transfer stations 921, 931 and configured to move a robot blade and wafer to each of the multiple sides.

[0066]

[0106] The cluster tool 900 includes multiple processing chambers, also referred to as process stations, 902, 904, 906, 908, 910, 912, 914, 916, and 918 connected to a central transfer station. The various processing chambers provide distinct processing regions isolated from adjacent processing stations. The processing chambers may be any suitable chamber, including, but not limited to, a pre-clean chamber, a buffer chamber, a transfer space, a wafer orienter / degassing chamber, a cryogenic cooling chamber, a deposition chamber, an annealing chamber, an etching chamber, a selective oxidation chamber, an oxide thinning chamber, or a wordline deposition chamber. The specific arrangement of process chambers and components may vary depending on the cluster tool and should not be considered limiting of the scope of this disclosure.

[0067]

[0107] In some embodiments, the cluster tool 900 includes a select gate for drain (SGD) patterning chamber, which in some embodiments comprises one or more selective etch chambers.

[0068]

[0108] 27, a factory interface 950 is connected to the front of the cluster tool 900. The factory interface 950 includes a loading chamber 954 and an unloading chamber 956 at the front 951 of the factory interface 950. Although the loading chamber 954 is shown on the left and the unloading chamber 956 is shown on the right, one skilled in the art will understand that this represents only one possible configuration.

[0069]

[0109] The size and shape of the loading chamber 954 and unloading chamber 956 can vary depending on, for example, the substrates being processed in the cluster tool 900. In the illustrated embodiment, the loading chamber 954 and unloading chamber 956 are sized to hold a wafer cassette having multiple wafers positioned within the cassette.

[0070]

[0110] A robot 952 resides within the factory interface 950 and can move between a loading chamber 954 and an unloading chamber 956. The robot 952 can transfer wafers from a cassette in the loading chamber 954 through the factory interface 950 to a load lock chamber 960. The robot 952 can also transfer wafers from the load lock chamber 962 through the factory interface 950 to a cassette in the unloading chamber 956. As will be appreciated by those skilled in the art, the factory interface 950 can include multiple robots 952. For example, the factory interface 950 can include a first robot that transfers wafers between the loading chamber 954 and the load lock chamber 960 and a second robot that transfers wafers between the load lock 962 and the unloading chamber 956.

[0071]

[0111] The illustrated cluster tool 900 includes a first section 920 and a second section 930. The first section 920 is connected to a factory interface 950 through load lock chambers 960 and 962. The first section 920 includes a first transfer chamber 921 having at least one robot 925 positioned therein. The robot 925 is also referred to as a robotic wafer transfer mechanism. The first transfer chamber 921 is centrally located relative to the load lock chambers 960 and 962, the process chambers 902, 904, 916, and 918, and the buffer chambers 922 and 924. In some embodiments, the robot 925 is a multi-arm robot capable of independently moving multiple wafers at a time. In some embodiments, the first transfer chamber 921 includes multiple robotic wafer transfer mechanisms. The robot 925 in the first transfer chamber 921 is configured to move wafers between chambers surrounding the first transfer chamber 921. Individual wafers are carried on a wafer transport blade located at the distal end of the first robotic mechanism.

[0072]

[0112] After processing the wafer in the first section 920, the wafer may be sent through a pass-through chamber to the second section 930. For example, chambers 922, 924 may be one-way or two-way pass-through chambers. The pass-through chambers 922, 924 may be used, for example, to cryogenically cool the wafer before processing in the second section 930 or to allow for wafer cooling or post-processing before returning to the first section 920.

[0073]

[0113] A system controller 990 communicates with the first robot 925, the second robot 935, the first plurality of processing chambers 902, 904, 916, 918, and the second plurality of processing chambers 906, 908, 910, 912, 914. The system controller 990 may be any suitable component capable of controlling the processing chambers and robots. For example, the system controller 990 may be a computer including a central processing unit, memory, appropriate circuitry, and storage.

[0074]

[0114] The processes may generally be stored in the memory of the system controller 990 as software routines that, when executed by a processor, cause the process chamber to perform the processes of the present disclosure. The software routines may also be stored and / or executed by a second processor (not shown) located remotely from the hardware controlled by the processor. Some or all of the methods of the present disclosure may also be performed in hardware. Thus, the processes may be implemented in software and executed using a computer system, or may be executed in hardware, for example, as an application-specific integrated circuit or other type of hardware implementation, or as a combination of software and hardware. The software routines, when executed by a processor, transform a general-purpose computer into a special-purpose computer (controller) that controls the operation of the chamber to perform the processes.

[0075]

[0115] In one or more embodiments, the processing tool includes a central transfer station including a robot configured to move the wafer; a plurality of process stations, each process station connected to the central transfer station and providing a processing region isolated from the processing regions of adjacent process stations, the plurality of process stations including select gate for drain (SGD) patterning chambers; and a controller connected to the central transfer station and the plurality of process stations, the controller configured to activate the robot to move the wafer between the process stations and to control the process performed at each of the process stations.

[0076]

[0116] One or more embodiments provide a non-transitory computer-readable medium comprising instructions that, when executed by a controller of a processing chamber, cause the processing chamber to perform steps of forming a memory hole in a memory stack comprising alternating layers of a first material and a second material on a substrate, recessing the second material through the memory hole to form a first recessed region, oxidizing a portion of the second material adjacent to the memory hole to form a blocking oxide layer, depositing a charge trapping layer on the blocking oxide layer, conformally depositing a sacrificial layer on the charge trapping layer, selectively removing the charge trapping layer from the sacrificial layer, removing the sacrificial layer, forming a bit line in the memory hole, patterning a slit, forming a plurality of word lines, and filling the slit.

[0077]

[0117] The use of the terms "a," "an," and "the" and similar referents in the context of describing the materials and methods described herein (particularly in the context of the claims below) should be construed to cover both the singular and the plural unless otherwise stated herein or clearly contradicted by context. The recitation of ranges of values herein is merely intended to serve as a shorthand method of referring individually to each individual value falling within the range, unless otherwise stated herein, and each individual value is incorporated herein as if the value were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise stated herein or clearly contradicted by context. The use of any and all examples, or exemplary language (e.g., "etc.") provided herein is intended merely to better clarify the materials and methods and does not impose a limitation on scope unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods.

[0078]

[0118] Throughout this specification, references to "one embodiment," "a particular embodiment," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with that embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of phrases such as "in one or more embodiments," "in a particular embodiment," "in one embodiment," or "in an embodiment" in various places throughout this specification do not necessarily refer to the same embodiment of the present disclosure. Furthermore, particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0079]

[0119] Although the disclosure herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made in the disclosed method and apparatus without departing from the spirit and scope of the disclosure. Therefore, it is intended that the disclosure cover modifications and variations that come within the scope of the appended claims and their equivalents.

Claims

1. 1. A semiconductor memory device, comprising: a plurality of memory cells formed around a memory hole extending through a memory stack on a substrate, the memory stack including a plurality of word lines and corresponding layers of dielectric material arranged alternately to form the memory stack, each of the plurality of memory cells including a plurality of transistor layers including a blocking oxide layer, a charge trapping layer, and a tunnel oxide layer; the blocking oxide layer and the charge trapping layer are confined to the dielectric material layer within each of the plurality of memory cells; the tunnel oxide layer extends continuously within the memory hole; a plurality of memory cells, the charge trapping layer being confined between the tunnel oxide layer and the word line in each of the plurality of memory cells, the charge trapping layer having a first thickness at a top and a second thickness at a center, the first thickness being different from the second thickness, and the charge trapping layer having a vertical height equal to a distance between the dielectric material layers; a filled slit extending through the memory stack adjacent the memory hole, the filled slit including one or more of a spacer material and a filler material; A semiconductor memory device comprising:

2. 2. The semiconductor memory device of claim 1, wherein the first thickness is at least 1% greater than the second thickness.

3. 2. The semiconductor memory device of claim 1, wherein the first thickness is at least 1% less than the second thickness.

4. The semiconductor memory device of claim 1 , wherein the charge trapping layer comprises silicon nitride (SiN).

5. The semiconductor memory device according to claim 1 , further comprising a bit line pad on an upper surface of the memory hole.

6. The semiconductor memory device of claim 1 , wherein the word lines comprise one or more of a metal, a metal nitride, a conductive metal compound, and a semiconductor material.

7. 7. The semiconductor memory device of claim 6, wherein the metal is selected from one or more of tungsten (W), molybdenum (Mo), tantalum (Ta), niobium (Nb), osmium (Os), zirconium (Zr), iridium (Ir), rhenium (Re), and titanium (Ti); the metal nitride is selected from one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), and zirconium nitride (ZrN); the conductive metal compound is selected from one or more of tungsten oxide (WOx), ruthenium oxide (RuOx), and iridium oxide (IrOx); and the semiconductor material is selected from one or more of silicon (Si), silicon germanium (SiGe), and germanium (Ge).

8. 10. The semiconductor memory device of claim 1, wherein the substrate is a common source line, the common source line comprising one or more of a common source sacrificial layer and a polysilicon layer.

9. 10. The semiconductor memory device of claim 1, wherein the semiconductor memory device is a 3D-NAND.

10. A method of forming the semiconductor memory device of claim 1, comprising: forming the memory hole in the memory stack including the plurality of dielectric material layers and corresponding plurality of second material layers alternately arranged in a plurality of stacked pairs on the substrate; recessing each of the plurality of second material layers through the memory hole to form a first recessed region; oxidizing a portion of each of the plurality of second material layers adjacent the memory hole to form the blocking oxide layer; depositing a charge trapping layer over the blocking oxide layer; conformally depositing a sacrificial layer onto the charge trapping layer; selectively removing the charge trapping layer from the sacrificial layer, wherein after the charge trapping layer has been selectively removed from the sacrificial layer, the charge trapping layer has a first thickness at a top portion and a second thickness at a center portion, the first thickness being different from the second thickness and having a vertical height equal to a distance between the dielectric material layers; removing the sacrificial layer; forming a bit line in the memory hole, the bit line including the plurality of transistor layers including the tunnel oxide layer; patterning a slit adjacent to the memory hole and extending from a top of the memory stack to the substrate; removing each of the plurality of second material layers to form a plurality of word line openings adjacent each of the plurality of dielectric material layers; forming a word line in each of the plurality of word line openings; filling the slit to form the filled slit; A method comprising:

11. The method of claim 10 , wherein the charge trapping layer is deposited by atomic layer deposition.

12. The method of claim 10 , wherein the first thickness is at least 1% greater than the second thickness.

13. The method of claim 10 , wherein the first thickness is at least 1% less than the second thickness.

14. forming the bit lines depositing the plurality of transistor layers within the memory hole, the plurality of transistor layers including one or more of a tunnel oxide layer, a channel material, and a core oxide material; The method of claim 10, comprising:

15. 11. The method of claim 10, wherein the substrate is a common source line, the common source line including one or more of a common source sacrificial layer and a polysilicon layer, the method further comprising removing the common source sacrificial layer from the common source line to form a common source opening.

16. The method of claim 10 further comprising forming a word line contact.

17. A non-transitory computer-readable medium containing instructions that, when executed by a controller of a processing chamber, cause the processing chamber to: forming a memory hole in a memory stack comprising a plurality of dielectric material layers and a corresponding plurality of second material layers arranged in a plurality of stacked pairs alternating on a substrate; recessing each of the plurality of second material layers through the memory holes to form first recessed regions; oxidizing a portion of each of the plurality of second material layers adjacent to the memory hole to form a blocking oxide layer; depositing a charge trapping layer over the blocking oxide layer; conformally depositing a sacrificial layer onto the charge trapping layer; selectively removing the charge trapping layer from the sacrificial layer, wherein after the charge trapping layer has been selectively removed from the sacrificial layer, the charge trapping layer has a first thickness at a top portion and a second thickness at a center portion, the first thickness being different from the second thickness and having a vertical height equal to a distance between the dielectric material layers; removing the sacrificial layer; forming a bit line in the memory hole by depositing a plurality of transistor layers in the memory hole; patterning a slit adjacent to the memory hole and extending from the top surface of the memory stack to the substrate; removing each of the plurality of second material layers to form a plurality of word line openings adjacent each of the plurality of dielectric material layers; forming a word line in each of the plurality of word line openings; and filling the slits; A non-transitory computer-readable medium for causing the execution of

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